Data Sheet

LF
PA
K
PSMN2R2-25YLC
N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using
NextPower technology
Rev. 1 — 2 May 2011
Product data sheet
1. Product profile
1.1 General description
Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
„ High reliability Power SO8 package,
qualified to 175°C
„ Optimised for 4.5V Gate drive utilising
NextPower Superjunction technology
„ Low parasitic inductance and
resistance
„ Ultra low QG, QGD and QOSS for high
system efficiencies at low and high
loads
1.3 Applications
„ DC-to-DC converters
„ Power OR-ing
„ Lithium-ion battery protection
„ Server power supplies
„ Load switching
„ Sync rectifier
1.4 Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source
voltage
25 °C ≤ Tj ≤ 175 °C
-
-
25
V
ID
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1
-
-
100
A
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
106
W
Tj
junction
temperature
-55
-
175
°C
VGS = 4.5 V; ID = 25 A;
Tj = 25 °C; see Figure 12
-
2.6
3.15
mΩ
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 12
-
2
2.4
mΩ
[1]
Static characteristics
RDSon
drain-source
on-state
resistance
PSMN2R2-25YLC
NXP Semiconductors
N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
Table 1.
Quick reference data …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Dynamic characteristics
[1]
QGD
gate-drain charge
VGS = 4.5 V; ID = 25 A;
VDS = 12 V; see Figure 14;
see Figure 15
-
5.2
-
nC
QG(tot)
total gate charge
VGS = 4.5 V; ID = 25 A;
VDS = 12 V; see Figure 15;
see Figure 14
-
18
-
nC
Continuous current is limited by package
2. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base;
connected to drain
Simplified outline
Graphic symbol
D
mb
G
mbb076
S
1 2 3 4
SOT669 (LFPAK;
Power-SO8)
3. Ordering information
Table 3.
Ordering information
Type number
PSMN2R2-25YLC
Package
Name
Description
Version
LFPAK; Power-SO8
plastic single-ended surface-mounted package; 4 leads SOT669
4. Marking
Table 4.
Marking codes
Type number
Marking code[1]
PSMN2R2-25YLC
2C225L
[1]
% = placeholder for manufacturing site code.
PSMN2R2-25YLC
Product data sheet
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Rev. 1 — 2 May 2011
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PSMN2R2-25YLC
NXP Semiconductors
N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
25
V
VDGR
drain-gate voltage
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
25
V
VGS
gate-source voltage
ID
drain current
-20
20
V
VGS = 10 V; Tmb = 25 °C; see Figure 1
[1]
-
100
A
VGS = 10 V; Tmb = 100 °C; see Figure 1
[1]
-
100
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C;
see Figure 4
-
636
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
106
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
Tsld(M)
peak soldering temperature
VESD
electrostatic discharge voltage
-
260
°C
MM (JEDEC JESD22-A115)
430
-
V
Source-drain diode
IS
source current
Tmb = 25 °C
-
96
A
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
-
636
A
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A;
Vsup ≤ 25 V; unclamped; RGS = 50 Ω;
see Figure 3
-
60
mJ
Avalanche ruggedness
EDS(AL)S
[1]
non-repetitive drain-source
avalanche energy
Continuous current is limited by package.
PSMN2R2-25YLC
Product data sheet
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Rev. 1 — 2 May 2011
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PSMN2R2-25YLC
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N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
003aaf707
180
03na19
120
ID
(A)
Pder
(%)
150
80
120
(1)
90
60
40
30
0
0
0
Fig 1.
50
100
150
Tmb(°C)
0
200
50
100
150
200
Tmb (°C)
Continuous drain current as a function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003a a f 721
103
I AL
(A)
102
(1)
(2)
10
1
10-1
10-3
Fig 3.
10-2
10-1
1
tAL (ms )
10
Single pulse avalanche rating; avalanche current as a function of avalanche time
PSMN2R2-25YLC
Product data sheet
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PSMN2R2-25YLC
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N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
003aaf708
104
ID
(A)
103
Limit RDSon = VDS / ID
tp =10 μ s
102
100 μ s
DC
10
1 ms
10 ms
100 ms
1
10-1
10-1
Fig 4.
1
10
102
VDS (V)
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
6. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance from
junction to mounting base
see Figure 5
-
1.25
1.42
K/W
003aaf709
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
δ=
P
10-1
0.05
tp
T
0.02
single shot
10
T
1e-6
Fig 5.
t
tp
-2
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN2R2-25YLC
Product data sheet
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N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
7. Characteristics
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
V
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
25
ID = 250 µA; VGS = 0 V; Tj = -55 °C
22.5
-
-
V
VGS(th)
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 10; see Figure 11
1.05
1.54
1.95
V
ID = 10 mA; VDS = VGS; Tj = 150 °C
0.5
-
-
V
IDSS
drain leakage current
IGSS
gate leakage current
RDSon
drain-source on-state
resistance
RG
gate resistance
ID = 1 mA; VDS = VGS; Tj = -55 °C
-
-
2.25
V
VDS = 25 V; VGS = 0 V; Tj = 25 °C
-
-
1
µA
VDS = 25 V; VGS = 0 V; Tj = 150 °C
-
-
100
µA
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
see Figure 12
-
2.6
3.15
mΩ
VGS = 4.5 V; ID = 25 A; Tj = 150 °C;
see Figure 13; see Figure 12
-
-
5.05
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 12
-
2
2.4
mΩ
VGS = 10 V; ID = 25 A; Tj = 150 °C;
see Figure 13; see Figure 12
-
-
3.85
mΩ
f = 1 MHz
-
0.9
1.8
Ω
ID = 25 A; VDS = 12 V; VGS = 10 V;
see Figure 14; see Figure 15
-
39
-
nC
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 15; see Figure 14
-
18
-
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
38
-
nC
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 14; see Figure 15
-
6.3
-
nC
-
4.1
-
nC
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGS(th)
pre-threshold
gate-source charge
QGS(th-pl)
post-threshold
gate-source charge
-
2.2
-
nC
QGD
gate-drain charge
-
5.2
-
nC
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 12 V; see Figure 14;
see Figure 15
-
2.7
-
V
Ciss
input capacitance
Coss
output capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
Crss
reverse transfer
capacitance
td(on)
turn-on delay time
tr
rise time
td(off)
tf
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
-
2542
-
pF
-
617
-
pF
-
216
-
pF
-
24
-
ns
-
34
-
ns
turn-off delay time
-
36
-
ns
fall time
-
16
-
ns
PSMN2R2-25YLC
Product data sheet
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Rev. 1 — 2 May 2011
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PSMN2R2-25YLC
NXP Semiconductors
N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
Table 7.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Qoss
output charge
VGS = 0 V; VDS = 12 V; f = 1 MHz;
Tj = 25 °C
-
16.7
-
nC
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 17
-
0.8
1.1
V
trr
reverse recovery time
-
35
-
ns
Qr
recovered charge
IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 12 V
-
31
-
nC
ta
reverse recovery rise
time
VGS = 0 V; IS = 25 A; dIS/dt = -100 A/µs;
VDS = 12 V; see Figure 18
-
21
-
ns
tb
reverse recovery fall
time
-
14
-
ns
003a a f 710
100
10
ID
(A)
3.5
RDS on
(mΩ)
10
3.0
80
4.5
8
VGS (V) = 2.8
60
003a a f 711
12
6
40
2.6
4
2.4
2
20
0
0
0
Fig 6.
0.5
1
1.5
VDS (V)
2
0
Output characteristics; drain current as a
function of drain-source voltage
PSMN2R2-25YLC
Product data sheet
Fig 7.
8
12
VGS (V)
16
Drain-source on-state resistance as a function
of gate-source voltage; typical values
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PSMN2R2-25YLC
NXP Semiconductors
N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
003a a f 716
160
003a a f 718
100
ID
(A)
gfs
(S )
80
120
60
80
40
Tj = 150 °C
40
Tj = 25 °C
20
0
0
0
Fig 8.
25
50
75
I D (A)
100
Forward transconductance as a function of
drain current; typical values
003a a f 715
10-1
0
Fig 9.
1
2
3
VGS (th)
(V)
-2
10
4
Transfer characteristics; drain current as a
function of gate-source voltage; typical values
003a a f 714
3
ID
(A)
VGS (V)
Max (1mA)
I D=5mA
Min
Typ
2
Max
1mA
10-3
10-4
1
Min (5mA)
10-5
10-6
0
1
2
VGS (V)
0
-60
3
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
PSMN2R2-25YLC
Product data sheet
0
60
120
Tj (°C)
180
Fig 11. Gate-source threshold voltage as a function of
junction temperature
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PSMN2R2-25YLC
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N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
003a a f 712
8
003a a f 713
2
3.0
2.8
RDS on
(mΩ)
a
VGS =10V
1.5
6
4.5V
VGS (V) = 3.5
4
1
4.5
2
0.5
10
0
0
20
40
60
80
I D (A)
0
-60
100
Fig 12. Drain-source on-state resistance as a function
of drain current; typical values
0
60
120
Tj (°C)
180
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
003a a f 719
10
VGS
(V)
VDS
8
ID
6
20V
VGS(pl)
12V
4
VGS(th)
VDS = 5V
VGS
QGS1
2
QGS2
QGS
QGD
QG(tot)
0
0
003aaa508
Fig 14. Gate charge waveform definitions
PSMN2R2-25YLC
Product data sheet
20
40
QG (nC)
60
Fig 15. Gate-source voltage as a function of gate
charge; typical values
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PSMN2R2-25YLC
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N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
003a a f 717
104
003a a f 720
100
IS
(A)
C
(pF)
80
Cis s
60
3
10
40
Cos s
Tj = 150 °C
20
Tj = 25 °C
Crs s
102
10-1
1
0
2
VDS (V) 10
10
0
Fig 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
0.3
0.6
0.9
VS D (V)
1.2
Fig 17. Source current as a function of source-drain
voltage; typical values
003a a f 444
ID
(A)
trr
ta
tb
0
0.25 IRM
I RM
t (s )
Fig 18. Reverse recovery timing definition
PSMN2R2-25YLC
Product data sheet
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N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
8. Package outline
Plastic single-ended surface-mounted package (LFPAK; Power-SO8); 4 leads
A2
A
E
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
e
4
w M A
b
1/2
X
c
e
A
(A 3)
C
A1
θ
L
detail X
y C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A1
A2
A3
b
b2
1.20 0.15 1.10
0.50 4.41
0.25
1.01 0.00 0.95
0.35 3.62
mm
b3
b4
2.2
2.0
0.9
0.7
c
D (1)
c2
D1(1)
E(1) E1(1)
max
0.25 0.30 4.10
4.20
0.19 0.24 3.80
5.0
4.8
3.3
3.1
e
H
L
L1
L2
w
y
θ
1.27
6.2
5.8
0.85
0.40
1.3
0.8
1.3
0.8
0.25
0.1
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT669
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
06-03-16
11-03-25
MO-235
Fig 19. Package outline SOT669 (LFPAK; Power-SO8)
PSMN2R2-25YLC
Product data sheet
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N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
9. Revision history
Table 8.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN2R2-25YLC v.1
20110502
Product data sheet
-
-
PSMN2R2-25YLC
Product data sheet
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© NXP B.V. 2011. All rights reserved.
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N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
10. Legal information
10.1 Data sheet status
Document status [1] [2]
Product status [3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
10.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
10.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
PSMN2R2-25YLC
Product data sheet
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 May 2011
© NXP B.V. 2011. All rights reserved.
13 of 15
PSMN2R2-25YLC
NXP Semiconductors
N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
10.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
11. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN2R2-25YLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 May 2011
© NXP B.V. 2011. All rights reserved.
14 of 15
PSMN2R2-25YLC
NXP Semiconductors
N-channel 25 V 2.4 mΩ logic level MOSFET in LFPAK using NextPower
12. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
10
10.1
10.2
10.3
10.4
11
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . .12
Legal information. . . . . . . . . . . . . . . . . . . . . . . .13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Contact information. . . . . . . . . . . . . . . . . . . . . .14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 May 2011
Document identifier: PSMN2R2-25YLC