Data Sheet

PSMN1R3-30YL
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
Rev. 02 — 25 June 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel MOSFET in LFPAK package qualified to 150 °C. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
„ Advanced TrenchMOS provides low
RDSon and low gate charge
„ Improved mechanical and thermal
characteristics
„ High efficiency gains in switching
power convertors
„ LFPAK provides maximum power
density in a Power SO8 package
1.3 Applications
„ DC-to-DC converters
„ Motor control
„ Lithium-ion battery protection
„ Server power supplies
„ Load switching
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max
Unit
-
-
30
V
-
-
100
A
-
-
121
W
-55
-
150
°C
VGS = 10 V; Tj(init) = 25 °C;
ID = 100 A; Vsup ≤ 30 V;
RGS = 50 Ω; unclamped
-
-
383
mJ
VGS = 4.5 V; ID = 25 A;
VDS = 12 V; see Figure 13;
see Figure 14
-
9.3
-
nC
-
46.6
-
nC
VDS
drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C
ID
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1;
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
Tj
junction temperature
[1]
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source
avalanche energy
Dynamic characteristics
QGD
gate-drain charge
QG(tot)
total gate charge
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
Table 1.
Quick reference …continued
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VGS = 10 V; ID = 15 A;
Tj = 100 °C; see Figure 12
-
-
1.8
mΩ
VGS = 10 V; ID = 15 A;
Tj = 25 °C; see Figure 17
-
1.04
1.3
mΩ
Static characteristics
RDSon
[1]
drain-source
on-state resistance
Continuous current is limited by package.
2. Pinning information
Table 2.
Pinning information
Pin
Symbol
Description
Simplified outline
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
Graphic symbol
D
G
mbb076
1
2
3
S
4
SOT1023
(LFPAK2)
3. Ordering information
Table 3.
Ordering information
Type number
PSMN1R3-30YL
Package
Name
Description
Version
LFPAK2
Plastic single-ende surface-mounted package (LFPAK2); 4 leads
SOT1023
PSMN1R3-30YL_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
2 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 150 °C
-
30
V
VDGR
drain-gate voltage
Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 kΩ
VGS
gate-source voltage
ID
drain current
-
30
V
-20
20
V
VGS = 10 V; Tmb = 100 °C; see Figure 1
[1]
-
100
A
VGS = 10 V; Tmb = 25 °C; see Figure 1
[1]
-
100
A
IDM
peak drain current
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
-
923
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
121
W
Tstg
storage temperature
-55
150
°C
Tj
junction temperature
-55
150
°C
Tsld(M)
peak soldering
temperature
-
260
°C
-
100
A
-
923
A
-
383
mJ
Source-drain diode
IS
source current
Tmb = 25 °C;
[1]
ISM
peak source current
tp ≤ 10 µs; pulsed; Tmb = 25 °C
Avalanche ruggedness
non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ≤ 30 V;
drain-source avalanche RGS = 50 Ω; unclamped
energy
EDS(AL)S
[1]
Continuous current is limited by package.
003aad141
250
ID
(A)
200
03aa15
120
Pder
(%)
80
150
100
40
50
0
0
0
Fig 1.
50
100
150
200
Tmb (°C)
Normalized continuous drain currnet as a
function of mounting base temperature
0
100
150
200
Tmb (°C)
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
PSMN1R3-30YL_2
Product data sheet
50
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
3 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
003aad145
104
ID
(A)
103
Limit RDSon = VDS / ID
tp = 10 us
10
2
100 us
DC
10
1 ms
10 ms
100 ms
1
10-1
10-1
Fig 3.
1
10
102
VDS (V)
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN1R3-30YL_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
4 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance from junction to
mounting base
see Figure 4
-
0.4
1.03
K/W
003aad142
1
Zth (j-mb)
(K/W)
10
δ = 0.5
-1
0.2
0.1
0.05
10-2
0.02
δ=
P
10-3
tp
T
single shot
t
tp
T
10-4
10-6
Fig 4.
10-5
10-4
10-3
10-2
10-1
1
tp (s)
10
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN1R3-30YL_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
5 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
VGS(th)
IDSS
IGSS
RDSon
RG
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
30
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
27
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 10; see Figure 11
1.3
1.7
2.15
V
ID = 1 mA; VDS = VGS; Tj = 150 °C;
see Figure 10
0.65
-
-
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 10
-
-
2.45
V
VDS = 30 V; VGS = 0 V; Tj = 25 °C
-
-
1
µA
VDS = 30 V; VGS = 0 V; Tj = 150 °C
-
-
100
µA
VGS = 15 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = -15 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = 4.5 V; ID = 15 A; Tj = 25 °C;
see Figure 17
-
1.43
1.95
mΩ
VGS = 10 V; ID = 15 A; Tj = 100 °C;
see Figure 12
-
-
1.8
mΩ
VGS = 10 V; ID = 15 A; Tj = 150 °C;
see Figure 12
-
1.9
2.8
mΩ
VGS = 10 V; ID = 15 A; Tj = 25 °C;
see Figure 17
-
1.04
1.3
mΩ
f = 1 MHz
-
0.89
-
Ω
ID = 25 A; VDS = 12 V; VGS = 10 V;
see Figure 13; see Figure 14
-
100
-
nC
drain leakage current
gate leakage current
drain-source on-state
resistance
gate resistance
Dynamic characteristics
QG(tot)
total gate charge
ID = 0 A; VDS = 0 V; VGS = 10 V
-
90
-
nC
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 13; see Figure 14
-
46.6
-
nC
QGS
gate-source charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 13; see Figure 14
-
17.9
-
nC
QGS(th)
pre-threshold
gate-source charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 13
-
11
-
nC
QGS(th-pl)
post-threshold
gate-source charge
-
6.9
-
nC
QGD
gate-drain charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 13; see Figure 14
-
9.3
-
nC
VGS(pl)
gate-source plateau
voltage
VDS = 12 V; see Figure 13; see Figure 14
-
2.53
-
V
Ciss
input capacitance
-
6227
-
pF
Coss
output capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 15
-
1415
-
pF
Crss
reverse transfer
capacitance
-
619
-
pF
PSMN1R3-30YL_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
6 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
td(on)
turn-on delay time
-
64
-
ns
tr
rise time
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 5.6 Ω
-
108
-
ns
td(off)
turn-off delay time
-
106
-
ns
tf
fall time
-
52
-
ns
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 16
-
0.88
1.2
V
trr
reverse recovery time
-
46
-
ns
Qr
recovered charge
IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V;
VDS = 20 V
-
53
-
nC
003aad147
8
RDS(on)
(mΩ)
003aad152
104
Ciss
C
(pF)
6
Crss
4
2
0
0
Fig 5.
5
10
15
VGS (V)
20
Drain-source on-state resistance as a function
of gate-source voltage; typical values.
103
10-1
Fig 6.
VGS (V)
10
Input and reverse transfer capacitances as a
function of gate-source voltage; typical values
PSMN1R3-30YL_2
Product data sheet
1
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
7 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
003aad153
200
003aad144
100
3
ID
(A)
gfs
(S)
80
VGS (V) = 2.8
3.5
150
2.6
10
60
100
40
2.4
50
20
2.2
0
0
0
Fig 7.
25
50
75
ID (A)
Forward transconductance as a function of
drain current; typical values
003aad148
100
0
100
ID
(A)
Fig 8.
1
2
VDS (V)
3
Output characteristics: drain current as a
function of drain-source voltage; typical values
003aab272
3
VGS(th)
(V)
75
max
2
typ
1.5
50
min
1
Tj = 150 °C
25
25 °C
0.5
0
0
Fig 9.
1
2
VGS (V)
3
0
-60
60
120
180
Tj (°C)
Transfer characteristics: drain current as a
function of gate-source voltage; typical
valuesvalues
Fig 10. Gate-source threshold voltage as a function of
junction temperature
PSMN1R3-30YL_2
Product data sheet
0
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
8 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
003aab271
10-1
ID
(A)
10-2
03aa27
2
a
1.5
min
typ
max
10-3
1
10
-4
0.5
10-5
10-6
0
1
2
VGS (V)
3
Fig 11. Sub-threshold drain current as a function of
gate-source voltage
0
−60
0
60
120
180
Fig 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
003aad150
10
VDS
Tj (°C)
VGS
(V)
ID
8
VGS(pl)
6
VDS = 12V
VGS(th)
VGS
4
QGS1
QGS2
QGS
QGD
QG(tot)
2
003aaa508
Fig 13. Gate charge waveform definitions
0
0
25
50
75
100
QG (nC)
Fig 14. Gate-source voltage as a function of gate
charge; typical values
PSMN1R3-30YL_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
9 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
003aad151
104
003aad149
100
IS
(A)
Ciss
C
(pF)
75
Coss
103
50
Crss
Tj = 150 °C
25
102
10-1
1
10
VDS (V)
25 °C
0
102
0
Fig 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
0.25
0.5
0.75
VSD (V)
1
Fig 16. Source current as a function of source-drain
voltage; typical values
003aad146
10
VGS (V) = 2.6
RDS(on)
(mΩ)
7.5
5
2.8
3
2.5
3.5
4.5
10
0
0
25
50
75
ID (A)
100
Fig 17. Drain-source on-state resistance as a function of drain current; typical values
PSMN1R3-30YL_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
10 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
7. Package outline
Plastic single-ended surface-mounted package (LFPAK2); 4 leads
A
E
SOT1023
E1
A
b1
b2
(3×)
c1
mounting
base
D1
D
H
L
1
2
3
4
b
e
A1
X
w
A
c
C
θ
Lp
detail X
0
2.5
mm
5 mm
scale
Dimensions
Unit
y C
A
A1
b
b1
b2
c
c1
D(1) D1(1) E(1) E1(1)
max 1.10 0.15 0.50 4.41
0.25 0.30 4.70 4.45 5.30
0.85
nom
min 0.95 0.00 0.35 3.62
0.19 0.24 4.45
4.95
e
3.7
H
L
Lp
6.2
1.3
0.85
1.27
3.5
5.9
0.8
w
y
0.25
0.1
8°
0.40
Note
1. Plastic or metal protrusions of 0.15 mm per side are not included.
Outline
version
JEDEC
0°
sot1023_po
References
IEC
θ
JEITA
European
projection
Issue date
08-10-13
09-05-26
SOT1023
Fig 18. Package outline SOT1023; Package outline
PSMN1R3-30YL_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
11 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN1R3-30YL_2
20090625
Product data sheet
-
PSMN2R3-30YL_1
Modifications:
PSMN1R3-30YL_1
•
•
Status changed from objective to product.
Various changes to content.
20090528
Objective data sheet
-
PSMN1R3-30YL_2
Product data sheet
-
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
12 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
9. Legal information
9.1
Data sheet status
Document status [1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PSMN1R3-30YL_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 25 June 2009
13 of 14
PSMN1R3-30YL
NXP Semiconductors
N-channel 30 V 1.3 mΩ logic level MOSFET in LFPAK
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . .12
Legal information. . . . . . . . . . . . . . . . . . . . . . . .13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Contact information. . . . . . . . . . . . . . . . . . . . . .13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 June 2009
Document identifier: PSMN1R3-30YL_2
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