Data Sheet

LF
PA
K
33
PSMN6R1-25MLD
N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33
using NextPowerS3 Technology
6 April 2016
Product data sheet
1. General description
Logic level gate drive N-channel enhancement mode MOSFET in LFPAK33 package.
NextPowerS3 portfolio utilising NXP’s unique “SchottkyPlus” technology delivers
high efficiency, low spiking performance usually associated with MOSFETS with an
integrated Schottky or Schottky-like diode but without problematic high leakage current.
NextPowerS3 is particularly suited to high efficiency applications at high switching
frequencies.
2. Features and benefits
•
•
•
•
•
•
•
•
Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching
frequencies
Superfast switching with soft-recovery; s-factor > 1
Low spiking and ringing for low EMI designs
Unique “SchottkyPlus” technology; Schottky-like performance with < 1 µA leakage at
25 °C
Optimised for 4.5 V gate drive
Low parasitic inductance and resistance
High reliability clip bonded and solder die attach Mini Power SO8 package; no glue,
no wire bonds, qualified to 175 °C
Exposed leads for optimal visual solder inspection
3. Applications
•
•
•
•
•
•
On-board DC:DC solutions for server and telecommunications
Secondary-side synchronous rectification in telecommunication applications
Voltage regulator modules (VRM)
Point-of-Load (POL) modules
Power delivery for V-core, ASIC, DDR, GPU, VGA and system components
Brushed and brushless motor control
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
-
25
V
ID
drain current
VGS = 10 V; Tmb = 25 °C; Fig. 2
-
-
60
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 1
-
-
42
W
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PSMN6R1-25MLD
NXP Semiconductors
N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
Symbol
Parameter
Tj
junction temperature
Conditions
Min
Typ
Max
Unit
-55
-
175
°C
-
8.98
10.3
mΩ
-
6.46
7.24
mΩ
-
10.7
-
nC
-
4.9
-
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
5.6
-
nC
ID = 15 A; VDS = 12 V; VGS = 4.5 V;
-
1.1
-
nC
-
1.3
-
Static characteristics
RDSon
drain-source on-state
resistance
VGS = 4.5 V; ID = 15 A; Tj = 25 °C;
Fig. 10
VGS = 10 V; ID = 15 A; Tj = 25 °C;
Fig. 10
Dynamic characteristics
QG(tot)
total gate charge
ID = 15 A; VDS = 12 V; VGS = 10 V;
Fig. 12; Fig. 13
ID = 15 A; VDS = 12 V; VGS = 4.5 V;
Fig. 12; Fig. 13
QGD
gate-drain charge
Fig. 12; Fig. 13
Source-drain diode
S
softness factor
IS = 15 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 12 V; Fig. 16
5. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
Simplified outline
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
Graphic symbol
D
G
mbb076
1
2
3
S
4
LFPAK33 (SOT1210)
6. Ordering information
Table 3.
Ordering information
Type number
PSMN6R1-25MLD
PSMN6R1-25MLD
Product data sheet
Package
Name
Description
Version
LFPAK33
Plastic single ended surface mounted package
(LFPAK33); 8 leads
SOT1210
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PSMN6R1-25MLD
NXP Semiconductors
N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
7. Marking
Table 4.
Marking codes
Type number
Marking code
PSMN6R1-25MLD
6D125L
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
25
V
VDGR
drain-gate voltage
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
25
V
VGS
gate-source voltage
-20
20
V
Ptot
total power dissipation
Tmb = 25 °C; Fig. 1
-
42
W
ID
drain current
VGS = 10 V; Tmb = 25 °C; Fig. 2
-
60
A
VGS = 10 V; Tmb = 100 °C; Fig. 2
-
41
A
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3
-
235
A
IDM
peak drain current
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
Tsld(M)
peak soldering temperature
-
260
°C
VESD
electrostatic discharge voltage
HBM
400
-
V
Source-drain diode
IS
source current
Tmb = 25 °C
-
38
A
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
-
241
A
-
51.3
mJ
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
ID = 15 A; Vsup ≤ 25 V; RGS = 50 Ω;
[1]
VGS = 10 V; Tj(init) = 25 °C; unclamped;
tp = 210 µs
[1]
PSMN6R1-25MLD
Product data sheet
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PSMN6R1-25MLD
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N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
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03aa16
120
ID
(A)
Pder
(%)
aaa-022417
80
60
80
40
40
20
0
Fig. 1.
ID
(A)
0
50
100
150
Tmb (°C)
0
200
Normalized total power dissipation as a
function of mounting base temperature
0
25
50
75
100
125
150 175
Tmb (°C)
200
VGS ≥ 10 V
Fig. 2.
Continuous drain current as a function of
mounting base temperature
aaa-022418
103
Limit RDSon = VDS / ID
102
tp = 10 us
100 us
10
DC
1 ms
10 ms
100 ms
1
10-1
10-1
1
10
102
VDS (V)
Tmb = 25 °C; IDM is a single pulse
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 4
-
3.04
3.32
K/W
PSMN6R1-25MLD
Product data sheet
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N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-a)
thermal resistance
from junction to
ambient
Fig. 5
-
57
-
K/W
Fig. 6
-
178
-
K/W
aaa-022419
10
Zth(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
0.05
10-1 0.02
P
single shot
δ=
tp
10-2
10-6
Fig. 4.
10-5
10-4
10-3
10-2
T
t
T
10-1
1
tp (s)
Transient thermal impedance from junction to mounting base as a function of pulse duration
aaa-008477
aaa-008476
Fig. 5.
tp
PCB layout for thermal resistance junction to
ambient 1" square pad; FR4 Board; 2oz copper
Fig. 6.
PCB layout for thermal resistance junction to
ambient minimum footprint; FR4 Board; 2oz
copper
10. Characteristics
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
25
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
22.5
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS=VGS; Tj = 25 °C
1.2
1.76
2.2
V
Static characteristics
V(BR)DSS
VGS(th)
PSMN6R1-25MLD
Product data sheet
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PSMN6R1-25MLD
NXP Semiconductors
N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ΔVGS(th)/ΔT
gate-source threshold
voltage variation with
temperature
25 °C ≤ Tj ≤ 175 °C
-
-4.1
-
mV/K
IDSS
drain leakage current
VDS = 20 V; VGS = 0 V; Tj = 25 °C
-
-
1
µA
VDS = 20 V; VGS = 0 V; Tj = 125 °C
-
0.8
-
µA
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = -20 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = 4.5 V; ID = 15 A; Tj = 25 °C;
-
8.98
10.3
mΩ
-
-
17.51
mΩ
-
6.46
7.24
mΩ
-
-
12.48
mΩ
f = 1 MHz
-
0.66
-
Ω
ID = 15 A; VDS = 12 V; VGS = 10 V;
-
10.7
-
nC
-
4.9
-
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
5.6
-
nC
IGSS
RDSon
gate leakage current
drain-source on-state
resistance
Fig. 10
VGS = 4.5 V; ID = 15 A; Tj = 175 °C;
Fig. 10; Fig. 11
VGS = 10 V; ID = 15 A; Tj = 25 °C;
Fig. 10
VGS = 10 V; ID = 15 A; Tj = 175 °C;
Fig. 10; Fig. 11
RG
gate resistance
Dynamic characteristics
QG(tot)
total gate charge
Fig. 12; Fig. 13
ID = 15 A; VDS = 12 V; VGS = 4.5 V;
Fig. 12; Fig. 13
QGS
gate-source charge
ID = 15 A; VDS = 12 V; VGS = 4.5 V;
-
2.3
-
nC
QGS(th)
pre-threshold gatesource charge
Fig. 12; Fig. 13
-
1.2
-
nC
QGS(th-pl)
post-threshold gatesource charge
-
1
-
nC
QGD
gate-drain charge
-
1.1
-
nC
VGS(pl)
gate-source plateau
voltage
ID = 15 A; VDS = 12 V; Fig. 12; Fig. 13
-
3
-
V
Ciss
input capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
-
702
-
pF
Coss
output capacitance
Tj = 25 °C; Fig. 14
-
590
-
pF
Crss
reverse transfer
capacitance
-
45
-
pF
td(on)
turn-on delay time
VDS = 12 V; RL = 1 Ω; VGS = 4.5 V;
-
7.7
-
ns
tr
rise time
RG(ext) = 5 Ω
-
7.9
-
ns
td(off)
turn-off delay time
-
7.8
-
ns
tf
fall time
-
4.7
-
ns
PSMN6R1-25MLD
Product data sheet
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PSMN6R1-25MLD
NXP Semiconductors
N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Qoss
output charge
VGS = 0 V; VDS = 12 V; f = 1 MHz;
-
9.2
-
nC
Tj = 25 °C
Source-drain diode
VSD
source-drain voltage
IS = 10 A; VGS = 0 V; Tj = 25 °C; Fig. 15
-
0.83
1.2
V
trr
reverse recovery time
IS = 15 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
19.3
-
ns
Qr
recovered charge
VDS = 12 V; Fig. 16
-
8.1
-
nC
ta
reverse recovery rise
time
-
8.6
-
ns
tb
reverse recovery fall
time
-
10.7
-
ns
S
softness factor
-
1.3
-
[1]
ID
(A)
includes capacitive recovery
aaa-022420
80
60
[1]
4.5 V
20
RDSon
(mΩ)
10 V
16
aaa-022421
3.5 V
12
40
8
VGS = 3 V
20
0
Fig. 7.
2.8 V
0
1
2
3
VDS (V)
4
0
4
0
2
4
6
8
10
12
14
VGS (V)
16
Tj = 25 °C
Tj = 25 °C; ID = 15 A
Output characteristics; drain current as a
Fig. 8.
function of drain-source voltage; typical values
Drain-source on-state resistance as a function
of gate-source voltage; typical values
PSMN6R1-25MLD
Product data sheet
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N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
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ID
(A)
aaa-022422
40
aaa-022423
60
RDSon
(mΩ)
50
32
3V
40
3.5 V
24
30
16
20
8
0
175°C
0
0.5
1
1.5
2
Tj = 25°C
2.5
3
3.5
VGS (V)
0
4
VDS = 12 V
Fig. 9.
a
4.5 V
10
VGS = 10 V
0
10
20
30
40
50
ID (A)
60
Tj = 25 °C
Transfer characteristics; drain current as a
function of gate-source voltage; typical values
Fig. 10. Drain-source on-state resistance as a function
of drain current; typical values
aaa-021697
2
VGS
(V)
10 V
1.6
1.2
aaa-022425
10
8
6
VGS = 4.5 V
20 V
0.8
12 V
4
VDS = 5 V
0.4
0
-60
2
-30
0
30
60
90
120 150
Tj (°C)
0
180
Fig. 11. Normalized drain-source on-state resistance
factor as a function of junction temperature
PSMN6R1-25MLD
Product data sheet
0
4
8
12
16
QG (nC)
20
Tj = 25 °C; ID = 15 A
Fig. 12. Gate-source voltage as a function of gate
charge; typical values
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PSMN6R1-25MLD
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N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
aaa-022426
104
C
(pF)
VDS
ID
103
VGS(pl)
Ciss
Coss
VGS(th)
VGS
QGS2
QGS1
QGS
102
Crss
QGD
QG(tot)
003aaa508
10
10-1
Fig. 13. Gate charge waveform definitions
1
10
VDS (V)
102
VGS = 0 V; f = 1 MHz
Fig. 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
IS
(A)
003aal160
aaa-022427
103
ID
(A)
102
trr
ta
0.25 IRM
1
175°C
10-1
tb
0
10
0
0.2
0.4
Tj = 25°C
0.6
0.8
1
VSD (V)
IRM
t (s)
1.2
VGS = 0 V
Fig. 16. Reverse recovery timing definition
Fig. 15. Source-drain (diode forward) current as a
function of source-drain (diode forward)
voltage; typical values
PSMN6R1-25MLD
Product data sheet
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PSMN6R1-25MLD
NXP Semiconductors
N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
11. Package outline
Plastic single ended surface mounted package (LFPAK33); 8 leads
E
e1
L
SOT1210
A
A
c1
b1
E1
D2
mounting
base
D1
D
H
1
4
e
b
w
X
A
A1
c
C
θ
Lp
y C
detail X
0
2.5
5 mm
scale
Dimensions
Unit(1)
mm
A
A1
b
b1
c
c1
D(1)
D1
D2
E(1)
E1
e
e1
H
L
Lp
w
y
max 0.90 0.10 0.35 0.35 0.20 0.30 2.70 2.35
3.40 2.45
3.40 0.25 0.50
nom
0.50
0.65 0.65
0.20 0.10
3.20 2.00
3.20 0.13 0.30
min 0.80 0.00 0.25 0.25 0.10 0.20 2.50 1.90
Note
1. Plastic or metal protrusions of 0.15 mm per side are not included.
Outline
version
JEDEC
8°
0°
sot1210_po
References
IEC
θ
JEITA
European
projection
Issue date
12-03-12
14-04-25
SOT1210
Fig. 17. Package outline LFPAK33 (SOT1210)
PSMN6R1-25MLD
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PSMN6R1-25MLD
NXP Semiconductors
N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
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punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
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whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
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PSMN6R1-25MLD
Product data sheet
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agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
All information provided in this document is subject to legal disclaimers.
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PSMN6R1-25MLD
NXP Semiconductors
N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
12.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip,
HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE,
MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP
Semiconductors N.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN6R1-25MLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
6 April 2016
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PSMN6R1-25MLD
NXP Semiconductors
N-channel 25 V, 6.8 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
13. Contents
1
General description ............................................... 1
2
Features and benefits ............................................1
3
Applications ........................................................... 1
4
Quick reference data ............................................. 1
5
Pinning information ............................................... 2
6
Ordering information ............................................. 2
7
Marking ................................................................... 3
8
Limiting values .......................................................3
9
Thermal characteristics .........................................4
10
Characteristics ....................................................... 5
11
Package outline ................................................... 10
12
12.1
12.2
12.3
12.4
Legal information .................................................11
Data sheet status ............................................... 11
Definitions ...........................................................11
Disclaimers .........................................................11
Trademarks ........................................................ 12
© NXP Semiconductors N.V. 2016. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 April 2016
PSMN6R1-25MLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
6 April 2016
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