Data Sheet

LF
PA
K
56
PSMN2R4-30YLD
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56
using NextPowerS3 Technology
7 February 2014
Product data sheet
1. General description
Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package.
NextPowerS3 portfolio utilising NXP’s unique “SchottkyPlus” technology delivers
high efficiency, low spiking performance usually associated with MOSFETs with an
integrated Schottky or Schottky-like diode but without problematic high leakage current.
NextPowerS3 is particularly suited to high efficiency applications at high switching
frequencies.
2. Features and benefits
•
•
•
•
•
•
•
•
Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching
frequencies
Superfast switching with soft-recovery; s-factor > 1
Low spiking and ringing for low EMI designs
Unique “SchottkyPlus” technology; Schottky-like performance with < 1µA leakage at
25 °C
Optimised for 4.5 V gate drive
Low parasitic inductance and resistance
High reliability clip bonded and solder die attach Power SO8 package; no glue, no
wire bonds, qualified to 175 °C
Wave solderable; exposed leads for optimal visual solder inspection
3. Applications
•
•
•
•
•
•
On-board DC-to-DC solutions for server and telecommunications
Secondary-side synchronous rectification in telecommunication applications
Voltage regulator modules (VRM)
Point-of-Load (POL) modules
Power delivery for V-core, ASIC, DDR, GPU, VGA and system components
Brushed and brushless motor control
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
-
30
V
ID
drain current
Tmb = 25 °C; VGS = 10 V; Fig. 2
-
-
100
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 1
-
-
106
W
Scan or click this QR code to view the latest information for this product
[1]
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
Tj
junction temperature
Min
Typ
Max
Unit
-55
-
175
°C
-
2.7
3.1
mΩ
-
2
2.4
mΩ
-
4.3
-
nC
-
16.2
-
nC
-
1
-
Static characteristics
RDSon
drain-source on-state
resistance
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
Fig. 10
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 10
Dynamic characteristics
QGD
gate-drain charge
VGS = 4.5 V; ID = 25 A; VDS = 15 V;
Fig. 12; Fig. 13
QG(tot)
total gate charge
VGS = 4.5 V; ID = 25 A; VDS = 15 V;
Fig. 12; Fig. 13
Source-drain diode
S
softness factor
IS 25 A; VGS = 0 V; dIS/dt = -100 A/s;
VDS = 15 V; Fig. 15
[1]
Continuous current is limited by package
5. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
Simplified outline
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
Graphic symbol
D
mb
G
mbb076
S
1 2 3 4
LFPAK56; PowerSO8 (SOT669)
6. Ordering information
Table 3.
Ordering information
Type number
PSMN2R4-30YLD
PSMN2R4-30YLD
Product data sheet
Package
Name
Description
Version
LFPAK56;
Power-SO8
Plastic single-ended surface-mounted package (LFPAK56;
Power-SO8); 4 leads
SOT669
All information provided in this document is subject to legal disclaimers.
7 February 2014
© NXP N.V. 2014. All rights reserved
2 / 13
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
7. Marking
Table 4.
Marking codes
Type number
Marking code
PSMN2R4-30YLD
2D430L
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
30
V
VDGR
drain-gate voltage
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
30
V
VGS
gate-source voltage
-20
20
V
Ptot
total power dissipation
Tmb = 25 °C; Fig. 1
-
106
W
ID
drain current
VGS = 10 V; Tmb = 25 °C; Fig. 2
[1]
-
100
A
VGS = 10 V; Tmb = 100 °C; Fig. 2
[1]
-
100
A
-
625
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
Tsld(M)
peak soldering temperature
-
260
°C
VESD
electrostatic discharge voltage
HBM (JEDEC JESD22-A114)
750
-
V
Source-drain diode
IS
source current
Tmb = 25 °C
-
88
A
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
-
625
A
-
217
mJ
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 25 A;
[2]
Vsup ≤ 30 V; RGS = 50 Ω; unclamped;
tp = 446 µs
[1]
[2]
PSMN2R4-30YLD
Product data sheet
Continuous current is limited by package
Protected by 100% test
All information provided in this document is subject to legal disclaimers.
7 February 2014
© NXP N.V. 2014. All rights reserved
3 / 13
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
03aa16
120
Pder
(%)
aaa-008273
200
ID
(A)
150
80
(1)
100
40
50
0
Fig. 1.
ID
(A)
0
50
100
150
Tmb (°C)
0
200
Normalized total power dissipation as a
function of mounting base temperature
0
25
50
75
100
125
150 175
Tj (°C)
200
(1) Capped at 100A due to package
Fig. 2.
Continuous drain current as a function of
mounting base temperature
aaa-008365
103
Limit RDSon = VDS / ID
tp = 10 us
102
100 us
10
DC
1 ms
10 ms
100 ms
1
10-1
10-1
Fig. 3.
1
10
102
VDS (V)
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 4
-
1.25
1.42
K/W
PSMN2R4-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
7 February 2014
© NXP N.V. 2014. All rights reserved
4 / 13
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-a)
thermal resistance
from junction to
ambient
Fig. 5
-
50
-
K/W
Fig. 6
-
125
-
K/W
003aaf661
10
Z th(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
10-1
P
0.05
tp
T
δ=
0.02
tp
single shot
10
-2
10-5
1e-6
Fig. 4.
10-4
10-3
10-2
10-1
1
tp (s)
Transient thermal impedance from junction to mounting base as a function of pulse duration
aaa-005751
aaa-005750
Fig. 5.
t
T
PCB layout for thermal resistance junction to
ambient 1” square pad; FR4 Board; 2oz copper
Fig. 6.
PCB layout for thermal resistance junction to
ambient minimum footprint; FR4 Board; 2oz
copper
10. Characteristics
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
30
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
27
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C
1.2
1.7
2.2
V
Static characteristics
V(BR)DSS
VGS(th)
PSMN2R4-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
7 February 2014
© NXP N.V. 2014. All rights reserved
5 / 13
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ΔVGS(th)/ΔT
gate-source threshold
voltage variation with
temperature
25 °C ≤ Tj ≤ 150 °C
-
-4.5
-
mV/K
IDSS
drain leakage current
VDS = 24 V; VGS = 0 V; Tj = 25 °C
-
-
1
µA
VDS = 24 V; VGS = 0 V; Tj = 125 °C
-
0.92
-
µA
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
-
2.7
3.1
mΩ
-
-
5.1
mΩ
-
2
2.4
mΩ
-
-
4
mΩ
f = 1 MHz
-
0.78
-
Ω
ID = 25 A; VDS = 15 V; VGS = 10 V;
-
31.3
-
nC
-
16.2
-
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
29.3
-
nC
IGSS
RDSon
gate leakage current
drain-source on-state
resistance
Fig. 10
VGS = 4.5 V; ID = 25 A; Tj = 150 °C;
Fig. 11; Fig. 10
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 10
VGS = 10 V; ID = 25 A; Tj = 150 °C;
Fig. 11; Fig. 10
RG
gate resistance
Dynamic characteristics
QG(tot)
total gate charge
Fig. 12; Fig. 13
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
Fig. 12; Fig. 13
QGS
gate-source charge
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
-
4.8
-
nC
QGS(th)
pre-threshold gatesource charge
Fig. 12; Fig. 13
-
3
-
nC
QGS(th-pl)
post-threshold gatesource charge
-
1.8
-
nC
QGD
gate-drain charge
-
4.3
-
nC
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 15 V; Fig. 12; Fig. 13
-
2.6
-
V
Ciss
input capacitance
VDS = 15 V; VGS = 0 V; f = 1 MHz;
-
2256
-
pF
Coss
output capacitance
Tj = 25 °C; Fig. 14
-
1175
-
pF
Crss
reverse transfer
capacitance
-
155
-
pF
td(on)
turn-on delay time
VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V;
-
16.3
-
ns
tr
rise time
RG(ext) = 5 Ω
-
27.5
-
ns
td(off)
turn-off delay time
-
17.4
-
ns
tf
fall time
-
13.9
-
ns
PSMN2R4-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
7 February 2014
© NXP N.V. 2014. All rights reserved
6 / 13
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Qoss
output charge
VGS = 0 V; VDS = 15 V; f = 1 MHz;
-
24.8
-
nC
Tj = 25 °C
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 15
-
0.81
1.2
V
trr
reverse recovery time
IS 25 A; dIS/dt = -100 A/s; VGS = 0 V;
-
30.3
-
ns
Qr
recovered charge
VDS = 15 V; Fig. 15
-
20
-
nC
ta
reverse recovery rise
time
-
15
-
ns
tb
reverse recovery fall
time
-
15
-
ns
S
softness factor
-
1
-
[1]
ID
(A)
Includes capacitive recovery
aaa-008276
80
60
[1]
10 V
20
RDSon
(mΩ)
4.5 V
16
aaa-008277
3.5 V
VGS = 3 V
12
40
8
2.8 V
20
4
2.6 V
0
Fig. 7.
0
0.5
1
1.5
2
VDS (V)
0
2.5
Output characteristics; drain current as a
Fig. 8.
function of drain-source voltage; typical values
PSMN2R4-30YLD
Product data sheet
0
2
6
8
10
12
14
VGS (V)
16
Drain-source on-state resistance as a function
of gate-source voltage; typical values
All information provided in this document is subject to legal disclaimers.
7 February 2014
4
© NXP N.V. 2014. All rights reserved
7 / 13
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
aaa-008278
200
ID
(A)
aaa-008279
25
RDSon
(mΩ)
3V
20
150
15
100
10
50
0
Fig. 9.
150°C
0
0.8
1.6
2.4
Tj = 25°C
3.2
VGS (V)
0
4
Transfer characteristics; drain current as a
function of gate-source voltage; typical values
4.5 V
VGS = 10 V
0
10
20
30
40
50
60
70
ID (A)
80
Fig. 10. Drain-source on-state resistance as a function
of drain current; typical values
003aal037
2
a
3.5 V
5
VDS
10 V
1.6
ID
VGS(pl)
1.2
VGS(th)
VGS = 4.5 V
0.8
VGS
QGS1
QGS2
QGS
0.4
QGD
QG(tot)
003aaa508
0
-60
-30
0
30
60
90
120 150
Tj (°C)
180
Fig. 12. Gate charge waveform definitions
Fig. 11. Normalized drain-source on-state resistance
factor as a function of junction temperature
PSMN2R4-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
7 February 2014
© NXP N.V. 2014. All rights reserved
8 / 13
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
VGS
(V)
aaa-008280
10
aaa-008281
104
C
(pF)
8
Ciss
Coss
103
6
24 V
15 V
4
Crss
102
VDS = 6 V
2
0
0
8
16
24
32
QG (nC)
10
10-1
40
Fig. 13. Gate-source voltage as a function of gate
charge; typical values
IS
(A)
1
10
VDS (V)
102
Fig. 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
aaa-008282
103
102
10
1
10-1
150°C
0
0.3
Tj = 25°C
0.6
0.9
VSD (V)
1.2
Fig. 15. Source current as a function of source-drain voltage; typical values
PSMN2R4-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
7 February 2014
© NXP N.V. 2014. All rights reserved
9 / 13
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
11. Package outline
Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads
E
A2
A
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
e
4
w
b
A
X
c
1/2 e
A
(A3)
A1
C
q
L
detail X
0
y C
θ
5 mm
8°
scale
0°
Dimensions (mm are the original dimensions)
Unit(1)
mm
A
A1
A2
A3
b
b2
max 1.20 0.15 1.10
0.50 4.41
nom
0.25
min 1.01 0.00 0.95
0.35 3.62
c
c2
D(1) D1(1) E(1) E1(1)
b3
b4
2.2
0.9
0.25 0.30 4.10 4.20
5.0
3.3
2.0
0.7
0.19 0.24 3.80
4.8
3.1
e
1.27
H
L
L1
L2
6.2
0.85
1.3
1.3
5.8
0.40
0.8
0.8
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
Outline
version
SOT669
References
IEC
JEDEC
JEITA
w
y
0.25
0.1
sot669_po
European
projection
Issue date
11-03-25
13-02-27
MO-235
Fig. 16. Package outline LFPAK56; Power-SO8 (SOT669)
PSMN2R4-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
7 February 2014
© NXP N.V. 2014. All rights reserved
10 / 13
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
12. Legal information
12.1 Data sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Definition
Please consult the most recently issued document before initiating or
completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nxp.com.
12.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
12.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
PSMN2R4-30YLD
Product data sheet
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
All information provided in this document is subject to legal disclaimers.
7 February 2014
© NXP N.V. 2014. All rights reserved
11 / 13
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
12.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN2R4-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
7 February 2014
© NXP N.V. 2014. All rights reserved
12 / 13
PSMN2R4-30YLD
NXP Semiconductors
N-channel 30 V, 2.4 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
13. Contents
1
General description ............................................... 1
2
Features and benefits ............................................1
3
Applications ........................................................... 1
4
Quick reference data ............................................. 1
5
Pinning information ............................................... 2
6
Ordering information ............................................. 2
7
Marking ................................................................... 3
8
Limiting values .......................................................3
9
Thermal characteristics .........................................4
10
Characteristics ....................................................... 5
11
Package outline ................................................... 10
12
12.1
12.2
12.3
12.4
Legal information .................................................11
Data sheet status ............................................... 11
Definitions ...........................................................11
Disclaimers .........................................................11
Trademarks ........................................................ 12
© NXP N.V. 2014. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 7 February 2014
PSMN2R4-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
7 February 2014
© NXP N.V. 2014. All rights reserved
13 / 13