Data Sheet

PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using
NextPower technology
22 August 2012
Product data sheet
1. Product profile
1.1 General description
Logic level enhancement mode N-channel MOSFET in LFPAK package. This product
is designed and qualified for use in a wide range of industrial, communications and
domestic equipment.
1.2 Features and benefits
• High reliability Power SO8 package, qualified to 175°C
• Optimised for 4.5V Gate drive utilising NextPower Superjunction technology
• Ultra low QG, QGD, & QOSS for high system efficiencies at low and high loads
• Ultra low Rdson and low parasitic inductance
1.3 Applications
• DC-to-DC converters
• Load switching
• Power OR-ing
• Server power supplies
• Sync rectifier
1.4 Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
-
40
V
ID
drain current
Tmb = 25 °C; VGS = 10 V; Fig. 1
-
-
100
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 2
-
-
272
W
Tj
junction temperature
-55
-
175
°C
-
1.8
2.1
mΩ
-
1.5
1.8
mΩ
-
10.9
-
nC
[1]
Static characteristics
RDSon
drain-source on-state
resistance
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
Fig. 12
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 12
Dynamic characteristics
QGD
gate-drain charge
VGS = 4.5 V; ID = 25 A; VDS = 20 V;
Fig. 15; Fig. 14
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PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
QG(tot)
total gate charge
VGS = 4.5 V; ID = 25 A; VDS = 20 V;
-
45
-
nC
Fig. 15; Fig. 14
[1]
Continuous current is limited by package.
2. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
Simplified outline
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
Graphic symbol
D
mb
G
S
mbb076
1 2 3 4
LFPAK; PowerSO8 (SOT669)
3. Ordering information
Table 3.
Ordering information
Type number
Package
PSMN1R8-40YLC
Name
Description
Version
LFPAK;
Power-SO8
plastic single-ended surface-mounted package; 4 leads
SOT669
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
40
V
VDGR
drain-gate voltage
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
40
V
VGS
gate-source voltage
-20
20
V
ID
drain current
VGS = 10 V; Tmb = 25 °C; Fig. 1
[1]
-
100
A
VGS = 10 V; Tmb = 100 °C; Fig. 1
[1]
-
100
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4
-
1128
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 2
-
272
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
Tsld(M)
peak soldering temperature
260
°C
PSMN1R8-40YLC
Product data sheet
-
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PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
Symbol
Parameter
Conditions
Min
Max
Unit
VESD
electrostatic discharge voltage
MM (JEDEC JESD22-A115)
890
-
V
-
100
A
Source-drain diode
IS
source current
Tmb = 25 °C
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
-
1128
A
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A;
-
248
mJ
[1]
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
Vsup ≤ 40 V; RGS = 50 Ω; unclamped;
Fig. 3
[1]
Continuous current is limited by package.
003aaj880
320
ID
(A)
03na19
120
Pder
(%)
240
80
160
(1)
40
80
0
Fig. 1.
0
50
100
150
Tmb (°C)
Continuous drain current as a function of
mounting base temperature
PSMN1R8-40YLC
Product data sheet
0
200
Fig. 2.
0
100
150
Tmb (°C)
200
Normalized total power dissipation as a
function of mounting base temperature
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PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
003aaj881
103
IAL(A)
102
(1)
10
(2)
1
10-3
Fig. 3.
10-2
10-1
1
tAL(ms)
10
Single pulse avalanche rating; avalanche current as a function of avalanche time
003aaj882
104
ID
(A)
103
Limit RDSon = V DS / ID
tp =10 µs
102
100 µs
10
DC
1 ms
10 ms
100 ms
1
10-1
10-1
Fig. 4.
1
10
102
V DS (V)
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 5
-
0.45
0.55
K/W
PSMN1R8-40YLC
Product data sheet
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PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
003aaj883
1
Zth(j-mb) δ = 0.5
(K/W)
0.2
10-1
0.1
0.05
P
0.02
10-2
tp
T
δ=
single shot
tp
10-3
Fig. 5.
10-6
10-5
10-4
10-3
10-2
t
T
10-1
1
tp (s)
Transient thermal impedance from junction to mounting base as a function of pulse duration
6. Characteristics
Table 6.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
40
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
36
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C;
1.05
1.45
1.95
V
0.5
-
-
V
-
-
2.25
V
VDS = 40 V; VGS = 0 V; Tj = 25 °C
-
-
1
µA
VDS = 40 V; VGS = 0 V; Tj = 150 °C
-
-
100
µA
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
-
1.8
2.1
mΩ
-
-
3.6
mΩ
-
1.5
1.8
mΩ
-
-
3.25
mΩ
Static characteristics
V(BR)DSS
VGS(th)
Fig. 10
ID = 10 mA; VDS = VGS; Tj = 150 °C;
Fig. 11
ID = 1 mA; VDS = VGS; Tj = -55 °C;
Fig. 11
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
Fig. 12
VGS = 4.5 V; ID = 25 A; Tj = 150 °C;
Fig. 12; Fig. 13
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 12
VGS = 10 V; ID = 25 A; Tj = 150 °C;
Fig. 12; Fig. 13
PSMN1R8-40YLC
Product data sheet
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PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RG
gate resistance
f = 1 MHz
0.5
1
2
Ω
ID = 25 A; VDS = 20 V; VGS = 10 V;
-
96
-
nC
-
45
-
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
88
-
nC
Dynamic characteristics
QG(tot)
total gate charge
Fig. 14; Fig. 15
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 15; Fig. 14
QGS
gate-source charge
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
-
15.5
-
nC
QGS(th)
pre-threshold gatesource charge
Fig. 15; Fig. 14
-
8.4
-
nC
QGS(th-pl)
post-threshold gatesource charge
-
7.1
-
nC
QGD
gate-drain charge
-
10.9
-
nC
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 20 V; Fig. 15; Fig. 14
-
2.7
-
V
Ciss
input capacitance
VDS = 20 V; VGS = 0 V; f = 1 MHz;
-
6680
-
pF
Coss
output capacitance
Tj = 25 °C; Fig. 16
-
825
-
pF
Crss
reverse transfer
capacitance
-
310
-
pF
td(on)
turn-on delay time
VDS = 20 V; RL = 0.8 Ω; VGS = 4.5 V;
-
32.2
-
ns
tr
rise time
RG(ext) = 5 Ω
-
37
-
ns
td(off)
turn-off delay time
-
62.5
-
ns
tf
fall time
-
31.7
-
ns
Qoss
output charge
-
30
-
nC
VGS = 0 V; VDS = 20 V; f = 1 MHz;
Tj = 25 °C
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 17
-
0.77
1.1
V
trr
reverse recovery time
IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
37
-
ns
Qr
recovered charge
VDS = 20 V
-
43
-
nC
ta
reverse recovery rise
time
VGS = 0 V; IS = 25 A; dIS/dt = -100 A/µs;
-
21
-
ns
-
16
-
ns
tb
VDS = 20 V; Fig. 18
reverse recovery fall
time
PSMN1R8-40YLC
Product data sheet
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PSMN1R8-40YLC
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N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
ID
(A)
100
003aaj884
4.5
3
10
003aaj885
10
RDSon
(mΩ)
2.6
80
7.5
60
2.4
5
40
20
0
Fig. 6.
2.5
VGS (V) = 2.2
0
0.5
1
1.5
VDS(V)
0
2
Output characteristics; drain current as a
Fig. 7.
function of drain-source voltage; typical values
003aaj886
300
gfs
(S)
250
0
4
8
12
VGS (V)
16
Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aaj887
100
ID
(A)
80
200
60
150
40
100
20
50
0
Fig. 8.
Tj = 150 °C
0
20
40
60
80
0
100
ID (A)
Forward transconductance as a function of
drain current; typical values
PSMN1R8-40YLC
Product data sheet
Fig. 9.
0
2
3
VGS (V)
4
Transfer characteristics; drain current as a
function of gate-source voltage; typical values
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Tj = 25 °C
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PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
003aaj888
10-1
ID
(A)
10
003aaj889
3
V GS(th)
Max (1mA)
(V)
-2
ID = 5mA
Min
10-3
Typ
2
Max
1mA
10-4
1 Min (5mA)
10-5
10-6
0
1
2
0
-60
3
V GS (V)
Fig. 10. Sub-threshold drain current as a function of
gate-source voltage
120
a
2.6
Tj (°C)
180
003aaj891
2
2.4
RDSon
(mΩ)
8
60
Fig. 11. Gate-source threshold voltage as a function of
junction temperature
003aaj890
10
0
10V
1.5
6
VGS =4.5V
1
4
3
0.5
4.5
2
VGS (V) = 10
0
0
20
40
60
80
ID (A)
0
-60
100
Fig. 12. Drain-source on-state resistance as a function
of drain current; typical values
PSMN1R8-40YLC
Product data sheet
0
60
120
Tj (°C)
180
Fig. 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
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PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
003aaj892
10
VGS
(V)
VDS
ID
8
VGS(pl)
8V
6
32 V
VGS(th)
VGS
4
QGS1
VDS = 20 V
QGS2
QGS
QGD
QG(tot)
2
003aaa508
0
Fig. 14. Gate charge waveform definitions
0
20
40
60
80
100
QG (nC)
Fig. 15. Gate-source voltage as a function of gate
charge; typical values
003aaj893
104
Ciss
C
(pF)
003aaj894
100
IS
(A)
80
60
10
3
Coss
40
Crss
20
Tj = 150°C
Tj = 25 °C
10
2
10-1
1
10
VDS (V)
0
102
0
0.3
0.6
0.9
VSD(V)
1.2
Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain
as a function of drain-source voltage; typical
voltage; typical values
values
PSMN1R8-40YLC
Product data sheet
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PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
003a a f 444
ID
(A)
trr
ta
tb
0
0.25 IR M
IRM
t (s )
Fig. 18. Reverse recovery timing definition
PSMN1R8-40YLC
Product data sheet
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PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
7. Package outline
Plastic single-ended surface-mounted package (LFPAK; Power-SO8); 4 leads
E
A2
A
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
e
4
w M A
b
X
c
1/2 e
A
(A 3)
A1
C
θ
L
detail X
0
2.5
y C
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
A2
A3
b
b2
1.20 0.15 1.10
0.50 4.41
0.25
1.01 0.00 0.95
0.35 3.62
mm
b3
b4
2.2
2.0
0.9
0.7
c
D (1)
c2
D1(1)
E(1) E1(1)
max
0.25 0.30 4.10
4.20
0.19 0.24 3.80
5.0
4.8
3.3
3.1
e
H
L
L1
L2
w
y
θ
1.27
6.2
5.8
0.85
0.40
1.3
0.8
1.3
0.8
0.25
0.1
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT669
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
06-03-16
11-03-25
MO-235
Fig. 19. Package outline LFPAK; Power-SO8 (SOT669)
PSMN1R8-40YLC
Product data sheet
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PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Definition
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limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
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Please consult the most recently issued document before initiating or
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PSMN1R8-40YLC
Product data sheet
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the Absolute Maximum Ratings System of IEC 60134) will cause permanent
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PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
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Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
8.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN1R8-40YLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
22 August 2012
© NXP B.V. 2012. All rights reserved
13 / 14
PSMN1R8-40YLC
NXP Semiconductors
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
9. Contents
1
1.1
1.2
1.3
1.4
Product profile ....................................................... 1
General description .............................................. 1
Features and benefits ...........................................1
Applications .......................................................... 1
Quick reference data ............................................ 1
2
Pinning information ............................................... 2
3
Ordering information ............................................. 2
4
Limiting values .......................................................2
5
Thermal characteristics .........................................4
6
Characteristics ....................................................... 5
7
Package outline ................................................... 11
8
8.1
8.2
8.3
8.4
Legal information .................................................12
Data sheet status ............................................... 12
Definitions ...........................................................12
Disclaimers .........................................................12
Trademarks ........................................................ 13
© NXP B.V. 2012. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 22 August 2012
PSMN1R8-40YLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
22 August 2012
© NXP B.V. 2012. All rights reserved
14 / 14
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