DFN Package Guidelines for Printed Circuit Board Design This technical note is intended to provide information about Kionix’s 5 x 5 mm DFN packages and guidelines for developing PCB land pattern layouts. These guidelines are general in nature and based on recommended industry practices. The user must apply their actual experiences and development efforts to optimize designs and processes for their manufacturing techniques and the needs of varying end-use applications. It should be noted that with the proper PCB footprint and solder stencil designs, the package will self-align during the solder reflow process. DFN Package Marking • Marking font type • Font size • Line space • Text information st : Arial : 1.5 Point (0.56 mm height) : 0.3 mm : - 1 line – Logo ( No additional dot type pin#1 mark ) nd - 2 line – Device name rd - 3 line – Assembly Build Lot code th - 4 line – Date code (WWYY) nd th Note - 2 ~ 4 line text shall be left justified. Figure 1. DFN package marking information. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © Kionix 2007 13-Oct-08 Page 1 of 1 DFN Package Outline and Dimensions As a starting point, the following diagrams show the outline of the 5 x 5 DFN packages with dimensions and tolerances. All dimensions and tolerances conform to ASME Y14.5M-1994. All dimensions are in millimeters and angles are in degrees. Figure 2. 5 x 5 x 1.8 mm package outline diagram with dimensions. © Kionix 2008 13-Oct-08 Page 2 of 2 Dim. b D D2 E E2 e L Min 0.18 3.50 4.20 0.35 mm Nom 0.23 5.00 3.60 5.00 4.30 0.50 0.40 Figure 3. 5 x 5 x 1.2 mm package outline diagram with dimensions. DFN PCB Layout Recommendations Given the above package dimensions, the following guidelines are recommended: z 0.15 mm Min gap X N y M R Figure 4. Land pattern layout with package overlay © Kionix 2008 13-Oct-08 Page 3 of 3 Max 0.28 3.70 4.40 0.45 Nominal Package I/O Pad Dimensions (mm) Pad Pad Pad Pitch (e) Width (b) Length (L) 0.5 0.23 0.4 I/O Land Dimension Guidelines (mm) Land Width (X) 0.28 Nom Outward Extension (y) 0.15 Min Inward Extension (z) 0.05 Min The perimeter I/O lands are slightly larger on all sides than the package I/O pads. The outward extension (y) of the I/O lands can be increased beyond the 0.15 mm minimum, when PCB area is available. However, any increase in the inward extension (z) must consider the effect on the isolation gap to the center pad. This gap must not be less than 0.15 mm to avoid shorting. Nominal Package Center Pad Dimensions (mm) Pad Width Pad Length (D2) (E2) 5 x 5 x 1.8 5 x 5 x 1.2 3.6 3.6 3.6 4.3 Center Pad Land Dimension Guidelines (mm) Land Width Land Outward (M) Length (N) Extension (R) 3.6 3.6 0 - 0.15 Max 3.6 4.3 0 - 0.15 Max The center pad land should be designed 0 mm to 0.15 mm larger per side than the package’s exposed center pad. An example of a PCB land pad layout is shown in Figure 5. Figure 5. Example of a PCB land pad layout for the 5 x 5 x 1.8 mm DFN package. © Kionix 2008 13-Oct-08 Page 4 of 4 DFN Solder Stencil Guidelines A laser-cut, stainless steel stencil with electro-polished trapezoidal walls is recommended. Solder stencil thickness: 0.125mm Re-flowed solder joints on the PCB perimeter I/O lands should have about a 50 to 75 µm (2 to 3 mil) standoff height. To achieve this, the stencil aperture size-toland size should typically be a 1:1 ratio. To reduce solder paste volume on the center pad, it is recommended that an array of smaller apertures be used instead of one large aperture. The smaller apertures can be circular or square and of various dimensions and array sizes. The main goal should be a dimensional combination that results in a 40% - 80% solder paste coverage. This reduced coverage on the center pad is important in achieving good coverage without excessive standoff or bridging to the PCB perimeter I/O lands. An example layout is given in the following figure: Figure 6. Example of a 5 x 5 x 1.8 mm DFN solder stencil layout. © Kionix 2008 13-Oct-08 Page 5 of 5 Traces, Vias Vias are not needed for thermal dissipation, as our part doesn't generate much heat. Therefore, only electrical vias are needed. If vias are not in the land pads, capped, plugged, tented, un-capped or un-plugged vias can be used. To ensure optimal performance, vias and traces should not be placed on the top layer directly beneath the accelerometer. The following figures illustrate an example of proper PCB via and trace placement. Obviously, each product will present its own physical limitations for accelerometer placement and trace routing. Therefore, these guidelines are general in nature. Engineering judgment should be used to try to avoid placement directly beneath the accelerometer. Figure 7. Via and Trace “Keepout” (Top Vew) Figure 8. Via and Trace “Keepout” (Side View) © Kionix 2008 13-Oct-08 Page 6 of 6 Tape and Reel Dimensions The following section provides information on the tape and reel used for shipping Kionix’s 5 x 5 mm DFN accelerometers. Package DFN (5x5) Tape Width Component Pitch Hole Pitch Reel Diameter 16mm 8mm 4mm 330mm Figure 9. Dimensions of the reel © Kionix 2008 13-Oct-08 Page 7 of 7 © Kionix 2008 13-Oct-08 Page 8 of 8 Direction of feed Figure 10. Orientation of the parts in the carrier tape and direction of feed © Kionix 2008 13-Oct-08 Page 9 of 9 Revision History Rev - Date 09-Oct-08 Description of Change Initial release "Kionix" is a registered trademark of Kionix, Inc. Products described herein are protected by patents issued or pending. No license is granted by implication or otherwise under any patent or other rights of Kionix. The information contained herein is believed to be accurate and reliable but is not guaranteed. Kionix does not assume responsibility for its use or distribution. Kionix also reserves the right to change product specifications, application notes, and technical notes or discontinue any product at any time without prior notice. This publication supersedes and replaces all information previously supplied. © 2008 Kionix, Inc. – All rights reserved © Kionix 2008 13-Oct-08 Page 10 of 10