Data Sheet

333
-8
PSMN017-30LL
DF
N3
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
Rev. 4 — 12 December 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel MOSFET in DFN3333-8 package qualified to 150 °C. This product
is designed and qualified for use in a wide range of industrial, communications and power
supply equipment.
1.2 Features and benefits
 High efficiency due to low switching
and conduction losses
 Suitable for logic level gate drive
sources
 Small footprint for compact designs
1.3 Applications
 Battery protection
 Load switching
 DC-to-DC converters
 Power ORing
1.4 Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 150 °C
-
-
30
V
ID
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1
-
-
15
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
Tj
junction temperature
-
-
37
W
-55
-
150
°C
VGS = 4.5 V; ID = 5 A; Tj = 25 °C;
see Figure 12
-
20.5
25
mΩ
VGS = 10 V; ID = 5 A; Tj = 100 °C;
see Figure 13
-
-
23.4
mΩ
VGS = 10 V; ID = 5 A; Tj = 25 °C;
see Figure 12
-
15
17
mΩ
Static characteristics
RDSon
drain-source on-state resistance
PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
Table 1.
Quick reference data …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VGS = 10 V; ID = 5 A; VDS = 15 V;
see Figure 14; see Figure 17
-
1.5
-
nC
-
10
-
nC
VGS = 4.5 V; ID = 5 A; VDS = 15 V;
see Figure 17; see Figure 14
-
5
-
nC
VGS = 10 V; Tj(init) = 25 °C;
ID = 35 A; Vsup ≤ 30 V; unclamped;
RGS = 50 Ω
-
-
8
mJ
Dynamic characteristics
QGD
gate-drain charge
QG(tot)
total gate charge
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
2. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
Simplified outline
1
S
source
2
S
source
3
S
source
4
G
gate
5,6,7,8
D
mounting base; connected to drain
Graphic symbol
8 7 6 5
D
G
mbb076
S
1 2 3 4
Transparent
top view
SOT873-1 (DFN3333-8)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN017-30LL
DFN3333-8
plastic thermal enhanced very thin small outline package; no
leads; 8 terminals
SOT873-1
PSMN017-30LL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
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PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 150 °C
-
30
V
VDGR
drain-gate voltage
Tj ≤ 150 °C; Tj ≥ 25 °C; RGS = 20 kΩ
-
30
V
VGS
gate-source voltage
ID
drain current
-20
20
V
VGS = 10 V; Tmb = 100 °C; see Figure 1
-
15
A
VGS = 10 V; Tmb = 25 °C; see Figure 1
-
15
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C;
see Figure 3
-
140
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
37
W
Tstg
storage temperature
-55
150
°C
Tj
junction temperature
-55
150
°C
Tsld(M)
peak soldering temperature
-
260
°C
Source-drain diode
IS
source current
Tmb = 25 °C
-
18
A
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
-
140
A
VGS = 10 V; Tj(init) = 25 °C; ID = 35 A;
Vsup ≤ 30 V; unclamped; RGS = 50 Ω
-
8
mJ
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
EDS(AL)S
003aae257
40
ID
(A)
003aab937
120
Pder
(%)
30
80
20
(1)
40
10
0
0
Fig 1.
50
100
150
Continuous drain current as a function of
mounting base temperature
PSMN017-30LL
Product data sheet
0
200
Tmb (°C)
0
50
100
150
200
Tmb (°C)
Fig 2.
Normalized total power dissipation as a
function of solder point temperature
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Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
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PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
003aae405
103
ID
(A)
Limit RDSon = VDS / ID
102
tp =10 μ s
10
100 μ s
DC
1 ms
1
10 ms
100 ms
10-1
10-1
Fig 3.
1
10
102
V DS (V)
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN017-30LL
Product data sheet
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Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
4 of 15
PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-mb)
thermal resistance from junction to mounting base
see Figure 4
thermal resistance from junction to ambient
Rth(j-a)
[1]
[1]
Min
Typ
Max
Unit
-
3.6
8.4
K/W
-
57
60
K/W
Rth(j-a) is guaranteed by design and assumes that the device is mounted on a 40mm x 40mm x 70µm copper pad at 20°C ambient
temperature. In practice Rth(j-a) will be determined by the customer’s PCB characteristics
003aae259
10
Zth(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
0.05
10-1
δ=
P
0.02
tp
T
single shot
t
tp
T
10-2
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s )
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration; typical
values
PSMN017-30LL
Product data sheet
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Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
5 of 15
PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
6. Characteristics
Table 6.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source breakdown
voltage
ID = 0.25 mA; VGS = 0 V; Tj = -55 °C
27
-
-
V
ID = 0.25 mA; VGS = 0 V; Tj = 25 °C
30
-
-
V
VGS(th)
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 150 °C;
see Figure 10
0.5
-
-
V
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 11; see Figure 10
1.3
1.7
2.15
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 10
-
-
2.55
V
-
0.02
1
µA
IDSS
drain leakage current
VDS = 30 V; VGS = 0 V; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 125 °C
-
-
50
µA
IGSS
gate leakage current
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
5
100
nA
VGS = -20 V; VDS = 0 V; Tj = 25 °C
-
5
100
nA
VGS = 4.5 V; ID = 5 A; Tj = 25 °C;
see Figure 12
-
20.5
25
mΩ
VGS = 10 V; ID = 5 A; Tj = 100 °C;
see Figure 13
-
-
23.4
mΩ
VGS = 10 V; ID = 5 A; Tj = 150 °C;
see Figure 13
-
27
30.6
mΩ
VGS = 10 V; ID = 5 A; Tj = 25 °C;
see Figure 12
-
15
17
mΩ
-
1.23
-
Ω
ID = 5 A; VDS = 15 V; VGS = 10 V;
see Figure 14; see Figure 17
-
10
-
nC
ID = 5 A; VDS = 15 V; VGS = 4.5 V;
see Figure 17; see Figure 14
-
5
-
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
9
-
nC
ID = 5 A; VDS = 15 V; VGS = 10 V;
see Figure 14
-
1.8
-
nC
-
1
-
nC
-
0.8
-
nC
RDSon
RG
drain-source on-state
resistance
internal gate resistance (AC) f = 1 MHz
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGS(th)
pre-threshold gate-source
charge
QGS(th-pl)
post-threshold gate-source
charge
QGD
gate-drain charge
ID = 5 A; VDS = 15 V; VGS = 10 V;
see Figure 14; see Figure 17
-
1.5
-
nC
VGS(pl)
gate-source plateau voltage
VDS = 15 V; see Figure 14;
see Figure 17
-
2.7
-
V
Ciss
input capacitance
-
526
-
pF
Coss
output capacitance
VDS = 15 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 15
-
108
-
pF
Crss
reverse transfer capacitance
-
53
-
pF
PSMN017-30LL
Product data sheet
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Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
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PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
td(on)
turn-on delay time
-
13
-
ns
tr
rise time
VDS = 15 V; RL = 3 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω; Tj = 25 °C
-
12
-
ns
td(off)
turn-off delay time
-
18.3
-
ns
tf
fall time
-
5.8
-
ns
-
0.85
1.2
V
Source-drain diode
VSD
source-drain voltage
IS = 5 A; VGS = 0 V; Tj = 25 °C;
see Figure 16
trr
reverse recovery time
Qr
recovered charge
IS = 5 A; dIS/dt = 100 A/µs; VGS = 0 V;
VDS = 15 V
003aae263
1000
C
(pF)
Ciss
-
10
-
ns
-
17
-
nC
003aae266
60
RDSon
(mΩ)
750
45
Crss
500
30
250
15
0
0
0
Fig 5.
3
6
9
VGS (V)
12
Input and reverse transfer capacitances as a
function of gate-source voltage, typical values
PSMN017-30LL
Product data sheet
0
Fig 6.
5
10
15
VGS (V)
20
Drain-source on-state resistance as a function
of gate-source voltage; typical values
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Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
7 of 15
PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
003aae262
30
003aae260
20
10
4.5 4.0
3.5
ID
(A)
gfs
(S)
15
20
10
3.0
10
5
2.8
0
0
Fig 7.
VGS (V) = 2.6
0
5
10
15
20
I D (A)
Forward transconductance as a function of
drain current; typical values
003aae261
20
ID
(A)
0
Fig 8.
0.25
0.5
0.75
VDS(V)
1
Output characteristics: drain current as a
function of drain-source voltage; typical values
003aae453
3
VGS (th)
(V)
15
max
2
typ
10
min
Tj = 150 °C
Tj = 25 °C
1
5
0
0
1
2
3
VGS (V)
4
0
-60
0
60
120
Tj (°C)
180
ID = 1 mA; VDS = VGS
Fig 9.
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
PSMN017-30LL
Product data sheet
Fig 10. Gate-source threshold voltage as a function of
junction temperature
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Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
8 of 15
PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
003aab271
10-1
ID
(A)
10-2
003aae265
60
VGS (V) = 30
RDSon
(mΩ)
min
typ
3.5
40
max
10-3
4.0
4.5
10-4
20
10
10-5
10-6
0
1
2
VGS (V)
3
Fig 11. Sub-threshold drain current as a function of
gate-source voltage
0
0
5
10
15
I D (A)
20
Fig 12. Drain-source on-state resistance as a function
of drain current; typical values
03aa27
2
VDS
a
ID
1.5
VGS(pl)
VGS(th)
1
VGS
QGS1
0.5
QGS2
QGS
QGD
QG(tot)
003aaa508
0
−60
0
60
120
Tj (°C)
180
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
PSMN017-30LL
Product data sheet
Fig 14. Gate charge waveform definitions
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Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
9 of 15
PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
003aae264
103
003aae268
20
IS
(A)
Ciss
C
(pF)
15
102
10
Coss
Crss
Tj = 150 °C
Tj = 25 °C
5
10
10-1
1
10
VDS (V)
0
102
0
Fig 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
0.3
0.6
0.9
VSD (V)
1.2
Fig 16. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values
003aae267
10
VGS
(V)
24V
7.5
6V
VDS = 15V
5
2.5
0
0
3
6
9
QG (nC)
12
Fig 17. Gate-source voltage as a function of gate charge; typical values
PSMN017-30LL
Product data sheet
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Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
10 of 15
PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
7. Package outline
DFN3333-8: plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 3.3 x 3.3 x 1.0 mm
SOT873-1
X
B
D
A
E
terminal 1
index area
A
A1
c
detail X
terminal 1
index area
e1
C
v
w
b
e
1
M
M
y
y1 C
C A B
C
4
L1
Eh
L2
8
5
Dh
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
mm
1
A1
b
0.05 0.45
0.00 0.25
c
D
Dh
E
0.2
3.4
3.2
2.4
2.2
3.4
3.2
Eh
e
e1
L1
L2
1.80
0.55 0.52
0.65 1.95
1.58
0.45 0.35
v
w
y
y1
0.1
0.05
0.1
0.1
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT873-1
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
10-04-19
11-12-01
Fig 18. Package outline SOT873-1 (DFN3333-8)
PSMN017-30LL
Product data sheet
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Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
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PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN017-30LL v.4
20111212
Product data sheet
-
PSMN017-30LL v.3
-
PSMN017-30LL v.2
Modifications:
PSMN017-30LL v.3
PSMN017-30LL
Product data sheet
•
Various changes to content.
20100707
Product data sheet
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Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
12 of 15
PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
9. Legal information
9.1
Data sheet status
Document status [1] [2]
Product status [3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
9.3
Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
PSMN017-30LL
Product data sheet
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
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malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
13 of 15
PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
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products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
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applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
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the product is not suitable for automotive use. It is neither qualified nor tested
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Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PSMN017-30LL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
14 of 15
PSMN017-30LL
NXP Semiconductors
N-channel DFN3333-8 30 V 17 mΩ logic level MOSFET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . .12
Legal information. . . . . . . . . . . . . . . . . . . . . . . .13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Contact information. . . . . . . . . . . . . . . . . . . . . .14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 December 2011
Document identifier: PSMN017-30LL