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STA321MP
Scalable digital microphone processor
Datasheet - production data
Description
TQFP - 64
10 mm x 10 mm
VFQFPN - 56
8 mm x 8 mm
Features
 8 digital processing channels each 24-bit
– 6 channels of PDM input
– 2 additional virtual channels
 >100 dB SNR and dynamic range
 Digital gain/attenuation +58 dB to -100 dB in
0.5 dB steps
 Soft volume update
 Individual channel and master level control
 Up to 10 independent 32-bit userprogrammable biquads (EQ) per channel
 Bass/treble tone control
 Pre- and post-EQ full 8-channel input mix on all
8 channels
 Dual independent limiters/compressors
 Dynamic range compression or anti-clipping
modes
 Individual channel and master soft/hard mute
The STA321MP is a PDM high-performance
multichannel processor with ultra-low quiescent
current designed for general-purpose digital
microphone applications. The device is fully
digital and is comprised of three main sections.
The first section is the PDM input interface which
can accept up to six serial digital inputs. The
second section is a high-quality audio processor
allowing flexible channel mixing/muxing and
provides up to 10 biquads for general sound
equalization and voice enhancement with
independent volume control. The last block is the
I²S output interface which streams out the
processed digital audio. The output interface can
also be programmed for flexible channel
mapping. The device offers some of the most
commonly required audio enhancements such as
programmable voice tuning and equalization,
limiter/compressor for improved voice quality,
multiband selection for customizable microphone
usage and configurable wind-noise rejection. The
embedded digital processor allows offloading the
microphone processing from the main CPU or
SoC, moving it to the device.
The STA321MP has six digital microphone inputs,
providing connections for up to three dualmembrane microphones.
 3 I²S data outputs
 I²S data output channel mapping function
 Independent channel volume and DSP bypass
 Channel mapping of any input to any
processing channel
Applications
Table 1. Device summary
Order code
Package
Packaging
STA321MPLTR
TQFP64
Tape and reel
STA321MPL
TQFP64
Tray
STA321MPTR
VFQFPN56
Tape and reel
STA321MP
VFQFPN56
Tray
 Tablets
 Gaming
 Audio conference sets
 Legacy microphone-equipped devices
September 2013
This is information on a product in full production.
DocID022647 Rev 5
1/84
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84
Contents
STA321MP
Contents
1
2
3
4
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Microphone interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
PDM clock generator (for microphones) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
PDM resampling interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
PDM recombination (dual-membrane microphone support) . . . . . . . . . . 15
3.4
Low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5
Sensitivity adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6
Normal channel attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7
Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
I2C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
4.1.1
Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.2
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.3
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4
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Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1
Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.2
Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.1
Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.2
Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.3
Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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4.4.4
5
Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.1
Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.2
Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 26
5.2.3
Configuration register D (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.4
Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.5
Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.6
Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.7
Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.8
Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2.9
Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.10
Master volume register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.11
Channel 1 volume (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.12
Channel 2 volume (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.13
Channel 3 volume (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.14
Channel 4 volume (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.15
Channel 5 volume (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.16
Channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.17
Channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.18
Channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.19
Channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 35
5.2.20
Channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 35
5.2.21
Channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 35
5.2.22
Channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 36
5.2.23
Channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 36
5.2.24
Channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 36
5.2.25
Channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 36
5.2.26
Channel 8 volume trim, mute, bypass (0x1A) . . . . . . . . . . . . . . . . . . . . 36
5.2.27
Fine volume (FineVol) (0x5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.28
Channel input mapping channels 1 and 2 (0x1B) . . . . . . . . . . . . . . . . . 38
5.2.29
Channel input mapping channels 3 and 4 (0x1C) . . . . . . . . . . . . . . . . . 38
5.2.30
Channel input mapping channels 5 and 6 (0x1D) . . . . . . . . . . . . . . . . . 38
5.2.31
Channel input mapping channels 7 and 8 (0x1E) . . . . . . . . . . . . . . . . . 38
5.2.32
AGEQ - graphic EQ 80-Hz band (0x23) . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.33
BGEQ - graphic EQ 300-Hz band (0x24) . . . . . . . . . . . . . . . . . . . . . . . 39
DocID022647 Rev 5
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Contents
STA321MP
5.3
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5.2.34
CGEQ - graphic EQ 1-kHz band (0x25) . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.35
DGEQ - graphic EQ 3-kHz band (0x26) . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.36
EGEQ - graphic EQ 8-kHz band (0x27) . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2.37
Biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 40
5.2.38
Mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.39
EQ bypass (0x2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.40
Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.41
Tone control (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2.42
Channel limiter select channels 1, 2, 3, 4 (0x2D) . . . . . . . . . . . . . . . . . 42
5.2.43
Channel limiter select channels 5, 6, 7, 8 (0x2E) . . . . . . . . . . . . . . . . . 42
5.2.44
Limiter 1 attack/release rate (0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2.45
Limiter 1 attack/release threshold (0x30) . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.46
Limiter 2 attack/release rate (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.47
Limiter 2 attack/release threshold (0x32) . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.48
Limiter description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.49
Channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2.50
Channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2.51
Channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2.52
Channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2.53
Coefficient address register 1 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2.54
Coefficient address register 2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2.55
Coefficient b1 data register, bits 23:16 (0x3D) . . . . . . . . . . . . . . . . . . . . 48
5.2.56
Coefficient b1 data register, bits 15:8 (0x3E) . . . . . . . . . . . . . . . . . . . . . 49
5.2.57
Coefficient b1 data register, bits 7:0 (0x3F) . . . . . . . . . . . . . . . . . . . . . . 49
5.2.58
Coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 49
5.2.59
Coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 49
5.2.60
Coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 49
5.2.61
Coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 49
5.2.62
Coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 49
5.2.63
Coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 50
5.2.64
Coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 50
5.2.65
Coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 50
5.2.66
Coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 50
5.2.67
Coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 50
5.2.68
Coefficient b0 data register, bits 15:8 (0x4A) . . . . . . . . . . . . . . . . . . . . . 50
5.2.69
Coefficient b0 data register, bits 7:0 (0x4B) . . . . . . . . . . . . . . . . . . . . . . 50
5.2.70
Coefficient write control register (0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . 51
Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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5.4
Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.5
Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.6
Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Configuration registers (0x77; 0x78; 0x79) . . . . . . . . . . . . . . . . . . . . . . 54
6.1
Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.2
Variable max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.2.1
6.3
Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.1
6.4
6.5
7
MPCC1-2 (0x4D, 0x4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DCC1-2 (0x4F, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PSCorrect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.4.1
PSC1-2: ripple correction value (RCV) (0x51, 0x52) . . . . . . . . . . . . . . . 59
6.4.2
PSC3: correction normalization value (CNV) (0x53) . . . . . . . . . . . . . . . 59
PDM and recombination IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.5.1
Mike recombination RAM BIST (0x5C) . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.5.2
Recombination control register 1 (0x5D) . . . . . . . . . . . . . . . . . . . . . . . . 60
6.5.3
PDM control register (0x5E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.5.4
Recombination control register 2, 3 and 4 (0x5F; 0x60; 0x61) . . . . . . . 61
6.5.5
Recombination control register 5, 6 and 7 (0x62; 0x63; 0x64) . . . . . . . 63
6.5.6
Recombination control register 8, 9 and 10 (0x65; 0x66; 0x67) . . . . . . 65
6.5.7
Recombination control register 11, 12 and 13 (0x68; 0x69; 0x6A) . . . . 66
6.5.8
Zero-mute threshold/hysteresis and RMS zero-mute selectors (0x6F) . 67
6.5.9
RMS post-processing selectors and Fs autodetection (0x70) . . . . . . . . 69
6.5.10
Clock manager configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5.11
RMS level registers (0x7A, 0x7B, 0x7C, 0x7D) . . . . . . . . . . . . . . . . . . . 72
Startup/shutdown pop noise removal . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.1
DPT: PWM and tristate delay (0x80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.2
Configuration register (0x81) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.3
User-defined delay time (0x82) and (0x83) . . . . . . . . . . . . . . . . . . . . . . . 76
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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List of tables
STA321MP
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
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Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description STA321MPL (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin description: STA321MP (VFQFPN56) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General interface electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC electrical characteristics: 3.3-V buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Modes for PDM resampling interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial audio output formats according to sampling rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
RAM block for biquads, mixing, and bass management. . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Gain adjustment (sensitivity). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Normal channel attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
RMS channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Zero-detect threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Zero-detect hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RMS post-processing channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
VFQFPN56 (8 x 8 mm) package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Exposed pad variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
DocID022647 Rev 5
STA321MP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Channel signal flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connections STA321MPL - TQFP64 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin connections STA321MP - VFQFPN56 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PDM clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PDM recombination block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Biquad filter structure with quantization error noise shaping . . . . . . . . . . . . . . . . . . . . . . . 58
Channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
TQFP64 (10 x 10 mm) package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
VFQFPN56 (8 x 8 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
DocID022647 Rev 5
7/84
Device overview
STA321MP
1
Device overview
1.1
Block diagram
Figure 1. Block diagram
SA SCL SDA
XTI
CKOUT
O U T1 A /B
I2C
PLL
O U T2 A /B
O U T3 A /B
FFX
SYSTEM
CONTROL
SYSTEM
TIMING
O U T4 A /B
O U T5 A /B
O U T6 A /B
OVERSAMPLING
O U T7 A /B
LRCKO
PDM1
PDM2
PDM3
PDM4
PDM5
PDM6
B IC K O
SERIAL
DATA
IN
CHANNEL
MAPPING
TREBLE
BASS,EQ
(BIQUADS)
VOLUME
LIMITING
Figure 2. Channel signal flow
8/84
DocID022647 Rev 5
SERIAL
DATA
OUT
SDO 12
SDO 34
SDO 56
SDO 78
STA321MP
1.2
Device overview
Pin description
Figure 3. Pin connections STA321MPL - TQFP64 (top view)
DocID022647 Rev 5
9/84
Device overview
STA321MP
Table 2. Pin description STA321MPL (TQFP64)
Pin number
Type
Name
1
5-V tolerant TTL input buffer
PDM_CLK
PDM I/F CLK
6
5-V tolerant TTL input buffer
PDMIN_6
PDM input channel 6
7
5-V tolerant TTL input buffer
PDMIN_5
PDM input channel 5
8
5-V tolerant TTL input buffer
PDMIN_4
PDM input channel 4
9
5-V tolerant TTL input buffer
PDMIN_3
PDM input channel 3
10
5-V tolerant TTL input buffer
PDMIN_2
PDM input channel 2
11
5-V tolerant TTL input buffer
PDMIN_1
PDM input channel 1
15
5-V tolerant TTL Schmitt trigger input buffer
RESETN
Global reset
16
CMOS input buffer with pull-down
PLLB
Bypass phase-locked loop
17
1.8-V CMOS input buffer with pull-down
SA
Select address (I2C)
18
Bidirectional buffer: 5-V tolerant TTL Schmitt
trigger input; 3.3-V capable 2 mA slew-rate
controlled output
SDA
Serial data (I2C)
19
5-V tolerant TTL Schmitt trigger input buffer
SCL
Serial clock (I2C)
20
5-V tolerant TTL Schmitt trigger input buffer
XTI
Crystal oscillator input (clock input)
N.C.
Not connected
GND
PLL ground
21
10/84
Description
23
Analog ground
25
3.3-V capable TTL tristate 4 mA output buffer CKOUT
Clock output
29
3.3-V capable TTL 2 mA output buffer
OUT8B
PWM channel 8 output B
30
3.3-V capable TTL 2 mA output buffer
OUT8A
PWM channel 8 output A
31
3.3-V capable TTL 2 mA output buffer
OUT7B
PWM channel 7 output B
32
3.3-V capable TTL 2 mA output buffer
OUT7A
PWM channel 7 output A
33
3.3-V capable TTL 2 mA output buffer
OUT6B
PWM channel 6 output B
34
3.3-V capable TTL 2 mA output buffer
OUT6A
PWM channel 6 output A
38
3.3-V capable TTL 2 mA output buffer
OUT5B
PWM channel 5 output B
39
3.3-V capable TTL 2 mA output buffer
OUT5A
PWM channel 5 output A
40
3.3-V capable TTL 2 mA output buffer
OUT4B
PWM channel 4 output B
41
3.3-V capable TTL 2 mA output buffer
OUT4A
PWM channel 4 output A
42
3.3-V capable TTL 2 mA output buffer
OUT3B
PWM channel 3 output B
43
3.3-V capable TTL 2 mA output buffer
OUT3A
PWM channel 3 output A
47
3.3-V capable TTL 2 mA output buffer
OUT2B
PWM channel 2 output B
48
3.3-V capable TTL 2 mA output buffer
OUT2A
PWM channel 2 output A
49
3.3-V capable TTL 2 mA output buffer
OUT1B
PWM channel 1 output B
50
3.3-V capable TTL 2 mA output buffer
OUT1A
PWM channel 1 output A
51
3.3-V capable TTL 4 mA output buffer
EAPD
Ext. amp power-down
DocID022647 Rev 5
STA321MP
Device overview
Table 2. Pin description STA321MPL (TQFP64) (continued)
Pin number
Type
Name
Description
55
3.3-V capable TTL 2 mA output buffer
BICKO
Output serial clock
56
3.3-V capable TTL 2 mA output buffer
LRCKO
Output left/right clock
57
3.3-V capable TTL 2 mA output buffer
SDO_12
Output serial data channels 1 & 2
58
3.3-V capable TTL 2 mA output buffer
SDO_34
Output serial data channels 3 & 4
62
3.3-V capable TTL 2 mA output buffer
SDO_56
Output serial data channels 5 & 6
63
3.3-V capable TTL 2 mA output buffer
SDO_78
Output serial data channels 7 & 8
64
5-V tolerant TTL Schmitt trigger input buffer
PWDN
Device power-down
3.3-V digital supply voltage
VDD
3.3-V supply
2,4,13, 27,36,
Digital ground
45,53,60
GND
Ground
14,21,22,26,
37, 46, 54,61
NC
3,12,24,
28,35,
44,52,59
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Not connected
11/84
Device overview
STA321MP
Figure 4. Pin connections STA321MP - VFQFPN56 (top view)
Table 3. Pin description: STA321MP (VFQFPN56)
Pin number
1
Type
Name
5-V tolerant TTL input buffer
2
PDM_CLK
PDM I/F CLK
RES
Reserved connect to GND
5
5-V tolerant TTL input buffer
PDMIN_6
PDM input channel 6
6
5-V tolerant TTL input buffer
PDMIN_5
PDM input channel 5
7
5-V tolerant TTL input buffer
PDMIN_4
PDM input channel 4
8
5-V tolerant TTL input buffer
PDMIN_3
PDM input channel 3
9
5-V tolerant TTL input buffer
PDMIN_2
PDM input channel 2
10
5-V tolerant TTL input buffer
PDMIN_1
PDM input channel 1
13
5-V tolerant TTL Schmitt trigger input buffer
RESETN
Global reset
RES
Reserved connect to GND
SA
Select address (I2C)
14
15
12/84
Description
1.8-V CMOS input buffer with pull-down
DocID022647 Rev 5
STA321MP
Device overview
Table 3. Pin description: STA321MP (VFQFPN56) (continued)
Pin number
Type
Name
Description
16
Bidirectional buffer: 5-V tolerant TTL Schmitt
trigger input; 3.3-V capable 2 mA slew-rate
controlled output
SDA
Serial data (I2C)
17
5-V tolerant TTL Schmitt trigger input buffer
SCL
Serial clock (I2C)
18
5-V tolerant TTL Schmitt trigger input buffer
XTI
Crystal oscillator input (clock input)
N.C.
Not connected
19
20
Analog ground
GNDA
PLL ground
22
3.3-V capable TTL tristate 4 mA output buffer
CKOUT
Clock output
25
3.3-V capable TTL 2 mA output buffer
OUT8B
PWM channel 8 output B
26
3.3-V capable TTL 2 mA output buffer
OUT8A
PWM channel 8 output A
27
3.3-V capable TTL 2 mA output buffer
OUT7B
PWM channel 7 output B
28
3.3-V capable TTL 2 mA output buffer
OUT7A
PWM channel 7 output A
29
3.3-V capable TTL 2 mA output buffer
OUT6B
PWM channel 6 output B
30
3.3-V capable TTL 2 mA output buffer
OUT6A
PWM channel 6 output A
33
3.3-V capable TTL 2 mA output buffer
OUT5B
PWM channel 5 output B
34
3.3-V capable TTL 2 mA output buffer
OUT5A
PWM channel 5 output A
35
3.3-V capable TTL 2 mA output buffer
OUT4B
PWM channel 4 output B
36
3.3-V capable TTL 2 mA output buffer
OUT4A
PWM channel 4 output A
37
3.3-V capable TTL 2 mA output buffer
OUT3B
PWM channel 3 output B
38
3.3-V capable TTL 2 mA output buffer
OUT3A
PWM channel 3 output A
41
3.3-V capable TTL 2 mA output buffer
OUT2B
PWM channel 2 output B
42
3.3-V capable TTL 2 mA output buffer
OUT2A
PWM channel 2 output A
43
3.3-V capable TTL 2 mA output buffer
OUT1B
PWM channel 1 output B
44
3.3-V capable TTL 2 mA output buffer
OUT1A
PWM channel 1 output A
45
3.3-V capable TTL 4 mA output buffer
EAPD
Ext. amp power-down
48
3.3-V capable TTL 2 mA output buffer
BICKO
Output serial clock
49
3.3-V capable TTL 2 mA output buffer
LRCKO
Output left/right clock
50
3.3-V capable TTL 2 mA output buffer
SDO_12
Output serial data channels 1 & 2
51
3.3-V capable TTL 2 mA output buffer
SDO_34
Output serial data channels 3 & 4
54
3.3-V capable TTL 2 mA output buffer
SDO_56
Output serial data channels 5 & 6
55
3.3-V capable TTL 2 mA output buffer
SDO_78
Output serial data channels 7 & 8
56
5-V tolerant TTL Schmitt trigger input buffer
PWDN
Device power-down
3,11,21,24,
31,39,46,52
3.3-V digital supply voltage
VDD
3.3-V supply
4,12,23,32,
40,47,53
Digital ground
GND
Ground
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Electrical characteristics
STA321MP
2
Electrical characteristics
2.1
Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol
2.2
Parameter
Min
Typ
Max
Unit
VDD
3.3-V I/O power supply
-0.5
4
V
VSA
Voltage on SA pin 15 (pin 17 in TQFP-64)
-0.5
2
V
Vi
Voltage on input pins
-0.5
VDD + 0.5 V
Vo
Voltage on output pins
-0.5
VDD + 0.3 V
Tstg
Storage temperature
-40
150
°C
Tamb
Ambient operating temperature
-40
90
°C
Thermal data
Table 5. Thermal data
Symbol
Rthj-amb
2.3
Parameter
Min
Thermal resistance, junction to ambient
Typ
Max
85
Unit
°C/W
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol
14/84
Parameter
Min
Typ
Max
VDD
I/O power supply
3.0
3.3
3.6
VSA
Voltage on SA pin 15 (STA321MP),
pin 17 (STA321MPL)
1.55
1.8
1.95
Tj
Operating junction temperature
-40
25
125
DocID022647 Rev 5
Unit
V
°C
STA321MP
2.4
Electrical characteristics
Electrical specifications
The following specifications are valid for VDD = 3.3 V ± 0.3 V, VSA = 0 V and Tamb = 25 °C,
unless otherwise stated.
Table 7. General interface electrical specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Iil
Low-level input, no pull-up
Vi = 0 V
1
µA
Iih
High-level input, no pull-down
Vi = VDD
2
µA
IOZ
Tristate output leakage without
pull-up/down
Vi = VDD
2
µA
Vesd
Electrostatic protection
(human body model)
Leakage < 1 µA
2000
V
Table 8. DC electrical characteristics: 3.3-V buffers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.8
V
VIL
Low-level input voltage
VIH
High-level input voltage
VILhyst
Low-level threshold
Input falling
0.8
1.35
V
VIHhyst
High-level threshold
Input rising
1.3
2.0
V
Vhyst
Schmitt trigger hysteresis
0.3
0.8
V
Vol
Low-level output
0.2
V
Voh
High-level output
Idd
2.0
V
IoI = 100 µA
Ioh = -100 µA
VDD0.2
V
Ioh = -2 mA
2.4
V
Reset conditions
15
Normal conditions with CKOUT
60
Quiescent current
mA
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Microphone interface
STA321MP
3
Microphone interface
3.1
PDM clock generator (for microphones)
In order to correctly start up the device in the microphone processor mode, it is necessary to
set registers 0x00 to 0x9B and register 0x5D to 0x01.
The CKOUT pin can be used to properly provide a clock source for digital microphones.
When the mikemode bit is asserted (reg 0x5D bit 0), the CKOUT generator is automatically
configured in order to generate a clock with sys_clk/32 frequency (corresponding to a PDM
oversampling rate of 64).
For example, considering a base sample frequency of:
Fs = 44.1 kHz
XTI = 11.289 MHz (user provided)
System clock = 90.3168 MHz (system generated)
Clock out = 2.8224 MHz (system generated)
Fs = 48.0 kHz
XTI = 12.288 MHz (user provided)
System clock= 98.304 MHz (system generated)
Clock out = 3.072 MHz (system generated)
Technical details
The clock generator creates two output clocks with the same frequency, CKOUT270
has a 270 degrees phase shift with respect to CKOUT. One is exported outside the device
and used to clock the microphones, the other is used internally to clock the PDM interface of
the STA321MP.
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STA321MP
Microphone interface
Figure 5. PDM clock generator
STA321MPL
CLK Generator
PDM Selector
CLKOUT
Dual Microphone 1
CLK
DataOut
CLKOUT_270
PDM_IC_CLK
PDM_1
PDM_1
PDM_2
PDM_2
PDM_3
PDM_3
PDM_4
PDM_4
PDM_5
PDM_5
PDM_6
PDM_6
D/S
0
Dual Microphone 2
CLK
DataOut
D/S
0
Dual Microphone 3
CLK
3.2
DataOut
D/S
0
PDM resampling interface
The PDM resampling interface is used to properly sample external data.
It can work in three different modes: Compatibility mode, Dual-membrane and Advanced. In
each mode data are sampled at the rising or falling edge.
Table 9. Modes for PDM resampling interface
Mode
Behavior
00
Compatibility (old)
01
Reserved
10
Dual-membrane
11
Advanced
Compatibility mode
In this mode every channel is sampled at the rising edge.
Dual-membrane mode
The dual-membrane mode is a particular configuration (automatically applied when the
proper bit is asserted) which permits the use of the dual-membrane microphone. In
particular it has 2 PDM data channels (normal and high) muxed in a single wire. The normal
channel is sampled at the falling edge, while the high channel is sampled at the rising edge.
Advanced mode
In this mode every channel can be sampled at the rising or falling edge according to the
configuration register.
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Microphone interface
3.3
STA321MP
PDM recombination (dual-membrane microphone support)
Dual microphone scenario:
A dual-membrane microphone has two separate PDM signal paths:

Normal channel for moderate SPL (Sound Pressure Level) acoustic signals

High channel for high SPL acoustic signals
The sensitivity of the high channel is configurable and is set by default to 20 dBSPL lower
than the sensitivity of the normal channel in order to avoid saturation in any part of the signal
path.
The two channels can be combined together in order to enlarge the dynamic range and
have a good trade-off between the DNR and the noise floor (which is lower in the case of the
normal channel).
The main functionality is based on a signal level measurement and a dual-threshold system.
If the signal of the normal channel is:

above the upper threshold (TH_H), the output will be taken from the high channel

under the lower threshold (TH_N), the output will be taken from the normal channel

between TH_H and TH_N, the output will be a combination of the high and normal
channels.
Figure 6. PDM recombination block diagram
Mike_N
Low Pass
Norm_Atten
Level Meter
Sens_Adj
Mike Recomb output
TH_H
TH_N
Recombination Engine
Mike_H
Low Pass
3.4
Low-pass filter
A filter is provided (and needed) in order to suppress the noise outside the audio band that
may be still present before the recombination stage.
The filter is a 2nd order IIR (Infinite Impulse Response) low-pass with a cutoff frequency of
20 kHz and it can be bypassed through the I2C bit.
Configuration registers: 0x62(6), 0x63(6), 0x64(6)
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STA321MP
3.5
Microphone interface
Sensitivity adjustment
The sensitivity adjustment control can be used to compensate the differences between the
theoretical and the real sensitivity. It is applied to all the membranes of the microphone.
Sensitivity adjustment = [-4, 3.875) with a 0.125 dB step
Configuration registers: 0x5F(5-0), 0x60(5-0), 0x61(5-0)
3.6
Normal channel attenuation
The NORM_Att is a parameter must be set to the sensitivity difference between the High
SPL channel and the Normal SPL channel. By default its value is set to 20 dB.
Configuration registers: 0x52(5-0), 0x63(5-0), 0x64(5-0)
3.7
Thresholds
The two thresholds can be configured in order to control/select the recombination engine
behavior. In particular they can be used to give more weight (in the final output) to the
Normal Channel or to the High Channel which will lead to choose the trade-off between
having lower distortion (High Channel) or lower noise floor (Normal Channel).
Configuration registers: 0x65(5-0), 0x66(5-0), 0x67(5-0), 0x68(5-0), 0x69(5-0), 0x6A(5-0)
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I2C bus operation
4
STA321MP
I2C bus operation
The STA321MP supports the I2C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master).
This protocol defines any device that sends data on to the bus as a transmitter and any
device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA321MP is always a slave device in all of its communications.
4.1
Communication protocol
4.1.1
Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. An SDA
transition while the clock is high is used to identify a START or STOP condition.
4.1.2
Start condition
START is identified by a high-to-low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
4.1.3
Stop condition
STOP is identified by a low-to-high transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A STOP condition terminates communication between
the STA321MP and the bus master.
4.1.4
Data input
During the data input the STA321MP samples the SDA signal on the rising edge of clock
SCL.
For correct device operation the SDA signal must be stable during the rising edge of the
clock and the data can change only when the SCL line is low.
4.2
Device addressing
To start communication between the master and the Omega FFX core, the master must
initiate with a start condition. Following this, the master sends 8 bits onto the SDA line (MSB
first) corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus
definition. In the STA321MP the I2C interface has two device addresses depending on the
SA port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0
for write mode. After a START condition the STA321MP identifies on the bus the device
20/84
DocID022647 Rev 5
I2C bus operation
STA321MP
address and if a match is found, it acknowledges the identification on SDA bus during the
9th-bit time. The byte following the device identification byte is the internal space address.
4.3
Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA321MP acknowledges this and the writes for the byte of internal address.
After receiving the internal byte address the STA321MP again responds with an
acknowledgement.
4.3.1
Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the Omega
FFX core. The master then terminates the transfer by generating a STOP condition.
4.3.2
Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Figure 7. Write mode sequence
ACK
DEV-ADDR
BYTE
WRITE
ACK
SUB-ADDR
RW
START
STOP
ACK
MULTIBYTE
WRITE
DEV-ADDR
START
ACK
DATA IN
ACK
SUB-ADDR
ACK
DATA IN
ACK
DATA IN
STOP
RW
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I2C bus operation
STA321MP
4.4
Read operation
4.4.1
Current address byte read
Following the START condition, the master sends a device select code with the RW bit set
to 1. The STA321MP acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
4.4.2
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA321MP. The master acknowledges each data
byte read and then generates a STOP condition, terminating the transfer.
4.4.3
Random address byte read
Following the START condition, the master sends a device select code with the RW bit set
to 0. The STA321MP acknowledges this and then the master writes the internal address
byte. After receiving the internal byte address, the STA321MP again responds with an
acknowledgement. The master then initiates another START condition and sends the device
select code with the RW bit set to 1. The STA321MP acknowledges this and then responds
by sending one byte of data. The master then terminates the transfer by generating a STOP
condition.
4.4.4
Random address multi-byte read
The multi-byte read mode can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA321MP. The master acknowledges each data
byte read and then generates a STOP condition, terminating the transfer.
Figure 8. Read mode sequence
ACK
CURRENT
ADDRESS
READ
DEV-ADDR
NO ACK
DATA
RW
START
STOP
ACK
RANDOM
ADDRESS
READ
DEV-ADDR
ACK
SUB-ADDR
RW
RW= ACK
HIGH
START
SEQUENTIAL
CURRENT
READ
ACK
DEV-ADDR
DEV-ADDR
S TAR T
NO ACK
DATA
RW
ACK
STOP
ACK
DATA
DATA
NO ACK
DATA
STOP
START
ACK
SEQUENTIAL
RANDOM
READ
DEV-ADDR
START
22/84
ACK
ACK
SUB-ADDR
RW
DEV-ADDR
S TAR T
ACK
DATA
RW
DocID022647 Rev 5
ACK
DATA
NO ACK
DATA
STOP
STA321MP
Registers
5
Registers
5.1
Register summary
Table 10. Register summary
Addr
Name
D7
D6
D5
D4
COS1
COS0
DSPB
IR1
SAOD4
D3
D2
D1
D0
IR0
MCS2
MCS1
MCS0
SAOFB
SAO3
SAO2
SAO1
SAO0
Configuration
0x00
CONFA
0x01
0x02
ConfC
0x03
ConfD
MPC
CSZ4
CSZ3
CSZ2
CSZ1
CSZ0
OM1
OM0
0x04
ConfE
C8BO
C7BO
C6BO
C5BO
C4BO
C3BO
C2BO
C1BO
0x05
ConfF
PWMS2 PWMS1 PWMS0 BQL
PSL
DEMP
DRC
HPB
0x06
ConfG
MPCV
DCCV
HPE
AM2E
AME
COD
SID
PWMD
0x07
ConfH
ECLE
LDTE
BCLE
IDE
ZDE
SVE
ZCE
NSBW
0x08
ConfI
EAPD
PSCE
Volume control
0x09
MMUTE
MMUTE
0x0A
Mvol
MV7
MV6
MV5
MV4
MV3
MV2
MV1
MV0
0x0B
C1Vol
C1V7
C1V6
C1V5
C1V4
C1V3
C1V2
C1V1
C1V0
0x0C
C2Vol
C2V7
C2V6
C2V5
C2V4
C2V3
C2V2
C2V1
C2V0
0x0D
C3Vol
C3V7
C3V6
C3V5
C3V4
C3V3
C3V2
C3V1
C3V0
0x0E
C4Vol
C4V7
C4V6
C4V5
C4V4
C4V3
C4V2
C4V1
C4V0
0x0F
C5Vol
C5V7
C5V6
C5V5
C5V4
C5V3
C5V2
C5V1
C5V0
0x10
C6Vol
C6V7
C6V6
C6V5
C6V4
C6V3
C6V2
C6V1
C6V0
0x11
C7Vol
C7V7
C7V6
C7V5
C7V4
C7V3
C7V2
C7V1
C7V0
0x12
C8Vol
C8V7
C8V6
C8V5
C8V4
C8V3
C8V2
C8V1
C8V0
0x13
C1VTMB C1M
C1VBP
C1VT4
C1VT3
C1VT2
C1VT1
C1VT0
0x14
C2VTMB C2M
C2VBP
C2VT4
C2VT3
C2VT2
C2VT1
C2VT0
0x15
C3VTMB C3M
C3VBP
C3VT4
C3VT3
C3VT2
C3VT1
C3VT0
0x16
C4VTMB C4M
C4VBP
C4VT4
C4VT3
C4VT2
C4VT1
C4VT0
0x17
C5VTMB C5M
C5VBP
C5VT4
C5VT3
C5VT2
C5VT1
C5VT0
0x18
C6VTMB C6M
C6VBP
C6VT4
C6VT3
C6VT2
C6VT1
C6VT0
0x19
C7VTMB C7M
C7VBP
C7VT4
C7VT3
C7VT2
C7VT1
C7VT0
0x1A
C8VTMB C8M
C8VBP
C8VT4
C8VT3
C8VT2
C8VT1
C8VT0
DocID022647 Rev 5
23/84
Registers
STA321MP
Table 10. Register summary (continued)
Addr
Name
D7
D6
D5
D4
D3
D2
D1
D0
Input mapping
0x1B
C12im
C2IM2
C2IM1
C2IM0
C1IM2
C1IM1
C1IM0
0x1C
C34im
C4IM2
C4IM1
C4IM0
C3IM2
C3IM1
C3IM0
0x1D
C56im
C6IM2
C6IM1
C6IM0
C5IM2
C5IM1
C5IM0
0x1E
C78im
C8IM2
C8IM1
C8IM0
C7IM2
C7IM1
C7IM0
C7BLP
C6BLP
C5BLP
C3BLP
C2BLP
C1BLP
Processing loop
0x28
BQlp
C8BLP
C4BLP
0x29
MXlp
C8MXLP C7MXLP C6MXLP C5MXLP C4MXLP C3MXLP C2MXLP C1MXLP
Processing bypass
0x2A
EQbp
C8EQBP C7EQBP C6EQBP C5EQB
0x2B
ToneBP C8TCB
C4EQBP C3EQBP C2EQBP C1EQBP
C7TCB
C6TCB
C5TCB
C4TCB
C3TCB
C2TCB
C1TCB
TTC2
TTC1
TTC0
BTC3
BTC2
BTC1
BTC0
Tone control
0x2C
Tone
TTC3
Dynamics control
0x2D
C1234ls C4LS1
C4LS0
C3LS1
C3LS0
C2LS1
C2LS0
C1LS1
C1LS0
0x2E
C5678ls C8LS1
C8LS0
C7LS1
C7LS0
C6LS1
C6LS0
C5LS1
C5LS0
0x2F
L1ar
L1A3
L1A2
L1A1
L1A0
L1R3
L1R2
L1R1
L1R0
0x30
L1atrt
L1AT3
L1AT2
L1AT1
L1AT0
L1RT3
L1RT2
L1RT1
L1RT0
0x31
L2ar
L2A3
L2A2
L2A1
L2A0
L2R3
L2R2
L2R1
L2R0
0x32
L2atrt
L2AT3
L2AT2
L2AT1
L2AT0
L2RT3
L2RT2
L2RT1
L2RT0
PWM output timing
0x33
C12ot
C2OT2
C2OT1
C2OT0
C1OT2
C1OT1
C1OT0
0x34
C34ot
C4OT2
C4OT1
C4OT0
C3OT2
C3OT1
C3OT0
0x35
C56ot
C6OT2
C6OT1
C6OT0
C5OT2
C5OT1
C5OT0
0x36
C78ot
C8OT2
C8OT1
C8OT0
C7OT2
C7OT1
C7OT0
I²S output channel mapping
24/84
0x37
C12om
C2OM2
C2OM1
C2OM0
C1OM2
C1OM1
C1OM0
0x38
C34om
C4OM2
C4OM1
C4OM0
C3OM2
C3OM1
C3OM0
0x39
C56om
C6OM2
C6OM1
C6OM0
C5OM2
C5OM1
C5OM0
0x3A
C78om
C8OM2
C8OM1
C8OM0
C7OM2
C7OM1
C7OM0
DocID022647 Rev 5
STA321MP
Registers
Table 10. Register summary (continued)
Addr
Name
D7
D6
D5
D4
D3
D2
D1
D0
User-defined coefficient RAM
0x3B
Cfaddr1
CFA9
CFA8
0x3C
Cfaddr2 CFA7
CFA6
CFA5
CFA4
CFA3
CFA2
CFA1
CFA0
0x3D
B1cf1
C1B23
C1B22
C1B21
C1B20
C1B19
C1B18
C1B17
C1B16
0x3E
B1cf2
C1B15
C1B14
C1B13
C1B12
C1B11
C1B10
C1B9
C1B8
0x3F
B1cf3
C1B7
C1B6
C1B5
C1B4
C1B3
C1B2
C1B1
C1B0
0x40
B2cf1
C2B23
C2B22
C2B21
C2B20
C2B19
C2B18
C2B17
C2B16
0x41
B2cf2
C2B15
C2B14
C2B13
C2B12
C2B11
C2B10
C2B9
C2B8
0x42
B2cf3
C2B7
C2B6
C2B5
C2B4
C2B3
C2B2
C2B1
C2B0
0x43
A1cf1
C3B23
C3B22
C3B21
C3B20
C3B19
C3B18
C3B17
C3B16
0x44
A1cf2
C3B15
C3B14
C3B13
C3B12
C3B11
C3B10
C3B9
C3B8
0x45
A1cf3
C3B7
C3B6
C3B5
C3B4
C3B3
C3B2
C3B1
C3B0
0x46
A2cf1
C4B23
C4B22
C4B21
C4B20
C4B19
C4B18
C4B17
C4B16
0x47
A2cf2
C4B15
C4B14
C4B13
C4B12
C4B11
C4B10
C4B9
C4B8
0x48
A2cf3
C4B7
C4B6
C4B5
C4B4
C4B3
C4B2
C4B1
C4B0
0x49
B0cf1
C5B23
C5B22
C5B21
C5B20
C5B19
C5B18
C5B17
C5B16
0x4A
B0cf2
C5B15
C5B14
C5B13
C5B12
C5B11
C5B10
C5B9
C5B8
0x4B
B0cf3
C5B7
C5B6
C5B5
C5B4
C5B3
C5B2
C5B1
C5B0
0x4C
Cfud
WA
W1
0x4D
MPCC1
MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9
MPCC8
0x4E
MPCC2
MPCC7
MPCC6
MPCC5
MPCC4
MPCC3
MPCC2
MPCC1
MPCC0
0x4F
DCC1
DCC15
DCC14
DCC13
DCC12
DCC11
DCC10
DCC9
DCC8
0x50
DCC2
DCC7
DCC6
DCC5
DCC4
DCC3
DCC2
DCC1
DCC0
0x51
PSC1
RCV11
RCV10
RCV9
RCV8
RCV7
RCV6
RCV5
RCV4
0x52
PSC2
RCV3
RCV2
RCV1
RCV0
CNV11
CNV10
CNV9
CNV8
0x53
PSC3
CNV7
CNV6
CNV5
CNV4
CNV3
CNV2
CNV1
CNV0
0x57
BACT
R8BACT R7BACT R6BACT R5BACT R4BACT R3BACT R2BACT R1BCAT
0x58
BEND
R8BEND R7BEND R6BEND
0x59
BBAD
R8BBAD R7BBAD R6BBAD R5BBAD R4BBAD R3BBAD R2BBAD R1BBAD
0x5A
L12new
0x5B
FineVol
BIST
R5BEND
R4BEND R3BEND R2BEND R1BEND
NLENAR
CFINE8 CFINE7 CFINE6 CFINE5
DocID022647 Rev 5
CFINE4 CFINE3 CFINE2 CFINE1
25/84
Registers
STA321MP
Table 10. Register summary (continued)
Addr
Name
D7
D6
D5
D4
D3
D2
D1
D0
PDM and recombination IP interface
0x5C
MRBist
MHFail
MHBad
MHEnd
0x5D
RCTR1
Boost6db
0x5E
PDMCT AdvM6
AdvM5
0x5F
RCTR2
bypRM1
CH1GG[5:0]
0x60
RCTR3
bypRM2
CH2GG[5:0]
0x61
RCTR4
bypRM3
CH3GG[5:0]
0x62
RCTR5
LP1en
CH1NCA[5:0]
0x63
RCTR6
LP2en
CH2NCA[5:0]
0x64
RCTR7
LP3en
CH3NCA[5:0]
0x65
RCTR8
CH1TH_N[5:0]
0x66
RCTR9
CH2TH_N[5:0]
0x67
RCTR10
CH3TH_N[5:0]
0x68
RCTR11
CH1TH_H[5:0]
0x69
RCTR12
CH2TH_H[5:0]
0x6A
RCTR13
CH3TH_H[5:0]
AdvM4
MHAct
MNFail
MNBad
MNEnd
MNAct
I²S_byp
I²S_en
mike_en mike_byp m_mode
AdvM3
AdvM2
AdvM1
PDMSM[1:0]
Clock manager configuration/status registers
0x71
pllfrac1
PLFI15
PLFI14
PLFI13
PLFI12
PLFI11
PLFI10
PLFI9
PLFI8
0x72
pllfrac0
PLFI7
PLFI6
PLFI5
PLFI4
PLFI3
PLFI2
PLFI1
PLFI0
0x73
pll div
PLLDD1 PLLDD0 PLLND5 PLLND4
0x74
pll conf0 PDPDC PLLFC
0x75
pll conf1
PLLBYP PLLDPR LOWEN BST32K
0x76
pll stat
PLLBYS PLLPDS OSCOK LOWCKS
PLLND3 PLLND2 PLLND1 PLLND0
PLSTRB PLSTBB PLIFD3
PLIFD2
PLIFD1
PLIFD0
Biquad configuration
0x77
CBQ1
EBQ3_1 EBQ3_0 EBQ2_1 EBQ2_0
EBQ1_1 EBQ1_0 EBQ0_0 EBQ0_0
0x78
CBQ2
EBQ7_1 EBQ7_0 EBQ6_1 EBQ6_0
EBQ5_1 EBQ5_0 EBQ4_0 EBQ4_0
0x79
CBQ3
nshen
EBQ9_1 EBQ9_0 EBQ8_0 EBQ8_0
RMS status registers
0x7A
rmsZMH RZM15
RZM14
RZM13
RZM12
RZM11
RZM10
RZM9
RZM8
0X7B
rmsZML RZM7
RZM6
RZM5
RZM4
RZM3
RZM2
RZM1
RZM0
0X7C
rmsPOH RPO15
RPO14
RPO13
RPO12
RPO11
RPO10
RPO9
RPO8
0X7D
rmsPOL RPO7
RPO6
RPO5
RPO4
RPO3
RPO2
RPO1
RPO0
DPT4
DPT3
DPT2
DPT1
DPT0
RL0
RD
SID1
FBYP
RTP
Tristate startup/shutdown pop removal signals
26/84
0x80
DPT
0x81
CFR129 RL3
0x82
TSDLY1 UDDT15 UDDT14 UDDT13 UDDT12 UDDT11 UDDT10 UDDT9
UDDT8
0x83
TSDLY2 UDDT7
UDDT0
RL2
UDDT6
RL1
UDDT5
UDDT4
DocID022647 Rev 5
UDDT3
UDDT2
UDDT1
STA321MP
Registers
5.2
Register description
5.2.1
Configuration register A (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
COS1
COS0
DSPB
IR1
IR0
MCS2
MCS1
MCS0
1
0
0
1
1
0
1
1
Bit
RW
RST
Name
0
RW
1
MCS0
1
RW
1
MCS1
2
RW
0
MCS2
Description
Master clock select: selects the ratio between the
input sampling frequency (PDM I/FCLK)and the
input clock (XTI).
 The internal clock depends on the external clock freq. provided to the XTI pin. It can be
either 90.3168 MHz or 98.304 MHz in case of XTI is respectively 11.2896MHz or
12.288MHz.
 The relationship between the input clock XTI and the PDM interface clock is determined
by both the MCSn and the IRn (input rate) register bits. IR[1,0] = 11 sets the PDM
interface enable and MCS[2:0]=011 means XTI=4*PDM interface clock.
If XTI input is not used, related pin must be tied to GND.
MCS[2:0]
Input sampling rate
IR
fs (kHz)
XTI
11
1xx
011
010
001
000
2*PDM_CK
4*PDM_CK
6*PDM_CK
8*PDM_CK
12*PDM_CK
Interpolation ratio select
Bit
RW
RST
Name
0
RW
0
DSPB
Description
DSP bypass bit:
0: normal operation
1: bypass of biquad and bass/treble functions
Setting the DSPB bit bypasses the biquad function of the FFX core.
DocID022647 Rev 5
27/84
Registers
STA321MP
COS [1,0]
CKOUT frequency
00
PLL output
01
PLL output / 4
10
PLL output / 8
11
PLL output / 16
cos [1,0] sets the clock out value; clock out frequency is a ratio of the internal clock, such
ratio depends on the cos[1,0] setting.
Example cos[1,0] =10:
XTI = 12.288
PLL output = 98.304 MHz
CK_out = 98.304 / 8 = 12.288
Clock out is automatically configured in order to obtain a frequency of 64 Fs (sys_clock/32)
if the bit0 of the register 0x5D is asserted. This generates a valid clock to be provided to a
digital (PDM) microphone.
28/84
DocID022647 Rev 5
STA321MP
5.2.2
Registers
Configuration register C (0x02) - serial output formats
D7
D6
D5
D4
D3
D2
D1
D0
SAOD4
SAOFB
SAO3
SAO2
SAIO
SAO0
0
0
0
0
0
0
Bit
RW
RST
Name
0
RW
0
SAO0
1
RW
0
SAO1
2
RW
0
SAO2
3
RW
0
SAO3
Description
Serial audio output interface format: determines the
interface format of the output serial digital audio
interface.
The STA321MP features a serial audio output interface that consists of 8 channels. The
serial audio output always acts as a slave to the serial audio input interface and, therefore,
all output clocks are synchronous with the input clocks. The output sampling frequency (fs)
is also equivalent to the input sampling frequency. In the case of PDM input, the serial audio
output acts as a master with an output sampling frequency of 8 xfs, 4 xfs or fs depending on
SAOD4 bit. The output serial format can be selected independently from the input format
and is done via the SAO and SAOFB bits.
Bit
RW
RST
Name
4
RW
0
SAOFB
Bit
RW
RST
Name
Description
SAOD4
Enables decimation by 4 on SAO interface for PDM
input; no effect for others.
0: div by 1
1: div by 4 (1)
5
RW
0
Description
Determines MSB or LSB first for all SAO formats:
0: MSB first
1: LSB first
1. To avoid any aliasing on SAO streaming, a low-pass filter is needed to be implemented in one of the
available user-programmable biquads.
DocID022647 Rev 5
29/84
Registers
STA321MP
Table 11. Serial audio output formats according to sampling rate
BICKO
SAO[3:0]
Interface data format
0111
I²S data
1111
Left/right-justified 16-bit data
1110
I²S data
0001
Left-justified data
1010
Right-justified 24-bit data
1011
Right-justified 20-bit data
1100
Right-justified 18-bit data
1101
Right-justified 16-bit data
0000
I²S data
0001
Left-justified data
0010
Right-justified 24-bit data
0011
Right-justified 20-bit data
0100
Right-justified 18-bit data
0101
Right-justified 16-bit data
32 * fs
48 * fs
64 * fs
30/84
DocID022647 Rev 5
STA321MP
5.2.3
Registers
Configuration register D (0x03)
D7
D6
D5
D4
D3
D2
D1
D0
MPC
CSZ4
CSZ3
CSZ2
CSZ1
CSZ0
OM1
OM0
1
1
1
1
1
1
1
0
Bit
RW
RST
Name
0
RW
0
OM0
1
RW
1
OM1
Description
FFX power output mode: selects configuration of
FFX output
The FFX power output mode selects how the FFX output timing is configured. Different
power devices use different output modes.
Bit
RW
RST
Name
2
RW
1
CSZ0
3
RW
1
CSZ1
4
RW
1
CSZ2
5
RW
1
CSZ3
6
RW
1
CSZ4
CSZ[4:0]
Description
Contra size register: when OM[1,0] = 11, this register
determines the size of the FFX compensating pulse
from 0 clock ticks to 31 clock periods
Compensating pulse size
00000
0 clock period compensating pulse size
00001
1 clock period compensating pulse size
…
11111
…
31 clock period compensating pulse size
DocID022647 Rev 5
31/84
Registers
5.2.4
STA321MP
Configuration register E (0x04)
D7
D6
D5
D4
D3
D2
D1
D0
C8BO
C7BO
C6BO
C5BO
C4BO
C3BO
C2BO
C1BO
0
0
0
0
0
0
0
0
Bit
RW
RST
Name
0
RW
0
C1BO
1
RW
0
C2BO
2
RW
0
C3BO
3
RW
0
C4BO
4
RW
0
C5BO
5
RW
0
C6BO
6
RW
0
C7BO
7
RW
0
C8BO
Description
Channels 1, 2, 3, 4, 5, 6, 7, and 8 binary output mode
enable bits. A setting of 0 indicates ordinary FFX
tristate output. A setting of 1 indicates binary output
mode.
Each individual channel output can be set to output a binary PWM stream. In this mode
output A of a channel will be considered the positive output and output B is the negative
inverse.
5.2.5
Configuration register F (0x05)
D7
D6
D5
D4
D3
D2
D1
D0
PWMS2
PWMS1
PWMS0
BQL
PSL
DEMP
DRC
HPB
0
0
0
0
0
0
0
0
Bit
RW
RST
Name
0
RW
0
HPB
Description
High-pass filter bypass bit: setting of one bypasses
internal AC coupling digital high-pass filter
The STA321MP features an internal digital high-pass filter for the purpose of AC coupling.
The purpose of this filter is to prevent DC signals from passing through an FFX amplifier. DC
signals can cause speaker damage.
If HPB = 1, then the filter that the high-pass filter utilizes is made available as userprogrammable biquad #1.
Bit
RW
RST
Name
1
RW
0
DRC
Description
Dynamic range compression/anti-clipping
0: limiters act in anti-clipping mode
1: limiters act in dynamic range compression mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression.
When used in anti-clipping mode, the limiter threshold values are constant and dependent
on the limiter settings.
32/84
DocID022647 Rev 5
STA321MP
Registers
In dynamic range compression mode, the limiter threshold values vary with the volume
settings allowing a nighttime listening mode that provides a reduction in the dynamic range
regardless of the volume level.
Bit
RW
RST
Name
2
RW
0
DEMP
Description
De-emphasis:
0: no de-emphasis
1: de-emphasis
By setting this bit to one de-emphasis will be implemented on all channels. When this is
used it takes the place of biquad #7 in each channel and any coefficients using biquad #1
will be ignored. The DSPB (DSP bypass) bit must be set to 0 for de-emphasis to function.
Bit
RW
RST
Name
3
RW
0
PSL
Description
Post-scale link:
0: each channel uses individual post-scale value
1: each channel uses channel 1 post-scale value
Post-scale functionality can be used for power-supply error correction. For multi-channel
applications running off the same power-supply, the post-scale values can be linked to the
value of channel 1 for ease of use and in order to update the values faster.
Bit
RW
RST
Name
4
RW
0
BQL
Description
Biquad link:
0: each channel uses coefficient values
1: each channel uses channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the channel 1
coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to
be performed once.
Bit
RW
RST
Name
7:5
RW
00
PWMS[2:0]
PWMS[1:0]
Description
PWM speed selection
PWM output speed
000
Normal speed (384 kHz) (all channels)
001
Half-speed (192 kHz) (all channels)
010
Double-speed (768 kHz) (all channels)
011
Normal speed (channels 1-6), double-speed (channels 7-8)
100
Odd speed (341.3 kHz) (all channels)
DocID022647 Rev 5
33/84
Registers
5.2.6
STA321MP
Configuration register G (0x06)
D7
D6
D5
D4
D3
D2
D1
D0
MPCV
DCCV
HPE
AM2E
AME
COD
SID
PWMD
0
0
0
0
0
0
0
0
Bit
RW
RST
Name
0
RW
0
PWMD
1
RW
0
SID
Serial interface (I²S out) disable:
0: I²S output normal
1: no I²S output
2
RW
0
COD
Clock output disable:
0: clock output normal
1: no clock output
Bit
RW
RST
Name
3
RW
0
AME
Description
PWM output disable:
0: PWM output normal
1: no PWM output
Description
AM mode enable:
0: normal FFX operation
1: AM reduction mode FFX operation
The STA321MP features an FFX processing mode that minimizes the amount of noise
generated in the frequency range of AM radio. This mode is intended for use when FFX is
operating in a device with an active AM tuner. The SNR of the FFX processing is reduced to
~83 dB in this mode, which is still greater than the SNR of AM radio.
Bit
RW
RST
Name
4
RW
0
AM2E
Description
AM2 mode enable:
0: normal FFX operation
1: AM2 reduction mode FFX operation
The STA321MP features two FFX processing modes that minimize the amount of noise
generated in the frequency range of AM radio. This second mode is intended for use when
FFX is operating in a device with an active AM tuner. This mode eliminates the noiseshaper.
Bit
RW
RST
Name
5
RW
0
HPE
Description
FFX headphone enable:
0: channels 7 and 8 normal FFX operation
1: channels 7 and 8 headphone operation
Channels 7 and 8 can be configured to be processed and output in such a manner that
headphones can be driven using an appropriate output device. This signal is a differential
3-wire drive called FFX headphone.
34/84
DocID022647 Rev 5
STA321MP
5.2.7
Registers
Bit
RW
RST
Name
6
RW
0
DCCV
Bit
RW
RST
Name
7
RW
0
MPCV
Description
Distortion compensation variable enable:
0: uses the preset DC coefficient
1: uses the DCC coefficient
Description
Max power correction variable:
0: uses the standard MPC coefficient
1: uses the MPCC bits for the MPC coefficient
Configuration register H (0x07)
D7
D6
D5
D4
D3
D2
D1
D0
ECLE
LDTE
BCLE
IDE
ZDE
SVE
ZCE
NSBW
0
1
1
1
1
1
1
0
Bit
RW
RST
Name
Description
0
RW
0
NSBW
Noise-shaper bandwidth selection:
1: 3rd order NS
0: 4th order NS
Bit
RW
RST
Name
Description
1
RW
1
ZCE
Zero-crossing volume enable:
1: volume adjustments will only occur at digital zerocrossings
0: volume adjustments will occur immediately
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital
zero-crossings, no clicks will be audible.
Bit
RW
RST
Name
2
RW
1
SVE
Bit
RW
RST
Name
3
RW
1
ZDE
Description
Soft volume enable:
1: volume adjustments use soft volume
0: volume adjustments occur immediately
Description
Zero-detect mute enable: setting of 1 enables the
automatic zero-detect mute
Setting the ZDE bit enables the zero-detect automatic mute. See Section 6.5.8 for more
details.
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35/84
Registers
STA321MP
Bit
RW
RST
Name
4
RW
1
IDE
Description
Invalid input detect mute enable:
1: enable the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I²S data and will
automatically mute if the signals are perceived as invalid.
Bit
RW
RST
Name
5
RW
1
BCLE
Description
Binary output mode clock loss detection enable
The BCLE bit detects loss of input MCLK in binary mode and will output 50% duty cycle.
Bit
RW
RST
Name
6
RW
1
LDTE
Description
LRCLK double trigger protection enable
The LDTE bit actively prevents double triggering of LRCLK.
Bit
RW
RST
Name
7
RW
0
ECLE
Description
Auto EAPD on clock loss
When active, the ECLE bit will issue a device power-down signal (EAPD) on clock loss
detection.
5.2.8
Configuration register I (0x08)
D7
D6
D5
D4
D3
D2
D1
D0
EAPD
PSCE
0
0
This feature utilizes an ADC on SDI78 that provides power supply ripple information for
correction. Registers PSC1, PSC2, PSC3 are utilized in this mode.
36/84
Bit
RW
RST
Name
0
RW
0
PSCE
Bit
RW
RST
Name
7
RW
0
EAPD
Description
Power supply ripple correction enable:
0: normal operation
1: PSCorrect operation
Description
External amplifier power-down:
0: external power stage power-down active
1: normal operation
DocID022647 Rev 5
STA321MP
5.2.9
Registers
Master mute register (0x09)
D7
D6
D5
D4
D3
D2
D1
D0
MMUTE
0
5.2.10
Master volume register (0x0A)
D7
D6
D5
D4
D3
D2
D1
D0
MV7
MV6
MV5
MV4
MV3
MV2
MV1
MV0
1
1
1
1
1
1
1
1
Note:
The value of the volume derived from MVOL is dependent on the AMV AutoMode volume
settings.
5.2.11
Channel 1 volume (0x0B)
5.2.12
5.2.13
5.2.14
D7
D6
D5
D4
D3
D2
D1
D0
C1V7
C1V6
C1V5
C1V4
C1V3
C1V2
C1V1
C1V0
0
1
1
0
0
0
0
0
Channel 2 volume (0x0C)
D7
D6
D5
D4
D3
D2
D1
D0
C2V7
C2V6
C2V5
C2V4
C2V3
C2V2
C2V1
C2V0
0
1
1
0
0
0
0
0
Channel 3 volume (0x0D)
D7
D6
D5
D4
D3
D2
D1
D0
C3V7
C3V6
C3V5
C3V4
C3V3
C3V2
C3V1
C3V0
0
1
1
0
0
0
0
0
Channel 4 volume (0x0E)
D7
D6
D5
D4
D3
D2
D1
D0
C4V7
C4V6
C4V5
C4V4
C4V3
C4V2
C4V1
C4V0
0
1
1
0
0
0
0
0
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Registers
5.2.15
5.2.16
5.2.17
5.2.18
5.2.19
5.2.20
5.2.21
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STA321MP
Channel 5 volume (0x0F)
D7
D6
D5
D4
D3
D2
D1
D0
C5V7
C5V6
C5V5
C5V4
C5V3
C5V2
C5V1
C5V0
0
1
1
0
0
0
0
0
Channel 6 volume (0x10)
D7
D6
D5
D4
D3
D2
D1
D0
C6V7
C6V6
C6V5
C6V4
C6V3
C6V2
C6V1
C6V0
0
1
1
0
0
0
0
0
Channel 7 volume (0x11)
D7
D6
D5
D4
D3
D2
D1
D0
C7V7
C7V6
C7V5
C7V4
C7V3
C7V2
C7V1
C7V0
0
1
1
0
0
0
0
0
Channel 8 volume (0x12)
D7
D6
D5
D4
D3
D2
D1
D0
C8V7
C8V6
C8V5
C8V4
C8V3
C8V2
C8V1
C8V0
0
1
1
0
0
0
0
0
Channel 1 volume trim, mute, bypass (0x13)
D7
D6
C1M
C1VBP
0
0
D5
0
D4
D3
D2
D1
D0
C1VT4
C1VT3
C1VT2
C1VT1
C1VT0
1
0
0
0
0
Channel 2 volume trim, mute, bypass (0x14)
D7
D6
C2M
C2VBP
0
0
D5
0
D4
D3
D2
D1
D0
C2VT4
C2VT3
C2VT2
C2VT1
C2VT0
1
0
0
0
0
Channel 3 volume trim, mute, bypass (0x15)
D7
D6
C3M
C3VBP
0
0
D5
0
D4
D3
D2
D1
D0
C3VT4
C3VT3
C3VT2
C3VT1
C3VT0
1
0
0
0
0
DocID022647 Rev 5
STA321MP
5.2.22
5.2.23
5.2.24
5.2.25
5.2.26
5.2.27
Registers
Channel 4 volume trim, mute, bypass (0x16)
D7
D6
C4M
C4VBP
0
0
D5
D4
D3
D2
D1
D0
C4VT4
C4VT3
C4VT2
C4VT1
C4VT0
1
0
0
0
0
0
Channel 5 volume trim, mute, bypass (0x17)
D7
D6
C5M
C5VBP
0
0
D5
D4
D3
D2
D1
D0
C5VT4
C5VT3
C5VT2
C5VT1
C5VT0
1
0
0
0
0
0
Channel 6 volume trim, mute, bypass (0x18)
D7
D6
C6M
C6VBP
0
0
D5
D4
D3
D2
D1
D0
C6VT4
C6VT3
C6VT2
C6VT1
C6VT0
1
0
0
0
0
0
Channel 7 volume trim, mute, bypass (0x19)
D7
D6
C7M
C7VBP
0
0
D5
D4
D3
D2
D1
D0
C7VT4
C7VT3
C7VT2
C7VT1
C7VT0
1
0
0
0
0
0
Channel 8 volume trim, mute, bypass (0x1A)
D7
D6
C8M
C8VBP
0
0
D5
D4
D3
D2
D1
D0
C8VT4
C8VT3
C8VT2
C8VT1
C8VT0
1
0
0
0
0
0
Fine volume (FineVol) (0x5B)
D7
D6
D5
D4
D3
D2
D1
D0
CFINE8
CFINE7
CFINE6
CFINE5
CFINE4
CFINE3
CFINE2
CFINE1
0
0
0
0
0
0
0
0
Bit
0-7
RW
RW
RST
0
Name
CFINEx
Description
Set for each channel a fine volume of -0.25dB,
this value has to be added to the whole volume.
0: fine vol off
1: fine vol on
DocID022647 Rev 5
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Registers
STA321MP
The volume structure of the STA321MP consists of individual volume registers for each
channel and a master volume register that provides an offset to each channel’s volume
setting. There is also an additional offset for each channel called channel volume trim. The
individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -78 dB. As an
example if C5V = 0xXX or +XXX dB and MV = 0xXX or -XX dB, then the total gain for
channel 5 = XX dB. The channel volume trim is adjustable independently on each channel
from -10 dB to +10 dB in 1 dB steps. A fine volume configuration register could be used to
offset at 0.25 dB step each channel.
The master mute when set to 1 will mute all channels at once, whereas the individual
channel mutes (CnM) will mute only that channel. Both the master mute and the channel
mutes provide a "soft mute" with the volume ramping down to mute in 8192 samples from
the maximum volume setting at the internal processing rate (~192 kHz). A "hard mute" can
be obtained by commanding a value of 0xFF (255) to any channel volume register or the
master volume register. When volume offsets are provided via the master volume register
any channel whose total volume is less than -91 dB will be muted. All changes in volume
take place at zero-crossings when ZCE = 1 (configuration register H) on a per-channel basis
as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates
occur immediately. Each channel also contains an individual channel volume bypass. If a
particular channel has volume bypassed via the CnVBP = 1 register, then only the channel
volume setting for that particular channel affects the volume setting, the master volume
setting will not affect that channel. Each channel also contains a channel mute. If CnM = 1,
a soft mute is performed on that channel.
MV[7:0]
Volume offset from channel value
0x00
0 dB
0x01
-0.5 dB
0x02
-1 dB
…
…
0x4C
-38 dB
…
…
0xFE
-127 dB
0xFF
Hardware channel mute
CnV[7:0]
40/84
Volume
0x00
+48 dB
0x01
+47.5 dB
0x02
+47 dB
…
…
0x5F
+0.5 dB
0x60
0 dB
0x61
-0.5 dB
…
…
0xFE
-79.5 dB
0xFF
Hardware channel mute
DocID022647 Rev 5
STA321MP
Registers
CnVT[4:0]
5.2.28
0x00 to 0x06
+10 dB
0x07
+9 dB
…
…
0x0F
+1 dB
0x10
0 dB
0x11
-1 dB
…
…
0x19
-9 dB
0x1A to 0x1F
-10 dB
Channel input mapping channels 1 and 2 (0x1B)
D7
5.2.29
D5
D4
C2IM2
C2IM1
0
0
D3
D2
D1
D0
C2IM0
C1IM2
C1IM1
C1IM0
1
0
0
0
D2
D1
D0
D6
D5
D4
D3
C4IM2
C4IM1
C4IM0
C3IM2
C3IM1
C3IM0
0
1
1
0
1
0
D2
D1
D0
Channel input mapping channels 5 and 6 (0x1D)
D7
5.2.31
D6
Channel input mapping channels 3 and 4 (0x1C)
D7
5.2.30
Volume
D6
D5
D4
D3
C6IM2
C6IM1
C6IM0
C5IM2
C5IM1
C5IM0
1
0
1
1
0
0
D2
D1
D0
Channel input mapping channels 7 and 8 (0x1E)
D7
D6
D5
D4
D3
C8IM2
C8M1
C8IM0
C7IM2
C7IM1
C7IM0
1
1
1
1
1
0
Each channel received via I²S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing, simplifies output
stage designs, and enables the ability to perform crossovers. The default settings of these
registers map each I²S input channel to its corresponding processing channel.
DocID022647 Rev 5
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Registers
STA321MP
CnIM[2:0]
5.2.32
000
Channel 1
001
Channel 2
010
Channel 3
011
Channel 4
100
Channel 5
101
Channel 6
110
Channel 7
111
Channel 8
AGEQ - graphic EQ 80-Hz band (0x23)
D7
5.2.33
D4
D3
D2
D1
D0
AGEQ4
AGEQ3
AGEQ2
AGEQ1
AGEQ0
0
1
1
1
1
D6
D5
D4
D3
D2
D1
D0
BGEQ4
BGEQ3
BGEQ2
BGEQ1
BGEQ0
0
1
1
1
1
D6
D5
D4
D3
D2
D1
D0
CGEQ4
CGEQ3
CGEQ2
CGEQ1
CGEQ0
0
1
1
1
1
D4
D3
D2
D1
D0
DGEQ4
DGEQ3
DGEQ2
DGEQ1
DGEQ0
0
1
1
1
1
DGEQ - graphic EQ 3-kHz band (0x26)
D7
42/84
D5
CGEQ - graphic EQ 1-kHz band (0x25)
D7
5.2.35
D6
BGEQ - graphic EQ 300-Hz band (0x24)
D7
5.2.34
Serial input from
D6
D5
DocID022647 Rev 5
STA321MP
5.2.36
Registers
EGEQ - graphic EQ 8-kHz band (0x27)
D7
D6
D5
D4
D3
D2
D1
D0
EGEQ4
EGEQ3
EGEQ2
EGEQ1
EGEQ0
0
1
1
1
1
xGEQ[4:0]
5.2.37
Boost / cut
11111
+16
11110
+15
11101
+14
…
…
10000
+1
01111
0
01110
-1
…
…
00001
-14
00000
-15
Biquad internal channel loop-through (0x28)
D7
D6
D5
D4
D3
D2
D1
D0
C8BLP
C7BLP
C6BLP
C5BLP
C4BLP
C3BLP
C2BLP
C1BLP
0
0
0
0
0
0
0
0
Each internal processing channel can receive two possible inputs at the input to the biquad
block. The input can come either from the output of that channel’s MIX#1 engine or from the
output of the bass/treble (biquad #10) of the previous channel. In this scenario, channel 1
receives channel 8. This enables the use of more than 10 biquads on any given channel at
the loss of the number of separate internal processing channels.
Bit
7:0
RW
RW
RST
0
Name
CnBLP
Description
For n = 1 to 8:
0: input from channel n MIX#1 engine output - normal
operation
1: input from channel (n - 1) biquad #10 output - loop
operation.
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Registers
5.2.38
STA321MP
Mix internal channel loop-through (0x29)
D7
D6
D5
D4
D3
D2
D1
D0
C8MXLP
C7MXLP
C6MXLP
C5MXLP
C4MXLP
C3MXLP
C2MXLP
C1MXLP
0
0
0
0
0
0
0
0
Each internal processing channel can receive two possible sets of inputs at the input to the
Mix#1 block. The inputs can come from the outputs of the interpolation block as normally
occurs (CnMXLP = 0) or they can come from the outputs of the Mix#2 block. This enables
the use of additional filtering after the second mix block at the expense of losing this
processing capability on the channel.
Bit
RW
7:0
5.2.39
RW
RST
0
Name
Description
CnMXLP
For n = 1 to 8:
0: inputs to channel n MIX#1 engine from interpolation
outputs - normal operation
1: inputs to channel n MIX#1 engine from MIX#2 engine
outputs - loop operation
EQ bypass (0x2A)
D7
D6
D5
D4
D3
D2
D1
D0
C8EQBP
C7EQBP
C6EQBP
C5EQBP
C4EQCBP
C3EQBP
C2EQBP
C1EQBP
0
0
0
0
0
0
0
0
EQ control can be bypassed on a per-channel basis. If EQ control is bypassed on a given
channel, the prescale and all 10 filters (high-pass, biquads, de-emphasis, bass
management cross-over, bass, treble in any combination) are bypassed for that channel.
5.2.40
Bit
RW
RST
Name
7:0
RW
0
CnEQBP
Description
For n = 1 to 8:
0: perform EQ on channel n - normal operation
1: bypass EQ on channel n
Tone control bypass (0x2B)
D7
D6
D5
D4
D3
D2
D1
D0
C8TCB
C7TCB
C6TCB
C5TCB
C4TCB
C3TCB
C2TCB
C1TCB
0
0
0
0
0
0
0
0
Tone control (bass/treble) can be bypassed on a per-channel basis. If tone control is
bypassed on a given channel, the two filters that tone control utilizes are made available as
user-programmable biquads #9 and #10.
44/84
DocID022647 Rev 5
STA321MP
5.2.41
Registers
Tone control (0x2C)
D7
D6
D5
D4
D3
D2
D1
D0
TTC3
TTC2
TTC1
TTC0
BTC3
BTC2
BTC1
BTC0
0
1
1
1
0
1
1
1
This is the tone control boost / cut as a function of the BTC and TTC bits.
BTC[3:0] / TTC[3:0)
5.2.42
5.2.43
5.2.44
Boost / cut
0000
-12 dB
0001
-12 dB
…
…
0111
-4 dB
0110
-2 dB
0111
0 dB
1000
+2 dB
1001
+4 dB
…
…
1101
+12 dB
1110
+12 dB
1111
+12dB
Channel limiter select channels 1, 2, 3, 4 (0x2D)
D7
D6
D5
D4
D3
D2
D1
D0
C4LS1
C4LS0
C3LS1
C3LS0
C2LS1
C2LS0
C1LS1
C1LS0
0
0
0
0
0
0
0
0
Channel limiter select channels 5, 6, 7, 8 (0x2E)
D7
D6
D5
D4
D3
D2
D1
D0
C8LS1
C8LS0
C7LS1
C7LS0
C6LS1
C6LS0
C5LS1
C5LS0
0
0
0
0
0
0
0
0
Limiter 1 attack/release rate (0x2F)
D7
D6
D5
D4
D3
D2
D1
D0
L1A3
L1A2
L1A1
L1A0
L1R3
L1R2
L1R1
L1R0
0
1
1
0
1
0
1
0
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45/84
Registers
5.2.45
5.2.46
5.2.47
5.2.48
STA321MP
Limiter 1 attack/release threshold (0x30)
D7
D6
D5
D4
D3
D2
D1
D0
L1AT3
L1AT2
L1AT1
L1AT0
L1RT3
L1RT2
L1RT1
L1RT0
0
1
1
0
1
0
0
1
Limiter 2 attack/release rate (0x31)
D7
D6
D5
D4
D3
D2
D1
D0
L2A3
L2A2
L2A1
L2A0
L2R3
L2R2
L2R1
L2R0
0
1
1
0
1
0
1
0
Limiter 2 attack/release threshold (0x32)
D7
D6
D5
D4
D3
D2
D1
D0
L2AT3
L2AT2
L2AT1
L2AT0
L2RT3
L2RT2
L2RT1
L2RT0
0
1
1
0
1
0
0
1
Limiter description
The STA321MP includes two independent limiter blocks. The purpose of the limiters is to
automatically reduce the dynamic range of a recording to prevent the outputs from clipping
in anti-clipping mode or to actively reduce the dynamic range for a better listening
environment such as a nighttime listening mode which is often needed for DVDs. The two
modes are selected via the DRC bit in configuration register B, bit 7 address 0x02. Each
channel can be mapped to either limiter or not mapped, meaning that the channel will clip
when 0 dBFS is exceeded. Each limiter will look at the present value of each channel that is
mapped to it, select the maximum absolute value of all these channels, perform the limiting
algorithm on that value, and then, if needed, adjust the gain of the mapped channels in
unison.
The limiter attack thresholds are determined by the LnAT registers. It is recommended in
anti-clipping mode to set this to 0 dBFS, which corresponds to the maximum unclipped
output power of an FFX amplifier. Since gain can be added digitally within the STA321MP it
is possible to exceed 0 dBFS or any other LnAT setting. When this occurs, the limiter, when
active, will automatically start reducing the gain. The rate at which the gain is reduced when
the attack threshold is exceeded is dependent upon the attack rate register setting for that
limiter. The gain reduction occurs on a peak-detect algorithm.
The release of the limiter, when the gain is again increased, is dependent on an RMS-detect
algorithm. The output of the volume/limiter block is passed through an RMS filter. The output
of this filter is compared to the release threshold, determined by the release threshold
register. When the RMS filter output falls below the release threshold, the gain is again
increased at a rate dependent upon the release rate register. The gain can never be
increased past its set value and therefore the release will only occur if the limiter has already
reduced the gain. The release threshold value can be used to set what is effectively a
minimum dynamic range, this is helpful as overlimiting can reduce the dynamic range to
virtually zero and cause program material to sound lifeless.
46/84
DocID022647 Rev 5
STA321MP
Registers
In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the
attack threshold is set relative to the maximum volume setting of the channels mapped to
that limiter and the release threshold is set relative to the maximum volume setting plus the
attack threshold.
Figure 9. Basic limiter and volume flow diagram
Limiter
RMS
Attenuation
Saturation
Gain/Volume
Input
Output
Gain
CnLS[1,0]
Channel limiter mapping
00
Channel has limiting disabled
01
Channel is mapped to limiter #1
10
Channel is mapped to limiter #2
LnA[3:0]
Attack rate (dB/ms)
0000
3.1584 (fast)
0001
2.7072
0010
2.2560
0011
1.8048
0100
1.3536
0101
0.9024
0110
0.4512
0111
0.2256
1000
0.1504
1001
0.1123
1010
0.0902
1011
0.0752
1100
0.0645
1101
0.0564
1110
0.0501
1111
0.0451 (slow)
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Registers
STA321MP
LnR[3:0]
Release rate (dB/ms)
0000
0.5116 (fast)
0001
0.1370
0010
0.0744
0011
0.0499
0100
0.0360
0101
0.0299
0110
0.0264
0111
0.0208
1000
0.0198
1001
0.0172
1010
0.0147
1011
0.0137
1100
0.0134
1101
0.0117
1110
0.0110
1111
0.0104 (slow)
Anti-clipping (AC)
(dB relative to FS)
LnAT[3:0]
48/84
0000
-12
0001
-10
0010
-8
0011
-6
0100
-4
0101
-2
0110
0
0111
+2
1000
+3
1001
+4
1010
+5
1011
+6
1100
+7
1101
+8
1110
+9
1111
+10
DocID022647 Rev 5
STA321MP
Registers
Anti-clipping (AC)
(dB relative to FS)
LnRT[3:0]
0000
-
0001
-29 dB
0010
-20 dB
0011
-16 dB
0100
-14 dB
0101
-12 dB
0110
-10 dB
0111
-8 dB
1000
-7 dB
1001
-6 dB
1010
-5 dB
1011
-4 dB
1100
-3 dB
1101
-2 dB
1110
-1 dB
1111
-0 dB
Dynamic range compression (DRC)
(dB relative to volume)
LnAT[3:0]
0000
-31
0001
-29
0010
-27
0011
-25
0100
-23
0101
-21
0110
-19
0111
-17
1000
-16
1001
-15
1010
-14
1011
-13
1100
-12
1101
-10
1110
-7
1111
-4
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Registers
STA321MP
Dynamic range compression (DRC)
(db relative to volume + LnAT)
LnRT[3:0]
5.2.49
0000
-
0001
-38 dB
0010
-36 dB
0011
-33 dB
0100
-31 dB
0101
-30 dB
0110
-28 dB
0111
-26 dB
1000
-24 dB
1001
-22 dB
1010
-20 dB
1011
-18 dB
1100
-15 dB
1101
-12 dB
1110
-9 dB
1111
-6 dB
Channel 1 and 2 output timing (0x33)
D7
5.2.50
D4
C2OT2
C2OT1
1
0
D3
D2
D1
D0
C2OT0
C1OT2
C1OT1
C1OT0
0
0
0
0
D2
D1
D0
D6
D5
D4
D3
C4OT2
C4OT1
C4OT0
C3OT2
C3OT1
C3OT0
1
1
0
0
1
0
D2
D1
D0
Channel 5 and 6 output timing (0x35)
D7
50/84
D5
Channel 3 and 4 output timing (0x34)
D7
5.2.51
D6
D6
D5
D4
C6OT2
C6OT1
C6OT0
C5OT2
C5OT1
C5OT0
1
0
1
0
0
1
DocID022647 Rev 5
D3
STA321MP
5.2.52
Registers
Channel 7 and 8 output timing (0x36)
D7
D6
D5
D4
C8OT2
C8OT1
1
1
D3
D2
D1
D0
C8OT0
C7OT2
C7OT1
C7OT0
1
0
1
1
The centering of the individual channel PWM output periods can be adjusted by the output
timing registers. The PWM slot settings can be chosen to ensure that pulse transitions do
not occur at the same time on different channels using the same power device. There are 8
possible settings, the appropriate setting varies based on the application and connections to
the FFX power devices.
CnOT[2:0]
5.2.53
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
8
Coefficient address register 1 (0x3B)
D7
5.2.54
5.2.55
PWM slot
D6
D5
D4
D3
D2
D1
D0
CFA9
CFA8
0
0
Coefficient address register 2 (0x3C)
D7
D6
D5
D4
D3
D2
D1
D0
CFA7
CFA6
CFA5
CFA4
CFA3
CFA2
CFA1
CFA0
0
0
0
0
0
0
0
0
Coefficient b1 data register, bits 23:16 (0x3D)
D7
D6
D5
D4
D3
D2
D1
D0
C1B23
C1B22
C1B21
C1B20
C1B19
C1B18
C1B17
C1B16
0
0
0
0
0
0
0
0
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Registers
5.2.56
5.2.57
5.2.58
5.2.59
5.2.60
5.2.61
5.2.62
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STA321MP
Coefficient b1 data register, bits 15:8 (0x3E)
D7
D6
D5
D4
D3
D2
D1
D0
C1B15
C1B14
C1B13
C1B12
C1B11
C1B10
C1B9
C1B8
0
0
0
0
0
0
0
0
Coefficient b1 data register, bits 7:0 (0x3F)
D7
D6
D5
D4
D3
D2
D1
D0
C1B7
C1B6
C1B5
C1B4
C1B3
C1B2
C1B1
C1B0
0
0
0
0
0
0
0
0
Coefficient b2 data register, bits 23:16 (0x40)
D7
D6
D5
D4
D3
D2
D1
D0
C2B23
C2B22
C2B21
C2B20
C2B19
C2B18
C2B17
C2B16
0
0
0
0
0
0
0
0
Coefficient b2 data register, bits 15:8 (0x41)
D7
D6
D5
D4
D3
D2
D1
D0
C2B15
C2B14
C2B13
C2B12
C2B11
C2B10
C2B9
C2B8
0
0
0
0
0
0
0
0
Coefficient b2 data register, bits 7:0 (0x42)
D7
D6
D5
D4
D3
D2
D1
D0
C2B7
C2B6
C2B5
C2B4
C2B3
C2B2
C2B1
C2B0
0
0
0
0
0
0
0
0
Coefficient a1 data register, bits 23:16 (0x43)
D7
D6
D5
D4
D3
D2
D1
D0
C1B23
C1B22
C1B21
C1B20
C1B19
C1B18
C1B17
C1B16
0
0
0
0
0
0
0
0
Coefficient a1 data register, bits 15:8 (0x44)
D7
D6
D5
D4
D3
D2
D1
D0
C3B15
C3B14
C3B13
C3B12
C3B11
C3B10
C3B9
C3B8
0
0
0
0
0
0
0
0
DocID022647 Rev 5
STA321MP
5.2.63
5.2.64
5.2.65
5.2.66
5.2.67
5.2.68
5.2.69
Registers
Coefficient a1 data register, bits 7:0 (0x45)
D7
D6
D5
D4
D3
D2
D1
D0
C3B7
0
C3B6
0
C3B5
0
C3B4
0
C3B3
0
C3B2
0
C3B1
0
C3B0
0
Coefficient a2 data register, bits 23:16 (0x46)
D7
D6
D5
D4
D3
D2
D1
D0
C4B23
C4B22
C4B21
C4B20
C4B19
C4B18
C4B17
C4B16
0
0
0
0
0
0
0
0
Coefficient a2 data register, bits 15:8 (0x47)
D7
D6
D5
D4
D3
D2
D1
D0
C4B15
0
C4B14
0
C4B13
0
C4B12
0
C4B11
0
C4B10
0
C4B9
0
C4B8
0
Coefficient a2 data register, bits 7:0 (0x48)
D7
D6
D5
D4
D3
D2
D1
D0
C4B7
0
C4B6
0
C4B5
0
C4B4
0
C4B3
0
C4B2
0
C4B1
0
C4B0
0
Coefficient b0 data register, bits 23:16 (0x49)
D7
D6
D5
D4
D3
D2
D1
D0
C5B23
C5B22
C5B21
C5B20
C5B19
C5B18
C5B17
C5B16
0
0
0
0
0
0
0
0
Coefficient b0 data register, bits 15:8 (0x4A)
D7
D6
D5
D4
D3
D2
D1
D0
C5B15
C5B14
C5B13
C5B12
C5B11
C5B10
C5B9
C5B8
0
0
0
0
0
0
0
0
Coefficient b0 data register, bits 7:0 (0x4B)
D7
D6
D5
D4
D3
D2
D1
D0
C5B7
C5B6
C5B5
C5B4
C5B3
C5B2
C5B1
C5B0
0
0
0
0
0
0
0
0
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Registers
5.2.70
STA321MP
Coefficient write control register (0x4C)
D7
D6
D5
D4
D3
D2
D1
D0
WA
W1
0
0
Coefficients for EQ and Bass Management are handled internally in the STA321MP via
RAM. Access to this RAM is available to the user via an I2C register interface.
A collection of I2C registers are dedicated to this function. One contains a coefficient base
address, five sets of three store the values of the 24-bit coefficients to be written or that were
read, and one contains bits used to control the write of the coefficient(s) to RAM. The
following are instructions for reading and writing coefficients.
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STA321MP
5.3
5.4
Registers
Reading a coefficient from RAM
1.
Write the top 2 bits of address to I2C register 0x3B
2.
Write the bottom 8 bits of address to I2C register 0x3C
3.
Read the top 8 bits of coefficient in I2C address 0x3D
4.
Read the middle 8 bits of coefficient in I2C address 0x3E
5.
Read the bottom 8 bits of coefficient in I2C address 0x3F
Reading a set of coefficients from RAM
1.
Write the top 2 bits of address to I2C register 0x3B
2.
Write the bottom 8 bits of address to I2C register 0x3C
3.
Read the top 8 bits of coefficient in I2C address 0x3D
4.
Read the middle 8 bits of coefficient in I2C address 0x3E
5.
Read the bottom 8 bits of coefficient in I2C address 0x3F
6.
Read the top 8 bits of coefficient b2 in I2C address 0x40
7.
Read the middle 8 bits of coefficient b2 in I2C address 0x41
8.
Read the bottom 8 bits of coefficient b2 in I2C address 0x42
9.
Read the top 8 bits of coefficient a1 in I2C address 0x43
10. Read the middle 8 bits of coefficient a1 in I2C address 0x44
11. Read the bottom 8 bits of coefficient a1 in I2C address 0x45
12. Read the top 8 bits of coefficient a2 in I2C address 0x46
13. Read the middle 8 bits of coefficient a2 in I2C address 0x47
14. Read the bottom 8 bits of coefficient a2 in I2C address 0x48
15. Read the top 8 bits of coefficient b0 in I2C address 0x49
16. Read the middle 8 bits of coefficient b0 in I2C address 0x4A
17. Read the bottom 8 bits of coefficient b0 in I2C address 0x4B
5.5
Writing a single coefficient to RAM
1.
Write the top 2 bits of address to I2C register 0x3B
2.
Write the bottom 8 bits of address to I2C register 0x3C
3.
Write the top 8 bits of coefficient in I2C address 0x3D
4.
Write the middle 8 bits of coefficient in I2C address 0x3E
5.
Write the bottom 8 bits of coefficient in I2C address 0x3F
6.
Write 1 to the W1 bit in I2C address 0x4C
DocID022647 Rev 5
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Registers
5.6
STA321MP
Writing a set of coefficients to RAM
1.
Write the top 2 bits of starting address to I2C register 0x3B
2.
Write the bottom 8 bits of starting address to I2C register 0x3C
3.
Write the top 8 bits of coefficient b1 in I2C address 0x3D
4.
Write the middle 8 bits of coefficient b1 in I2C address 0x3E
5.
Write the bottom 8 bits of coefficient b1 in I2C address 0x3F
6.
Write the top 8 bits of coefficient b2 in I2C address 0x40
7.
Write the middle 8-bits of coefficient b2 in I2C address 0x41
8.
Write the bottom 8 bits of coefficient b2 in I2C address 0x42
9.
Write the top 8 bits of coefficient a1 in I2C address 0x43
10. Write the middle 8 bits of coefficient a1 in I2C address 0x44
11. Write the bottom 8 bits of coefficient a1 in I2C address 0x45
12. Write the top 8 bits of coefficient a2 in I2C address 0x46
13. Write the middle 8 bits of coefficient a2 in I2C address 0x47
14. Write the bottom 8 bits of coefficient a2 in I2C address 0x48
15. Write the top 8-bits of coefficient b0 in I2C address 0x49
16. Write the middle 8 bits of coefficient b0 in I2C address 0x4A
17. Write the bottom 8 bits of coefficient b0 in I2C address 0x4B
18. Write 1 to the WA bit in I2C address 0x4C
The mechanism for writing a set of coefficients to RAM provides a method of updating the
five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible
unpleasant acoustic side-effects.
When using this technique, the 10-bit address would specify the address of the biquad b1
coefficient (for example, decimals 0, 5, 10, 15, …, 100, … 395), and the STA321MP will
generate the RAM addresses as offsets from this base value to write the complete set of
coefficient data.
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STA321MP
6
Configuration registers (0x77; 0x78; 0x79)
Configuration registers (0x77; 0x78; 0x79)
CBQ1 (reg 0x77)
D7
D6
D5
D4
D3
D2
D1
D0
EBQ3_1
EBQ3_0
EBQ2_1
EBQ2_0
EBQ1_1
EBQ1_0
EBQ0_0
EBQ0_0
0
0
0
0
0
0
0
0
CBQ2 (reg 0x78)
D7
D6
D5
D4
D3
D2
D1
D0
EBQ7_1
EBQ7_0
EBQ6_1
EBQ6_0
EBQ5_1
EBQ5_0
EBQ4_1
EBQ4_0
0
0
0
0
0
0
0
0
D5
D4
D3
D2
D1
D0
nshen
EBQ9_1
EBQ9_0
EBQ8_1
EBQ8_0
1
0
0
0
0
CBQ3 (reg 0x79)
D7
D6
0
0
0
The STA321MP EQ biquads use the following equation:
Y[n] = 2 * (b0 / 2) * X[n] + 2 * (b1 / 2) * X[n-1] + b2 * X[n-2] - 2 * (a1 / 2) * Y[n-1] - a2 * Y[n-2]
= b0 * X[n] + b1 * X[n-1] + b2 * X[n-2] - a1 * Y[n-1] - a2 * Y[n-2]
where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed
fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF
(0.9999995231628). The default coefficient range (+/-1) can be reconfigured to 2 or 4
with the 0x77, 0x78 and 0x79 I2C registers. The coefficients range setting is common for all
the channels.

(EBQx_1;EBQx_0)=”00”: Biquad x use +/-1 range

(EBQx_1;EBQx_0)=”01”: Biquad x use +/-2 range

(EBQx_1;EBQx_0)=”10”: Biquad x use +/-4 range

(EBQx_1;EBQx_0)=”11”: reserved
Coefficients stored in the user-defined coefficient RAM are referenced in the following
manner:
CxHy0 = b1 / 2
CxHy1 = b2
CxHy2 = -a1 / 2
CxHy3 = -a2
CxHy4 = b0 / 2
where x represents the channel and the y the biquad number. For example, C0H41 is the b2
coefficient in the fourth biquad for channel 2.
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Configuration registers (0x77; 0x78; 0x79)
STA321MP
By default, all user-defined filters are pass-through where all coefficients are set to 0, except
the b0/2 coefficient which is set to 0x400000 (representing 0.5). Mix coefficients use only 1
range.
A special feature inside the digital processing block is available (active when the nshen bit is
set to ‘1’). In case of poles positioned at very low frequencies, biquads filters can generate
some audible quantization noise or unwanted DC level. In order to avoid this kind of effect a
quantization noise-shaping capability can be used. The filter structure including this special
feature, relative to each biquad is shown in Figure 10.
The new feature can be enabled independently for each biquad using the I2C registers. The
D7 bit, when set, is responsible for activating this function on the crossover filter while the
other bits address any specific biquads according to the previous table. Channels 1 and 2
share the same settings. Bit D7 is effective also for channel 3 if the related OCFG is used.
Figure 10. Biquad filter structure with quantization error noise shaping
In(t)
b0
z-1
-
+
Q
z-1
Out(t)
z-1
b1
a1
z-1
z-1
b2
a2
Figure 11. Channel mixer
CxMIX1
Channel 1
CxMIX2
Channel 2
CxMIX3
Channel 3
CxMIX4
Channel 4
CxMIX5
Channel 5
CxMIX6
Channel 6
CxMIX7
Channel 7
CxMIX8
Channel 8
58/84
DocID022647 Rev 5
Channel x
STA321MP
6.1
Configuration registers (0x77; 0x78; 0x79)
Post-scale
The STA321MP provides one additional multiplication after the last interpolation stage and
before the distortion compensation on each channel. This is a 24-bit signed fractional
multiply.
The scale factor for this multiply is loaded into RAM using the same I2C registers as the
biquad coefficients and the bass-management.
This post-scale factor can be used in conjunction with an ADC-equipped microcontroller to
perform power-supply error correction. All channels can use the channel 1 by setting the
post-scale link bit.
Table 12. RAM block for biquads, mixing, and bass management
Index
Index
(decimal)
(hex)
0
0x00
1
Parameter
Channel 1 - Biquad 1
Coefficient
Default
C1H10 (b1/2)
0x000000
0x01
C1H11 (b2)
0x000000
2
0x02
C1H12 (a1/2)
0x000000
3
0x03
C1H13 (a2)
0x000000
4
0x04
C1H14 (b0/2)
0x400000
5
0x05
Channel 1 - Biquad 2
C1H20
0x000000
…
…
…
…
…
49
0x31
Channel 1 - Biquad 10
C1HA4
0x400000
50
0x32
Channel 2 - Biquad 1
C2H10
0x000000
51
0x33
C2H11
0x000000
…
…
…
…
…
99
0x63
Channel 2 - Biquad 10
C2HA4
0x4000000
100
0x64
Channel 3 - Biquad 1
C3H10
0x000000
…
…
…
…
…
399
0x18F
Channel 8 - Biquad 10
C8HA4
0x400000
400
0x190
Channel 1 - Pre-scale
C1PreS
0x7FFFFF
401
0x191
Channel 2 - Pre-scale
C2PreS
0x7FFFFF
402
0x192
Channel 3 - Pre-scale
C3PreS
0x7FFFFF
…
…
…
…
…
407
0x197
Channel 8 - Pre-scale
C8PreS
0x7FFFFF
408
0x198
Channel 1 - Post-scale
C1PstS
0x7FFFFF
409
0x199
Channel 2 - Post-scale
C2PstS
0x7FFFFF
…
…
…
…
…
415
0x19F
Channel 8 - Post-scale
C8PstS
0x7FFFFF
416
0x1A0
Channel 1 - Mix# 1 1
C1MX11
0x7FFFFF
DocID022647 Rev 5
59/84
Configuration registers (0x77; 0x78; 0x79)
STA321MP
Table 12. RAM block for biquads, mixing, and bass management (continued)
60/84
Index
Index
(decimal)
(hex)
Parameter
Coefficient
Default
417
0x1A1
Channel 1 - Mix#1 2
C1MX12
0x000000
…
…
…
…
…
423
0x1A7
Channel 1 - Mix#1 8
C1MX18
0x000000
424
0x1A8
Channel 2 - Mix#1 1
C2MX11
0x000000
425
0x1A9
Channel 2 - Mix#1 2
C2MX12
0x7FFFFF
…
…
…
…
…
479
0x1DF
Channel 8 - Mix#1 8
C8MX18
0x7FFFFF
480
0x1E0
Channel 1 - Mix#2 1
C1MX21
0x7FFFFF
481
0x1E1
Channel 1 - Mix#2 2
C1MX22
0x000000
…
…
…
…
…
487
0x1E7
Channel 1 - Mix#2 8
C1MX28
0x000000
488
0x1E8
Channel 2 - Mix#2 1
C2MX21
0x000000
489
0x1E9
Channel 2 - Mix#2 2
C2MX22
0x7FFFFF
…
…
…
…
…
543
0x21F
Channel 8 - Mix#2 8
C8MX28
0x7FFFFF
DocID022647 Rev 5
STA321MP
Configuration registers (0x77; 0x78; 0x79)
6.2
Variable max power correction
6.2.1
MPCC1-2 (0x4D, 0x4E)
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is
used in place of the default coefficient when MPCV = 1.
D7
D6
D5
D4
D3
D2
D1
D0
MPCC15
MPCC14
MPCC13
MPCC12
MPCC11
MPCC10
MPCC9
MPCC8
0
0
1
0
1
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
MPCC7
MPCC6
MPCC5
MPCC4
MPCC3
MPCC2
MPCC1
MPCC0
1
1
0
0
0
0
0
0
6.3
Variable distortion compensation
6.3.1
DCC1-2 (0x4F, 0x50)
The DCC bits determine the 16 MSBs of the distortion compensation coefficient. This
coefficient is used in place of the default coefficient when DCCV = 1.
D7
D6
D5
D4
D3
D2
D1
D0
DCC15
DCC14
DCC13
DCC12
DCC11
DCC10
DCC9
DCC8
1
1
1
1
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
DCC7
DCC6
DCC5
DCC4
DCC3
DCC2
DCC1
DCC0
0
0
1
1
0
0
1
1
DocID022647 Rev 5
61/84
Configuration registers (0x77; 0x78; 0x79)
6.4
STA321MP
PSCorrect registers
An ADC is used to input ripple data to SDI78. The left channel (7) is used internally. No
audio data can therefore be used on these channels, although all channel mapping and
mixing from other inputs to channels 7 and 8 internally are still valid.
6.4.1
PSC1-2: ripple correction value (RCV) (0x51, 0x52)
This value is equivalent to the negative maximum ripple peak as a percentage of Vcc
(MPR), scaled by the inverse of the maximum ripple p-p as a percentage of the full-scale
analog input to the ADC. It is represented as a 1.11 signed fractional number.
6.4.2
D7
D6
D5
D4
D3
D2
D1
D0
RCV11
RCV10
RCV9
RCV8
RCV7
RCV6
RCV5
RCV4
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
RCV3
RCV2
RCV1
RCV0
CNV11
CNV10
CNV9
CNV8
0
0
0
0
1
1
1
1
PSC3: correction normalization value (CNV) (0x53)
This value is equivalent to 1 / (1+MPR) expressed as a 0.12 unsigned fractional number.
D7
D6
D5
D4
D3
D2
D1
D0
CNV7
CNV6
CNV5
CNV4
CNV3
CNV2
CNV1
CNV0
1
1
1
1
1
1
1
1
6.5
PDM and recombination IP
6.5.1
Mike recombination RAM BIST (0x5C)
62/84
D7
D6
D5
D4
D3
D2
D1
D0
MHFail
MHBad
MHEnd
MHAct
MNFail
MNBad
MNEnd
MNAct
0
0
0
0
0
0
0
0
DocID022647 Rev 5
STA321MP
6.5.2
Configuration registers (0x77; 0x78; 0x79)
Bit
RW
RST
Name
Description
7
RW
0
MHFail
‘1’ : MHBist computation bit fail
6
RW
0
MHBad
‘1’ : MHBist computation bad
5
RW
0
MHEnd
‘1’ : MHBist computation finished
4
RW
0
MHAct
‘1’ : MHBist computation start
3
RW
0
MNFail
‘1’ : MNBist computation bit fail
2
RW
0
MNBad
‘1’ : MNBist computation bad
1
RW
0
MNEnd
‘1’ : MNBist computation finished
0
RW
0
MNAct
‘1’ : MNBist computation start
Recombination control register 1 (0x5D)
D7
D6
D5
D4
D3
Boost6db
0
0
0
0
0
D2
D1
D0
mike_en
mike_byp
m_mode
0
0
0
Bit
RW
RST
Name
Description
7
RW
0
Boost6dB(1)
'1': Output (after recombination) multiplied x2
'0': Output (after recombination) as it is
6
RW
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
mike_en
'1': Microphone recombination IP is active
‘0': Microphone recombination IP is not active
(acts like an HW Bypass)
1
RW
0
mike_byp
'1': Microphone recombination is bypassed
'0': Microphone recombination is used
0
RW
0
m_mode
'1': Auto-configuration of the CLKOUT generator
to Fout = sys_clk/32
'0': CLKOUT is configured only through COS bits
1. Mike recomb only
DocID022647 Rev 5
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Configuration registers (0x77; 0x78; 0x79)
6.5.3
6.5.4
STA321MP
PDM control register (0x5E)
D7
D6
D5
D4
D3
D2
AdvM6
AdvM5
AdvM4
AdvM3
AdvM2
AdvM1
0
0
0
0
0
0
Bit
RW
RST
Name
7
RW
AdvM6
6
RW
AdvM5
5
RW
AdvM4
4
RW
AdvM3
3
RW
AdvM2
2
RW
AdvM1
1
RW
0
RW
D0
PDMSM[1:0]
0
0
Description
PDMSM
PDM channel x sampling edge configuration:
'1': rising edge (of internal _CLK)
'0': falling edge (of internal _CLK)
(Active in Advance mode only, PDMSM = ’11’)
00: Normal mode
01: reserved
10: Dual-membrane
11: Advanced
Recombination control register 2, 3 and 4 (0x5F; 0x60; 0x61)
D7
D6
D5
D4
D3
bypRM1
D2
D1
D0
CH1GG[5:0]
0
0
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
bypRM2
CH2GG[5:0]
0
0
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
bypRM3
0
64/84
D1
0
CH3GG[5:0]
1
RST
0
Bit
RW
7
RW
reserved
6
RW
bypRMx
5
RW
4
RW
3
RW
2
RW
1
RW
0
RW
0
Name
CHxGG[5:0]
0
Description
'1': Recombination of Mike_x is bypassed
'0': Recombination of Mike_x is active
see Table 13
DocID022647 Rev 5
STA321MP
Configuration registers (0x77; 0x78; 0x79)
Table 13. Gain adjustment (sensitivity)
Index
dB
Index
dB
Index
dB
0x00
-4
0x16
-1.25
0x2C
1.5
0x01
-3.875
0x17
-1.125
0x2D
1.625
0x02
-3.75
0x18
-1
0x2E
1.75
0x03
-3.625
0x19
-0.875
0x2F
1.875
0x04
-3.5
0x1A
-0.75
0x30
2
0x05
-3.375
0x1B
-0.625
0x31
2.125
0x06
-3.25
0x1C
-0.5
0x32
2.25
0x07
-3.125
0x1D
-0.375
0x33
2.375
0x08
-3
0x1E
-0.25
0x34
2.5
0x09
-2.875
0x1F
-0.125
0x35
2.625
0x0A
-2.75
0x20
0
0x36
2.75
0x0B
-2.625
0x21
0.125
0x37
2.875
0x0C
-2.5
0x22
0.25
0x38
3
0x0D
-2.375
0x23
0.375
0x39
3.125
0x0E
-2.25
0x24
0.5
0x3A
3.25
0x0F
-2.125
0x25
0.625
0x3B
3.375
0x10
-2
0x26
0.75
0x3C
3.5
0x11
-1.875
0x27
0.875
0x3D
3.625
0x12
-1.75
0x28
1
0x3E
3.75
0x13
-1.625
0x29
1.125
0x3F
3.875
0x14
-1.5
0x2A
1.25
0x15
-1.375
0x2B
1.375
DocID022647 Rev 5
65/84
Configuration registers (0x77; 0x78; 0x79)
6.5.5
STA321MP
Recombination control register 5, 6 and 7 (0x62; 0x63; 0x64)
D7
D6
D5
D4
D3
LP1en
D1
D0
CH1NCA[5:0]
0
1
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
LP2en
CH2NCA[5:0]
0
1
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
LP3en
0
CH3NCA[5:0]
1
Bit
RW
7
RW
6
RW
5
RW
4
RW
3
RW
2
RW
1
RW
0
RW
1
RST
0
0
Name
LPxen
CHxNCA[5:0]
66/84
D2
0
Description
'1': Low-pass filter of mike x is enabled
'0': Low-pass filter of mike x is not enabled
see Table 14
DocID022647 Rev 5
STA321MP
Configuration registers (0x77; 0x78; 0x79)
Table 14. Normal channel attenuation
Index
dB
Index
dB
Index
dB
0x00
0
0x16
18.75
0x2C
21.5
0x01
10.5
0x17
18.875
0x2D
21.625
0x02
11
0x18
19
0x2E
21.75
0x03
11.5
0x19
19.125
0x2F
21.875
0x04
12
0x1A
19.25
0x30
22
0x05
12.5
0x1B
19.375
0x31
22.5
0x06
13
0x1C
19.5
0x32
23
0x07
13.5
0x1D
19.625
0x33
23.5
0x08
14
0x1E
19.75
0x34
24
0x09
14.5
0x1F
19.875
0x35
24.5
0x0A
15
0x20
20
0x36
25
0x0B
15.5
0x21
20.125
0x37
25.5
0x0C
16
0x22
20.25
0x38
26
0x0D
16.5
0x23
20.375
0x39
26.5
0x0E
17
0x24
20.5
0x3A
27
0x0F
17.5
0x25
20.625
0x3B
27.5
0x10
18
0x26
20.75
0x3C
28
0x11
18.125
0x27
20.875
0x3D
28.5
0x12
18.25
0x28
21
0x3E
29
0x13
18.375
0x29
21.125
0x3F
29.5
0x14
18.5
0x2A
21.25
0x15
18.625
0x2B
21.375
DocID022647 Rev 5
67/84
Configuration registers (0x77; 0x78; 0x79)
6.5.6
STA321MP
Recombination control register 8, 9 and 10 (0x65; 0x66; 0x67)
D7
D6
D5
D4
D3
D2
D1
D0
CH1TH_N[5:0]
0
0
1
1
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
CH2TH_N[5:0]
0
0
1
1
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
1
1
CH3TH_N[5:0]
0
0
Bit
RW
7
RW
6
RW
5
RW
4
RW
3
RW
2
RW
1
RW
0
RW
1
RST
1
0
Name
Description
Reserved
CHxTH_N[5:0]
68/84
0
see Table 15
DocID022647 Rev 5
STA321MP
Configuration registers (0x77; 0x78; 0x79)
Table 15. Threshold configuration
6.5.7
Index
dB
Index
dB
Index
dB
Index
dB
Index
dB
Index
dB
0x00
0
0x0B
-11
0x16
-22
0x21
-33
0x2C
-44
0x37
-55
0x01
-1
0x0C
-12
0x17
-23
0x22
-34
0x2D
-45
0x38
-56
0x02
-2
0x0D
-13
0x18
-24
0x23
-35
0x2E
-46
0x39
-57
0x03
-3
0x0E
-14
0x19
-25
0x24
-36
0x2F
-47
0x3A
-58
0x04
-4
0x0F
-15
0x1A
-26
0x25
-37
0x30
-48
0x3B
-59
0x05
-5
0x10
-16
0x1B
-27
0x26
-38
0x31
-49
0x3C
-60
0x06
-6
0x11
-17
0x1C
-28
0x27
-39
0x32
-50
0x3D
-61
0x07
-7
0x12
-18
0x1D
-29
0x28
-40
0x33
-51
0x3E
-62
0x08
-8
0x13
-19
0x1E
-30
0x29
-41
0x34
-52
0x3F
-63
0x09
-9
0x14
-20
0x1F
-31
0x2A
-42
0x35
-53
0x0A
-10
0x15
-21
0x20
-32
0x2B
-43
0x36
-54
Recombination control register 11, 12 and 13 (0x68; 0x69; 0x6A)
D7
D6
D5
D4
D3
D2
D1
D0
CH1TH_H[5:0]
0
0
0
1
1
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
CH2TH_H[5:0]
0
0
0
1
1
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
1
1
CH3TH_H[5:0]
0
0
0
Bit
RW
RST
7
RW
0
6
RW
0
5
RW
0
4
RW
1
3
RW
1
2
RW
0
1
RW
1
0
RW
1
1
1
Name
0
Description
Reserved
CHxHCT[5:0]
see Table 15
DocID022647 Rev 5
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Configuration registers (0x77; 0x78; 0x79)
6.5.8
STA321MP
Zero-mute threshold/hysteresis and RMS zero-mute selectors (0x6F)
Zero-mute (0x6F)
D7
D6
D5
D4
D3
D2
D1
D0
RMSZS2
RMSZS1
RMSZS0
ZMTHS2
ZMTHS1
ZMTHS0
ZMHYS1
ZMHYS0
0
0
0
0
0
0
0
0
Bit
RW
RST
Name
7
RW
0
RMSZS2
6
RW
0
RMSZS1
5
RW
0
RMSZS0
4
RW
0
ZMTHS2
3
RW
0
ZMTHS1
2
RW
0
ZMTHS1
1
RW
0
ZMHYS1
0
RW
0
ZMHYS0
Description
Select channel for reading the zero-mute RMS
level on registers rmsZMH (0x7A) & rmsZML
(0x7B).
Select the zero-mute threshold level. If signal is
below this level, output will be in switch off mode.
Select the hysteresis window width.
The STA321MP implements an RMS-based zero-detect function (on serial input interface
data) able to detect in a very reliable way the presence of an input signal, so that the power
bridge outputs can be automatically connected to ground. When active, the function will
mute the output PWM when the input level become less than threshold - hysteresis.
Once muted, the PWM will be unmuted when the input level is detected greater than
threshold + hysteresis .
The measured level is then reported (each input channel is selected by RMSZS[2:0] value)
on registers 0x7A, 0x7B.
Table 16. RMS channel select
70/84
RMSZS[2:0]
Channel
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
8
DocID022647 Rev 5
STA321MP
Configuration registers (0x77; 0x78; 0x79)
Table 17. Zero-detect threshold
ZMTHS[2:0]
Equivalent input level (dB)
000
-78
001
-84
010
-90
011
-96
100
-102
101
-108
110
-114
111
-114
Table 18. Zero-detect hysteresis
ZMHYS[1:0]
Equivalent input level hysteresis(dB)
00
3
01
4
10
5
11
6
DocID022647 Rev 5
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Configuration registers (0x77; 0x78; 0x79)
6.5.9
STA321MP
RMS post-processing selectors and Fs autodetection (0x70)
D7
D6
D5
D4
RMSOS2
RMSOS1
RMSOS0
0
0
0
D3
D2
D1
D0
FXLRC0
0
0
0
0
0
RMS out selector
Bit
RW
RST
Name
Description
7
RW
0
RMSOS2
6
RW
0
RMSOS1
5
RW
0
RMSOS0
RMS post-processing selectors. For each
channel the current RMS value after the
processing step is available on registers rmsPOH
(0x7C) and rmsPOL (0x7D).
Table 19. RMS post-processing channel select
RMSOS[2:0]
Channel
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
8
Fs autodetection
Bit
0
72/84
RW
RW
RST
0
Name
FXLRC0
Description
If set to 1, the IR and BST32K parameters are
auto-selected by the Fs autodetection internal
block; otherwise, the I2C register values are
used.
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6.5.10
Configuration registers (0x77; 0x78; 0x79)
Clock manager configuration
PLL configuration registers (0x71, 0x72, 0x73, 0x74)
PLL multiplication factor (fractional part, H) (0x71)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
D2
D1
D0
0
0
0
PLLFI[15:8]
0
0
0
0
0
PLL multiplication factor (fractional part, L) (0x72)
D7
D6
D5
D4
D3
PLLFI[7:0]
0
0
0
0
0
PLL multiplication factor (integral part) named as N Division Factor (NDIV)
and dithering (0x73)
D7
D6
D5
D4
D3
PLLDD[1:0]
0
D2
D1
D0
0
0
PLLND[5:0]
0
0
0
Bit
RW
RST
Name
7
RW
0
PLLDD1
6
RW
0
PLLDD0
5
RW
0
PLLND5
4
RW
0
PLLND4
3
RW
0
PLLND3
2
RW
1
PLLND2
1
RW
0
PLLND1
0
RW
1
PLLND0
0
0
Description
PLL dithering:
00 : PLL clock dithering disabled
01 : PLL clock dithering enabled (triangular)
10 : PLLclock dithering enabled (rectangular)
11 : reserved
N (loop) Division Factor
This factor should be:
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Configuration registers (0x77; 0x78; 0x79)
STA321MP
PLL input division factor and others (0x74)
D7
D6
D5
D4
D3
D2
D1
D0
PDPDC
PLLFC
PLSTRB
PLSTBB
PLIDF3
PLIDF2
PLIDF1
PLIDF0
0
0
0
0
0
0
0
0
By default the STA321MP is able to configure the embedded PLL automatically depending
on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a
manual PLL configuration can be used (setting PLLFC to 1). The output PLL frequency
formula is:
Fin
FI 
Fout = ----------   ND + -------IDF 
2 16
when PLLFC = 1
Fin
Fout = ----------   ND 
IDF
when PLLFC = 0
Clock manager configuration register (0x75)
D7
D5
D4
D3
D2
D1
D0
PLLBYP
PLLDPR
LOWEN
BST32K
0
0
0
0
Bit
RW
RST
Name
3
RW
0
PLLBYP
PLL bypass enable
‘0’: disabled
‘1’: bypassed
PLLDPR
PLL direct programming
‘0’: PLL configuration depends on MCS
‘1’: PLL configuration depends on I2C regs (0x72,
0x73 and 0x74)
2
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D6
RW
0
Description
1
RW
0
LOWEN
Low clock enable
‘0’: if input clock is too slow, master clock will become
the internal oscillator clock (20 MHz), PLL bypassed
‘1’: disabled
0
RW
0
BST32K
Boost oversampling for fs = 32 kHz
‘0’: disabled
‘1’: input oversampling is selected x 3
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STA321MP
Configuration registers (0x77; 0x78; 0x79)
Clock manager status register (0x76)
D7
6.5.11
D6
D5
D4
D3
D2
D1
D0
PLLBYS
PLLPDS
OSCOK
LOWCKS
0
0
0
0
Bit
RW
RST
Name
3
R
0
PLLBYS
PLL bypass status
‘0’: normal
‘1’: bypassed
2
R
0
PLLPDS
PLL power-down status
‘0’: normal
‘1’: standby
Oscillator clock OK
‘0’: not ready
‘1’: ready
1
R
0
OSCOK
0
R
0
LOWCKS
Description
Low clock status
‘0’: normal
‘1’: input clock too slow
RMS level registers (0x7A, 0x7B, 0x7C, 0x7D)
Two set of registers are available to monitor the RMS level detected by the zero-mute block
and after the signal processing.
The measured level for a selected channel is given in 0x7A & 0x7B (zero-mute level) and
0x7C & 0x7D (PWM out level) according to the following expression:
Value(dB) = 20Log(rms[15:0]/(216 x 0.635))
where rms[15:0] is an unsigned integer formed by:
rms[15:0] = rmsZMH[7:0], rmsZML[7:0] for zero-mute level
or
rms[15:0] = rmsPOH[7:0], rmsPOL[7:0] for PWM output level
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Configuration registers (0x77; 0x78; 0x79)
STA321MP
rmsZMx
D7
D6
D5
D4
D3
D2
D1
D0
RZM15
RZM14
RZM13
RZM12
RZM11
RZM10
RZM9
RZM8
0
0
0
0
0
0
0
0
RZM7
RZM6
RZM5
RZM4
RZM3
RZM2
RZM1
RZM0
0
0
0
0
0
0
0
0
rmsZMH
Bit
RW
RST
Name
Description
7
R
RZM15
6
R
RZM14
5
R
RZM13
4
R
RZM12
3
R
RZM11
2
R
RZM10
1
R
RZM9
0
R
RZM8
RMS zero-detect level register, H
rmsZML
Bit
RW
RST
Name
7
R
RZM7
6
R
RZM6
5
R
RZM5
4
R
RZM4
3
R
RZM3
2
R
RZM2
1
R
RZM1
0
R
RZM0
Description
RMS zero detect level register, L
rmsPOx
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D7
D6
D5
D4
D3
D2
D1
D0
RPO15
RPO14
RPO13
RPO12
RPO11
RPO10
RPO9
RPO8
0
0
0
0
0
0
0
0
RPO7
RPO6
RPO5
RPO4
RPO3
RPO2
RPO1
RPO0
0
0
0
0
0
0
0
0
DocID022647 Rev 5
STA321MP
Configuration registers (0x77; 0x78; 0x79)
rmsPOH
Bit
RW
RST
Name
7
R
RPO15
6
R
RPO14
5
R
RPO13
4
R
RPO12
3
R
RPO11
2
R
RPO10
1
R
RPO9
0
R
RPO8
Description
RMS PWM out (post-processing) register, H
rmsPOL
Bit
RW
RST
Name
7
R
RPO7
6
R
RPO6
5
R
RPO5
4
R
RPO4
3
R
RPO3
2
R
RPO2
1
R
RPO1
0
R
RPO0
Description
RMS PWM out (post-processing) register, L
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Startup/shutdown pop noise removal
STA321MP
7
Startup/shutdown pop noise removal
7.1
DPT: PWM and tristate delay (0x80)
D7
7.2
D5
D4
D3
D2
D1
D0
DPT4
DPT3
DPT2
DPT1
DPT0
1
1
1
0
0
Bit
RW
RST
Name
0
RW
0
DPT0
1
RW
0
DPT1
2
RW
1
DPT2
3
RW
1
DPT3
4
RW
1
DPT4
Description
Set a delay between the PWM and the tristate
signal to compensate the external amplifier delay.
Configuration register (0x81)
D7
D6
D5
D4
D3
D2
D1
D0
RL3
RL2
RL1
RL0
RD
SID1
FBYP
RTP
0
0
0
0
0
1
0
1
RST
Name
Bit
78/84
D6
RW
0
RW
1
RTP
Bit
RW
RST
Name
1
RW
0
FBYP
Description
Remove tristate initial pulses
1: remove the tristate initilal pulses with frequency less
than 16 kHz
0: the tristate initial pulses are not removed
Description
Fault user-defined bypass mode
1: the fault internal management is disabled
0: the fault internal management is enabled
DocID022647 Rev 5
STA321MP
Startup/shutdown pop noise removal
Bit
RW
RST
Name
Description
2
RW
1
SID1
Serial interface (I²S out)
1: SDO_56 is connected to the fault signal and SDO_78
outputs the tristate signal
0: I²S out normal
Bit
RW
RST
Name
Description
RD
Startup/shutdown pop noise disable
1: the startup/shutdown tristate sequence used to remove
the pop noise is disabled
0: the startup/shutdown tristate signal sequence used to
remove the pop noise is enabled. This feature is available
only when PWMS output speed is set to 384 kHz.
3
RW
0
Bit
RW
RST
Name
4
RW
0
RL0
5
RW
0
RL1
6
RW
0
RL2
7
RW
0
RL3
Description
Set a tristate duration (same value for
startup/shutdown pop noise removal)
RL[3:0]
7.3
Tristate duration
0000
default duration equal to 116 ms
0001
default value x2
0010
default value x3
0011
default value x4
0100
default value x5
0101
default value x6
0110
default value x7
User-defined delay time (0x82) and (0x83)
D7
D6
D5
D4
D3
D2
D1
D0
UDDT15
UDDT14
UDDT13
UDDT12
UDDT11
UDDT10
UDDT9
UDDT8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
UDDT7
UDDT6
UDDT5
UDDT4
UDDT3
UDDT2
UDDT1
UDDT0
1
1
1
1
1
1
1
1
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Package information
8
STA321MP
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 12. TQFP64 (10 x 10 mm) package dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
A
MIN.
TYP.
1.60
A1
0.05
0.15
0.063
0.002
0.006
A2
1.35
1.40
1.45
0.053
B
0.17
0.22
0.27
0.0066 0.0086 0.0106
0.055
0.057
C
0.09
D
11.80
12.00
12.20
0.464
0.472
0.480
D1
9.80
10.00
10.20
0.386
0.394
0.401
0.0035
D3
7.50
0.295
e
0.50
0.0197
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
0.45
0.60
0.75
0.0177 0.0236 0.0295
E3
7.50
L
OUTLINE AND
MECHANICAL DATA
MAX.
0.295
L1
1.00
K
0˚ (min.), 3.5˚ (min.), 7˚(max.)
0.0393
ccc
0.080
TQFP64 (10 x 10 x 1.4mm)
0.0031
D
D1
A
D3
A2
A1
48
33
49
32
0.08mm ccc
E
E1
E3
B
B
Seating Plane
17
64
1
16
C
L
L1
e
K
TQFP64
0051434 E
80/84
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Package information
Table 20. VFQFPN56 (8 x 8 mm) package dimensions
mm
Reference
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0
0.05
D
8.00
D2
See exposed pad variations
E
8.00
E2
See exposed pad variations
b
b1
e (pad pitch)
0.25
0.30
0.35
0.20
0.25
0.30
(1)
L1
0.05
0.15
aaa
0.15
bbb
0.10
ddd
0.05
eee
0.08
fff
0.10
ccc
0.10
1. Refer to Figure 13.
Table 21. Exposed pad variations
D2
E2
Variation
Min.
Typ.
Max
Min.
Typ.
Max.
A
5.85
5.90
5.95
5.85
5.90
5.95
B
4.25
4.30
4.35
4.25
4.30
4.35
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Package information
STA321MP
Figure 13. VFQFPN56 (8 x 8 mm) package outline
The axis of each pad must lie simultaneously in both tolerance zones.
(4) - The terminal A1 corner must be identified on the top surface through inked or lasered mark dot.
A distinguishing feature is allowable on the bottom surface of the package, chamfer at die paddle corner to
identify the terminal A1. Exact shape of each corner is optional.
(5) – All dimensions are in mm.
826820
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9
Revision history
Revision history
Table 22. Document revision history
Date
Revision
Changes
07-Feb-2012
1
Initial release
20-Dec-2012
2
Updated pins 17, 21, and 22 in Figure 3: Pin connections STA321MPL - TQFP64 (top
view) and Table 2: Pin description STA321MPL (TQFP64)
05-Mar-2013
3
Updated Description
Updated Table 1: Device summary
Updated Section 1.2: Pin description, Table 2, 3
Updated Table 4, 5, 6, 7
Removed section “Pin description”
Added Section 3: Microphone interface, Figure 5, 6, and Table 9
Added Section 4.4: Read operation
Removed “Application reference schematics” section
Updated Section 5: Registers, Section 5.1, Table 10: Register summary, Section 5.2,
added Figure 9
Added Section 5.2.3: Configuration register D (0x03)
Added Section 5.2.27: Fine volume (FineVol) (0x5B)
Added Section 5.2.32 through Section 5.2.36
Added Section 5.2.42 through Section 5.2.48
Renamed Section 6 and added Section 6.4 and 6.5
Added Section 7: Startup/shutdown pop noise removal
02-May-2013
4
Textual update in Section 3.6: Normal channel attenuation and Interpolation ratio select
03-Sep-2013
5
Added sentence “If XTI input is not used, related pin must be tied to GND”
Chapter 5.2.1: Configuration register A (0x00) on page 27.
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STA321MP
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