I2P AK PSMN3R5-80ES N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK Rev. 02 — 19 April 2011 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in I2PAK package qualified to 175C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits High efficiency due to low switching and conduction losses Suitable for standard level gate drive 1.3 Applications DC-to-DC converters Motor control Load switch Server power supplies 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 80 V - - 120 A - - 338 W -55 - 175 °C - 5 5.8 mΩ - 3 3.5 mΩ - 27 - nC - 139 - nC - - 676 mJ ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 Ptot total power dissipation Tmb = 25 °C; see Figure 2 Tj junction temperature [1] Static characteristics RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 12 VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 13 [2] Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge VGS = 10 V; ID = 75 A; VDS = 40 V; see Figure 14; see Figure 15 Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 120 A; Vsup ≤ 80 V; RGS = 50 Ω; unclamped PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK [1] Continuous current is limited by package. [2] Measured 3 mm from package. 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 D drain 3 S source mb D drain Simplified outline Graphic symbol D mb G mbb076 S 1 2 3 SOT226 (I2PAK) 3. Ordering information Table 3. Ordering information Type number PSMN3R5-80ES PSMN3R5-80ES Product data sheet Package Name Description Version I2PAK plastic single-ended package (I2PAK); TO-262 SOT226 All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 2 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 80 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 80 V VGS gate-source voltage ID drain current -20 20 V VGS = 10 V; Tmb = 100 °C; see Figure 1 [1] - 120 A VGS = 10 V; Tmb = 25 °C; see Figure 1 [1] - 120 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3 - 803 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 338 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C - 120 A Source-drain diode [1] IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 803 A VGS = 10 V; Tj(init) = 25 °C; ID = 120 A; Vsup ≤ 80 V; RGS = 50 Ω; unclamped - 676 mJ Avalanche ruggedness non-repetitive drain-source avalanche energy EDS(AL)S [1] Continuous current is limited by package. 003aaf615 240 ID (A) 03aa16 120 Pder (%) 180 80 120 (1) 40 60 0 0 0 Fig 1. 50 100 150 200 Tmb (°C) Continuous drain current as a function of mounting base temperature PSMN3R5-80ES Product data sheet 0 50 100 150 200 Tmb (°C) Fig 2. Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 3 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK 003aaf614 103 ID (A) Limit RDSon = VDS / ID tp =10 μ s 10 2 100 μ s 10 DC 1 ms 10 ms 1 100 ms 10-1 10-1 Fig 3. 1 10 102 103 V DS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN3R5-80ES Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 4 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 0.22 0.44 K/W Rth(j-a) thermal resistance from junction to ambient Vertical in free air - 60 - K/W 003aaf613 1 Zth(j-mb) (K/W) 10-1 δ = 0.5 0.2 0.1 0.05 10-2 P 0.02 δ= tp T single shot t tp T 10-3 10-6 Fig 4. 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN3R5-80ES Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 5 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 73 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 80 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 10 1 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 10 - - 4.6 V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 10; see Figure 11 2 3 4 V IDSS drain leakage current VDS = 80 V; VGS = 0 V; Tj = 25 °C - 0.02 10 µA VDS = 80 V; VGS = 0 V; Tj = 175 °C - - 500 µA IGSS gate leakage current VGS = -20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 10 V; ID = 25 A; Tj = 175 °C; see Figure 12 - 7.2 8.4 mΩ VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 12 - 5 5.8 mΩ - 3 3.5 mΩ f = 1 MHz - 0.9 - Ω RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 13 RG internal gate resistance (AC) [1] Dynamic characteristics QG(tot) total gate charge ID = 0 A; VDS = 0 V; VGS = 10 V - 135 - nC 139 - nC gate-source charge ID = 75 A; VDS = 40 V; VGS = 10 V; see Figure 14; see Figure 15 - QGS - 51 - nC QGS(th) pre-threshold gate-source charge - 30 - nC QGS(th-pl) post-threshold gate-source charge - 21 - nC QGD gate-drain charge - 27 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 40 V; see Figure 14; see Figure 15 - 5.8 - V Ciss input capacitance - 9961 - pF Coss output capacitance VDS = 40 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 - 847 - pF Crss reverse transfer capacitance - 401 - pF td(on) turn-on delay time tr rise time td(off) tf VDS = 40 V; RL = 0.53 Ω; VGS = 10 V; RG(ext) = 10 Ω; ID = 75 A - 41 - ns - 43 - ns turn-off delay time - 109 - ns fall time - 44 - ns PSMN3R5-80ES Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 6 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit - 0.8 1.2 V - 63 - ns - 121 - nC Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17 trr reverse recovery time Qr recovered charge IS = 25 A; dIS/dt = 100 A/µs; VGS = 0 V; VDS = 20 V [1] Measured 3 mm from package. 003aaf602 250 003aaf603 75 gfs (S) ID (A) 200 50 150 100 25 Tj = 175 °C 50 0 0 0 Fig 5. Tj = 25 °C 20 40 60 ID (A) 80 Forward transconductance as a function of drain current; typical values 003aaf604 30 RDSon (mΩ) 25 0 Fig 6. 2 4 VGS (V) 6 Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aaf606 16000 C (pF) Ciss 12000 20 15 Crss 8000 10 4000 5 0 0 Fig 7. 5 10 15 VGS (V) Drain-source on-state resistance as a function of gate-source voltage; typical values PSMN3R5-80ES Product data sheet 0 10-1 20 Fig 8. 1 10 2 VGS (V) 10 Input and reverse transfer capacitances as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 7 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK 003aad685 160 5.5 6 8 10 ID (A) 003aad280 5 5 VGS(th) (V) 4 max 120 3 typ 4.5 80 2 min 40 1 VGS (V) = 4 0 0 Fig 9. 0.5 1 1.5 VDS (V) 0 −60 2 Output characteristics: drain current as a function of drain-source voltage; typical values ID (A) 60 120 180 Tj (°C) Fig 10. Gate-source threshold voltage as a function of junction temperature 03aa35 10−1 0 003aaf608 3 a min 10−2 typ max 2.4 10−3 1.8 10−4 1.2 10−5 0.6 10−6 0 2 4 6 0 -60 VGS (V) Fig 11. Sub-threshold drain current as a function of gate-source voltage PSMN3R5-80ES Product data sheet 0 60 120 Tj (°C) 180 Fig 12. Normailzed drain-source on-state resistance factor as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 8 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK 003aaf612 15 RDSon (mΩ) 12.5 VDS ID VGS (V) = 4.5 10 VGS(pl) VGS(th) 7.5 VGS 5 QGS1 5.5 QGS 6.0 20.0 2.5 QGS2 QGD QG(tot) 003aaa508 0 0 10 20 30 ID (A) 40 Fig 13. Drain-source on-state resistance as a function of drain current; typical values 003aaf609 10 VGS (V) Fig 14. Gate charge waveform definitions 003aaf610 105 C (pF) 40V 64V 104 7.5 Ciss VDS = 16V 103 5 Coss Crss 102 2.5 0 0 40 80 120 Q (nC)160 G Fig 15. Gate-source voltage as a function of gate charge; typical values PSMN3R5-80ES Product data sheet 10 10-1 1 10 VDS (V) 102 Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 9 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK 003aaf611 25 IS (A) 20 15 10 5 Tj = 175 °C Tj = 25 °C 0 0 0.25 0.5 0.75 VSD (V) 1 Fig 17. Source current as a function of source-drain voltage; typical values PSMN3R5-80ES Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 10 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK 7. Package outline Plastic single-ended package (I2PAK); low-profile 3-lead TO-262 SOT226 A A1 E D1 mounting base D L1 Q b1 L 1 2 3 c b e e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 c D max D1 E e L L1 Q mm 4.5 4.1 1.40 1.27 0.85 0.60 1.3 1.0 0.7 0.4 11 1.6 1.2 10.3 9.7 2.54 15.0 13.5 3.30 2.79 2.6 2.2 OUTLINE VERSION SOT226 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 06-02-14 09-08-25 TO-262 Fig 18. Package outline SOT226 (I2PAK) PSMN3R5-80ES Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 11 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN3R5-80ES v.2 20110419 Product data sheet - PSMN3R5-80ES v.1 - - Modifications: PSMN3R5-80ES v.1 PSMN3R5-80ES Product data sheet • • Status changed from objective to product. Various changes to content. 20101224 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 12 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK 9. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 13 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PSMN3R5-80ES Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 19 April 2011 © NXP B.V. 2011. All rights reserved. 14 of 15 PSMN3R5-80ES NXP Semiconductors N-channel 80 V, 3.5 mΩ standard level MOSFET in I2PAK 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .12 Legal information. . . . . . . . . . . . . . . . . . . . . . . .13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Contact information. . . . . . . . . . . . . . . . . . . . . .14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 19 April 2011 Document identifier: PSMN3R5-80ES