1ED020I12FTA Data Sheet (852 KB, EN)

1ED020I12FTA
Single IGBT Driver IC
SP001054670
1
Overview
Main Features
•
Single channel isolated IGBT Driver
•
For 600V/1200V IGBTs
•
2 A rail-to-rail output
•
Vcesat-detection
•
Active Miller Clamp
•
Two level turn off
Product Highlights
•
Coreless transformer isolated driver
•
Basic insulation according to DIN EN 60747-5-2
•
Basic insulation recognized under UL 1577
•
Integrated protection features
•
Suitable for operation at high ambient temperature
•
AEC Qualified
Typical Application
•
Drive inverters for HEV and EV
•
Auxiliary inverters for HEV and EV
•
High Power DC/DC inverters
Description
The 1ED020I12FTA is a galvanic isolated single channel IGBT driver in PG-DSO-20 package that provides an
output current capability of typically 2A.
All logic pins are 5V CMOS compatible and could be directly connected to a microcontroller.
The data transfer across galvanic isolation is realized by the integrated Coreless Transformer Technology.
The 1ED020I12FTA provides several protection features like IGBT two level turn off, desaturation protection, active
Miller clamping and active shut down.
Type
Package
Marking
1ED020I12FTA
PG-DSO-20
1ED020I12FTA
Data Sheet
www.infineon.com
1
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.5
4.6
4.7
4.8
4.8.1
4.8.2
4.8.3
4.9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READY Status Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Inverting and Inverting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two-Level Turn-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimal On Time / Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
11
11
11
11
11
12
12
12
13
13
13
13
13
13
5
5.1
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two-level Turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
15
15
16
16
17
18
18
19
19
20
21
21
6
6.1
6.2
6.3
Insulation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Certified according to DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation . . . . . . . . . .
Recognized under UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
22
22
7
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data Sheet
2
Rev. 3.0
2016-04-05
EiceDRIVER™
1ED020I12FTA
9.1
9.2
Reference Layout for Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Printed Circuit Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data Sheet
3
Rev. 3.0, 2016-04-05
1ED020I12FTA
Single IGBT Driver IC
List of Figures
Figure 2-1
Figure 3-1
Figure 4-1
Figure 4-2
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10
Figure 8-1
Figure 9-1
Data Sheet
Block Diagram 1ED020I12FTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration PG-DSO-20 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Application Example Bipolar Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application Example Unipolar Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Propagation Delay, Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Principle Switching Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical Switching Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DESAT Switch-OFF Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Short Switch ON Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Short Switch OFF Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Short Switch OFF Pulses, Ringing Surpression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VCC2 Ramp Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VCC2 Ramp Down and VCC2 Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Typical TTLSET Time over CTLSET Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PG-DSO-20 (Plastic (Green) Dual Small Outline Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reference Layout for Thermal Data (Copper thickness 102 μm) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
List of Tables
Table 3-1
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 5-6
Table 5-7
Table 5-8
Table 5-9
Table 5-10
Table 5-11
Table 5-12
Table 6-1
Table 6-2
Data Sheet
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Logic Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Two-level Turn-off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Certified according to DIN EN 60747-5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Recognized under UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Block Diagram
2
Block Diagram
VCC1 18
UVLO
UVLO
&
6
VCC2
8
CLAMP
7
OUT
5
TLSET
3
DESAT
4
GND2
K4
2V
IN+ 13
delay
TX
delay
&
RX
1
VCC1
VCC2
20MHz
IN- 14
VEE2
&
OSC LOGIC
VCC1
RDY 15
&
/RDY
1
DECODER
RX
TX
VCC2
500µA
ENCODER
VCC1
7V
1
K3
S
FLT2
Q
Q
R
VCC1
S
9V
R
150Ω
≥1
/RST 17
delay
1
RST
VEE2
11
12
GND1 GND1
Figure 2-1
Data Sheet
1
19
20
1ED020I12FTA
GND1 GND1
1
2
VEE2 VEE2
9
250Ω
FLT
VCC2
&
500µA
&
RDY2
FLTNL
/FLT 16
VEE2
250Ω
10
VEE2 VEE2
Block Diagram 1ED020I12FTA
6
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Pin Configuration and Functionality
3
Pin Configuration and Functionality
3.1
Pin Configuration
Table 3-1
Pin Configuration
Pin No. Name
Function
1
VEE2
Negative power supply output side
2
VEE2
Negative power supply output side
3
DESAT
Desaturation protection
4
GND2
Signal ground output side
5
TLSET
Two level set
6
VCC2
Positive power supply output side
7
OUT
Driver output
8
CLAMP
Miller clamping
9
VEE2
Negative power supply output side
10
VEE2
Negative power supply output side
11
GND1
Ground input side
12
GND1
Ground input side
13
IN+
Non inverted driver input
14
IN-
Inverted driver input
15
RDY
Ready output
16
FLT
Fault output, low active
17
RST
Reset input, low active
18
VCC1
Positive power supply input side
19
GND1
Ground input side
20
GND1
Ground input side
Data Sheet
7
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Pin Configuration and Functionality
1
VEE2
GND1 20
2
VEE2
GND1 19
3
DESAT
VCC1 18
4
GND2
/RST 17
5
TLSET
/FLT 16
6
VCC2
RDY 15
7
OUT
IN- 14
8
CLAMP
IN+ 13
9
VEE2
GND1 12
10
VEE2
GND1 11
Figure 3-1
Pin Configuration PG-DSO-20 (top view)
3.2
Pin Functionality
GND1
Ground connection of the input side.
IN+ Non Inverting Driver Input
IN+ control signal for the driver output if IN- is set to low. (The IGBT is on if IN+ = high and IN- = low)
A minimum pulse width is defined to make the IC robust against glitches at IN+. An internal Pull-Down-Resistor
ensures IGBT Off-State.
IN- Inverting Driver Input
IN- control signal for driver output if IN+ is set to high. (IGBT is on if IN- = low and IN+ = high)
A minimum pulse width is defined to make the IC robust against glitches at IN-. An internal Pull-Up-Resistor
ensures IGBT Off-State.
/RST Reset Input
Function 1: Enable/shutdown of the input chip. (The IGBT is off if /RST = low). A minimum pulse width is
defined to make the IC robust against glitches at /RST.
Function 2: Resets the DESAT-FAULT-state of the chip if /RST is low for a time TRST. An internal Pull-Up-Resistor
is used to ensure /FLT status output.
/FLT Fault Output
Open-drain output to report a desaturation error of the IGBT (FLT is low if desaturation occurs)
RDY Ready Status
Open-drain output to report the correct operation of the device (RDY = high if both chips are above the UVLO
level and the internal chip transmission is faultless).
Data Sheet
8
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Pin Configuration and Functionality
VCC1
5 V power supply of the input chip
VEE2
Negative power supply pins of the output chip. If no negative supply voltage is available, all VEE2 pins have to
be connected to GND2.
DESAT Desaturation Detection Input
Monitoring of the IGBT saturation voltage (VCE) to detect desaturation caused by short circuits. If OUT is high,
VCE is above a defined value and a certain blanking time has expired, the desaturation protection is activated
and the IGBT is switched off. The blanking time is adjustable by an external capacitor.
CLAMP Miller Clamping
Ties the gate voltage to ground after the IGBT has been switched off at a defined voltage to avoid a parasitic
switch-on of the IGBT.During turn-off, the gate voltage is monitored and the clamp output is activated when
the gate voltage goes below 2 V below VEE2.
GND2 Reference Ground
Reference ground of the output chip.
OUT Driver Output
Output pin to drive an IGBT. The voltage is switched between VEE2 and VCC2. In normal operating mode Vout
is controlled by IN+, IN- and /RST. During error mode (UVLO, internal error or DESAT) Vout is set to VEE2
independent of the input control signals.
VCC2
Positive power supply pin of the output side.
TLSET Two Level Turn Off Adjust
Circuitry at TLSET adjust the two level turn off time with an external capacitor to GND2 and the two level
voltage with an external Zener diode to GND2, for wave forms please see Figure 7-4.
Data Sheet
9
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Functional Description
4
Functional Description
4.1
Introduction
The 1ED020I12FTA is an advanced IGBT gate driver for motor drives typical greater 10 kW. Control and
protection functions are included to make possible the design of high reliability systems.
The device consists of two galvanic separated parts. The input chip can be directly connected to a standard
5 V DSP or microcontroller with CMOS in/output and the output chip is connected to the high voltage side.
An effective active Miller clamp function avoids the need of negative gate driving in some applications and
allows the use of a simple bootstrap supply for the high side driver.
A rail-to-rail driver output enables the user to provide easy clamping of the IGBTs gate voltage during short
circuit of the IGBT. So an increase of short circuit current due to the feedback via the Miller capacitance can be
avoided. Further, a rail-to-rail output reduces power dissipation.
The device also includes an IGBT desaturation protection with a FAULT status output.
A two-level turn-off feature with adjustable delay protects against excessive overvoltage at turn-off in case of
overcurrent or short circuit condition. The same delay is applied at turn-on to prevent pulse width distortion.
A READY status output reports if the device is supplied and operates correctly.
10R
10k
10k
+5V
SGND
VCC1
+15V
VCC2
100n
1µ
1k
DESAT
GND1
CLAMP
IN+
IN+
RDY
FLT
/RST
10V
47p
220p
GND2
/FLT
RST
10R
TLSET
IN-
RDY
OUT
1µ
VEE2
-8V
1ED020I12FTA
Figure 4-1
Application Example Bipolar Supply
4.2
Supply
The driver 1ED020I12FTA is designed to support two different supply configurations, bipolar supply and
unipolar supply.
In bipolar supply the driver is typically supplied with a positive voltage of 15V at VCC2 and a negative voltage
of -8V at VEE2, refer to Figure 4-1. Negative supply prevents a dynamic turn on due to the additional charge
which is generated from IGBT input capacitance times negative supply voltage. If an appropriate negative
supply voltage is used, connecting CLAMPxx to IGBT gate is redundant and therefore typically not necessary.
For unipolar supply configuration the driver is typically supplied with a positive voltage of 15V at VCC2.
Erratically dynamic turn on of the IGBT could be prevented with active Miller clamp function, so CLAMP output
is directly connected to IGBT gate, refer to Figure 4-2.
Data Sheet
10
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Functional Description
10R
10k
10k
+5V
VCC1
1µ
100n
SGND
+15V
VCC2
1k
DESAT
GND1
CLAMP
IN+
IN+
TLSET
IN-
RDY
RDY
FLT
10R
OUT
10V
47p
220p
GND2
/FLT
RST
/RST
VEE2
1ED020I12FTA
Figure 4-2
Application Example Unipolar Supply
4.3
Internal Protection Features
4.3.1
Undervoltage Lockout (UVLO)
To ensure correct switching of IGBTs the device is equipped with an undervoltage lockout for both chips, refer
to Figure 7-8 and Figure 7-9.
If the power supply voltage VVCC1 of the input chip drops below VUVLOL1 a turn-off signal is sent to the output
chip before power-down. The IGBT is switched off and the signals at IN+ and IN- are ignored as long as VVCC1
reaches the power-up voltage VUVLOH1.
If the power supply voltage VVCC2 of the output chip goes down below VUVLOL2 the IGBT is switched off and
signals from the input chip are ignored as long as VVCC2 reaches the power-up voltage VUVLOH2. VEE2 is not
monitored, otherwise negative supply voltage range from 0 V to -12 V would not be possible.
4.3.2
READY Status Output
The READY output at pin /RDY shows the status of three internal protection features.
•
•
•
UVLO of the input chip
UVLO of the output chip after a short delay
Internal signal transmission after a short delay
It is not necessary to reset the READY signal since its state only depends on the status of the former mentioned
protection signals.
4.3.3
Watchdog Timer
During normal operation the internal signal transmission is monitored by a watchdog timer. If the
transmission fails for a given time, the IGBT is switched off and the READY output reports an internal error.
4.3.4
Active Shut-Down
The Active Shut-Down feature ensures a safe IGBT off-state if the output chip is not connected to the power
supply, IGBT gate is clamped at OUT to VEE2.
Data Sheet
11
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Functional Description
4.4
Non-Inverting and Inverting Inputs
There are two possible input modes to control the IGBT. At non-inverting mode IN+ controls the driver output
while IN- is set to low. At inverting mode IN- controls the driver output while IN+ is set to high, refer to
Figure 7-2. A minimum input pulse width is defined to filter occasional glitches.
4.5
Driver Output
The output driver section uses only MOSFETs to provide a rail-to-rail output. This feature permits that tight
control of gate voltage during on-state and short circuit can be maintained as long as the drivers supply is
stable. Due to the low internal voltage drop, switching behaviour of the IGBT is predominantly governed by
the gate resistor. Furthermore, it reduces the power to be dissipated by the driver.
4.6
Two-Level Turn-Off
The Two-Level Turn-OFF introduces a second turn off voltage level at the driver output in between ON- and
OFF-level, refer to Figure 7-3. This additional level ensures lower VCE overshoots at turn off by reducing gate
emitter voltage of the IGBT at short circuits or over current events. The VGE level is adjusting the current of the
IGBT at the end two level turn off interval, the required timing is depending on stray inductance and over
current at beginning of two level turn off interval.
Reference voltage level and hold up time could be adjusted at TLSET pin. The reference voltage is set by the
required Zener diode connected between pin TLSET and GND2. The holdup time is set by the capacitor
connected to the same pin TLSET and GND2.
The hold time can be adjusted during switch on using the whole capacitance connected at pin TLSET including
capacitor, parasitic wiring capacitance and junction capacitance of Zener diode. When a switch on signal is
given the IC starts to discharge CTLSET. Discharging CTLSET is stopped after 500 ns. Then Ctlset is charged with
an internal charge current ITLSET. When the voltage of the capacitor CTLSET exceeds 7 V a second current source
starts charging CTLSET up to VZDIODE. At the end of this discharge-charge cycle the gate driver is switched on.
The time between IN initiated switch-on signal (minus an internal propagation delay of approximately 200 ns)
and switch-on of the gate drive is sampled and stored digitally. It represents the two level turn off set time
TTLSET during switch-off. Due to digitalization the tpdon time can vary in time steps of 50 ns.
If switch off is initiated from IN+, IN- or /RST signal, the gate driver is switched off immediately after internal
propagation delay of approximately 200 ns and VOUT begins to decrease to the second gate voltage level.
For switch off initiated by DESAT, the gate driver switch off is delayed by desaturation sense to OUT delay,
afterwards VOUT begins to decrease to the second gate voltage level.
For reaching second gate voltage level the output voltage VOUT is sensed and compared with the Zener voltage
VZDIODE. When VOUT falls below the reference voltage VZDIODE of the Zener diode the switch off process is
interrupted and VOUT is adjusted to VZDIODE. OUT is switched to VEE2 after the holdup time has passed.
The Two-Level Turn-OFF function cannot be disabled.
Data Sheet
12
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Functional Description
4.7
Minimal On Time / Off Time
The 1ED020I12FTA driver requires minimal on and off time for proper operation in the application. Minimal on
time must be greater than the adjustable two level plateau time TTLSET, shorter on times will be suppressed by
generating of the plateau time refer to Figure 7-5. Due to the short on time, the voltage at TLSET pin does not
reach the comparator threshold; therefore the driver does not turn on. A similar principle takes place for off
time. Minimal off time must be greater than TTLSET; shorter off times will be suppressed, which means OUT
stays on refer to Figure 7-6. A two level turn off plateau cannot be shortened by the driver. If the driver has
entered the turn off sequence it cannot switch off due to the fact, that the driver has already entered the shut
off mode. But if the driver input signal is turned on again, it will leave the lower level after TTLSET time by
switching OUT to high, refer to Figure 7-7.
4.8
External Protection Features
4.8.1
Desaturation Protection
A desaturation protection ensures the protection of the IGBT at short circuit. When the DESAT voltage goes up
and reaches 9 V, the output is driven low, refer to Figure 7-4. Further, the FAULT output is activated. A
programmable blanking time is used to allow enough time for IGBT saturation. Blanking time is provided by a
highly precise internal current source and an external capacitor.
4.8.2
Active Miller Clamp
In a half bridge configuration the switched off IGBT tends to dynamically turn on during turn on phase of the
opposite IGBT. A Miller clamp allows sinking the Miller current across a low impedance path in this high dV/dt
situation. Therefore in many applications, the use of a negative supply voltage can be avoided.
During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes
below typical 2 V (related to VEE2). The clamp is designed for a Miller current up to 2 A.
4.8.3
Short Circuit Clamping
During short circuit the IGBTs gate voltage tends to rise because of the feedback via the Miller capacitance. An
additional protection circuit connected to OUT and CLAMP limits this voltage to a value slightly higher than
the supply voltage. A current of maximum 500 mA for 10 μs may be fed back to the supply through one of this
paths. If higher currents are expected or a tighter clamping is desired external Schottky diodes may be added.
4.9
RESET
The reset input has two functions.
Firstly, /RST is in charge of setting back the FAULT output. If /RST is low longer than a given time, /FLT will be
cleared at the rising edge of /RST, refer to Figure 7-4; otherwise, it will remain unchanged. Moreover, it works
as enable/shutdown of the input logic, refer to Figure 7-2.
Data Sheet
13
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Electrical Parameters
5
Electrical Parameters
5.1
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. Unless otherwise noted all parameters refer to GND1.
Table 5-1
Absolute Maximum Ratings
Parameter
Symbol
Values
Min.
Max.
Unit
Note
Positive power supply output side
VVCC2
-0.3
20
V
1)
Negative power supply output side
VVEE2
-12
0.3
V
1)
Maximum power supply voltage output side
(VVCC2 - VVEE2)
Vmax2
–
28
V
–
Gate driver output
VOUT
VVEE2-0.3
VVCC2+0.3 V
–
Gate driver high output maximum current
IOUT
–
2.4
A
t = 2 µs
Gate & Clamp driver low output maximum
current
IOUT
–
2.4
A
t = 2 µs
Maximum short circuit clamping time
tCLP
–
10
μs
ICLAMP/OUT =
500 mA
Positive power supply input side
VVCC1
-0.3
6.5
V
–
Logic input voltages
(IN+,IN-,RST)
VLogicIN
-0.3
6.5
V
–
Opendrain Logic output voltage (FLT)
VFLT#
-0.3
6.5
V
–
Opendrain Logic output voltage (RDY)
VRDY
-0.3
6.5
V
–
Opendrain Logic output current (FLT)
IFLT#
–
10
mA
–
Opendrain Logic output current (RDY)
IRDY
–
10
mA
–
Pin DESAT voltage
VDESAT
-0.3
VVCC2 +0.3 V
1)
Pin CLAMP voltage
VCLAMP
-0.3
VVCC2
+0.32)
V
3)
Junction temperature
TJ
-40
150
°C
–
Storage temperature
TS
-55
150
°C
–
Power dissipation, per input part
PD, IN
–
100
mW
4)
@TA = 25°C
Power dissipation, per output part
PD, OUT
–
700
mW
4)
@TA = 25°C
K/W
4)
@TA = 25°C
@TA = 25°C
Thermal resistance (Input part)
RTHJA,IN
–
139
Thermal resistance (Output chip active)
RTHJA,OUT
–
117
K/W
4)
ESD Capability
VESD
–
1.5
kV
Human Body
Model5)
1) With respect to GND2.
2) May be exceeded during short circuit clamping.
Data Sheet
14
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Electrical Parameters
3) With respect to VEE2.
4) Output IC power dissipation is derated linearly at 8.5 mW/°C above 68°C. Input IC power dissipation does not require
derating. See Figure 9-1 for reference layouts for these thermal data. Thermal performance may change significantly
with layout and heat dissipation of components in close proximity.
5) According to EIA/JESD22-A114-B (discharging a 100 pF capacitor through a 1.5 kΩ series resistor).
5.2
Operating Parameters
Note: Within the operating range the IC operates as described in the functional description. Unless otherwise
noted all parameters refer to GND1.
Table 5-2
Operating Parameters
Parameter
Symbol
Values
Min.
Max.
Unit
Note
Positive power supply output side
VVCC2
13
20
V
1)
Negative power supply output side
VVEE2
-12
0
V
1)
Maximum power supply voltage output side
(VVCC2 - VVEE2)
Vmax2
–
28
V
–
Positive power supply input side
VVCC1
4.5
5.5
V
–
Logic input voltages
(IN+,IN-,RST)
VLogicIN
-0.3
5.5
V
–
Pin CLAMP voltage
VCLAMP
VVEE2-0.3
VVCC22)
V
–
Pin DESAT voltage
VDESAT
-0.3
VVCC2
V
1)
Pin TLSET voltage
VTLSET
-0.3
VVCC2
V
1)
TA
-40
125
°C
–
50
kV/μs
@ 500 V
Ambient temperature
3)
Common mode transient immunity
|DVISO/dt| –
1) With respect to GND2.
2) May be exceeded during short circuit clamping.
3) The parameter is not subject to production test - verified by design/characterization
5.3
Recommended Operating Parameters
Note: Unless otherwise noted all parameters refer to GND1.
Table 5-3
Recommended Operating Parameters
Parameter
Symbol
Value
Unit
Note
Positive power supply output side
VVCC2
15
V
1)
Negative power supply output side
VVEE2
-8
V
1)
Positive power supply input side
VVCC1
5
V
–
1) With respect to GND2.
Data Sheet
15
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Electrical Parameters
5.4
Electrical Characteristics
Note: The electrical characteristics include the spread of values in supply voltages, load and junction
temperatures given below. Typical values represent the median values at TA = 25°C. Unless otherwise
noted all voltages are given with respect to their respective GND (GND1 for pins 11 to 20, GND2 for pins 1
to 10).
5.4.1
Voltage Supply
Table 5-4
Voltage Supply
Parameter
Symbol
Values
Unit
Note
Min.
Typ.
Max.
VUVLOH1
–
4.1
4.3
V
–
VUVLOL1
3.5
3.8
–
V
–
VHYS1
0.15
–
–
V
–
–
12.0
12.6
V
–
10.4
11.0
–
V
–
UVLO Hysteresis Output Chip VHYS2
(VUVLOH1 - VUVLOL1)
0.7
0.9
–
V
–
Quiescent Current Input Chip IQ1
–
7
9
mA
VVCC1 =5 V
IN+ = High,
IN- = Low
=>OUT = High,
RDY = High,
/FLT = High
Quiescent Current Output
Chip
–
4.5
6
mA
VVCC2 =15 V
VVEE2 =-8 V
IN+ = High,
IN- = Low
=>OUT = High,
RDY = High,
/FLT = High
UVLO Threshold Input Chip
UVLO Hysteresis Input Chip
(VUVLOH1 - VUVLOL1)
UVLO Threshold Output Chip VUVLOH2
VUVLOL2
Data Sheet
IQ2
16
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Electrical Parameters
5.4.2
Logic Input and Output
Table 5-5
Logic Input and Output
Parameter
Symbol
Values
Unit
Note
Min.
Typ.
Max.
IN+,IN-, RST Low Input Voltage VIN+L,
VIN-L,
VRSTL#
–
–
1.5
V
–
IN+,IN-, RST High Input Voltage VIN+H,
VIN-H,
VRSTH#
3.5
–
–
V
–
IN-, RST Input Current
IIN-, IRST#
–
100
400
μA
VIN- = GND1
VRST# = GND1
IN+ Input Current
IIN+,
–
100
400
μA
VIN+ = VCC1
RDY,FLT Pull Up Current
IPRDY, IPFLT#
–
100
400
μA
VRDY = GND1
VFLT# = GND1
Input Pulse Suppression IN+,
IN-
TMININ+,
TMININ-
30
40
–
ns
–
Input Pulse Suppression RST
for ENABLE/SHUTDOWN
TMINRST
30
40
–
ns
–
Pulse Width RST
for Reseting FLT
TRST
800
–
–
ns
–
FLT Low Voltage
VFLTL
–
–
300
mV
ISINK(FLT#) = 5 mA
RDY Low Voltage
VRDYL
–
–
300
mV
ISINK(RDY) = 5 mA
Data Sheet
17
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Electrical Parameters
5.4.3
Gate Driver
Table 5-6
Gate Driver
Parameter
Symbol
Values
Unit
Note
Min.
Typ.
Max.
VOUTH1
VVCC2-1.2
VVCC2-0.8
–
V
IOUTH = -20 mA
VOUTH2
VVCC2-2.5
VVCC2-2.0
–
V
IOUTH = -200 mA
VOUTH3
VVCC2-9
VVCC2-5
–
V
IOUTH = -1 A
VOUTH4
–
VVCC2-10
–
V
IOUTH = -2 A
High Level Output
Peak Current
IOUTH
-1.5
-2.0
–
A
IN+ = High, IN- = Low;
OUT = High
Low Level Output
Voltage
VOUTL1
–
VVEE2+0.04
VVEE2+0.09
V
IOUTL = 20 mA
VOUTL2
–
VVEE2+0.3
VVEE2+0.85
V
IOUTL = 200 mA
VOUTL3
–
VVEE2+2.1
VVEE2+5.0
V
IOUTL = 1 A
VOUTL4
–
VVEE2+7
–
V
IOUTL = 2 A
1.5
2.0
–
A
IN+ = Low, IN- = Low;
OUT = Low,
VVCC2 =15 V,
VVEE2 =-8 V
Unit
Note
High Level Output
Voltage
Low Level Output Peak IOUTL
Current
5.4.4
Active Miller Clamp
Table 5-7
Active Miller Clamp
Parameter
Symbol
Values
Min.
Typ.
Max.
VCLAMPL1
–
VVEE2+0.03
VVEE2 +0.08
V
IOUTL = 20 mA
VCLAMPL2
–
VVEE2+0.3
VVEE2 +0.8
V
IOUTL = 200 mA
VCLAMPL3
–
VVEE2+1.9
VVEE2 +4.8
V
Low Level Clamp
Current
ICLAMPL
2
–
–
A
IOUTL = 1 A
1)
Clamp Threshold
Voltage
VCLAMP
1.6
2.1
2.4
V
Related to VEE2
Low Level Clamp
Voltage
1) The parameter is not subject to production test - verified by design/characterization
Data Sheet
18
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Electrical Parameters
5.4.5
Short Circuit Clamping
Table 5-8
Short Circuit Clamping
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note
Clamping voltage (OUT)
(VOUT-VVCC2)
VCLPout
–
0.8
1.3
V
IN+=High, IN- = Low,
OUT = High
IOUT = 500 mA
(pulse test,
tCLPmax = 10 μs)
Clamping voltage
(CLAMP) (VVCLAMP-VVCC2)
VCLPclamp
–
1.3
–
V
IN+ = High, IN- = Low,
OUT = High
ICLAMP = 500 mA
(pulse test,
tCLPmax = 10 μs)
Clamping voltage (CLAMP)
VCLPclamp
–
0.7
1.1
V
IN+ = High, IN- = Low,
OUT = High
ICLAMP = 20 mA
5.4.6
Dynamic Characteristics
Dynamic characteristics are measured with VVCC1 = 5 V, VVCC2 = 15 V and VVEE2 = -8 V.
Table 5-9
Dynamic Characteristics
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note
IN+, IN- Input to output
propagation delay ON and
OFF
TPDON
1.5
1.75
2.0
μs
CTLSET = 0 pF,
CLOAD = 100 pF,
TA = 25°C
N+, IN- Input to output
propagation delay
distortion (TPDOFF-TPDON)
TPDISTO
-50
0
50
ns
CTLSET = 0 pF,
CLOAD = 100 pF,
TA = 25°C
N+, IN- Input to output
propagation delay ON and
OFF
TPDONt
1.5
1.9
2.3
μs
CTLSET = 0 pF,
CLOAD = 100 pF,
TA = 125°C
N+, IN- Input to output
propagation delay
distortion (TPDOFF-TPDON)
TPDISTOt
-20
45
70
ns
CTLSET = 0 pF,
CLOAD = 100 pF,
TA = 125°C
IN+, IN- Input to output
propagation delay ON and
OFF
TPDONt
1.45
1.75
2.05
μs
CTLSET = 0 pF,
CLOAD = 100 pF,
TA = -40°C
IN+ Input to output
propagation delay
distortion (TPDOFF-TPDON)
TPDISTOt
-60
-5
50
ns
CTLSET = 0 pF,
CLOAD = 100 pF,
TA = -40°C
Data Sheet
19
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Electrical Parameters
Table 5-9
Dynamic Characteristics (cont’d)
Parameter
Symbol
Rise Time
TRISE
Fall Time
5.4.7
TFALL
Values
Unit
Note
Min.
Typ.
Max.
10
30
60
ns
CLOAD = 1 nF,
VL 10%, VH 90%
150
400
800
ns
CLOAD = 34 nF
VL 10%, VH 90%
10
20
40
ns
CLOAD = 1 nF
VL 10%, VH 90%
100
250
500
ns
CLOAD = 34 nF
VL 10%, VH 90%
Unit
Note
Desaturation Protection
Table 5-10 Desaturation Protection
Parameter
Symbol
Values
Min.
Typ.
Max.
Blanking Capacitor Charge IDESATC
Current
450
500
550
μA
VVCC2 =15 V,
VVEE2 =-8 V
VDESAT = 2 V
Blanking Capacitor
Discharge Current
IDESATD
11
15
–
mA
VVCC2 =15 V,
VVEE2 =-8 V
VDESAT =6 V
Desaturation Reference
Level
VDESAT
8.5
9
9.5
V
VVCC2 =15 V
Desaturation Sense to OUT TDESATOUT
TLTO
–
250
320
ns
VOUT =90%
CLOAD = 1 nF
Desaturation Sense to FLT
Low Delay
TDESATFLT
–
–
2.25
μs
VFLT #=10%;
IFLT #=5 mA
Desaturation Low Voltage
VDESATL
40
70
110
mV
IN+=Low, IN-=Low,
OUT=Low
Data Sheet
20
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Electrical Parameters
5.4.8
Active Shut Down
Table 5-11 Active Shut Down
Parameter
Symbol
Active Shut Down Voltage
VACTSD1)
Values
Min.
Typ.
Max.
–
–
2.0
Unit
Note
V
IOUT = -200 mA,
VCC2 open
Unit
Note
1) With reference to VEE2
5.4.9
Two-level Turn-off
Table 5-12 Two-level Turn-off
Parameter
Symbol
Values
Min.
Typ.
Max.
External reference voltage
range (Zener-Diode)
VZDIODE
7.5
–
VCC2-0.5
V
–
Reference Voltage for setting
two-level delay time
VTLSET
6.6
7
7.3
V
–
Current for setting two-level
ITLSET
delay time and external
reference voltage (Zener-Diode)
420
500
550
μA
VTLSET = 10 V
External Capacitance Range
0
–
220
pF
–
Data Sheet
CTLSET
21
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Insulation Characteristics
6
Insulation Characteristics
Insulation characteristics are guaranteed only within the safety maximum ratings which must be ensured by
protective circuits in application. Surface mount classification is class A in accordance with CECCOO802.
This coupler is suitable for “basic insulation” only within the safety ratings. Compliance with the safety ratings
shall be ensured by means of suitable protective circuits.
6.1
Certified according to DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic
Insulation
Table 6-1
Certified according to DIN EN 60747-5-2
Description
Symbol
Characteristic
Unit
Installation classification per EN 60664-1, Table 1
for rated mains voltage ≤ 150 VRMS
for rated mains voltage ≤ 300 VRMS
for rated mains voltage ≤ 600 VRMS
I-IV
I-III
I-II
Climatic Classification
40/125/21
–
Pollution Degree (EN 60664-1)
2
–
–
Minimum External Clearance
CLR
8
mm
Minimum External Creepage
CPG
8
mm
Minimum Comparative Tracking Index
CTI
175
–
Maximum Repetitive Insulation Voltage
VIORM
1420
VPEAK
Highest Allowable Overvoltage
VIOTM
6000
VPEAK
Maximum Surge Insulation Voltage
VIOSM
6000
V
Description
Symbol
Characteristic
Unit
Insulation Withstand Voltage / 1 min
VISO
3750
Vrms
Insulation Test Voltage / 1 s
VISO
4500
Vrms
6.2
Recognized under UL 1577
Table 6-2
Recognized under UL 1577
6.3
Reliability
For Qualification Report please contact your local Infineon Technologies office.
Data Sheet
22
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Timing Diagrams
7
Timing Diagrams
All diagrams related to the Two-level switch-off feature
50%
IN+
90%
50%
OUT
10%
TPDON
Figure 7-1
TRISE
TPDOFF
TFALL
Propagation Delay, Rise and Fall Time
IN+
IN/RST
OUT
Figure 7-2
Principle Switching Behavior
IN+
V ZDIODE
VTLSET , typ. 7V
TLSET
TPD
TADJ1
V ZDIODE
TTLSET
TPD
TTLFALL
OUT
TPDONADJ
Figure 7-3
Data Sheet
TTLSET
Typical Switching Behavior
23
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Timing Diagrams
IN+
TPDON
OUT
TTLSET
TTLSET
TDESATOUT
TDESATOUT
VDESAT typ. 9V
DESAT
/FLT
TDESATFLT
TDESATFLT
/RST
>TRSTmin
Figure 7-4
DESAT Switch-OFF Behavior
IN+
TLSET
TPD
TTLSET
TTLSET
OUT
Figure 7-5
Data Sheet
TTLSET
TPDON
TPD
TPDON
TPDOFF
Short Switch ON Pulses
24
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Timing Diagrams
IN+
TLSET
TTLSET
TTLSET
TPD
Figure 7-6
TPD
TPDOFF
OUT
TTLSET
TPDON
TPDOFF
TPDON
TPDOFF
Short Switch OFF Pulses
IN+
TLSET
TPD
OUT
TTLSET
TPDON
TTLSET
TPDOFF
TTLSET
TPDOFF
TTLSET
TPD
TPDOFF
TPDON
forced turn off after three
consecutive on -cycles
Figure 7-7
Data Sheet
Short Switch OFF Pulses, Ringing Surpression
25
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Timing Diagrams
VUVLOH2
VCC2
IN+
TPDON
OUT
TPDOFF
I DESAT
RDY
Figure 7-8
VCC2 Ramp Up
VCC2
VUVLOH2
VUVLOL2
TPDD
TPDD
IN+
TPDD
TTLSET
TLSET
Vz
OUT
TPDON
RDY
/FLT
Figure 7-9
Data Sheet
VCC2 Ramp Down and VCC2 Drop
26
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Timing Diagrams
5
TTLSET [usec]
4
3
2
1
0
0
50
100
150
200
C TLSET [pF]
Figure 7-10 Typical TTLSET Time over CTLSET Capacitance
Data Sheet
27
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Package Outlines
8
Package Outlines
Figure 8-1
PG-DSO-20 (Plastic (Green) Dual Small Outline Package)
Data Sheet
28
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Application Notes
9
Application Notes
9.1
Reference Layout for Thermal Data
The PCB layout shown in Figure 9-1 represents the reference layout used for the thermal characterisation. Pins
11, 12, 19 and 20 (GND1) and pins 1, 2, 9 and 10 (VEE2) require ground plane connections for achiving
maximum power dissipation. The 1ED020I12FTA is conceived to dissipate most of the heat generated through
this pins.
Figure 9-1
Reference Layout for Thermal Data (Copper thickness 102 μm)
9.2
Printed Circuit Board Guidelines
Following factors should be taken into account for an optimum PCB layout.
•
•
•
•
Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits.
The same minimum distance between two adjacent high-side isolated parts of the PCB should be
maintained to increase the effective isolation and reduce parasitic coupling.
In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be
kept as short as possible.
Lowest trace length for VEE2 to GND2 decoupling could be achieved with capacitor closed to pins 2 and 4.
Data Sheet
29
Rev. 3.0
2016-04-05
1ED020I12FTA
Single IGBT Driver IC
Revision History
Page or Item
Subjects (major changes since previous revision)
Rev. 3.0, 2016-04-05
All
Update latest template
Page 8
removed Target Application Figure
Page 14
Editorial changes, typos:
- Symbol changed from Vmax2 to Vcc2 in Gate driver output
- Pin CLAMP voltage unit changed from °C to V
- Desaturation protection filter time changed
Page 6
Updated Block Diagram
Page 14,
Page 15,
Page 16,
Page 17,
Page 18,
Page 19,
Page 20,
Page 21
removed “Test Condition” from table header
Data Sheet
30
Rev. 3.0
2016-04-05
Please read the Important Notice and Warnings at the end of this document
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HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™,
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Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2016-04-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG.
All Rights Reserved.
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aspect of this document?
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