1EDIxxI12MH EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Features • • • • • • • Single channel isolated IGBT driver For 600 V/650 V/1200 V IGBTs Up to 3 A rail-to-rail output Active Miller clamp Galvanically isolated coreless transformer driver Wide input voltage operating range Suitable for operation at high ambient temperature Applications • • • • • • AC and brushless DC motor drives High voltage DC/DC-converter and DC/AC-inverter Induction heating resonant application UPS-systems Welding Solar Product Type Output current configuration Package 1EDI10I12MH ±1.0 A with 1.0 A Miller clamp PG-DSO-8-59 1EDI20I12MH ±2.0 A with 2.0 A Miller clamp PG-DSO-8-59 1EDI30I12MH ±3.0 A with 3.0 A Miller clamp PG-DSO-8-59 Description The 1EDI10I12MH, 1EDI20I12MH and 1EDI30I12MH are galvanically isolated single channel IGBT driver in a PG-DSO-8-59 package that provide output currents up to 3 A and an integrated active Miller clamp circuit with the same current rating to protect against parasitic turn on. The input logic pins operate on a wide input voltage range from 3 V to 15 V using scaled CMOS threshold levels to support even 3.3 V microcontroller. Data transfer across the isolation barrier is realized by the coreless transformer technology. Every driver family member comes with logic input and driver output under voltage lockout (UVLO) and active shutdown. VCC1 OUT IN+ IN- EiceDRIVERTM 1EDIxxI12MH CLAMP GND1 GND2,H VCC1 VCC2,L Control OUT IN+ TM IN- EiceDRIVER 1EDIxxI12MH CLAMP GND1 Preliminary Datasheet VCC2,H GND2,L Please read the Important Notice and Warnings at the end of this document www.infineon.com/eicedriver Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.1 2.2 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.4 3.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Active Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Non-Inverting and Inverting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Logic Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3.4 4.3.5 4.3.6 4.3.7 Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6 6.1 6.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reference Layout for Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Printed Circuit Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Preliminary Datasheet 2 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Table of Contents Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Preliminary Datasheet 3 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Block Diagram 1 Block Diagram VCC2 VCC1 1 2V UVLO 8 CLAMP 7 OUT 6 VCC2 5 GND2 & GND2 IN+ 2 input filter GND1 VCC2 & active filter TX RX & VCC1 IN- 3 input filter GND2 UVLO GND1 Figure 1 4 Block Diagram Preliminary Datasheet 4 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Pin Configuration and Functionality 2 Pin Configuration and Functionality 2.1 Pin Configuration Table 1 Pin Configuration Pin No. Name Function 1 VCC1 Positive logic supply 2 IN+ Non-inverted driver input (active high) 3 IN- Inverted driver input (active low) 4 GND1 Logic ground 5 GND2 Power ground 6 VCC2 Positive power supply voltage 7 OUT Driver output 8 CLAMP Active Miller clamp Figure 2 1 VCC1 CLAMP 8 2 IN+ OUT 7 3 IN- VCC2 6 4 GND1 GND2 5 PG-DSO-8-59 (top view) 2.2 Pin Functionality VCC1 Logic input supply voltage of 3.3 V up to 15 V wide operating range. IN+ Non Inverting Driver Input IN+ non-inverted control signal for driver output if IN- is set to low. (Output sourcing active at IN+ = high and IN= low) Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN+. An internal weak pull-down-resistor favors off-state. Preliminary Datasheet 5 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Pin Configuration and Functionality IN- Inverting Driver Input IN- inverted control signal for driver output if IN+ is set to high. (Output sourcing active at IN- = low and IN + = high) Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN-. An internal weak pull-up-resistor favors off-state. GND1 Ground connection of input circuit. GND2 Reference Ground Reference ground of the output driving circuit. VCC2 Positive power supply pin of output driving circuit. A proper blocking capacitor has to be placed close to this supply pin. OUT Driver Output Combined source and sink output pin to external IGBT. The output voltage will be switched between VCC2 and GND2 and is controlled by IN+ and IN-. In case of an UVLO event this output will be switched off and an active shut down keeps the output voltage at a low level. CLAMP Active Miller Clamp Connect gate of external IGBT directly to this pin. As soon as the gate voltage has dropped below 2 V referred to GND2 during turn off state the CLAMP function ties its output to GND2 to avoid parasitic turn on of the connected IGBT. Preliminary Datasheet 6 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Functional Description 3 Functional Description 3.1 Introduction The 1EDIxxI12MH is a general purpose IGBT gate driver. Basic control and protection features support fast and easy design of highly reliable systems. The integrated galvanic isolation between control input logic and driving output stage grants additional safety. Its wide input voltage supply range support the direct connection of various signal sources like DSPs and microcontrollers. With the rail-to-rail output and the additional active Miller clamp, dynamic turn on due to Miller capacitance is suppressed. 3.2 Supply The driver can operate over a wide supply voltage range. +5V VCC1 SGND IN Figure 3 +15V VCC2 1µ 100n 10R OUT GND1 IN+ CLAMP IN- GND2 Application Example The typical positive supply voltage for the driver is 15V at VCC2. Erratical dynamic turn on of the IGBT can be prevented with the active Miller clamp function, in which the CLAMP output is directly connected to the IGBT gate. Preliminary Datasheet 7 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Functional Description 3.3 Protection Features 3.3.1 Undervoltage Lockout (UVLO) IN+ VUVLOH1 VUVLOL1 VCC1 VUVLOH2 VUVLOL2 VCC2 OUT Figure 4 UVLO Behavior To ensure correct switching of IGBTs the device is equipped with an under voltage lockout for input and output independently. Operation starts only after both VCC levels have increased beyond the respective VUVLOH levels If the power supply voltage VVCC1 of the input chip drops below VUVLOL1 a turn-off signal is sent to the output chip before power-down. The IGBT is switched off and the signals at IN+ and IN- are ignored until VVCC1 reaches the power-up voltage VUVLOH1 again. If the power supply voltage VVCC2 of the output chip goes down below VUVLOL2 the IGBT is switched off and signals from the input chip are ignored until VVCC2 reaches the power-up voltage VUVLOH2 again. 3.3.2 Active Shut-Down The active shut-down feature ensures a safe IGBT off-state if the output chip is not connected to the power supply or an under voltage lockout is in effect. The IGBT gate is clamped at OUT to GND2. 3.3.3 Short Circuit Clamping During short circuit the IGBT’s gate voltage tends to rise because of the feedback via the Miller capacitance. An additional protection circuit connected to OUT and CLAMP limits this voltage to a value slightly higher than the supply voltage. A maximum current of 500 mA may be fed back to the supply through one of these paths for 10 μs. If higher currents are expected or tighter clamping is desired external Schottky diodes may be added. 3.3.4 Active Miller Clamp In a half bridge configuration the switched off IGBT tends to dynamically turn on during turn on phase of the opposite IGBT. A Miller clamp allows sinking the Miller current across a low impedance path in this high dV/dt situation. Therefore in many applications, the use of a negative supply voltage can be avoided. During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage drops below typical 2 V (referred to GND2). The clamp is designed for a Miller current in the same range as the nominal output current. Preliminary Datasheet 8 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Functional Description 3.4 Non-Inverting and Inverting Inputs IN+ IN- OUT Figure 5 Typical Switching Behavior There are two possible input modes to control the IGBT. At non-inverting mode IN+ controls the driver output while IN- is set to low. At inverting mode IN- controls the driver output while IN+ is set to high. A minimum input pulse width is defined to filter occasional glitches. 3.5 Driver Output The output driver section uses MOSFETs to provide a rail-to-rail output. This feature permits that tight control of gate voltage during on-state and short circuit can be maintained as long as the driver’s supply is stable. Due to the low internal voltage drop, switching behavior of the IGBT is predominantly governed by the gate resistor. Furthermore, it reduces the power to be dissipated by the driver. Preliminary Datasheet 9 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Electrical Parameters 4 Electrical Parameters 4.1 Absolute Maximum Ratings Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. Unless otherwise noted all parameters refer to GND1 Table 2 Absolute Maximum Ratings Parameter Symbol Values Min. Max. 201) Unit Note or Test Condition Power supply output side VVCC2 -0.3 V 2) Gate driver output VOUT VGND2-0.3 VVCC2+0.3 V 2) Maximum short circuit clamping time tCLP – 10 μs ICLAMP/OUT = 500 mA Positive power supply input side VVCC1 -0.3 18.0 V – Logic input voltages (IN+,IN-) VLogicIN -0.3 18.0 V – Pin CLAMP voltage VCLAMP -0.3 VVCC2 +0.31) V 2) Input to output isolation voltage (GND2) VGND2 -1200 1200 V GND2 - GND1 Junction temperature TJ -40 150 °C – Storage temperature TS -55 150 °C – Power dissipation (Input side) PD, IN – 25 mW 3) @T Power dissipation (Output side) PD, OUT – 400 mW 3) @T Thermal resistance (Input side) RTHJA,IN – 145 K/W 3) @T Thermal resistance (Output side) RTHJA,OUT – 165 K/W 3) @T ESD capability VESD,HBM – 2 kV Human body model4) VESD,CDM – 1 kV Charged device model5) 1 2 3 4 5 A = 25°C A = 25°C A = 85°C A = 85°C May be exceeded during short circuit clamping. With respect to GND2. See Figure 8 for reference layouts for these thermal data. Thermal performance may change significantly with layout and heat dissipation of components in close proximity. According to EIA/JESD22-A114-C (discharging a 100 pF capacitor through a 1.5 kΩ series resistor). According to EIA/JESD22-C101 (specified waveform characteristics) Preliminary Datasheet 10 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Electrical Parameters 4.2 Operating Parameters Note: Within the operating range the IC operates as described in the functional description. Unless otherwise noted all parameters refer to GND1. Table 3 Operating Parameters Parameter Symbol Values Min. Max. Unit Note or Test Condition Power supply output side VVCC2 13 18 V 6) Power supply input side VVCC1 3.1 17 V – Logic input voltages (IN+,IN-) VLogicIN -0.3 17 V – Pin CLAMP voltage VCLAMP VGND2-0.3 VVCC27) V 6) Switching frequency fsw – 1.0 MHz 8)9) Ambient temperature TA -40 125 °C – Thermal coefficient, junction-top Ψth,jt – 4.8 K/W @TA = 85°C Common mode transient immunity |dVISO/dt| – 100 kV/μs 9) @ 1000 V 4.3 Electrical Characteristics Note: The electrical characteristics include the spread of values in supply voltages, load and junction temperatures given below. Typical values represent the median values at TA = 25°C. Unless otherwise noted all voltages are given with respect to their respective GND (GND1 for pins 1 to 3, GND2 for pins 5 to 7). 4.3.1 Table 4 Voltage Supply Voltage Supply Parameter Symbol Values Min. UVLO threshold input chip UVLO hysteresis input chip (VUVLOH1 - VUVLOL1) 6 7 8 9 Typ. Unit Note or Test Condition Max. VUVLOH1 – 2.85 3.1 V – VUVLOL1 2.55 2.75 – V – VHYS1 0.09 0.10 – V – With respect to GND2. May be exceeded during short circuit clamping. do not exceed max. power dissipation Parameter is not subject to production test - verified by design/characterization Preliminary Datasheet 11 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Electrical Parameters Table 4 Voltage Supply (Continued) Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. UVLO threshold output chip (IGBT VUVLOH2 supply) VUVLOL2 – 11.9 12.7 V 10) 10.5 11.0 – V 10) UVLO hysteresis output chip (VUVLOH1 - VUVLOL1) VHYS2 0.7 0.85 – V – Quiescent current input chip IQ1 – 0.6 1 mA VVCC1 = 5 V IN+ = High, IN- = Low =>OUT = High Quiescent current output chip IQ2 – 1.2 2 mA VVCC2 = 15 V IN+ = High, IN- = Low =>OUT = High Unit Note or Test Condition 4.3.2 Table 5 Logic Input Logic Input Parameter Symbol Values Min. Typ. Max. IN+,IN- low input voltage VIN+L, VIN-L – – 30 % of VCC1 IN+,IN- high input voltage VIN+H, VIN- 70 – – % of VCC1 VIN+L,VIN-L – – 1.5 V VCC1 = 5.0V VIN+H,VIN- 3.5 – – V VCC1 = 5.0V H IN+,IN- low input voltage IN+,IN- high input voltage H IN- input current IIN- – 70 200 μA VIN- = GND1, VCC1 = 5.0V IN+ input current IIN+, – 70 200 μA VIN+ = VCC1, VCC1 = 5.0V 10 With respect to GND2. Preliminary Datasheet 12 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Electrical Parameters 4.3.3 Gate Driver Note: minimum Peak current rating valid over temperature range! Table 6 Gate Driver Parameter Symbol Values Min. High level output peak current (source) 1EDI10I12MH 1EDI20I12MH 1EDI30I12MH IOUT,H,PEAK Low level output peak current 1EDI10I12MH 1EDI20I12MH 1EDI30I12MH IOUT,L,PEAK 4.3.4 Table 7 Typ. Note or Test Condition A 11) Max. – 1.0 2.0 3.0 Unit IN+ = High, IN- = Low, VVCC2 = 15 V 1.9 3.5 5.2 – 1.0 2.0 3.0 A 1.7 3.2 4.5 IN+ = Low, IN- = Low, VVCC2 = 15 V Short Circuit Clamping Short Circuit Clamping Parameter Symbol Values Min. Typ. Unit Note or Test Condition 12)IN+ = High, IN- = Max. Clamping voltage (OUT) (VOUT - VVCC2) VCLPout – 0.9 1.3 V Clamping voltage (CLAMP) (VVCLAMP-VVCC2) VCLPclamp1 – 1.3 – V Clamping voltage (CLAMP) VCLPclamp2 – 0.7 1.1 V 11 12 11) Low, IOUT = 500 mA (pulse test tCLPmax = 10 μs) 12)IN+ = High, IN- = Low, ICLAMP = 500 mA (pulse test tCLPmax = 10 μs) 12)IN+ = High, IN- = Low, ICLAMP = 20 mA specified min. output current is forced; voltage across the device V(VCC2 - OUT) or V(OUT - GND2) < VVCC2. With respect to GND2. Preliminary Datasheet 13 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Electrical Parameters 4.3.5 Table 8 Active Miller Clamp Active Miller Clamp Parameter Symbol Values Min. Typ. ICLAMP,PEA Low level clamp current 1EDI10I12MH 1EDI20I12MH 1EDI30I12MH K Clamp threshold voltage VCLAMP 4.3.6 – Unit Note or Test Condition A 13) Max. – IN+ = Low, IN- = Low, VCLAMP = 15 V pulsed tpulse = 2 μs 1.0 2.0 3.0 1.6 2.0 2.4 V 14) Dynamic Characteristics Dynamic characteristics are measured with VVCC1 = 5 V and VVCC2 = 15 V. 50% IN+ 80% 50% 20% OUT TPDON Figure 6 Propagation Delay, Rise and Fall Time Table 9 Dynamic Characteristics Parameter TRISE TPDOFF Symbol Values Min. Typ. TFALL Unit Note or Test Condition CLOAD = 100 pF VIN+ = 50%, VOUT=50% @ 25°C Max. Input IN to output propagation delay ON TPDON 270 300 330 ns Input IN to output propagation delay OFF TPDOFF 270 300 330 ns Input IN to output propagation delay distortion (TPDOFF - TPDON) TPDISTO -30 5 40 ns Input pulse suppression time IN+, TMININ+, INTMININ- 230 240 – ns 13 14 Parameter is not subject to production test - verified by design/characterization With respect to GND2. Preliminary Datasheet 14 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Electrical Parameters Table 9 Dynamic Characteristics (Continued) Parameter Symbol Values Min. Typ. ns 15)C VIN+ = 50%, VOUT=50% Max. TPDONt IN input to output propagation delay OFF variation due to temp TPDONt – – 14 ns IN input to output propagation delay distortion variation due to temp (TPDOFF-TPDON) TPDISTOt – – 8 ns Rise time TRISE 5 10 20 ns Fall time TFALL 3 9 19 ns Table 10 – Note or Test Condition IN input to output propagation delay ON variation due to temp 4.3.7 – Unit 14 LOAD = 100 pF CLOAD = 1 nF VL 20%, VH 80% Active Shut Down Active Shut Down Parameter Symbol Values Min. Active shut down voltage VACTSD Typ. – 2.0 Unit Note or Test Condition V 16)I Max. 2.3 OUT/IOUT,PEAK=0.1, VCC2 open 15 16 Parameter is not subject to production test - verified by design/characterization With respect to GND2. Preliminary Datasheet 15 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Package Outline 5 Package Outline DOCUMENT NO. Z8B00179262 A A1 A2 b c D E E1 e N L L2 h MILLIMETERS MIN MAX 2.65 0.10 0.20 2.25 2.45 0.30 0.50 0.23 0.32 6.20 6.40 10.00 10.60 7.40 7.60 1.27 BSC 8 0.50 0.90 0.25 BSC 0.25 0.45 ccc ddd 0.10 0.25 DIM Figure 7 INCHES MIN 0.004 0.089 0.012 0.009 0.244 0.394 0.291 SCALE MAX 0.104 0.008 0.096 0.020 0.013 0.252 0.417 0.299 0 2 0 2 4mm EUROPEAN PROJECTION 0.050 BSC 8 0.020 0.035 0.010 BSC 0.010 0.018 0.004 0.010 ISSUE DATE 05.11.2015 REVISION 01 PG-DSO-8-59 (Plastic (Green) Dual Small Outline Package) Preliminary Datasheet 16 Rev. 1.0 2016-04-14 EiceDRIVER™ 1EDI Compact Single channel IGBT gate driver IC with clamp in wide body package Application Notes 6 Application Notes 6.1 Reference Layout for Thermal Data Figure 8 Reference Layout for Thermal Data (Copper thickness 35 μm) This PCB layout represents the reference layout used for the thermal characterization. Pin 4 (GND1) and pin 5 (GND2) require each a ground plane of 100 mm² for achieving maximum power dissipation. The package is built to dissipate most of the heat generated through these pins. The thermal coefficient junction-top (Ψth,jt) can be used to calculate the junction temperature at a given top case temperature and driver power dissipation: 6.2 Printed Circuit Board Guidelines The following factors should be taken into account for an optimum PCB layout. • Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits. • The same minimum distance between two adjacent high-side isolated parts of the PCB should be maintained to increase the effective isolation and to reduce parasitic coupling. • In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be kept as short as possible. Revision History Page or Item Subjects (major changes since previous revision) Rev. 1.0, 2016-04-14 el. Parameters missing product parameters updated Rev. 0.51, 2015-11-05 all pages change of template, standardized package drawing included Rev. 0.50, 2014-05-06 all pages Preliminary Datasheet initial version 17 Rev. 1.0 2016-04-14 Trademarks of Infineon Technologies AG µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™. Trademarks Update 2015-12-22 Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2016-04-14 Published by Infineon Technologies AG 81726 Munich, Germany © 2016 Infineon Technologies AG All Rights Reserved. Do you have a question about any aspect of this document? Email: [email protected] Document reference IFX-sch1433998947775 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 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