Data Sheet

PH2525L
N-channel TrenchMOS logic level FET
Rev. 02 — 5 December 2006
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
n Logic level threshold
n Optimized for use in DC-to-DC
converters
n 100 % RG tested
n Lead-free package
n Very low switching and conduction
losses
1.3 Applications
n DC-to-DC converters
n Voltage regulators
n Switched-mode power supplies
n PC Motherboards
1.4 Quick reference data
n VDS ≤ 25 V
n RDSon ≤ 2.5 mΩ
n ID ≤ 100 A
n QGD = 6.8 nC (typ)
2. Pinning information
Table 1.
Pin
Pinning
Description
1, 2, 3
source (S)
4
gate (G)
mb
mounting base; connected to drain (D)
Simplified outline
Symbol
D
mb
G
mbb076
1 2 3 4
SOT669 (LFPAK)
S
PH2525L
NXP Semiconductors
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2.
Ordering information
Type number
PH2525L
Package
Name
Description
Version
LFPAK
plastic single-ended surface-mounted package; 4 leads
SOT669
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 150 °C
-
25
V
VDGR
drain-gate voltage (DC)
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
-
25
V
VGS
gate-source voltage
-
±20
V
ID
drain current
Tmb = 25 °C; VGS = 10 V; see Figure 2 and 3
-
100
A
Tmb = 100 °C; VGS = 10 V; see Figure 2
-
76.7
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
-
300
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 1
-
62.5
W
Tstg
storage temperature
−55
+150
°C
Tj
junction temperature
−55
+150
°C
Source-drain diode
IS
source current
Tmb = 25 °C
-
52
A
ISM
peak source current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
-
208
A
unclamped inductive load; ID = 80 A;
tp = 0.22 ms; VDS ≤ 25 V; RGS = 50 Ω;
VGS = 10 V; starting at Tj = 25 °C
-
320
mJ
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
PH2525L_2
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 02 — 5 December 2006
2 of 12
PH2525L
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa15
120
003aab426
120
Pder
Ider
(%)
(%)
80
80
40
40
0
0
0
50
100
0
200
150
50
100
Tmb (°C)
P tot
P der = ------------------------ × 100 %
P tot ( 25°C )
150
200
Tmb (°C)
ID
I der = -------------------- × 100 %
I D ( 25°C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
003aab427
103
Limit RDSon = VDS / ID
ID
(A)
tp = 10 µs
102
100 µs
1 ms
DC
10
10 ms
100 ms
1
10-1
1
10
102
VDS (V)
Tmb = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH2525L_2
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 02 — 5 December 2006
3 of 12
PH2525L
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4.
Thermal characteristics
Symbol Parameter
Conditions
thermal resistance from junction to mounting base see Figure 4
Rth(j-mb)
Min
Typ
Max
Unit
-
-
2
K/W
003aab428
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
10-1
0.05
δ=
P
tp
T
0.02
single pulse
t
tp
10-2
10-5
T
10-4
10-3
10-2
10-1
1
tp (s)
10
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PH2525L_2
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 02 — 5 December 2006
4 of 12
PH2525L
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5.
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tj = 25 °C
25
-
-
V
Tj = −55 °C
22.5
-
-
V
Static characteristics
V(BR)DSS drain-source breakdown
voltage
VGS(th)
IDSS
gate-source threshold voltage
drain leakage current
ID = 250 µA; VGS = 0 V
ID = 1 mA; VDS = VGS; see Figure 9 and 10
Tj = 25 °C
1.3
1.7
2.15
V
Tj = 150 °C
0.8
-
-
V
Tj = −55 °C
-
-
2.6
V
VDS = 25 V; VGS = 0 V
Tj = 25 °C
-
-
1
µA
Tj = 150 °C
-
-
100
µA
IGSS
gate leakage current
VGS = ±16 V; VDS = 0 V
-
-
100
nA
RG
gate resistance
f = 1 MHz
-
0.7
-
Ω
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 25 A; see Figure 6 and 8
Tj = 25 °C
-
1.8
2.5
mΩ
Tj = 150 °C
-
3.1
4.25
mΩ
VGS = 4.5 V; ID = 25 A; see Figure 6 and 8
-
2.6
3.9
mΩ
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 11 and 12
-
34.7
-
nC
-
14.4
-
nC
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGS1
pre-VGS(th) gate-source charge
-
7.2
-
nC
QGS2
post-VGS(th) gate-source charge
-
7.2
-
nC
QGD
gate-drain charge
-
6.8
-
nC
VGS(pl)
gate-source plateau voltage
-
2.9
-
V
QG(tot)
total gate charge
ID = 0 A; VDS = 0 V; VGS = 4.5 V
-
27.6
-
nC
VGS = 0 V; VDS = 12 V; f = 1 MHz;
see Figure 14
-
4470
-
pF
-
1070
-
pF
-
470
-
pF
5120
-
pF
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer capacitance
Ciss
input capacitance
VGS = 0 V; VDS = 0 V; f = 1 MHz
-
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG = 5.6 Ω
-
41
-
ns
-
92
-
ns
td(on)
turn-on delay time
tr
rise time
td(off)
turn-off delay time
-
53
-
ns
tf
fall time
-
37
-
ns
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; see Figure 13
-
0.77
1.2
V
trr
reverse recovery time
IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V
-
50
-
ns
Qr
recovered charge
-
22
-
nC
PH2525L_2
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 02 — 5 December 2006
5 of 12
PH2525L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab429
100
10
ID
(A)
4.5
3.6
3.4
003aab430
20
2.8
RDSon
(mΩ)
80
3
16
3.2
VGS (V) = 3.2
12
60
3
40
8
3.4
2.8
20
3.6
4.5
10
4
2.6
VGS (V) = 2.4
0
0
0.2
0.4
0.6
0.8
VDS (V)
0
0
1
Tj = 25 °C
20
40
60
80
ID (A)
100
Tj = 25 °C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of drain current; typical values
003aab431
100
ID
(A)
003aab467
2
a
80
1.6
60
1.2
40
0.8
Tj = 150 °C
25 °C
20
0.4
0
0
1
2
3
VGS (V)
4
Tj = 25 °C and 150 °C; VDS > ID × RDSon
0
-60
60
120
Tj (°C)
180
R DSon
a = ----------------------------R DSon ( 25°C )
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
PH2525L_2
Product data sheet
0
© NXP B.V. 2006. All rights reserved.
Rev. 02 — 5 December 2006
6 of 12
PH2525L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab272
3
VGS(th)
(V)
2.5
003aab271
10-3
ID
(A)
max
10-4
2
min
typ
1.5
typ
max
min
10-5
1
0.5
0
-60
10-6
0
60
120
Tj (°C)
180
0
0.5
1
1.5
2
VGS (V)
2.5
Tj = 25 °C; VDS = 5 V
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
003aab432
10
ID = 25 A
Tj = 25 °C
VGS
(V)
8
VDS
ID
6
12 V
VDS = 19 V
VGS(pl)
4
VGS(th)
VGS
2
QGS1
QGS2
QGS
0
0
30
60
QG (nC)
90
QGD
QG(tot)
003aaa508
ID = 25 A; VDS = 12 V and 19 V
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Gate charge waveform definitions
PH2525L_2
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 02 — 5 December 2006
7 of 12
PH2525L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab433
100
003aab434
104
IS
(A)
80
Ciss
C
(pF)
60
103
Coss
40
150 °C
Crss
Tj = 25 °C
20
0
0.2
0.4
0.6
0.8
VSD (V)
102
10-1
1
Tj = 25 °C and 150 °C; VGS = 0 V
1
10
VDS (V)
102
VGS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain
voltage; typical values
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aab435
104
Ciss
C
(pF)
Crss
103
10-1
1
VGS (V)
10
VDS = 0 V; f = 1 MHz
Fig 15. Input and reverse transfer capacitances as a function of gate-source voltage; typical values
PH2525L_2
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 02 — 5 December 2006
8 of 12
PH2525L
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
A2
A
E
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
e
4
w M A
b
X
c
1/2 e
A
(A 3)
A1
C
θ
L
detail X
y C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
A1
A2
A3
b
b2
1.20 0.15 1.10
0.50 4.41
0.25
1.01 0.00 0.95
0.35 3.62
b3
b4
2.2
2.0
0.9
0.7
c
D (1)
c2
D1(1)
E(1) E1(1)
max
0.25 0.30 4.10
4.20
0.19 0.24 3.80
5.0
4.8
3.3
3.1
e
H
L
L1
L2
w
y
θ
1.27
6.2
5.8
0.85
0.40
1.3
0.8
1.3
0.8
0.25
0.1
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT669
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-10-13
06-03-16
MO-235
Fig 16. Package outline SOT669 (LFPAK)
PH2525L_2
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 02 — 5 December 2006
9 of 12
PH2525L
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 6.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PH2525L_2
20061205
Product data sheet
-
PH2525L_1
-
-
Modifications:
PH2525L_1
•
Section 1.2: updated the list
20061010
Product data sheet
PH2525L_2
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 02 — 5 December 2006
10 of 12
PH2525L
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
PH2525L_2
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 02 — 5 December 2006
11 of 12
PH2525L
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
11
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 5 December 2006
Document identifier: PH2525L_2
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