Data Sheet

PH3330L
N-channel TrenchMOS logic level FET
Rev. 02 — 22 October 2008
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ High efficiency due to low switching
and conduction losses
„ Suitable for logic level gate drive
sources
1.3 Applications
„ DC-to-DC converters
„ Switched-mode power supplies
„ Notebook computers
„ Voltage regulators
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C
-
-
30
V
ID
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1; see Figure 3
-
-
100
A
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
62.5
W
VGS = 4.5 V; ID = 25 A;
VDS = 12 V; see Figure 12;
see Figure 13
-
6.9
-
nC
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 10;
see Figure 11
-
2.3
3.3
mΩ
Dynamic characteristics
QGD
gate-drain charge
Static characteristics
RDSon
drain-source
on-state resistance
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
Symbol
Description
Simplified outline
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
Graphic symbol
D
mb
G
S
mbb076
1 2 3 4
SOT669
(LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
PH3330L
LFPAK
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
SOT669
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 150 °C
-
30
V
VDGR
drain-gate voltage
Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 kΩ
-
30
V
VGS
gate-source voltage
-20
20
V
ID
drain current
VGS = 10 V; Tmb = 25 °C; see Figure 1; see Figure
3
-
100
A
VGS = 10 V; Tmb = 100 °C; see Figure 1
-
54.2
A
-
300
A
IDM
peak drain current
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
62.5
W
Tstg
storage temperature
-55
150
°C
Tj
junction temperature
-55
150
°C
Source-drain diode
IS
source current
Tmb = 25 °C
-
52
A
ISM
peak source current
tp ≤ 10 µs; pulsed; Tmb = 25 °C
-
208
A
-
245
mJ
Avalanche ruggedness
EDS(AL)S
non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 70 A; Vsup ≤ 30 V;
drain-source avalanche tp = 0.15 ms; RGS = 50 Ω; unclamped
energy
PH3330L_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 22 October 2008
2 of 13
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa23
120
03aa15
120
Ider
(%)
Pder
(%)
80
80
40
40
0
0
0
50
100
150
200
0
50
100
150
Tmb (°C)
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
200
Tmb (°C)
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aab259
103
ID
(A)
Limit RDSon = VDS / ID
tp = 10 μ s
102
100 μ s
1 ms
DC
10
10 ms
100 ms
1
10-1
Fig 3.
1
10
102
VDS (V)
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH3330L_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 22 October 2008
3 of 13
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-mb)
thermal resistance from see Figure 4
junction to mounting
base
Min
Typ
Max
Unit
-
-
2
K/W
003aab260
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
0.05
10-1
δ=
P
0.02
tp
T
single pulse
t
tp
T
10
Fig 4.
-2
10-5
10-4
10-3
10-2
10-1
1
tp (s)
10
Transient thermal impedance from junction to mounting base as a function of pulse duration
PH3330L_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 22 October 2008
4 of 13
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
VGS(th)
IDSS
IGSS
RDSon
RG
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
30
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
27
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C; see
Figure 8; see Figure 9
1.3
1.7
2.15
V
ID = 1 mA; VDS = VGS; Tj = 150 °C; see
Figure 8; see Figure 9
0.8
-
-
V
ID = 1 mA; VDS = VGS; Tj = -55 °C; see
Figure 8; see Figure 9
-
-
2.6
V
VDS = 30 V; VGS = 0 V; Tj = 25 °C
-
-
1
µA
VDS = 30 V; VGS = 0 V; Tj = 150 °C
-
-
100
µA
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = 10 V; ID = 25 A; Tj = 25 °C; see
Figure 10; see Figure 11
-
2.3
3.3
mΩ
VGS = 10 V; ID = 25 A; Tj = 150 °C; see
Figure 11; see Figure 10
-
4.1
6
mΩ
VGS = 4.5 V; ID = 25 A; Tj = 25 °C; see
Figure 10; see Figure 11
-
3.4
4.5
mΩ
f = 1 MHz
-
0.7
-
Ω
ID = 25 A; VDS = 12 V; VGS = 4.5 V; see
Figure 12; see Figure 13
-
30.5
-
nC
ID = 0 A; VDS = 0 V; VGS = 4.5 V
-
28.5
-
nC
ID = 25 A; VDS = 12 V; VGS = 4.5 V; see
Figure 12; see Figure 13
-
15.4
-
nC
-
7.7
-
nC
-
7.7
-
nC
drain leakage current
gate leakage current
drain-source on-state
resistance
gate resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGS1
pre-threshold
gate-source charge
QGS2
post-threshold
gate-source charge
QGD
gate-drain charge
-
6.9
-
nC
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 12 V; see Figure 12; see
Figure 13
-
3.4
-
V
Ciss
input capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 14
-
4840
-
pF
VDS = 0 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C
-
5380
-
pF
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 14
-
960
-
pF
-
410
-
pF
Coss
output capacitance
Crss
reverse transfer
capacitance
PH3330L_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 22 October 2008
5 of 13
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
td(on)
turn-on delay time
-
41
-
ns
tr
rise time
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 5.6 Ω
-
75
-
ns
td(off)
turn-off delay time
-
52
-
ns
tf
fall time
-
27
-
ns
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C; see
Figure 15
-
0.82
1.2
V
trr
reverse recovery time
-
52
-
ns
Qr
recovered charge
IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V;
VDS = 25 V
-
23
-
nC
PH3330L_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 22 October 2008
6 of 13
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab261
100
VGS (V) = 10
ID
(A)
5 4.5
3.8
3.6
3.4
003aab263
100
ID
(A)
80
80
60
60
3.2
40
40
3
Tj = 150 °C
20
20
2.8
25 °C
2.6
0
0
0
Fig 5.
0.2
0.4
0.6
VDS (V)
0.8
Output characteristics: drain current as a
function of drain-source voltage; typical values
0
Fig 6.
003aab267
104
1
2
3
VGS (V)
4
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
003aab272
3
Ciss
VGS(th)
(V)
C
(pF)
max
2
typ
Crss
103
1.5
min
1
0.5
102
10-1
Fig 7.
1
VGS (V)
0
-60
10
60
120
180
Tj (°C)
Input and reverse transfer capacitances as a
function of gate-source voltage; typical values
Fig 8.
Gate-source threshold voltage as a function of
junction temperature
PH3330L_2
Product data sheet
0
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 22 October 2008
7 of 13
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab271
10−3
003aab262
10
VGS (V) = 3
RDSon
(mΩ)
ID
(A)
3.2
3.4
8
10−4
max
typ
min
6
3.6
3.8
4
4.5
5
10−5
10
2
10−6
0
0
Fig 9.
0.5
1
1.5
2
Sub-threshold drain current as a function of
gate-source voltage
003aab273
2
0
2.5
VGS (V)
40
60
ID (A)
100
003aab264
10
ID = 25 A
Tj = 25 °C
1.6
8
1.2
6
VDS = 19 V
12 V
0.8
4
0.4
2
0
-60
80
Fig 10. Drain-source on-state resistance as a function
of drain current; typical values
VGS
(V)
a
20
0
0
60
120
Tj (°C)
180
0
20
40
60
QG (nC)
80
Fig 12. Gate-source voltage as a function of gate
charge; typical values
Fig 11. Normalized drain-source on-state resistance
factor as a function of junction temperature
PH3330L_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 22 October 2008
8 of 13
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab266
104
VDS
Ciss
C
(pF)
ID
VGS(pl)
VGS(th)
103
Coss
VGS
QGS1
QGS2
QGS
Crss
QGD
QG(tot)
003aaa508
102
10-1
Fig 13. Gate charge waveform definitions
1
10
VDS (V)
102
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aab265
100
IS
(A)
80
60
40
20
0
0.2
150 °C
0.4
0.6
Tj = 25 °C
0.8
VSD (V)
1
Fig 15. Source current as a function of source-drain voltage; typical values
PH3330L_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 22 October 2008
9 of 13
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
A2
A
E
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
e
4
w M A
b
1/2
X
c
e
A
(A 3)
A1
C
θ
L
detail X
y C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
A1
A2
A3
b
b2
1.20 0.15 1.10
0.50 4.41
0.25
1.01 0.00 0.95
0.35 3.62
b3
b4
2.2
2.0
0.9
0.7
c
D (1)
c2
D1(1)
E(1) E1(1)
max
0.25 0.30 4.10
4.20
0.19 0.24 3.80
5.0
4.8
3.3
3.1
e
H
L
L1
L2
w
y
θ
1.27
6.2
5.8
0.85
0.40
1.3
0.8
1.3
0.8
0.25
0.1
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT669
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-10-13
06-03-16
MO-235
Fig 16. Package outline SOT669 (LFPAK)
PH3330L_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 22 October 2008
10 of 13
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PH3330L_2
20081022
Product data sheet
-
PH3330L_1
Modifications:
PH3330L_1
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
20060201
Product data sheet
-
PH3330L_2
Product data sheet
-
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 22 October 2008
11 of 13
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status [1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PH3330L_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 22 October 2008
12 of 13
PH3330L
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . .12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 22 October 2008
Document identifier: PH3330L_2
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