Data Sheet

PHD97NQ03LT
N-channel TrenchMOS logic level FET
Rev. 01 — 24 March 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Fast switching
„ Low on-state resistance
„ Lead-free packing
„ Suitable for high frequency
applications due to fast switching
characteristics
„ Logic level threshold
1.3 Applications
„ Computer motherboard high
frequency DC-to-DC convertors
„ Switched-mode power supplies
„ Voltage regulators
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
25
V
ID
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1; see Figure 3
-
-
75
A
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
107
W
VGS = 4.5 V; ID = 25 A;
VDS = 12 V; see Figure 9;
see Figure 10
-
1.9
-
nC
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 7;
see Figure 8
-
5.3
6.3
mΩ
Dynamic characteristics
QGD
gate-drain charge
Static characteristics
RDSon
drain-source
on-state resistance
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
Symbol
Description
Simplified outline
1
G
gate
2
D
drain
3
S
source
mb
D
mounting base; connected to
drain
Graphic symbol
D
mb
G
S
mbb076
2
1
3
SOT428
(SC-63; DPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
PHD97NQ03LT
SC-63; DPAK
Description
plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped)
Version
SOT428
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
25
V
VDGR
drain-gate voltage
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
25
V
VGS
gate-source voltage
-20
20
V
ID
drain current
VGS = 10 V; Tmb = 100 °C; see Figure 1
-
69
A
VGS = 10 V; Tmb = 25 °C; see Figure 1; see Figure 3
-
75
A
IDM
peak drain current
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
-
300
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
107
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
Source-drain diode
IS
source current
Tmb = 25 °C
-
75
A
ISM
peak source current
tp ≤ 10 µs; pulsed; Tmb = 25 °C
-
240
A
-
60
mJ
Avalanche ruggedness
EDS(AL)S
non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 35 A; Vsup ≤ 25 V;
drain-source avalanche unclamped; tp = 0.1 ms; RGS = 50 Ω
energy
PHD97NQ03LT_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 24 March 2009
2 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab533
120
03aa16
120
Ider
(%)
Pder
(%)
80
80
40
40
0
0
0
50
100
150
200
0
50
100
Tj (°C)
Fig 1.
150
200
Tmb (°C)
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aab556
103
ID
(A)
RDSon = VDS / ID
tp = 10 μs
102
100 μs
DC
10
1 ms
10 ms
1
10−1
1
102
10
VDS (V)
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHD97NQ03LT_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 24 March 2009
3 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance from junction to
mounting base
see Figure 4
-
-
1.4
K/W
Rth(j-a)
thermal resistance from junction to
ambient
minimum footprint
-
75
-
K/W
[1]
[1]
Mounted on a printed-circuit board; vertical in still air
003aab535
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
10-1
0.05
0.02
δ=
P
tp
T
single pulse
t
tp
10
T
-2
10-5
Fig 4.
10-4
10-3
10-2
10-1
1
tp (s)
10
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHD97NQ03LT_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 24 March 2009
4 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
VGS(th)
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
25
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
22
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 5; see Figure 6
1.3
1.7
2.15
V
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 5
0.7
-
-
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 5
-
-
2.6
V
IDSS
drain leakage current
VDS = 25 V; VGS = 0 V; Tj = 25 °C
-
-
1
µA
IGSS
gate leakage current
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = 10 V; ID = 25 A; Tj = 175 °C;
see Figure 7; see Figure 8
-
10.1
12
mΩ
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
see Figure 7; see Figure 8
-
8
10.6
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 7; see Figure 8
-
5.3
6.3
mΩ
RDSon
drain-source on-state
resistance
IDSS
drain leakage current
VDS = 25 V; VGS = 0 V; Tj = 175 °C
-
-
100
µA
RG
gate resistance
f = 1 MHz
-
1.5
-
Ω
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 9; see Figure 10
-
11.7
-
nC
ID = 0 A; VDS = 0 V; VGS = 4.5 V
-
10.2
-
nC
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 9; see Figure 10
-
6.2
-
nC
-
3.4
-
nC
-
2.8
-
nC
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGS1
pre-threshold
gate-source charge
QGS2
post-threshold
gate-source charge
QGD
gate-drain charge
-
1.9
-
nC
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 12 V; see Figure 9; see
Figure 10
-
3.1
-
V
Ciss
input capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 11
-
1570
-
pF
VDS = 0 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C
-
1800
-
pF
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 11
-
380
-
pF
-
160
-
pF
Coss
output capacitance
Crss
reverse transfer
capacitance
PHD97NQ03LT_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 24 March 2009
5 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
td(on)
turn-on delay time
-
18
-
ns
tr
rise time
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 5.6 Ω
-
33
-
ns
td(off)
turn-off delay time
-
20
-
ns
tf
fall time
-
12
-
ns
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 12
-
0.87
1.2
V
trr
reverse recovery time
-
38
-
ns
Qr
recovered charge
IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 30 V
-
14
-
nC
003aab272
3
003aab271
10−3
ID
(A)
VGS(th)
(V)
max
10−4
2
max
typ
min
typ
1.5
min
10−5
1
0.5
0
-60
10−6
0
60
120
180
0
Tj (°C)
Fig 5.
Gate-source threshold voltage as a function of
junction temperature
Fig 6.
1
1.5
2
2.5
VGS (V)
Sub-threshold drain current as a function of
gate-source voltage
PHD97NQ03LT_1
Product data sheet
0.5
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 24 March 2009
6 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab467
2
a
1.6
20
1.2
15
0.8
10
0.4
5
0
−60
VGS (V) = 3.3
3.7
4.1
4.5
5
6
10
0
0
60
120
0
180
Normalized drain-source on-state resistance
factor as a function of junction temperature
40
60
ID (A)
80
Drain-source on-state resistance as a function
of drain current; typical values
003aab539
10
VDS
ID = 25 A
Tj = 25 °C
VGS
(V)
20
Tj (°C)
Fig 8.
Fig 7.
003aab537
25
RDSon
(mΩ)
ID
8
VGS(pl)
6
VDS = 19 V
12 V
VGS(th)
VGS
4
QGS1
QGS2
QGS
2
QGD
QG(tot)
003aaa508
0
0
Fig 9.
10
20
QG (nC)
30
Fig 10. Gate charge waveform definitions
Gate-source voltage as a function of gate
charge; typical values
PHD97NQ03LT_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 24 March 2009
7 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab542
104
003aab541
80
IS
(A)
C
(pF)
60
Ciss
3
10
40
Tj = 25 °C
175 °C
20
Coss
Crss
102
10-1
1
10
VDS (V)
102
Fig 11. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
0
0
0.8
VSD (V)
1.2
Fig 12. Source current as a function of source-drain
voltage; typical values
PHD97NQ03LT_1
Product data sheet
0.4
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 24 March 2009
8 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)
SOT428
y
E
A
A
A1
b2
E1
mounting
base
D2
D1
HD
2
L
L2
1
L1
3
b1
b
w
M
c
A
e
e1
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
b1
b2
c
D1
D2
min
E
E1
min
e
e1
HD
L
L1
min
L2
w
y
max
mm
2.38
2.22
0.93
0.46
0.89
0.71
1.1
0.9
5.46
5.00
0.56
0.20
6.22
5.98
4.0
6.73
6.47
4.45
2.285
4.57
10.4
9.6
2.95
2.55
0.5
0.9
0.5
0.2
0.2
OUTLINE
VERSION
SOT428
REFERENCES
IEC
JEDEC
JEITA
TO-252
SC-63
EUROPEAN
PROJECTION
ISSUE DATE
06-02-14
06-03-16
Fig 13. Package outline SOT428 (DPAK)
PHD97NQ03LT_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 24 March 2009
9 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PHD97NQ03LT_1
20090324
Product data sheet
-
-
PHD97NQ03LT_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 24 March 2009
10 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status [1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PHD97NQ03LT_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 24 March 2009
11 of 12
PHD97NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10
Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 24 March 2009
Document identifier: PHD97NQ03LT_1
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