Data Sheet

SO
8
PHK18NQ03LT
N-channel TrenchMOS logic level FET
Rev. 03 — 17 March 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ High efficiency due to low switching
and conduction losses
„ Suitable for logic level gate drive
sources
1.3 Applications
„ DC-to-DC converters
„ Switched-mode power supplies
„ Notebook computers
„ Voltage regulators
1.4 Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 150 °C
-
-
30
ID
drain current
Tsp = 25 °C; VGS = 10 V;
see Figure 1; see Figure 3
-
-
20.3 A
Ptot
total power dissipation
Tsp = 25 °C; see Figure 2
-
-
6.25 W
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 10;
see Figure 11
-
7.1
8.9
mΩ
VGS = 4.5 V; ID = 15 A;
VDS = 12 V; see Figure 12;
see Figure 13
-
2.5
-
nC
V
Static characteristics
RDSon
drain-source on-state
resistance
Dynamic characteristics
QGD
gate-drain charge
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
1
S
source
2
S
source
3
S
source
4
G
gate
5
D
drain
6
D
drain
7
D
drain
8
D
drain
Simplified outline
8
Graphic symbol
D
5
G
1
4
S
mbb076
SOT96-1 (SO8)
3. Ordering information
Table 3.
Ordering information
Type number
Package
PHK18NQ03LT
Name
Description
Version
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 150 °C
-
30
V
VDGR
drain-gate voltage
Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 kΩ
-
30
V
VGS
gate-source voltage
-20
20
V
ID
drain current
Tsp = 25 °C; VGS = 10 V; see Figure 1;
see Figure 3
-
20.3
A
Tsp = 100 °C; VGS = 10 V; see Figure 1
-
12.1
A
IDM
peak drain current
Tsp = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
-
80
A
Ptot
total power dissipation
Tsp = 25 °C; see Figure 2
-
6.25
W
Tstg
storage temperature
-55
150
°C
Tj
junction temperature
-55
150
°C
Source-drain diode
IS
source current
Tsp = 25 °C
-
5.2
A
ISM
peak source current
Tsp = 25 °C; pulsed; tp ≤ 10 µs
-
20.8
A
VGS = 10 V; Tj(init) = 25 °C; ID = 31.5 A;
Vsup ≤ 25 V; unclamped; tp = 0.07 ms;
RGS = 50 Ω
-
50
mJ
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
PHK18NQ03LT
Product data sheet
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Rev. 03 — 17 March 2011
© NXP B.V. 2011. All rights reserved.
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N-channel TrenchMOS logic level FET
03aa25
120
03aa17
120
Ider
(%)
Pder
(%)
80
80
40
40
0
0
0
50
100
150
200
0
50
100
Tsp (°C)
Fig 1.
150
200
Tsp (°C)
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of solder point temperature
003aaa680
103
ID
(A)
Limit RDSon = VDS / ID
102
tp = 10 μ s
100 μ s
10
1 ms
DC
10 ms
1
100 ms
10-1
10-1
1
10
102
VDS (V)
Tsp = 25 °C; IDM is single pulse
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHK18NQ03LT
Product data sheet
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Rev. 03 — 17 March 2011
© NXP B.V. 2011. All rights reserved.
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N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-sp)
thermal resistance from junction to
solder point
Min
Typ
Max
Unit
-
-
20
K/W
003aaa681
102
Zth(j-sp)
(K/W)
δ = 0.5
10
0.2
0.1
0.05
1
δ=
P
tp
T
0.02
single pulse
10-1
10-5
Fig 4.
t
tp
T
10-4
10-3
10-2
10-1
1
tp (s)
10
Transient thermal impedance from junction to solder point as a function of pulse duration
PHK18NQ03LT
Product data sheet
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Rev. 03 — 17 March 2011
© NXP B.V. 2011. All rights reserved.
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PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ID = 250 µA; VGS = 0 V; Tj = 25 °C
30
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
27
-
-
V
1.3
1.7
2.15
V
ID = 1 mA; VDS = VGS; Tj = 150 °C;
see Figure 8; see Figure 9
0.8
-
-
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 8; see Figure 9
-
-
2.6
V
Static characteristics
V(BR)DSS
drain-source breakdown
voltage
VGS(th)
gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 8; see Figure 9
IDSS
drain leakage current
VDS = 30 V; VGS = 0 V; Tj = 25 °C
-
-
1
µA
VDS = 30 V; VGS = 0 V; Tj = 150 °C
-
-
100
µA
IGSS
gate leakage current
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 10; see Figure 11
-
7.1
8.9
mΩ
VGS = 10 V; ID = 25 A; Tj = 150 °C;
see Figure 10
-
12.1
15.1
mΩ
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
see Figure 10; see Figure 11
-
10.1
12.5
mΩ
f = 1 MHz
-
1.6
-
Ω
ID = 15 A; VDS = 12 V; VGS = 4.5 V;
see Figure 12; see Figure 13
-
10.6
-
nC
RDSon
RG
drain-source on-state
resistance
gate resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
-
4.85
-
nC
QGS1
pre-threshold gate-source
charge
-
2.4
-
nC
QGS2
post-threshold gate-source
charge
-
2.45
-
nC
QGD
gate-drain charge
-
2.5
-
nC
VGS(pl)
gate-source plateau voltage
ID = 15 A; VDS = 12 V; see Figure 12;
see Figure 13
-
3
-
V
Ciss
input capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 14
-
1380
-
pF
VDS = 0 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 14
-
1590
-
pF
Coss
output capacitance
Crss
reverse transfer capacitance
td(on)
turn-on delay time
tr
rise time
td(off)
turn-off delay time
-
19
-
ns
tf
fall time
-
11
-
ns
PHK18NQ03LT
Product data sheet
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 14
VDS = 12 V; RL = 0.8 Ω; VGS = 4.5 V;
RG(ext) = 5.6 Ω
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2011
-
290
-
pF
-
135
-
pF
-
19
-
ns
-
22
-
ns
© NXP B.V. 2011. All rights reserved.
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PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Source-drain diode
VSD
source-drain voltage
IS = 20 A; VGS = 0 V; Tj = 25 °C;
see Figure 15
-
0.95
1.2
V
trr
reverse recovery time
IS = 15 A; dIS/dt = -100 A/µs;
VGS = 0 V; VDS = 30 V
-
34
-
ns
Qr
recovered charge
IS = 15 A; dIS/dt = -100 A/µs;
VGS = 0 V
-
14
-
nC
003aaa682
20
10 4.5 3.4
003aaa683
40
3.2
ID
(A)
ID
(A)
3
15
30
10
20
2.8
5
10
Tj = 150 °C
2.6
25 °C
VGS (V) = 2.4
0
0
0
0.2
0.4
0.6
VDS (V)
0.8
0
Tj = 25 °C
Fig 5.
1
2
3
4
VGS (V)
Tj = 25 °C and 150 °C; VDS > ID x RDSon
Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6.
003aaa688
104
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
003aab272
3
VGS(th)
(V)
C
(pF)
max
Ciss
2
typ
Crss
3
1.5
10
min
1
0.5
102
10-1
1
VGS (V)
0
-60
10
0
60
120
180
Tj (°C)
VGS = 0 V; f = 1 MHz
Fig 7.
Input and reverse transfer capacitances as a
function of gate-source voltage; typical values
PHK18NQ03LT
Product data sheet
Fig 8.
Gate-source threshold voltage as a function of
junction temperature
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Rev. 03 — 17 March 2011
© NXP B.V. 2011. All rights reserved.
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PHK18NQ03LT
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N-channel TrenchMOS logic level FET
003aab271
10-1
ID
(A)
10-2
a
1.6
min
typ
max
10-3
1.2
10-4
0.8
10-5
0.4
10-6
0
Fig 9.
003aab467
2
1
2
VGS (V)
3
Sub-threshold drain current as a function of
gate-source voltage
0
−60
0
60
120
180
Tj (°C)
Fig 10. Normalized drain-source on-state resistance
factor as a function of junction temperature
003aaa684
50
3
VGS (V) = 2.8
RDSon
(mΩ)
VDS
ID
40
VGS(pl)
30
VGS(th)
3.2
VGS
20
3.4
QGS1
4.5
10
10
QGS2
QGS
QGD
QG(tot)
003aaa508
0
0
5
10
15
ID (A)
20
Tj = 25 °C
Fig 11. Drain-source on-state resistance as a function
of drain current; typical values
PHK18NQ03LT
Product data sheet
Fig 12. Gate charge waveform definitions
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© NXP B.V. 2011. All rights reserved.
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PHK18NQ03LT
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N-channel TrenchMOS logic level FET
003aaa685
10
003aaa687
104
ID = 15 A
Tj = 25 °C
VGS
(V)
C
(pF)
8
6
VDS = 19 V
12 V
Ciss
103
4
2
Coss
0
5
10
15
Crss
102
10-1
0
20
25
QG (nC)
ID = 15 A; VDS = 12 V and 19 V
1
10
VDS (V)
102
VGS = 0 V; f = 1 MHz
Fig 13. Gate-source voltage as a function of gate
charge; typical values
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aaa686
40
IS
(A)
30
20
10
150 °C
Tj = 25 °C
0
0
0.4
0.8
VSD (V)
1.2
Tj = 25 °C and 150 °C; VGS = 0 V
Fig 15. Source current as a function of source-drain voltage; typical values
PHK18NQ03LT
Product data sheet
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Rev. 03 — 17 March 2011
© NXP B.V. 2011. All rights reserved.
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PHK18NQ03LT
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N-channel TrenchMOS logic level FET
7. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
inches
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
o
8
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 16. Package outline SOT96-1 (SO8)
PHK18NQ03LT
Product data sheet
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Rev. 03 — 17 March 2011
© NXP B.V. 2011. All rights reserved.
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N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PHK18NQ03LT v.3
20110317
Product data sheet
-
PHK18NQ03LT v.2
-
PHK18NQ03LT v.1
Modifications:
PHK18NQ03LT v.2
PHK18NQ03LT
Product data sheet
•
Various changes to content.
20101221
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2011
© NXP B.V. 2011. All rights reserved.
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N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status [1] [2]
Product status [3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
9.3
Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
PHK18NQ03LT
Product data sheet
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Rev. 03 — 17 March 2011
© NXP B.V. 2011. All rights reserved.
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N-channel TrenchMOS logic level FET
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PHK18NQ03LT
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2011
© NXP B.V. 2011. All rights reserved.
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N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10
Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 17 March 2011
Document identifier: P
HK18NQ03LT