Data Sheet

PHP101NQ03LT
N-channel TrenchMOS logic level FET
Rev. 04 — 2 March 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Suitable for logic level gate drive
sources
„ Simple gate drive required due to low
gate charge
1.3 Applications
„ DC-to-DC convertors
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
30
V
ID
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1; see Figure 3
-
-
75
A
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
166
W
VGS = 5 V; ID = 50 A;
VDS = 15 V; Tj = 25 °C;
see Figure 11
-
8
-
nC
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 9;
see Figure 10
-
4.5
5.5
mΩ
Dynamic characteristics
QGD
gate-drain charge
Static characteristics
RDSon
drain-source
on-state resistance
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
Symbol
Description
1
G
gate
2
D
drain
3
S
source
mb
D
mounting base; connected to
drain
Simplified outline
Graphic symbol
D
mb
G
mbb076
S
1 2 3
SOT78
(TO-220AB; SC-46)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
PHP101NQ03LT TO-220AB; SC-46 plastic single-ended package; heatsink mounted; 1 mounting hole;
3-lead TO-220AB
PHP101NQ03LT_4
Product data sheet
Version
SOT78
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 March 2009
2 of 13
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
30
V
VDGR
drain-gate voltage
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
VGS
gate-source voltage
ID
drain current
-
30
V
-20
20
V
VGS = 10 V; Tmb = 100 °C; see Figure 1
-
75
A
VGS = 10 V; Tmb = 25 °C; see Figure 1;
see Figure 3
-
75
A
IDM
peak drain current
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
-
240
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
166
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
VGSM
peak gate-source voltage
-55
175
°C
pulsed; δ = 25 %; tp ≤ 50 µs; Tj ≤ 150 °C
-25
25
V
Source-drain diode
IS
source current
Tmb = 25 °C
-
75
A
ISM
peak source current
tp ≤ 10 µs; pulsed; Tmb = 25 °C
-
240
A
VGS = 10 V; Tj(init) = 25 °C; ID = 43 A;
Vsup ≤ 15 V; unclamped; tp = 0.19 ms;
RGS = 50 Ω
-
185
mJ
Avalanche ruggedness
non-repetitive
drain-source avalanche
energy
EDS(AL)S
03ai19
120
Ider
(%)
Pder
(%)
80
80
40
40
0
0
0
Fig 1.
03aa16
120
50
100
150
200
Tmb (°C)
Normalized continuous drain current as a
function of mounting base temperature
0
100
150
200
Tmb (°C)
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
PHP101NQ03LT_4
Product data sheet
50
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 March 2009
3 of 13
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ai21
103
ID
(A)
Limit RDSon = VDS / ID
tp = 10 μ s
100 μ s
102
DC
1 ms
10
10 ms
1
1
Fig 3.
10
102
VDS (V)
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHP101NQ03LT_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 March 2009
4 of 13
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Rth(j-a)
Rth(j-mb)
Conditions
Min
Typ
Max
Unit
thermal resistance from junction to ambient vertical in free air
-
60
-
K/W
thermal resistance from junction to
mounting base
-
-
0.19
K/W
see Figure 4
03ai20
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
10-1
0.1
0.05
10-2
δ=
P
0.02
tp
T
single pulse
t
tp
T
10
Fig 4.
-3
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHP101NQ03LT_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 March 2009
5 of 13
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
27
-
-
V
ID = 250 µA; VGS = 0 V; Tj = 25 °C
30
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 7; see Figure 8
-
-
2.9
V
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 7; see Figure 8
0.6
-
-
V
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 7; see Figure 8
1
1.9
2.5
V
VDS = 30 V; VGS = 0 V; Tj = 25 °C
-
0.05
1
µA
VDS = 30 V; VGS = 0 V; Tj = 175 °C
-
-
500
µA
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
10
100
nA
VGS = -20 V; VDS = 0 V; Tj = 25 °C
-
10
100
nA
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 9; see Figure 10
-
4.5
5.5
mΩ
VGS = 5 V; ID = 25 A; Tj = 175 °C;
see Figure 9; see Figure 10
-
10.5
13.5
mΩ
VGS = 5 V; ID = 25 A; Tj = 25 °C;
see Figure 9; see Figure 10
-
5.8
7.5
mΩ
ID = 50 A; VDS = 15 V; VGS = 5 V;
Tj = 25 °C; see Figure 11
-
23
-
nC
-
10.5
-
nC
-
8
-
nC
-
2180
-
pF
-
600
-
pF
-
225
-
pF
-
23
-
ns
-
90
-
ns
Static characteristics
V(BR)DSS
VGS(th)
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGD
gate-drain charge
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer
capacitance
td(on)
turn-on delay time
tr
rise time
td(off)
turn-off delay time
-
37
-
ns
tf
fall time
-
33
-
ns
VDS = 25 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 12
VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V;
RG(ext) = 5.6 Ω; Tj = 25 °C; ID = 25 A
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 13
-
0.85
1.2
V
trr
reverse recovery time
-
37
-
ns
Qr
recovered charge
IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 25 V; Tj = 25 °C
-
33
-
nC
PHP101NQ03LT_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 March 2009
6 of 13
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ai22
80
VGS (V) = 10
ID
(A)
5 4.5
ID
(A)
3.8
Tj = 25 °C
03ai24
80
4
60
60
3.6
40
40
3.4
3.2
20
20
175 °C
3
Tj = 25 °C
2.8
0
0
0
Fig 5.
0.2
0.4
0.6
0.8
VDS (V)
1
Output characteristics: drain current as a
function of drain-source voltage; typical values
03ai29
3.2
0
Fig 6.
1
2
3 V (V) 4
GS
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
03ai28
10-1
ID
(A)
VGS(th)
(V)
max
10-2
typ
10-3
2.4
min
typ
max
1.6
10-4
min
0.8
10-5
0
-60
Fig 7.
10-6
0
60
120
Tj (°C)
180
Gate-source threshold voltage as a function of
junction temperature
0
Fig 8.
1.6
2.4
VGS(V)
3.2
Sub-threshold drain current as a function of
gate-source voltage
PHP101NQ03LT_4
Product data sheet
0.8
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 March 2009
7 of 13
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ai23
16
Tj = 25 °C
RDSon
(mΩ)
03af18
2
VGS (V) = 3.8
a
12
1.5
4
8
1
4.5
5
10
4
0.5
0
-60
0
0
Fig 9.
20
40
60
ID (A)
80
Drain-source on-state resistance as a function
of drain current; typical values
03ai27
10
8
60
120
Tj (°C)
180
Fig 10. Normalized drain-source on-state resistance
factor as a function of junction temperature
03ai26
104
ID = 50 A
Tj = 25 °C
VDS = 15 V
VGS
(V)
0
C
(pF)
Ciss
6
103
4
Coss
2
Crss
0
0
10
20
30
40
50
QG (nC)
Fig 11. Gate-source voltage as a function of gate
charge; typical values
102
10-1
10
VDS (V)
102
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PHP101NQ03LT_4
Product data sheet
1
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 March 2009
8 of 13
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ai25
80
VGS = 0 V
IS
(A)
60
40
20
175 °C
Tj = 25 °C
0
0
0.3
0.6
0.9
VSD (V)
1.2
Fig 13. Source current as a function of source-drain voltage; typical values
PHP101NQ03LT_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 March 2009
9 of 13
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
SOT78
E
A
A1
p
q
mounting
base
D1
D
L1(1)
L2(1)
Q
L
b1(2)
(3×)
b2(2)
(2×)
1
2
3
b(3×)
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
b1(2)
b2(2)
c
D
D1
E
e
L
L1(1)
L2(1)
max.
p
q
Q
mm
4.7
4.1
1.40
1.25
0.9
0.6
1.6
1.0
1.3
1.0
0.7
0.4
16.0
15.2
6.6
5.9
10.3
9.7
2.54
15.0
12.8
3.30
2.79
3.0
3.8
3.5
3.0
2.7
2.6
2.2
Notes
1. Lead shoulder designs may vary.
2. Dimension includes excess dambar.
OUTLINE
VERSION
SOT78
REFERENCES
IEC
JEDEC
JEITA
3-lead TO-220AB
SC-46
EUROPEAN
PROJECTION
ISSUE DATE
08-04-23
08-06-13
Fig 14. Package outline SOT78 (TO-220AB)
PHP101NQ03LT_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 March 2009
10 of 13
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PHP101NQ03LT_4
20090302
Product data sheet
-
PHP_PHU101NQ03LT_3
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
PHP_PHU101NQ03LT_3
20051117
Product data sheet
CPCN # 200309016
PHP_PHU101NQ03LT-02
PHP_PHU101NQ03LT-02
(9397 750 10927)
20030225
Product data
-
PHP_PHD_PHB_PHU101
NQ03LT-01
PHP_PHD_PHB_PHU101
NQ03LT-01
(9397 750 09307)
20020220
Product data
-
-
PHP101NQ03LT_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 March 2009
11 of 13
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status [1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PHP101NQ03LT_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 March 2009
12 of 13
PHP101NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . .12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 2 March 2009
Document identifier: PHP101NQ03LT_4
Similar pages