1EDS20I12SV Data Sheet (1.1 MB, EN)

Eice DR IV ER ™ - Sa fe
High voltage gate driver IC with reinforced isolation
1E DS -S R C
Real-time adjustable gate current control IC
1EDS20I12SV
EiceDRIVER™
Targ et d at asheet
<Revision 0.73>, 05.06.2014
Indust rial Po wer & Con trol
Edition 05.06.2014
Published by
Infineon Technologies AG
81726 Munich, Germany
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1EDS - slew rate control IGBT driver IC
Revision History
Page or Item
Subjects (major changes since previous revision)
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22
Inserted new parameter “Quiescent current output side VEE2”
all
minor editorial changes
30
revised fig. 16
31
revised package drawing
1
corrected sales code
20
Insert note on derating for power dissipation
27
UL 1577 recognition
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Last Trademarks Update 2010-10-26
Target datasheet
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Table of Contents
1
Overview ............................................................................................................................................. 6
2
Block diagram..................................................................................................................................... 7
3
3.1
3.2
Pin configuration, description, and functionality ........................................................................... 8
Terminal configuration .......................................................................................................................... 8
Terminal functionality ........................................................................................................................... 9
4
4.1
4.2
4.2.1
4.2.2
4.3
4.4
4.5
4.6
4.7
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.8.7
4.8.8
4.8.9
4.8.10
Functional description ..................................................................................................................... 13
Introduction ......................................................................................................................................... 13
IC Supply ............................................................................................................................................ 13
Input side ............................................................................................................................................ 14
Output side ......................................................................................................................................... 14
Non-inverting and inverting input terminals INP and INN .................................................................. 14
Driver output terminal ON .................................................................................................................. 14
Preboost setting ................................................................................................................................. 15
Gate turn-off terminal OFF ................................................................................................................. 16
Terminal EN ....................................................................................................................................... 16
Protection and diagnosis features ...................................................................................................... 17
Undervoltage lockout (UVLO) ............................................................................................................ 17
Ready and status output terminals..................................................................................................... 17
Fault indication (terminal /FLT) .......................................................................................................... 17
Watchdog ........................................................................................................................................... 17
I/O signature check ............................................................................................................................ 17
Two-level turn-off (TLTO) ................................................................................................................... 18
Desaturation shut down protection..................................................................................................... 19
IGBT overcurrent detection ................................................................................................................ 19
Overcurrent protection ON/OFF ......................................................................................................... 19
Soft turn-off......................................................................................................................................... 19
5
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
Electrical parameters ....................................................................................................................... 20
Absolute maximum ratings ................................................................................................................. 20
Operating range ................................................................................................................................. 21
Electrical characteristics ..................................................................................................................... 22
Voltage supply .................................................................................................................................... 22
Logic input and output ........................................................................................................................ 22
Gate driver .......................................................................................................................................... 23
Desaturation protection (DESAT)....................................................................................................... 25
Overcurrent protection disable (OCOFF) ........................................................................................... 25
Current sense (CS) ............................................................................................................................ 25
Two-level turn-off (CZ, VZ, GATE) ..................................................................................................... 26
6
6.1
6.2
Insulation characteristics ................................................................................................................ 27
Reinforced insulation requirements according to VDE 0884-10 (pending) ........................................ 27
Recognized under UL 1577 (pending) ............................................................................................... 27
7
Timing diagrams............................................................................................................................... 28
8
8.1
Package ............................................................................................................................................. 31
PG-DSO-36 ........................................................................................................................................ 31
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List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Block diagram for 1EDS20I12SV ......................................................................................................... 7
Terminal configuration of 1EDS20I12SV (Top View) ........................................................................... 8
Typical application .............................................................................................................................. 13
Timing diagram for turn-on ................................................................................................................. 15
External circuit for setting of preboost current (left: unipolar supply; right: bipolar supply) ............... 16
I/O signature check ............................................................................................................................ 18
Timing of turn-on and turn-off propagation delay without two-level turn-off mode ............................ 28
Timing of EN turn-on and shut down propagation delay .................................................................... 28
Timing of short pulse suppression terminal INP ................................................................................ 28
Timing of short pulse suppression terminal INN ................................................................................ 28
Timing of short pulse suppression terminal EN and EN propagation delay to turn-on ...................... 29
Timing of short pulse suppression terminal SIGI ............................................................................... 29
Timing for fault reset at terminal EN (left) and EN shut down time to soft turn-off (right) .................. 29
Timing of CS events incl. terminals SOFF, /FLT and EN................................................................... 29
Timing for DESAT events incl. terminals SOFF, /FLT and EN .......................................................... 30
Timing for two-level turn-off incl. terminals CZ and OFF ................................................................... 30
Package drawing ................................................................................................................................ 31
PCB reference layout (left: top layer, right: bottom layer) .................................................................. 32
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Terminal Description ............................................................................................................................ 8
Driver IC status for EN, INP, and INN ................................................................................................ 16
Driver IC status UVLO at VCC1, VCC2 and PADP (EN = high) ........................................................ 17
Abs. maximum ratings ........................................................................................................................ 20
Operating parameters ........................................................................................................................ 21
Voltage supply .................................................................................................................................... 22
Logic input and output ........................................................................................................................ 22
Gate driver .......................................................................................................................................... 23
Desaturation protection ...................................................................................................................... 25
Overcurrent protection disable ........................................................................................................... 25
Current sense ..................................................................................................................................... 25
Two-level turn-off................................................................................................................................ 26
Reinforced insulation .......................................................................................................................... 27
Recognized under UL 1577 ............................................................................................................... 27
Target datasheet
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EiceDRIVER™ Safe
Real-time adjustable gate current control IC
1
1EDS20I12SV
Overview
Main features









Single-channel isolated IGBT Driver
Supports IGBT up to 1200 V
IGBT off-state: 2 A rail to rail
Overcurrent protection for sense IGBTs and conventional IGBTs
Desaturation detection
Soft turn-off shut down
Two-level turn-off
Operation at high ambient temperature up to 105°C
Compatible inputs for 3.3 V, 5 V, and 15 V logic voltages
PG-DSO36
Product highlights



Optimized short circuit control for 3-level inverters
Online adjustable current source slew rate control during IGBT turn-on
Reinforced isolation according VDE 0884-10
Typical applications





AC and brushless DC motor drives
High-voltage DC/DC converters
UPS systems
Welding
Servo drives
Description
The 1EDS20I12SV is a single-channel IGBT driver in a PG-DSO-36-64 package with a reinforced galvanically
isolated barrier. The driver IC controls up to three external p-channel MOSFET as a controlled current source
during turn-on. The IC is therefore able to control precisely the turn-on process in order to avoid excessive dv/dt
or di/dt transients. The IC has a peak sinking capability of 2A for turning off the IGBT. An external PNP
transistoror is required to support IGBT with currents ratings higher than 75 A.
The logic input pins are 3.3 V, 5 V, and 15 V CMOS-compatible. The data transfer across the galvanic isolation
barrier is accomplished with an integrated coreless transformer technology. The 1EDS20I12SV provides several
protection features such as IGBT desaturation shut down protection for IGBT, overcurrent protection for sense
IGBT, soft turn-off shut down, and two-level turn-off.
Target datasheet
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Block diagram
2
VCC1
VCC2
UVLO /
Bias
UVLO /
Bias
/FLT
CS
DESAT / CS
Detection
circuits
RDY2
DESAT
Safety
Logic
OCOFF
RDY1
MAIN
LOGIC
/
CT
Transceiver
PADP
PADP
MAIN
LOGIC
/
CT
Transceiver
INN
PRB
RSENSE
ON
ON
INP
PADN
ON
CT Isolated
Transmission
path
(bidirectional)
Input
stage
Control loop
VCC2
GATE
TLTO
EN
TLTO
CZ
Control loop
PADN
VZ
PADN
CZ
VZ
OFF
SPEED
PADN
VEE2
VCC1
SIGI
SOFF
VCC1
Signature
Logic
SIGO
VEE2
GND1
GND2
Input Side
Figure 1
Output Side
Block diagram for 1EDS20I12SV
Target datasheet
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3
Pin configuration, description, and functionality
3.1
Terminal configuration
VEE2
1
36 GND1
DESAT
2
35 PADN
OFF
3
34 VCC1
OCOFF
4
33 PADP
CS
5
32 INN
GATE
6
31 INP
SOFF
7
30 EN
GND2
8
29 SPEED
VEE2
9
1EDS20I12SV
RSENSE 10
27 /FLT
VCC2 11
26 RDY1
ON 12
25 RDY2
NC 13
24 NC
PRB 14
Figure 2
28 GND1
23 SIGI
CZ 15
22 SIGO
VZ 16
21 TST1
TST2 17
20
VEE2 18
19 GND1
NC
Terminal configuration of 1EDS20I12SV (Top View)
Table 1
Terminal Description
Terminal
number
1
Terminal
name
VEE2
2
DESAT
Desaturation shut down protection
3
OFF
Gate turn-off
4
OCOFF
Overcurrent protection on/off
5
CS
Sense IGBT overcurrent
6
GATE
IGBT gate connection
7
SOFF
Gate soft turn-off
8
GND2
Signal ground, output side
9
VEE2
Negative power supply, output side
10
RSENSE
Sense resistor input
11
VCC2
Positive power supply, output side
Target datasheet
Description
Negative power supply, output side
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Table 1
Terminal Description
Terminal
number
Terminal
name
ON
12
Description
Driver output ON terminal, MOSFET connection
13
NC
Not connected, GND2 recommended
14
PRB
Preboost current adjust
15
CZ
Two-level turn-off time set
16
VZ
Two-level turn-off voltage set
17
TST2
Reserved terminal, to be connected to VEE2 during operation
18
VEE2
Negative power supply, output side
19
GND1
Ground, input side
20
NC
Not connected
21
TST1
Reserved terminal, to be connected to GND1 during operation
22
SIGO
Signature test output
23
SIGI
Signature test input
24
NC
Not connected, GND1 recommended
25
RDY2
Ready signal, output side
26
RDY1
Ready signal, input side
27
/FLT
Fault output
28
GND1
Ground, input side
29
SPEED
IGBT gate current setting (analog)
30
EN
Enable, shutdown, and fault reset input
31
INP
Inverted driver input
32
INN
Non-inverted driver input
33
PADP
Input side logic reference voltage
34
VCC1
Positive power supply, input side
35
PADN
Input side logic reference ground
36
GND1
Ground, input side
3.2
Terminal functionality
GND1
Logic ground terminal of the input side.
PADN
Input side logic reference ground. Direct connection to GND1 is required.
VCC1
5 V power supply for the input side.
PADP
3.3 V, 5 V or 15 V input side logic reference voltage.
The reference terminal for PADP is PADN.
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INN inverting driver input
INN control signal for the driver output while INP is set to high. The IGBT is turned on, if INN is set to low, and is
turned off, if INN is set to high, respectively. A minimum pulse width is required to prevent from glitches while
controlling the IGBT. An internal pull-up resistor ensures that the IGBT is kept in off-state, if terminal INN is left
unconnected.
The reference terminal for INN is PADN.
INP non-inverting driver input
INP control signal for the driver output while INN is set to low. The IGBT is turned on, if INP is set to high, and is
turned off, if INP is set to low, respectively. A minimum pulse width is required to suppress glitches while
controlling the IGBT. An internal pull-down resistor ensures that the IGBT is kept in off-state, if terminal INP is
left unconnected.
The reference terminal for INP is PADN.
EN input
Terminal EN needs to be set high for INP and INN to control the IGBT switching.
The EN input terminal serves two purposes:
Feature 1: Enable / shutdown of the output side. The IGBT is turned off by a soft turn-off, if terminal EN is set to
low. A minimum pulse width is defined to help suppress glitches on terminal EN.
The IGBT is switched on without preboost on the rising edge of terminal EN, if terminal INP is set high and
terminal INN is set low before activating EN.
Feature 2: Resets the desaturation or overcurrent condition signaled on terminal /FLT, if terminal EN is set to
low for more than 800 ns. A reset is asserted at the rising edge of terminal EN.
The reference terminal for EN is PADN.
SPEED
IGBT on-state gate current setting sent from input side. This is an analog input terminal. The reference voltage
of the internal ADC is PADP.The reference terminal for SPEED is PADN.
/FLT fault output
Open-drain output terminal to signal desaturation of conventional IGBTs or overcurrent of sense IGBTs.
Terminal /FLT is set low, if desaturation or overcurrent occurs. The /FLT terminal must be connected via a pullup resistor to PADP.
The reference terminal for /FLT is GND1.
RDY1 ready status
Open-drain output to signal the proper operation of the input side. RDY1 is set to high if the input side terminals
VCC1 and PADP are above their respective undervoltage thresholds. The RDY1 terminal should be connected
a via pull-up resistor to PADP.
The reference ground terminal for RDY1 is GND1.
RDY2 ready status
Open-drain output to signal the proper operation of the output side. RDY2 is set to high, if the output side supply
is above the UVLO2 level and the internal chip data transmission is operating properly. The RDY2 terminal
should be connected via a pull-up resistor to PADP.
The reference ground terminal for RDY2 is GND1.
SIGI
I/O signature check input terminal (5 V, CMOS-compatible)
The reference terminal for SIGI is GND1.
SIGO
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I/O signature check output terminal (5 V, CMOS-compatible)
The reference terminal for SIGO is GND1.
TST1
Terminal TST1 is a reserved terminal and has to be connected to GND1.
TST2
TST2 is a reserved terminal and has to be connected to VEE2.
VEE2
Negative power supply terminal for the output side: All VEE2 terminals must be connected to GND2, if no
separate negative supply voltage is required.
DESAT
Monitoring of the IGBT saturation voltage VCE(sat) to detect desaturation caused by a short: The IGBT is shut
down by activating soft turn-off, if the voltage at this pin is above a given threshold. Two additional filters provide
a large robustness against noise and coupling effects. One of these filters is adjustable in terms of the filter time.
The reference terminal for DESAT is GND2.
OFF
Gate turn-off terminal in normal operation mode
The reference terminal for OFF is VEE2.
OCOFF
Input terminal to inhibit the automatic turn-off of the IGBT in case of a desaturation or current sense failure. The
fault status continues to be signaled on terminal /FLT. This feature is deactivated (internal pull-down resistor to
GND2), if the terminal is left open.
The reference terminal for OCOFF is GND2
CS
Current sense comparator input terminal for sense IGBTs or standard IGBTs with external emitter shunts.
The reference terminal for CS is GND2. If this terminal is connected to GND2, this feature is deactivated.
GATE
Input terminal for sensing the gate voltage at resistor ROFF according to Figure 3.
The reference terminal for GATE is GND2.
PRB
For preboost current adjustment connect a voltage divider between GND2 and VEE2 for a bipolar supply and
VCC2 and VEE2 for unipolar supply.
The reference terminal for PRB is VEE2.
SOFF
Output terminal for IGBT soft turn-off in case of short circuit or overcurrent events
The reference terminal for SOFF is VEE2.
GND2
Reference ground terminal of the output side.
RSENSE
Current sense feedback input of the turn-on gate current control loop.
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The reference terminal for RSENSE is VCC2.
VCC2
Positive power supply terminal of the output side.
ON
Terminal for the connection to the gate terminal of an external P-channel OptiMOS™ BSD314SPE boost
transistor. This transistor is used to drive the IGBT turn-on.
The reference terminal for ON is VCC2.
CZ
This terminal sets the two-level turn-off timing via an external capacitor against VEE2. A short between
terminals CZ and VEE2 deactivates the two-level turn-off.
The reference terminal for CZ is VEE2.
VZ
Voltage adjustment terminal for the two-level turn-off feature: This terminal can be connected to VEE2 via a
resistor (9.5 V), shorted against VEE2 (11.7 V), or left floating (10.6 V).
The reference terminal for VZ is VEE2.
Target datasheet
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4
Functional description
4.1
Introduction
The 1EDS20I12SV is an advanced IGBT gate driver with various control and protection features to allow the
design of highly reliable systems. The integrated circuit consists of two reinforced isolated sides, called input
side and output side. The input side is typically interfaced with a CMOS-compatible standard DSP or a
microcontroller. The galvanically isolated output side is connected to the high voltage domain. The adjustable
gate current source allows the tuning of the IGBT turn-on slew rate to limit the EMI radiation.
The turn-off process is accomplished with an internal MOSFET stage capable of driving 2 A. An internal
MOSFET switch capable of driving 1 A is connected to an external high-impedance gate resistor and prevents
from an overvoltage at the IGBT in case of a short or an overcurrent.
The driver also includes IGBT desaturation protection for conventional IGBTs and overcurrent protection for
sense IGBTs with the fault status output terminal. Two ready status output terminals indicate whether the driver
is properly supplied and operates normally. A two-level turn-off feature with adjustable delay protects against
excessive overvoltage at turn-off in case of an overcurrent or a short. The same delay is applied at turn-on to
prevent pulse width distortions.
5V
5V
VCC2
VCC1
VCC2
RDESAT
/FLT
DESAT
RDY2
CS
RDY1
OCOFF
DDESAT
RS
ON
PADP
CDESAT
CD
RSENSE
C1
Control
Unit
RD
T1
T2
INP
GATE
INN
CZ
EN
RSOFF
VZ
PADN
ROFF
RF
SPEED
CF
SIGI
OFF
SOFF
PRB
SIGO
RPRB2
GND1
GND
Figure 3
4.2
RPRB1
VCC2
VEE2
C3
C2
GND2
Typical application
IC Supply
The start up of the input section and the output section of the 1EDS02I12SV needs approx. tbd µs for the VCC1/
PADP domains and tbd µs for the VCC2 domain. However, the IC is in a safe state in any case, meaning that
the gate drive outputs are never activated before each part of the IC is ready to operate. The startup times are
given in section 5.3.1.
Target datasheet
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4.2.1
Input side
The driver is supplied with 5 V between terminals VCC1 to GND1. This supply voltage manages the basic
functions of the control side. The control side contains a second voltage domain for the logic input signals INP,
INN, and EN. This special voltage domain is supplied by the terminals PADP and PADN and can range from
3.3V over 5V to 15V. It is mandatory to connect directly the terminals PADN and GND1. It is important to note,
that the voltage domains VCC1 and PADP have independent undervoltage lockout levels and both domains
must be supplied appropriately for operation.
VCC1 can be shorted to GND1 in order to deactivate the driver. No turn-on signals will be transmitted from the
input to the output side even if terminal VCC1 is left floating. Therefore, the IGBT won’t be turned on.
4.2.2
Output side
The EiceDRIVER™ 1EDS20I12SV is designed to support both bipolar and unipolar power supply
configurations. The driver IC is typically supplied with a positive voltage of 15 V on terminal VCC2 and a
negative voltage of -8 V on terminal VEE2, if configured for bipolar supply. The driver IC is typically supplied
with a positive voltage of 15 V on terminal VCC2 for a unipolar supply configuration. VEE2 and GND2 have to
be connected together as short as possible in this case.
4.3
Non-inverting and inverting input terminals INP and INN
There are two input modes to control the IGBT. In non-inverting mode, terminal INP controls the driver output
while terminal INN is set to low. In inverting mode, terminal INN controls the driver output while terminal INP is
set to high. A low signal at terminal INN will activate the output ON. A minimum input pulse width is defined to
suppress potential glitches.
4.4
Driver output terminal ON
The output stage consists of the internal regulation circuit inside the driver, an external sense resistor RSENSE,
and up to three external P-channel transistors placed in parallel. The recommended P-channel transistor is a
BSD314SPE (OptiMOS™-P 3, 30 V, 140 mΩ).
After a short propagation delay, the IGBT is switched on by a regulated current source. The entire turn-on
procedure is separated into three phases according to Figure 4: the preboost, the turn-on, and the VCC2
clamping phase.
The preboost phase controls a high current to drive the gate of the IGBT. This brings the gate voltage from its
negative level to a voltage slightly lower than the gate-emitter threshold voltage if the IGBT, i.e. VGATE < VGE(th),
within a period of typ. 135 ns. The value of the preboost current IPRB is proportional to the voltage VPRB at
terminal PRB. The maximum voltage VPRB against VEE2 is 5 V. The preboost current IPRB is defined as:
|
|
(1)
The change from the preboost phase into the turn-on phase needs less than 25 ns. This time must be
considered for the setting of the preboost current amplitude in order not to overcharge the gate during the
preboost phase.
The gate current during the turn-on phase can be selected out of 11 levels for the proper adjustment of the turnon transition. The fine granularity between levels 1 and 10 allows accurate slope control. It behaves similar as a
traditional driver at level 11. The driver controls the voltage drop across the sense resistor RS. The
corresponding gate current Igg is
(2)
The selection of the gate current for the turn-on phase is accomplished with terminal SPEED on the input side.
Terminal SPEED is an input terminal with voltage levels between 0 V and 3.3 V. The lowest voltage at terminal
SPEED corresponds with the highest gate current level, e.g. by connecting SPEED to GND1.
Target datasheet
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VCC2
tracking
vRS(t)
RS
RSENSE
external
turn-on
ON
igg(t)
GATE
Rg int
von(t)
vGE(t)
GND2
1EDS-SRC
Phases:
vRS
igg
preboost
1.33V at VEE2=8V
turn-on current source
VCC2 clamping
preboost value =
f(VEE2, RPRB1, RPRB2)
0.516V (step 3)
135ns
t
<100ns
vON
v VCC2
VMiller
VCC2-Von=6V
VGE(th)
vGE
0
t
VEE2
t0
Figure 4
t1
t3
t2
Timing diagram for turn-on
Finally, the IGBT gate voltage saturates at VCC2 in the VCC2 clamping phase. The driver clamps the gate
voltage of the external P-channel transistor 6 V below VCC2 according to Figure 4. This provides a low-ohmic
connection between the gate of the IGBT and VCC2
It is good board layout engineering to keep tight proximity of the control loop consisting of driver IC, sense
resistor, and p-channel MOSFET to avoid oscillations.
4.5
Preboost setting
The preboost timer is always active, both in bipolar or unipolar power supply configuration. The only exception is
if the IGBT is turned on via EN according to section 4.7
The preboost current may be set by a simple voltage divider for bipolar gate supply as well as for unipolar
supply. In case of bipolar power supply, connect the voltage divider between GND2, PRB, and VEE2. In case of
a unipolar power supply, use VCC2, PRB, and VEE2 according to Figure 5.
Target datasheet
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VCC2
VCC2
RPRB1
PRB
GND2
RPRB1
RPRB2
PRB
GND2
1EDS-SRC
Figure 5
RPRB2
VEE2
1EDS-SRC
VEE2
External circuit for setting of preboost current (left: unipolar supply; right: bipolar supply)
The selected preboost current amplitude should charge the IGBT gate from the negative voltage VEE2 to a
value between 0 V and VGE(th) of the IGBT within 135 ns. The corresponding IGBT gate charge curves should be
consulted for the various collector-emitter voltages VCE for best accuracy.
4.6
Gate turn-off terminal OFF
The driver IC is able to sink a minimum gate current of 1.5A peak. The closed loop controlled sink MOSFET
establishes the two-level turn-off function according to section 4.8.6 by controlling the second level during the
turn-off process for an adjustable time period TTLSET. An external turn-off boost transistor is recommended for
larger sink current capability.
4.7
Terminal EN
Terminal EN is used to enable the input side for normal operation. A soft turn-off is always initiated, when the
signal at terminal EN is logic low regardless of the status of signals at terminals INP and INN. The status of EN
is dominant over all communications over the insulation barrier. If therefore a shutdown is initiated via terminal
EN during normal operation and an overcurrent is detected simultaneously, the IGBT is turned off via soft turnoff. However, /FLT is not activated as the chip is already being reset. /FLT will be activated after IC enable, if the
overcurrent still exists on the next IGBT turn-on command.
Signals on terminal EN have also priority over INN and INP. The signals at terminal EN must also pass a noise
filter. The EN signal is suppressed, if the pulse duration is shorter than the filter time.evaluated and the driver
reacts as described in Table 2.
Table 2
Driver IC status for EN, INP, and INN
EN
INP
INN
Result
high
high
high
regular turn-off / soft off*
high
low
low
regular turn-off / soft off*
high
high 
low
turn-on
high
high
high 
low 
low
turn-on
high
turn-on without preboost
* soft turn-off only in case of simultaneous CS / DESAT event
A second function of the EN terminal is to reset the driver IC after an overcurrent event, which was triggered by
the DESAT or CS function. The IC is reset by holding EN low for 800 ns or longer. The fault indication at
terminal /FLT follows on the next rising edge of signal EN
Target datasheet
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4.8
Protection and diagnosis features
4.8.1
Undervoltage lockout (UVLO)
The device is equipped with a system of defined undervoltage lockout (UVLO) levels on both the input and
output side to ensure proper operation of the IGBT.
Any triggering of UVLO will turn-off the IGBT by means of the soft turn-off function. All signals at INP and INN
are ignored until the voltage at terminals VCC1 recovers above VUVLOH1 at terminals VCC1 and VUVLOH3 at
terminal PADP.
The IGBT is switched off via terminal OFF only in case of an UVLO event at pin VCC2. Signals from the input
side are ignored until VCC2 recovers to the power-up level of VUVLOH2. The IC will perform an immediate turn-on
after recovery of VCC2 according to Table 3.
4.8.2
Ready and status output terminals
The ready signal RDY1 for the control side covers the following conditions:
 UVLO status of the control side supply voltage domains at terminals VCC1 and PADP
 Establishment of correct signal transmission from input side to output side across the insulation barrier
The ready signal RDY2 for the output side indicates after a short delay:
 UVLO status of the output side supply voltage VCC2
 Establishment of bidirectional signal transmission across the insulation barrier
Both signals are monitoring signals only and need not to be reset actively.
Table 3
Driver IC status UVLO at VCC1, VCC2 and PADP (EN = high)
VCC1
VCC2
PADP
RDY1
RDY2
Result
UVLO 
good
good
low
X
SOFF and 5µs watchdog
UVLO 
good
good
high
high
acc. INP / INN (turn-on with preboost)
UVLO 
X
good
UVLO
low
high
OFF
UVLO 
X
X
low
activate OFF and SOFF simultaneously
good
UVLO 
good
high
high
acc. INP / INN (turn-on with preboost)
UVLO
good
low
high
OFF
X
UVLO 
X
UVLO 
low
high
SOFF and 5µs watchdog
good
good
UVLO 
high
high
acc. INP / INN (turn-on with preboost)
4.8.3
Fault indication (terminal /FLT)
Terminal /FLT is the indicator for a triggered DESAT or CS event. It is pulled low by an internal FET. The /FLT
function is reset by means of a low signal at terminal EN for more than tEN,RST = tbd ns
4.8.4
Watchdog
The bidirectional signal transmission across the insulation barrier is monitored by watchdogs on the input and
output side. These are the most important ones:


The IGBT is switched off via terminal SOFF and additionally switched off via terminal OFF, if the
transmission fails for a given duration.
Another watchdog activates the terminal OFF after 5 µs in any case of a soft turn-off event.
4.8.5
I/O signature check
The I/O signature check is a feature that allows the confirmation of switching commands sent by the
microcontroller to the driver IC. The SIGO output terminal is an exclusive-or (XOR) combination of the terminals
Target datasheet
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INN, INP and EN according to Figure 6. The desaturation status on terminal DESAT and the correct voltage at
terminal PADP are also monitored.
To save PCB space, the SIGI and SIGO terminals of a series of drivers can be interconnected via a daisy chain.
In this case, terminal SIGI of the first driver in the daisy chain should be connected to VCC1 or GND1. Terminal
SIGI of the next driver should be connected to terminal SIGO of the previous driver. Terminal SIGO of the last
driver in the daisy chain should be connected to the microcontroller.
The I/O signature check does not monitor the status of the IGBT.
Monitored status
 INN / INP and EN
 DESAT
 PADP undervoltage
The reference terminals are VCC1 and GND1.
EN
INN
VPADP
VPADN
A
N
D
INP
DESAT/CS*
1:FAIL
0:NO FAIL
VPADP
UVLO (<2,7V)
0:FAIL
1:NO FAIL
VPADN
SIGI
AND
AND
X
O
R
X
O
R
GND1
SIGO
Figure 6
4.8.6
I/O signature check
Two-level turn-off (TLTO)
The TLTO function is activated, if a capacitor is applied between terminal CZ and terminal VEE2. It affects any
turn-on and turn-off process, which is either initiated by the input signals INP, INN or EN or by any protection
function on the output side. Connecting terminal CZ with terminal VEE2 will deactivate the two-level turn-off
function.
The two-level turn-off introduces a second (lower) gate voltage level during the turn-off process according to
Figure 16This additional level ensures lower collector-emitter voltage overshoots during turn-off. The second
gate voltage level reduces the collector current of the IGBT when reaching this level. The obtained diC/dt is
therefore slower and generates less induced overvoltage. The required timing, which can be adjusted by the
capacitance value at terminal CZ, depends on stray inductance and overcurrent at the beginning of the two-level
turn-off period.
Three voltage levels are available:



The voltage level is set to 11.7 V, if terminal VZ is connected to VEE2,
the voltage level is set to 10.6 V, if terminal VZ is floating,
the voltage level is set to 9.5 V, if terminal VZ is connected to VEE2 via a 27 kΩ resistor
IO_si
Target datasheet
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The second voltage level is set in a way that turn-off losses are the same as during normal turn-off for nominal
current values. The turn-on signal is delayed by the duration of the two-level turn-off in order to achieve identical
pulse lengths.
The duration of the plateau is set by the capacitor connected between terminals CZ and VEE2.
The IC starts charging the capacitance on CZ for obtaining the two-level set time TTLSET, when a turn-on signal is
given. The IC starts the turn-on sequence and resets the capacitor at terminal CZ as soon as the voltage at
terminal CZ exceeds 3 V.
The IC activates additionally a soft turn-off sequence, if a turn-off is initiated due to a desaturation condition on
terminal DESAT.
4.8.7
Desaturation shut down protection
Desaturation protection ensures the protection of the IGBT in case of a short. When the desaturation voltage on
terminal DESAT rises and reaches 9 V, the output is driven low by soft turn-off and the /FLT output terminal is
activated. The blanking time is determined by the combination of the highly precise internal current source and
an external capacitor. Desaturation protection is only set active 400ns after the preboost phase.
4.8.8
IGBT overcurrent detection
The IGBT overcurrent detection is a protection feature that senses the emitter current on current-sense IGBTs
or standard IGBTs via using an emitter shunt resistor. The voltage is measured by a comparator that triggers at
0.35 V. The current sense signal at terminal CS is ignored while the IGBT is off. An external blanking circuit is
necessary to prevent false tripping during turn-on. With non-sensing IGBT types, a low resistance shunt is used
to sense the emitter current. When a short is detected, the IGBT is switched off by a soft turn-off. Both the
desaturation and the current sense features can be used at the same time. The fault status is signaled on
terminal /FLT. The fault status has to be reset via terminal EN. IGBT overcurrent detection is only active 400ns
after the preboost phase.
4.8.9
Overcurrent protection ON/OFF
If terminal OCOFF is connected to GND2 or left unconnected, the IGBT is switched off via a soft turn-off in case
of a CS or DESAT event. If terminal OCOFF is connected to VCC2, the IGBT is not switched off in such cases.
The IGBT can be turned off externally instead, e.g. via control input EN. However, the signaling of CS or DESAT
events to output /FLT is done in any case.
4.8.10
Soft turn-off
The IGBT can be turned off smoothly via an external higher-ohmic gate resistor attached to terminal SOFF. The
soft turn-off speed can be adjusted by selecting the appropriate resistor value. The soft turn-off reduces the
voltage overshoot considerably and may be used in combination with the two-level turn-off function of the IC.
The regular turn-off function at terminal OFF supports the soft turn-off as soon as the voltage between terminals
GATE and VEE2 drops below 3 V. An additional safety feature is installed by means of a watchdog timer, which
starts at the same time the soft turn-off is triggered. The watchdog turns off the IGBT in any case via terminal
OFF after 5 µs. If the soft-off function is not used, both the terminals SOFF and OFF can be combined to
increase the turn-off current capability of the IC.
Trigger conditions for a soft turn-off:






Desaturation condition at terminal DESAT
Overcurrent condition at terminal CS
Driver Enable OFF (EN equals GND1)
UVLO1 of the input side supply VCC1
UVLO of the input side logic reference PADP
Internal signal transmission error
Target datasheet
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5
Electrical parameters
5.1
Absolute maximum ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of
the integrated circuit. Unless otherwise noted all parameters refer to GND1 and to TA =25°C.
Table 4
Abs. maximum ratings
Parameter
Min.
Max.
Unit
Positive power supply input side
Symbol
VVCC1
-0.3
6.5
V
PADP voltage
VPADP
-0.3
16.05
PADN voltage
Voltage at terminals INN, INP, EN, RDY1, RDY2, /FLT, EN
Voltage at terminals SIGI, SIGO, SPEED
VPADN
-0.3
VTERMINAL -0.3
-0.3
0.3
VPADP
VVCC1
-5
-0.3
-0.3
-0.3
VVCC2
VVCC2
VVCC2
5.5
VVCC2
-0.3
20.3
VVEE2
-12
0.3
Maximum power supply voltage output side (VVCC2 - VVEE2)
Vmax2
–
28
Open drain output current (/FLT, RDY2, RDY1)
IOD
–
10
Output current at terminals SIGO
Peak output current at terminal ON (tp = 2 µs, f = 20 kHz)
ISIGO
-6
6
ION,pk
–
50
DC output current at terminal ON (VCC2 = 20 V)
ION,DC
–
10
Peak output current at terminal OFF (tp = 2 µs, , f = 20 kHz)
IOFF
–
2.4
Peak output current at terminal SOFF (tp = 2 µs, , f = 20 kHz)
ISOFF
–
1.05
Junction temperature
TJ
-40
125
TS
-55
125
PD,tot
–
980
mW
Rth(j-a)
–
102
K/W
VESD
–
tbd
kV
|dVISO/dt|
50
1)
Voltage at terminals DESAT
2)
Voltage at terminals GATE ,
1)
2)
2)
2)
Voltage at terminals OCOFF , RSENSE , OFF , SOFF
1)
2)
2)
2)
Voltage at terminals CS , VZ , CZ , PRB
Positive power supply output side
1)
Negative power supply output side
1)
Storage temperature
Total power dissipation
3)
Thermal resistance (Both chips active), TA = 25 °C
ESD Capability
HBM
4)
CDM
5)
Common mode transient immunity
mA
A
°C
tbd
–
kV/µs
1)
with respect to terminal GND2
with respect to terminal VEE2
3)
Power dissipation is derated linearly with 9.8 mW/°C above an ambient temperature of TA = 25°C. See Figure
18 for reference layouts for these thermal data. Thermal performance may change significantly with layout and
heat dissipation of components in close proximity.
4)
According to EIA/JESD22-A114-B
5)
According to EIA/JESD22-C101
2)
Target datasheet
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5.2
Operating range
Note: The IC operates as described in the functional description within the operating range. Unless otherwise
noted all parameters refer to terminal GND1 and (TA = 25°C).
Table 5
Operating parameters
Parameter
Positive power supply input side
Input side logic reference voltage VPADP - VPADN
Input side logic reference voltage VPADP - VPADN
Symbol
VVCC1
VPADP =3.3V VPAD
VPADP = 15V
Min.
Typ.
Max.
Unit
4.75
5
5.5
V
3
3.3
5.5
7
15
15.75
weitere Parameter aus abs max. ratings
Control voltage by terminal SPEED at terminal RSENSE
VIN,RSENSE
VVCC2- –
1.7
VSPEED
0
–
3.3
VVCC2
–
15
20
VVEE2
-12
-8
0
Power supply voltage output side
(VVCC2 - VVEE2)
Output current at terminal SIGO
Vmax2
–
–
25
ISIGO
-5
–
5
mA
Ambient temperature
TA
-40
–
105
°C
Voltage at terminal SPEED
2)
Positive power supply output side
Negative power supply output side
1)
1)
VVCC20.2V
1) With respect to terminal GND2.
2) With respect to terminal PADN
3) With respect to terminal VEE2
Target datasheet
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5.3
Electrical characteristics
Note: The electrical characteristics include the spread of values in supply voltages, load and junction
temperatures given below. Typical values represent the median values at TA = 25°C, VVCC1 = VPADP = 5V,
VPADN = VGND1 =, VVCC2 = 15V, VVEE2 = -8V and the given test conditions. Unless otherwise noted all voltages
are given with respect to their respective reference terminal (GND1 for terminals 19 to 36, GND2 for
terminals 1 to 18).
5.3.1
Voltage supply
Table 6
Voltage supply
Parameter
Symbol
UVLO threshold for VCC1
VUVLOH1
power up
power down VUVLOL1
UVLO hysteresis VCC1 (VUVLOH1 - VUVLOL1)
Min.
Typ.
Max.
–
–
tbd
tbd
–
–
Unit
Test condition
V
VRDY1 > tbd
VRDY1 < tbd
–
0.15
–
–
12.6
VRDY2 > tbd
10.4
–
–
VRDY2 < tbd
(VUVLOH2 - VUVLOL2) VUV,hys2
tbd
0.9
–
VUVLOH3
power up
power down VUVLOL3
tbd
–
tbd
VRDY1 > tbd
tbd
VRDY1 < tbd
UVLO threshold VCC2
UVLO hysteresis VCC2
VUVLO1,hys
Values
VUVLOH2
power up
power down VUVLOL2
UVLO threshold for PADP
tbd
–
UVLO hysteresis PADP (VUVLOH3 - VUVLOL3)
VUVLO3,hys
tbd
0.75
Quiescent current input side
IQ1
–
tbd
tbd
–
tbd
tbd
Quiescent current input side
mA
VINP = VPADP, VINN =
VPADN
VRDY1 = VRDY2 = VFLT
= VPADP
VINP = VPADP = VFLT
= VRDY1 = VRDY2 =
15V, VINN = VPADN
Quiescent current output side VCC2
IQ2
–
7
tbd
VINP = VPADP, VINN =
VPADN
VRDY1 = VRDY2 = VFLT
= VPADP
Quiescent current output side
IQ2,UVLO
–
tbd
tbd
tbd.
Quiescent current output side VEE2
IQ3
Quiescent current PADP
IQ4
5.3.2
Logic input and output
Table 7
Logic input and output
Parameter
Low level input voltage terminals INP, INN,
EN
Target datasheet
tbd
Symbol
VIL
tbd.
VINP = VPADP, VINN =
VPADN
VRDY1 = VRDY2 = 5 V
VFLT = 5 V
Values
Unit
Min.
Typ.
Max.
tbd
1.7
–
22
Test condition
V
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Table 7
Logic input and output
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Test condition
High level input voltage terminals INP, INN,
EN
VIH
–
3.3
tbd
Low level input voltage terminal SIGI
tbd
1.8
tbd
High level input voltage terminal SIGI
VIL,SIGI
VIH,SIGI
tbd
2.75
tbd
Low level output voltage terminal SIGO
V OL,SIGO
VGND1
0.2
High level output voltage terminal SIGO
V OH,SIGO
4.7
Low level output voltage terminals /FLT,
RDY1, RDY2
0.15
tbd
Input bias current INP
VOL,FLT,
VOL,RDY1,
VOL,RDY2
IIH,INP
4.3
–
0.5
VVCC1
tbd
55
tbd
Input bias current EN
IIH,EN
tbd
55
tbd
VEN = 5 V
Input bias current INN
IIL,INN
tbd
-740
tbd
VINN = 0 V
Input bias current SPEED
IIH,SPEED
tbd
TFILIN
tbd
tbd
–
VSPEED = 5 V
Input filter time terminals INP, INN, SIGI
5.6
–
Input filter time terminal EN
TFILEN
tbd
–
–
VEN = 5 V
Fault reset duration terminal EN
TEN,RST
tbd
–
tbd
VEN = 0 V
Propagation delay EN
TEN,ON
tbd
neuer Parameter !
Shut down propagation delay EN to SOFF
TEN,SOFF
tbd
neuer Parameter !
5.3.3
Gate driver
Table 8
Gate driver
Parameter
Symbol
Values
V
IIL,SIGO = 5mA
IIL,SIGO = - 5mA
IIL,pin = 5 mA
µA
ns
VINP = 5 V
VTERMINAL = 5 V
Unit
Test condition
V
IC in control mode
Min.
Typ.
Max.
VVCC21.7
tbd
–
VVCC20.2V
tbd
Detection of gate current level 2
tbd
VVCC20.29
tbd
2.75V≤VSPEED≤3.03
V
Detection of gate current level 3
tbd
VVCC20.38
tbd
2.48V≤VSPEED≤2.75
V
tbd
VVCC20.47
VVCC20.56
VVCC20.64
tbd
2.2V≤VSPEED≤2.48V
tbd
1.93V≤VSPEED≤2.2V
tbd
1.65V≤VSPEED≤1.93
V
Input voltage terminal RSENSE
VIN,RSENSE
Detection of gate current level 1
VRSENSE
Detection of gate current level 4
Detection of gate current level 5
1)
VRSENSE
tbd
VVCC20.2
3.03V ≤ VSPEED ≤
3.3V
Detection of gate current level 6
tbd
Detection of gate current level 7
tbd
VVCC20.73
tbd
1.38V≤VSPEED≤1.65
V
Detection of gate current level 8
tbd
VVCC20.82
tbd
1.11V≤VSPEED≤1.38
V
Target datasheet
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Table 8
Gate driver
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Detection of gate current level 9
tbd
VVCC20.91
tbd
Detection of gate current level 10
tbd
VVCC21.0
tbd
Detection of gate current level 11
tbd
VVCC21.57
tbd
VRSENSE hyseresis
tbd
–
tbd
VEE2+
–
tbd
VEE2+0.3 VEE2+
tbd
VEE2+2.3 VEE2+
tbd
VEE2+7 –
–
–
Low level output voltage terminal OFF
VOFFL
–
–
–
Low level output voltage terminal SOFF
VSOFFL
–
–
Input voltage terminal ON
VOH,ON
tbd
Test condition
0.83V≤VSPEED≤1.11
V
V
0.55V≤VSPEED≤0.83
V
0V≤VSPEED≤0.55V
mV
V
IOFFL = 20 mA
IOFFL = 200 mA
IOFFL = 1 A
IOFFL = 2 A
2)
VEE2+
tbd
VEE2+0.3 VEE2+
tbd
VEE2+7.3 VEE2+
tbd
ISOFFL = 20 mA
–
I_on = 8 mA
ISOFFL = 200 mA
ISOFFL = 1 A
–
I_on = -8 mA
VOL,ON
VVCC2tbd
–
VVCC2tbd
3
TPRB
–
135
tbd
ns
TSPEED
–
–
120
µs
IGBT is turn on
Fall time
TFALL
–
tbd
tbd
Turn-on propagation delay without PMOS
TPDON
–
460
tbd
ns
TA = 25°C
Turn-off propagation delay
TPDOFF
–
460
tbd
Turn-on propagation delay variation over
2)
junction temperature
Turn-off propagation delay variation over
2)
junction temperature
Matching delay (TPDON - TPDOFF)
TPDONt
tbd
–
tbd
TPDOFFt
–
–
tbd
MT
–
–
tbd
Matching delay over temperature (TPDONt 2)
TPDOFFt)
MTt
–
–
tbd
Turn-on clamping voltage terminal ON
VON,ON
–
Turn-off threshold voltage terminal GATE
VGATE,th
Preboost time
Speed setting propagation delay
2)
–
TA = 25°C
TA = 25°C
1) Default state after power on (VVCC1 > VUVLOH1)
2) The Parameter is not subject to production test - verified by design / characterization
Target datasheet
24
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EiceDRIVER™ Safe
1EDS - slew rate control IGBT driver IC
5.3.4
Desaturation protection (DESAT)
Table 9
Desaturation protection
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Test condition
Desaturation trigger level
VDESAT
tbd
9
tbd
V
Blanking capacitor charge current
tbd
500
tbd
µA
VDESAT = 2 V
Blanking capacitor discharge current
IDESAT,C
IDESAT,D
–
12
–
mA
VDESAT = 6 V
Desaturation leading edge blanking time
TDESATleb
–
tbd
–
ns
TDESATFIL
–
tbd
–
TSOFF
–
350
tbd
–
5
tbd
µs
–
700
tbd
ns
Desaturation filter time
1)
DESAT shut down propagation delay to
SOFF
DESAT shut down propagation delay to OFF TDESATOFF
TDESATFLT
DESAT to /FLT propagation delay
tbd
OCOFF = high
1) The Parameter is not subject to production test
5.3.5
Overcurrent protection disable (OCOFF)
Table 10
Overcurrent protection disable
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
High level input voltage terminal OCOFF
VIH,OCOFF
0.7 x
VVCC2
–
–
Low level input voltage terminal OCOFF
VIL,OCOFF
–
–
0.3 x
VVCC2
Input bias current OCOFF
IIH,OCOFF
–
140
tbd
5.3.6
Current sense (CS)
Table 11
Current sense
Parameter
Symbol
Values
Min.
Typ.
Max.
V
µA
VOCOFF = 15 V
Unit
Test condition
VSOFF < 4 V
VCS = 0 V
Current sense trigger threshold
VCS
tbd
350
tbd
V
Input bias current CS
IIH,CS
tbd
-115
tbd
µA
TCS,blank
–
tbd
–
ns
Shut down propagation delay CS to SOFF
TCS
–
400
tbd
Propagation delay CS to /FLT
TCS,FLT
–
700
tbd
Over current detection blanking time
1)
Test condition
tbd
1) The parameter is not subject to production test
Target datasheet
25
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EiceDRIVER™ Safe
1EDS - slew rate control IGBT driver IC
5.3.7
Two-level turn-off (CZ, VZ, GATE)
Table 12
Two-level turn-off
Parameter
Symbol
Values
Unit
Test condition
V
Terminal VZ
connected to VEE2
VZ open
connected to VEE2
RVZ = 27 kΩ
connected to VEE2
VCZ = VEE2 + 1V
Min.
Typ.
Max.
Tbd
11.7
Tbd
Tbd
10.6
Tbd
Tbd
9.5
Tbd
VTLTO,th
–
3
–
Two-level turn-off charging current
ICZ
tbd
1000
tbd
µA
Two-level turn-off time limitation
TTLLIM
Tbd
5
tbd
µs
VTLTO
Two-level voltage terminal VZ
Two-level turn-off threshold voltage
Two-level voltage slope
2)
1)
dVTLTO/dt
15
V/µs
1) Referenced to VEE2
2) The parameter is not subject to production test - verified by design / characterization
Target datasheet
26
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EiceDRIVER™ Safe
1EDS - slew rate control IGBT driver IC
6
Insulation characteristics
6.1
Reinforced insulation requirements according to VDE 0884-10 (pending)
Table 13
Reinforced insulation
Parameter
Symbol
Characteristic
Installation classification per EN 60664-1, Table 1
For rated mains voltage ≤ 150 Vrms
For rated mains voltage ≤ 300 Vrms
For rated mains voltage ≤ 600 Vrms
For rated mains voltage ≤ 1000 Vrms
Rated Impulse Voltage
I-IV = 4000 V
I-IV = 6000 V
I-IV = 8000 V
I-III = 8000 V
Climatic Classification according to IEC 68
40 / 105 / 21
Pollution degree (EN 60664-1)
Unit
2
Minimum external clearance
Minimum external creepage
Minimum Comparative Tracking Index
Maximum Repetitive Insulation Voltage
Input to output test voltage, method b
VIORM * 1.875 = VPR, productive test, tm = 1 sec,
Partial discharge < 5 pC
Highest allowable overvoltage
Maximum withstanding insulation voltage, 1 min
Insulation resistance at Ts, VIO = 500 V
CLR
CPG
CTI
VIORM
VPR
8.2
VIOTM
VISO
RIO
8000
mm
8.2
>400
1420
Vpk
2662
5000
9
> 10
Vrms
Ω
Notes
This coupler is suitable for “reinforced insulation” only within the safety ratings. Compliance with the safety
ratings shall be ensured by means of suitable protective circuits.
6.2
Recognized under UL 1577 (pending)
Table 14
Recognized under UL 1577
Parameter
Symbol
Insulation withstand voltage / 1 min
VISO
VISO
Insulation test voltage / 1 s
Target datasheet
27
Characteristic
5000
6000
Unit
VRMS
VRMS
<Revision 0.73>, 05.06.2014
EiceDRIVER™ Safe
1EDS - slew rate control IGBT driver IC
Timing diagrams
7
2.5 V
TPDON
INP
13.8 V
ON
2.5 V
TPDOFF
INN
2.5 V
2.5 V
13.8 V
ON
TPDOFF
TPDON
13.5V
13.5 V
OFF
OFF
TFALL
-5.5V
Figure 7
Timing of turn-on and turn-off propagation delay without two-level turn-off mode
EN
2.5V
TEN,ON
13.8V
ON
Figure 8
TEN,SOFF
13.5V
SOFF
TP > TFILIN
TP < TFILIN
TP
INP
TFILIN
INP
TP
TP > TFILIN
TFILIN
TP
ON
ON
TFILIN
TFILIN
TP
Timing of short pulse suppression terminal INP
TP < TFILIN
TP > TFILIN
TP < TFILIN
TP
INN
TFILIN
INN
TP
TP > TFILIN
TFILIN
TP
ON
Figure 10
2.5V
Timing of EN turn-on and shut down propagation delay
TP < TFILIN
Figure 9
EN
ON
TFILIN
TFILIN
TP
Timing of short pulse suppression terminal INN
Target datasheet
28
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EiceDRIVER™ Safe
1EDS - slew rate control IGBT driver IC
EN
TP < TFILEN
TP > TFILEN
TP
TP
TFILEN
TEN,ON
TP
ON
TFILEN
TFILEN
TP
Timing of short pulse suppression terminal EN and EN propagation delay to turn-on
TP < TFILIN
TP > TFILIN
TP < TFILIN
TP
SIGI
TFILIN
TP
INN
TP > TFILIN
TFILIN
TP
SIGO
Figure 12
TP > TFILIN
TP
TP
EN
TFILEN
ON
Figure 11
TP < TFILEN
ON
TFILIN
TFILIN
TP
Timing of short pulse suppression terminal SIGI
TP < TEN,RST
TP > TEN,RST
TP
TP
2.5V
EN
EN
TEN,RST
TEN,RST
TEN,SOFF
4.5V
/FLT
Figure 13
SOFF
Timing for fault reset at terminal EN (left) and EN shut down time to soft turn-off (right)
tCS,blank
VCS
CS
SOFF
tCS
tCS,FLT
/FLT
tEN,RST
EN
Figure 14
Timing of CS events incl. terminals SOFF, /FLT and EN
Target datasheet
29
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EiceDRIVER™ Safe
1EDS - slew rate control IGBT driver IC
INP
TPDON
TPDON
TSOFF
TPDOFF
SOFF
TPDON
TDESATOFF
OFF
TDESATFIL
TDESATleb
VDESAT
DESAT
Blanking time
TDESATleb
TDESATFLT
/FLT
TEN,RST
EN
Figure 15
Timing for DESAT events incl. terminals SOFF, /FLT and EN
INP
3V
CZ
VTLTOx
OFF
TPDOFF
TTLSET
TTLSET
TTLLIM
ON
Figure 16
TPDON
Timing for two-level turn-off incl. terminals CZ and OFF
Target datasheet
30
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EiceDRIVER™ Safe
1EDS - slew rate control IGBT driver IC
8
Package
8.1
PG-DSO-36
Figure 17
Package drawing
Target datasheet
31
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EiceDRIVER™ Safe
1EDS - slew rate control IGBT driver IC
Figure 18
Dimension [mm³]
25.0  31.5  1.5
therm [W/mK]
Material
FR4
0.3
Metalization [µm]
35
388
Vias
 = 0.3 mm; plating 25 µm; 14 pcs.
Package Attach [50µm]
Solder
55
PCB reference layout (left: top layer, right: bottom layer)
Thermal performance may change significantly with layout and heat dissipation of components in close
proximity.
Target datasheet
32
<Revision 0.73>, 05.06.2014
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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