Data Sheet

SI4410DY
N-channel TrenchMOS logic level FET
Rev. 03 — 4 December 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
„ DC motor control
„ Notebook computers
„ DC-to-DC convertors
„ Portable equipment
„ Lithium-ion battery applications
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C
-
-
30
V
ID
drain current
Tamb = 25 °C; pulsed;
see Figure 1 and 3
-
-
10
A
Ptot
total power
dissipation
Tamb = 25 °C; pulsed;
see Figure 2
-
-
2.5
W
VGS = 10 V; ID = 10 A;
VDS = 15 V; Tj = 25 °C;
see Figure 12
-
7
-
nC
VGS = 4.5 V; ID = 5 A;
Tj = 25 °C;
see Figure 10 and 11
-
15
20
mΩ
VGS = 10 V; ID = 10 A;
Tj = 25 °C;
see Figure 10 and 11
-
11
13.5
mΩ
Dynamic characteristics
QGD
gate-drain charge
Static characteristics
RDSon
drain-source
on-state resistance
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
Symbol
Description
1
S
source
2
S
source
3
S
source
4
G
gate
5
D
drain
6
D
drain
7
D
drain
8
D
drain
Simplified outline
8
Graphic symbol
D
5
G
1
mbb076
4
S
SOT96-1 (SO8)
3. Ordering information
Table 3.
Ordering information
Type number
SI4410DY
Package
Name
Description
Version
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 150 °C
-
30
V
VGS
gate-source voltage
-20
20
V
ID
drain current
Tamb = 70 °C; pulsed;
see Figure 1
-
8
A
Tamb = 25 °C; pulsed;
see Figure 1 and 3
-
10
A
IDM
peak drain current
tp ≤ 10 µs; Tamb = 25 °C; pulsed;
see Figure 3
-
50
A
Ptot
total power dissipation
Tamb = 70 °C; pulsed;
see Figure 2
-
1.6
W
Tamb = 25 °C; pulsed;
see Figure 2
-
2.5
W
Tstg
storage temperature
-55
150
°C
Tj
junction temperature
-55
150
°C
-
2.3
A
Source-drain diode
IS
source current
Tamb = 25 °C; pulsed
SI4410DY_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 4 December 2009
2 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa19
120
Ider
(%)
Pder
(%)
80
80
40
40
0
0
0
Fig 1.
03aa11
120
50
100
150
200
Tamb (°C)
0
Normalized continuous drain current as a
function of ambient temperature
Fig 2.
50
100
150
200
Tamb (°C)
Normalized total power dissipation as a
function of ambient temperature
03ae23
102
RDSon = VDS/ID
ID
(A)
tp = 10 µs
1 ms
10
10 ms
1
100 ms
δ=
P
D.C.
tp
T
10−1
10 s
t
tp
10−2
10−1
T
1
102
10
VDS (V)
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
SI4410DY_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 4 December 2009
3 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Rth(j-sp)
Rth(j-a)
Conditions
Min
Typ
Max
Unit
thermal resistance from
junction to solder point
-
-
-
K/W
thermal resistance from mounted on a printed-circuit board;
junction to ambient
minimum footprint; tp ≤ 10 s;
see Figure 4
-
-
50
K/W
03ad49
102
Zth(j-amb)
(K/W)
δ = 0.5
0.2
10
0.1
0.05
0.02
1
δ=
P
10−1
tp
T
single pulse
t
tp
T
10−2
10−4
Fig 4.
10−3
10−2
10−1
1
10
102
tp (s)
103
Transient thermal impedance from junction to solder point as a function of pulse duration
SI4410DY_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 4 December 2009
4 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
VGS(th)
gate-source threshold
voltage
ID = 250 µA; VDS= VGS; Tj = 25 °C;
see Figure 9
1
-
-
V
IDSS
drain leakage current
VDS = 30 V; VGS = 0 V; Tj = 25 °C
-
-
1
µA
VDS = 30 V; VGS = 0 V; Tj = 55 °C
-
-
25
µA
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = -20 V; VDS = 0 V; Tj = 25 °C
-
-
100
nA
VGS = 4.5 V; ID = 5 A; Tj = 25 °C;
see Figure 10 and 11
-
15
20
mΩ
VGS = 10 V; ID = 10 A; Tj = 25 °C;
see Figure 10 and 11
-
11
13.5
mΩ
VDS ≥ 5 V; VGS = 10 V
20
-
-
A
ID = 10 A; VDS = 15 V; VGS = 5 V;
Tj = 25 °C; see Figure 12
-
21.5
34
nC
ID = 10 A; VDS = 15 V; VGS = 10 V;
Tj = 25 °C; see Figure 12
-
40
60
nC
-
8
-
nC
-
7
-
nC
-
13.5
30
ns
-
9
20
ns
IGSS
RDSon
IDSon
gate leakage current
drain-source on-state
resistance
on-state drain-source
current
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGD
gate-drain charge
td(on)
turn-on delay time
tr
rise time
td(off)
turn-off delay time
-
70
100
ns
tf
fall time
-
30
80
ns
gfs
transfer conductance
VDS = 15 V; ID = 10 A; Tj = 25 °C;
see Figure 13
-
34
-
S
VDS = 25 V; RL = 25 Ω; VGS = 10 V;
RG(ext) = 6 Ω; Tj = 25 °C
Source-drain diode
VSD
source-drain voltage
IS = 2.3 A; VGS = 0 V; Tj = 25 °C;
see Figure 14
-
0.7
1.1
V
trr
reverse recovery time
IS = 2.3 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 25 V; Tj = 25 °C
-
50
80
ns
SI4410DY_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 4 December 2009
5 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ad50
50
10 V
ID
(A)
5V
3.8 V
ID
VDS > ID x R DSon
(A)
40
3.6 V
40
03ad52
50
3.4 V
30
30
3.2 V
20
20
3V
2.8 V
10
10
Tj = 150 °C
VGS = 2.6 V
25 °C
0
0
0
Fig 5.
0.5
1
VDS (V)
1.5
Output characteristics: drain current as a
function of drain-source voltage; typical values
03aa36
10-1
ID
(A)
0
Fig 6.
1
2
3
VGS (V)
4
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
03ad54
104
C
10-2
(pF)
10-3
min
typ
max
Ciss
103
10-4
Coss
10-5
Crss
10-6
10
0
Fig 7.
1
2
VGS (V)
3
Sub-threshold drain current as a function of
gate-source voltage
Fig 8.
10−1
10
VDS (V)
102
Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
SI4410DY_3
Product data sheet
1
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 4 December 2009
6 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa33
2.5
VGS(th)
(V)
03ad51
0.03
RDSon
(Ω)
2
Tj = 25 °C VGS = 3.2 V
3.4 V
3.6 V 3.8 V
max
0.02
1.5
4.5 V
typ
5V
min
1
10 V
0.01
0.5
0
-60
Fig 9.
0
0
60
120
Gate-source threshold voltage as a function of
junction temperature
03ad57
2
0
180
Tj (°C)
20
30
40
ID (A)
50
Fig 10. Drain-source on-state resistance as a function
of drain current; typical values
03ad55
10
VGS
a
10
ID = 10 A
(V)
8
VDD = 15 V
1.5
Tj = 25 ºC
6
1
4
0.5
2
0
−60
0
0
60
120
Tj (°C)
180
Fig 11. Normalized drain-source on-state resistance
factor as a function of junction temperature
0
20
30
QG (nC)
40
Fig 12. Gate-source voltage as a function of gate
charge; typical values
SI4410DY_3
Product data sheet
10
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 4 December 2009
7 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ae24
40
gfs
VDS > ID x RDSon
(S)
VGS = 0 V
40
Tj = 25 °C
30
03ad53
50
IS
(A)
30
150 °C
20
20
10
10
150 °C
Tj = 25 °C
0
0
0
10
20
30
40
50
0
ID (A)
Fig 13. Forward transconductance as a function of
drain current; typical values
0.8
1.2
VSD (V)
1.6
Fig 14. Source current as a function of source-drain
voltage; typical values
SI4410DY_3
Product data sheet
0.4
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 4 December 2009
8 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
inches
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
o
8
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 15. Package outline SOT96-1 (SO8)
SI4410DY_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 4 December 2009
9 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SI4410DY_3
20091204
Product data sheet
-
SI4410DY-02
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
SI4410DY-02
20010705
Product specification
-
SI4410DY-01
SI4410DY-01
20010220
Product specification
-
-
SI4410DY_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 4 December 2009
10 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URLhttp://www.nxp.com.
9.2
Definitions
Draft— The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet— A short data sheet is an extract from a full data sheet with
the same product type number(s) and title. A short data sheet is intended for
quick reference only and should not be relied upon to contain detailed and full
information. For detailed and full information see the relevant full data sheet,
which is available on request via the local NXP Semiconductors sales office.
In case of any inconsistency or conflict with the short data sheet, the full data
sheet shall prevail.
9.3
Disclaimers
General— Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes— NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use— NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications— Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data— The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values— Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale— NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
athttp://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license— Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control— This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS— is a trademark of NXP B.V.
10. Contact information
For more information, please visit:http://www.nxp.com
For sales office addresses, please send an email to:[email protected]
SI4410DY_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 4 December 2009
11 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10
Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 4 December 2009
Document identifier: SI4410DY_3
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