Data Sheet

PHD38N02LT
N-channel TrenchMOS logic level FET
Rev. 02 — 2 February 2007
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
n Low on-state resistance
n 2.5 V gate drive
1.3 Applications
n Linear regulator for Double-Data Rate (DDR) memory
1.4 Quick reference data
n VDS ≤ 20 V
n RDSon ≤ 16 mΩ
n ID ≤ 44.7 A
n Ptot ≤ 57.6 W
2. Pinning information
Table 1.
Pinning
Pin
Description
1
gate (G)
2
drain (D)
3
source (S)
mb
mounting base; connected to drain (D)
Simplified outline
Symbol
D
mb
[1]
G
mbb076
2
1
3
SOT428 (DPAK)
[1]
It is not possible to make a connection to pin 2.
S
PHD38N02LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2.
Ordering information
Type number
PHD38N02LT
Package
Name
Description
Version
DPAK
plastic single-ended surface-mounted package; 3 leads
(one lead cropped)
SOT428
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
20
V
VDGR
drain-gate voltage (DC)
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
20
V
VGS
gate-source voltage
-
±12
V
ID
drain current
Tmb = 25 °C; VGS = 5 V; see Figure 2 and 3
-
44.7
A
Tmb = 100 °C; VGS = 5 V; see Figure 2
-
31.6
A
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
-
179
Tmb = 25 °C; see Figure 1
Ptot
total power dissipation
-
57.6
W
Tstg
storage temperature
−55
+175
°C
Tj
junction temperature
−55
+175
°C
Source-drain diode
IS
source current
Tmb = 25 °C
-
44.7
A
ISM
peak source current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
-
179
A
PHD38N02LT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
2 of 12
PHD38N02LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa16
120
03aa24
120
Ider
Pder
(%)
(%)
80
80
40
40
0
0
0
50
100
150
Tmb (°C)
200
P tot
P der = ------------------------ × 100 %
P tot ( 25°C )
0
50
100
150
200
Tmb (°C)
ID
I der = -------------------- × 100 %
I D ( 25°C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
003aab706
103
ID
(A)
Limit RDSon = VDS / ID
tp = 10 µ s
2
10
100 µ s
10
1 ms
DC
10 ms
1
1
10
102
VDS (V)
Tmb = 25 °C; IDM is single pulse; VGS = 5 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHD38N02LT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
3 of 12
PHD38N02LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4.
Thermal characteristics
Symbol Parameter
Conditions
Rth(j-mb)
thermal resistance from junction to mounting base see Figure 4
Rth(j-a)
thermal resistance from junction to ambient
SOT428
minimum footprint
SOT404 minimum footprint
[1]
[1]
Min
Typ
Max
Unit
-
-
2.6
K/W
-
75
-
K/W
-
50
-
K/W
Mounted on a printed-circuit board; vertical in still air.
003aab707
10
Zth(j-mb)
(K/W)
1 δ = 0.5
0.2
0.1
0.05
-1
10
δ=
P
0.02
tp
T
single pulse
t
tp
T
10-2
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PHD38N02LT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
4 of 12
PHD38N02LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5.
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tj = 25 °C
20
-
-
V
Tj = −55 °C
18
-
-
V
Static characteristics
V(BR)DSS drain-source breakdown
voltage
VGS(th)
IDSS
gate-source threshold voltage
drain leakage current
ID = 250 µA; VGS = 0 V
ID = 250 µA; VDS = VGS; see Figure 9 and 10
Tj = 25 °C
0.5
1.0
1.5
V
Tj = 175 °C
0.3
-
-
V
Tj = −55 °C
-
-
1.8
V
VDS = 20 V; VGS = 0 V
Tj = 25 °C
-
0.05
1.0
µA
Tj = 175 °C
-
-
500
µA
-
10
100
nA
IGSS
gate leakage current
VGS = ±12 V; VDS = 0 V
RDSon
drain-source on-state
resistance
VGS = 5 V; ID = 25 A; see Figure 6 and 8
Tj = 25 °C
-
13.5
16
mΩ
Tj = 175 °C
-
24.3
28.8
mΩ
-
15.1
-
nC
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGD
gate-drain charge
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer capacitance
td(on)
turn-on delay time
tr
rise time
td(off)
tf
ID = 25 A; VDS = 10 V; VGS = 5 V;
see Figure 11 and 12
-
4.5
-
nC
-
4.2
-
nC
VGS = 0 V; VDS = 20 V; f = 1 MHz;
see Figure 14
-
800
-
pF
-
260
-
pF
-
190
-
pF
VDS = 10 V; ID = 25 A; VGS = 10 V;
RG = 5.6 Ω
-
4
-
ns
-
12.5
-
ns
turn-off delay time
-
30
-
ns
fall time
-
23
-
ns
-
0.98
1.2
V
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; see Figure 13
PHD38N02LT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
5 of 12
PHD38N02LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab708
30
Tj = 25 °C 10 V 5 V
ID
(A)
3V
2.6 V
2.4 V
003aab710
30
Tj = 25 °C
RDSon
(mΩ)
VGS = 2.4 V
2.6 V
20
20
2.2 V
2V
10
3V
5V
10 V
10
1.8 V
VGS = 1.6 V
0
0
0
0.2
0.4
0.6
0.8
VDS (V)
1
0
Tj = 25 °C
10
20
30
ID (A)
Tj = 25 °C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of drain current; typical values
003aab709
25
ID
(A)
03af18
2
a
20
1.5
15
1
10
0.5
5
175 °C
Tj = 25 °C
0
0
1
2
VGS (V)
3
Tj = 25 °C and 175 °C; VDS > ID × RDSon
0
-60
60
120
Tj (°C)
180
R DSon
a = ----------------------------R DSon ( 25°C )
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
PHD38N02LT_2
Product data sheet
0
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
6 of 12
PHD38N02LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
03al82
2
VGS(th)
03an65
10-3
ID
(A)
(V)
1.5
max
1
10-4
typ
typ
min
10-5
max
min
0.5
10-6
0
-60
0
60
120
180
0
0.4
0.8
Tj (°C)
1.2
1.6
VGS (V)
Tj = 25 °C; VDS = 5 V
ID = 0.25 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
003aab713
10
VGS
(V)
ID = 25 A
Tj = 25 °C
VDS = 10 V
8
VDS
ID
6
VGS(pl)
4
VGS(th)
VGS
2
QGS1
QGS2
QGS
0
0
10
20
QG (nC)
30
QGD
QG(tot)
003aaa508
ID = 25 A; VDS = 10 V
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Gate charge waveform definitions
PHD38N02LT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
7 of 12
PHD38N02LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab712
25
IS
(A)
003aab711
104
VGS = 0 V
20
C
(pF)
15
103
Ciss
10
Coss
5
Tj = 25 °C
175 °C
Crss
0
0
0.3
0.6
0.9
VSD (V)
1.2
Tj = 25 °C and 175 °C; VGS = 0 V
102
10-1
10
VDS (V)
102
VGS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain
voltage; typical values
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PHD38N02LT_2
Product data sheet
1
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
8 of 12
PHD38N02LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)
SOT428
y
E
A
A
A1
b2
E1
mounting
base
D2
D1
HD
2
L
L2
1
L1
3
b1
b
w
M
c
A
e
e1
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
b1
b2
c
D1
D2
min
E
E1
min
e
e1
HD
L
L1
min
L2
w
y
max
mm
2.38
2.22
0.93
0.46
0.89
0.71
1.1
0.9
5.46
5.00
0.56
0.20
6.22
5.98
4.0
6.73
6.47
4.45
2.285
4.57
10.4
9.6
2.95
2.55
0.5
0.9
0.5
0.2
0.2
OUTLINE
VERSION
SOT428
REFERENCES
IEC
JEDEC
JEITA
TO-252
SC-63
EUROPEAN
PROJECTION
ISSUE DATE
06-02-14
06-03-16
Fig 15. Package outline SOT428 (DPAK)
PHD38N02LT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
9 of 12
PHD38N02LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 6.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PHD38N02LT_2
20070202
Product data sheet
-
PHB_PHD38N02LT-01
Modifications:
PHB_PHD38N02LT-01
(9397 750 11614)
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
PHB38N02LT has been discontinued.
20030630
Product data
-
PHD38N02LT_2
Product data sheet
-
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
10 of 12
PHD38N02LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
PHD38N02LT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
11 of 12
PHD38N02LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
11
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 2 February 2007
Document identifier: PHD38N02LT_2
Similar pages