Data Sheet

Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection. It is intended for use in
DC-DC converters and general
purpose switching applications.
PINNING - SOT223
PIN
PHT8N06LT
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
PIN CONFIGURATION
MAX.
UNIT
55
7.5
1.8
150
80
V
A
W
˚C
mΩ
SYMBOL
DESCRIPTION
d
4
1
gate
2
drain
3
source
4
drain (tab)
g
2
1
s
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
ID
Drain current (DC)
IDM
Ptot
Ptot
Drain current (pulse peak value)
Total power dissipation
Total power dissipation
Tstg, Tj
Storage & operating temperature
RGS = 20 kΩ
Tsp = 25 ˚C
On PCB in Fig.2
Tamb = 25 ˚C
On PCB in Fig.2
Tamb = 100 ˚C
Tsp = 25 ˚C
Tsp = 25 ˚C
On PCB in Fig.2
Tamb = 25 ˚C
-
MIN.
MAX.
UNIT
-
55
55
13
7.5
3.5
V
V
V
A
A
-
2.2
A
-
40
8.3
1.8
A
W
W
- 55
150
˚C
MIN.
MAX.
UNIT
-
2
kV
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
VC
Electrostatic discharge capacitor
voltage
Human body model
(100 pF, 1.5 kΩ)
January 1998
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHT8N06LT
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
Rth j-sp
Rth j-amb
From junction to solder point
From junction to ambient
Mounted on any PCB
Mounted on PCB of Fig.17
TYP.
MAX.
UNIT
12
-
15
70
K/W
K/W
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA
VGS(TO)
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 150˚C
Tj = -55˚C
IDSS
Zero gate voltage drain current
VDS = 55 V; VGS = 0 V;
IGSS
Gate source leakage current
VGS = ±5 V
±V(BR)GSS
RDS(ON)
Gate source breakdown voltage IG = ±1 mA
Drain-source on-state
VGS = 5 V; ID = 5 A
resistance
Tj = 150˚C
Tj = 150˚C
Tj = 150˚C
MIN.
TYP.
MAX.
UNIT
55
50
1.0
0.6
10
-
1.5
0.05
0.02
65
-
2.0
2.3
10
100
1
5
80
148
V
V
V
V
V
µA
µA
µA
µA
V
mΩ
mΩ
MIN.
TYP.
MAX.
UNIT
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
gfs
Forward transconductance
VDS = 25 V; ID = 5 A; Tj = 25˚C
4
-
-
S
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 7 A; VDD = 44 V; VGS = 5 V
-
11.2
2.2
5
-
nC
nC
nC
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
500
110
60
650
135
85
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 7 A;
VGS = 5 V; RG = 10 Ω;
-
10
30
30
30
15
50
45
40
ns
ns
ns
ns
MIN.
TYP.
MAX.
UNIT
Tj = 25˚C
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = -55 to 175˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
IDR
Tsp = 25˚C
-
-
7.5
A
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Tsp = 25˚C
IF = 5 A; VGS = 0 V
-
0.85
40
1.1
A
V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 5 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
38
0.2
-
ns
µC
January 1998
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHT8N06LT
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 2.5 A; VDD ≤ 25 V;
VGS = 5 V; RGS = 50 Ω; Tsp = 25 ˚C
January 1998
3
MIN.
TYP.
MAX.
UNIT
-
-
30
mJ
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
120
PHT8N06LT
Normalised Power Derating
PD%
Zth/ (K/W)
100
110
100
90
10
0.5
80
0.2
70
60
50
0.1
0.05
1
0.02
40
30
PD
tp
D=
0.1
20
10
tp
T
t
T
0
0
20
40
60
80
100
Tmb / C
120
140
0.01
1.0E-06
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tsp)
120
0.01
t/s
1
100
Fig.4. Transient thermal impedance.
Zth j-sp = f(t); parameter D = tp/T
Normalised Current Derating
ID%
0.0001
Drain current, ID (A)
40
10
7
6
110
100
90
VGS = 5.0 V
4.6
30
80
70
4.0
60
50
20
3.6
40
30
3.2
3.0
10
20
10
2.6
2.4
0
0
20
40
60
80
Tmb / C
100
120
140
0
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 5 V
0
2
4
6
8
Drain-source voltage, VDS (V)
10
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
100
115
RDS(ON)/mOhm
ID/A
110
RDS(ON) = VDS/ID
tp =
10
DC
4.2
105
1 us
10us
4
4.4
100
100 us
95
1 ms
90
1
4.6
4.8
5
85
10ms
80
100ms
75
0.1
1
10
VDS/V
70
100
Fig.3. Safe operating area. Tsp = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
January 1998
5
10
ID/A
15
20
25
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHT8N06LT
20
2.5
VGS(TO) / V
ID/A
BUK98xx-55
max.
2
15
typ.
1.5
10
min.
1
5
0.5
Tj/C =
0
25
150
0
1
2
VGS/V
3
4
0
-100
5
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
-50
0
50
Tj / C
150
200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Transconductance, gfs (S)
15
100
Sub-Threshold Conduction
1E-01
14
13
1E-02
12
11
2%
1E-03
typ
98%
10
9
1E-04
8
7
1E-05
6
5
0
5
10
Drain current, ID (A)
15
1E-05
20
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
2.5
BUK98XX-55
a
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
1
Rds(on) normalised to 25degC
.9
.8
Thousands pF
2
1.5
.7
.6
.5
Ciss
.4
.3
1
.2
.1
0.5
-100
-50
0
50
Tmb / degC
100
150
0
0.01
200
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5 A; VGS = 5 V
January 1998
Coss
Crss
0.1
1
VDS/V
10
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
5
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHT8N06LT
6
120
110
VDS/V
5
WDSS%
100
90
VDS = 14V
4
80
70
VDS = 44V
60
3
50
40
2
30
20
1
10
0
0
0
2
4
6
QG/nC
8
10
20
12
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 7 A; parameter VDS
40
60
80
100
Tmb / C
120
140
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tsp); conditions: ID = 2.5 A
40
VDD
+
IF/A
L
30
Tj/V =
VDS
25
150
-
VGS
20
-ID/100
T.U.T.
0
10
RGS
0
0
0.5
1
VSDS/V
1.5
2
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
January 1998
R 01
shunt
6
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHT8N06LT
PRINTED CIRCUIT BOARD
Dimensions in mm.
36
18
60
4.5
4.6
9
10
7
15
50
Fig.17. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick).
January 1998
7
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHT8N06LT
MECHANICAL DATA
Dimensions in mm
6.7
6.3
Net Mass: 0.11 g
B
3.1
2.9
0.32
0.24
0.2
4
A
A
0.10
0.02
16
max
M
7.3
6.7
3.7
3.3
13
2
1
10
max
1.8
max
1.05
0.80
2.3
0.60
0.85
4.6
3
0.1 M
B
(4x)
Fig.18. SOT223 surface mounting package.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to surface mounting instructions for SOT223 envelope.
3. Epoxy meets UL94 V0 at 1/8".
January 1998
8
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHT8N06LT
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
January 1998
9
Rev 1.100
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