D2 PA K PSMN057-200B N-channel TrenchMOS SiliconMAX standard level FET 15 August 2013 Product data sheet 1. General description SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 2. Features and benefits • • • Higher operating power due to low thermal resistance Low conduction losses due to low on-state resistance Suitable for high frequency applications due to fast switching characteristics 3. Applications • • DC-to-DC converters Switched-mode power supplies 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 200 V ID drain current Tmb = 25 °C - - 39 A Ptot total power dissipation - - 250 W VGS = 10 V; ID = 17 A; Tj = 25 °C - 41 57 mΩ VGS = 10 V; ID = 39 A; VDS = 160 V; - 37 50 nC Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge Tj = 25 °C Scan or click this QR code to view the latest information for this product PSMN057-200B NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 G gate 2 D drain 3 S source mb D mounting base; connected to drain Graphic symbol mb D G 1 S mbb076 2 3 D2PAK (SOT404) 6. Ordering information Table 3. Ordering information Type number Package PSMN057-200B Name Description Version D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404 (one lead cropped) 7. Marking Table 4. Marking codes Type number Marking code PSMN057-200B PSMN057-200B 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 200 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 200 V VGS gate-source voltage -20 20 V ID drain current Tmb = 100 °C - 27.5 A Tmb = 25 °C - 39 A IDM peak drain current pulsed; Tmb = 25 °C - 156 A Ptot total power dissipation Tmb = 25 °C - 250 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C PSMN057-200B Product data sheet All information provided in this document is subject to legal disclaimers. 15 August 2013 © NXP N.V. 2013. All rights reserved 2 / 11 PSMN057-200B NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET Symbol Parameter Conditions Min Max Unit Source-drain diode IS source current Tmb = 25 °C - 39 A ISM peak source current pulsed; Tmb = 25 °C - 156 A VGS = 10 V; Tj(init) = 25 °C; ID = 35 A; - 300 mJ - 35 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Vsup ≤ 50 V; unclamped; tp = 100 µs; RGS = 50 Ω IAS non-repetitive avalanche current Vsup ≤ 50 V; VGS = 10 V; Tj(init) = 25 °C; RGS = 50 Ω; unclamped 003aae646 100 Pder (%) 80 60 60 40 40 20 20 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 Normalized total power dissipation as a function of mounting base temperature Fig. 2. 003aae648 103 IDM (A) 0 50 100 150 200 Normalized continuous drain current as a function of mounting base temperature 003aae660 102 tp = 10 µs D.C. 25 °C 10 100 µs 10 Tmb (°C) lAS (A) RDS(on) = VDS / ID 102 003aae647 100 ID (%) 80 Tj prior to avalanche = 150 °C 1 ms 10 ms 1 Fig. 3. 100 ms 1 10 102 VDS (V) 1 10- 3 103 10- 2 10- 1 1 tAV (ms) 10 Tmb = 25 °C; IDM is single pulse unclamped inductive load Safe operating area; continuous and peak drain Fig. 4. currents as a function of drain-source voltage Single-shot avalanche rating; avalanche current as a function of avalanche period PSMN057-200B Product data sheet All information provided in this document is subject to legal disclaimers. 15 August 2013 © NXP N.V. 2013. All rights reserved 3 / 11 PSMN057-200B NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-mb) thermal resistance from junction to mounting base Rth(j-a) thermal resistance from junction to ambient minimum footprint ; FR4 board 10- 1 10- 2 Max Unit - - 0.6 K/W - 50 - K/W δ = 0.5 0.2 0.1 0.05 0.02 P δ= single pulse tp 10- 3 10- 6 Fig. 5. Typ 003aae649 1 Zth(j-mb) (K/W) Min 10- 5 10- 4 10- 3 10- 2 tp T t T 10- 1 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 200 - - V ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 178 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 175 °C 1 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C 2 3 4 V ID = 1 mA; VDS = VGS; Tj = -55 °C - - 4.4 V VDS = 200 V; VGS = 0 V; Tj = 175 °C - - 500 µA VDS = 200 V; VGS = 0 V; Tj = 25 °C - 0.03 10 µA VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; ID = 17 A; Tj = 175 °C - - 165 mΩ VGS = 10 V; ID = 17 A; Tj = 25 °C - 41 57 mΩ Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance PSMN057-200B Product data sheet All information provided in this document is subject to legal disclaimers. 15 August 2013 © NXP N.V. 2013. All rights reserved 4 / 11 PSMN057-200B NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET Symbol Parameter Conditions Min Typ Max Unit RG internal gate resistance (AC) f = 1 MHz - 2 4.1 Ω total gate charge ID = 39 A; VDS = 160 V; VGS = 10 V; - 96 135 nC QGS gate-source charge Tj = 25 °C - 13 - nC QGD gate-drain charge - 37 50 nC Ciss input capacitance VDS = 25 V; VGS = 0 V; f = 1 MHz; - 3750 5036 pF Coss output capacitance Tj = 25 °C - 385 520 pF Crss reverse transfer capacitance - 180 252 pF td(on) turn-on delay time VDS = 100 V; RL = 2.7 Ω; VGS = 10 V; - 18 - ns tr rise time RG(ext) = 5.6 Ω; Tj = 25 °C - 58 - ns td(off) turn-off delay time - 105 - ns tf fall time - 78 - ns LD internal drain inductance measured from tab to centre of die ; Tj = 25 °C - 3.5 - nH LS internal source inductance measured from source lead to source bond pad ; Tj = 25 °C - 7.5 - nH Dynamic characteristics QG(tot) Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C - 0.85 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 133 173 ns Qr recovered charge VDS = 30 V; Tj = 25 °C - 895 - nC 003aae650 50 lD (A) 40 VGS(V) = 10 4.8 4.8 4.6 10 Fig. 6. 4.6 0.1 5.2 5 20 0 4.2 4.4 RDS(on) (Ω) 8 6 30 003aae651 0.14 5 0.06 5.2 4.4 4.2 0 0.4 0.8 1.2 1.6 2 VDS (V) 0.02 6 VGS (V) = 10 0 10 20 30 40 ID (A) 50 Tj = 25 °C Tj = 25 °C Output characteristics: drain current as a Fig. 7. function of drain-source voltage; typical values Drain-source on-state resistance as a function of drain current; typical values PSMN057-200B Product data sheet All information provided in this document is subject to legal disclaimers. 15 August 2013 © NXP N.V. 2013. All rights reserved 5 / 11 PSMN057-200B NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 003aae652 40 003aae653 50 gfs (S) 40 ID (A) 30 Tj = 25 °C Tj = 175 °C 30 20 20 Tj = 175 °C 10 0 10 Tj = 25 °C 0 2 4 0 6 VGS (V) VDS > ID x RDSon Fig. 8. 0 10 20 30 ID (A) 40 VDS > ID x RDSon Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aae654 2.9 Fig. 9. Forward transconductance as a function of drain current; typical values 003aae655 5 VGS(th) (V) 4 a 2.1 1.3 maximum 3 typical 2 minimum 1 0.5 - 60 20 100 Tj (°C) 0 - 60 180 Fig. 10. Normalized drain-source on-state resistance factor as a function of junction temperature 003aae656 10- 1 lD (A) 10- 2 20 100 Tj (°C) 180 ID = 1 mA; VDS = VGS Fig. 11. Gate-source threshold voltage as a function of junction temperature 003aae657 104 Ciss C (pF) 10- 3 minimum 10- 4 typical 103 maximum Coss Crss 10- 5 10- 6 0 1 2 3 4 VGS (V) 102 10- 1 5 Tj = 25 °C; VDS = VGS Product data sheet 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig. 12. Sub-threshold drain current as a function of gate-source voltage PSMN057-200B 1 Fig. 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. 15 August 2013 © NXP N.V. 2013. All rights reserved 6 / 11 PSMN057-200B NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 003aae658 16 003aae659 40 IF (A) VGS (V) 30 12 8 VDD = 40 V 20 VDD = 160 V 10 4 0 Tj = 25 °C Tj = 175 °C 0 40 80 120 QG (nC) 0 160 Fig. 14. Gate-source voltage as a function of gate charge; typical values Product data sheet 0.4 0.8 VSDS (V) 1.2 VGS = 0 V Tj = 25 °C; ID = 39 A PSMN057-200B 0 Fig. 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values All information provided in this document is subject to legal disclaimers. 15 August 2013 © NXP N.V. 2013. All rights reserved 7 / 11 PSMN057-200B NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 11. Package outline Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 b2 c b e e Q 0 5 mm scale Dimensions (mm are the original dimensions) Unit max nom min mm A A1 b b2 c 4.5 1.40 0.85 1.45 0.64 4.1 1.27 0.60 1.05 0.46 D D1 E 11 1.6 10.3 1.2 9.7 e 2.54 HD Lp Q 15.8 2.9 2.6 14.8 2.1 2.2 sot404_po Outline version References IEC JEDEC JEITA European projection Issue date 06-03-16 13-02-25 SOT404 Fig. 16. Package outline D2PAK (SOT404) PSMN057-200B Product data sheet All information provided in this document is subject to legal disclaimers. 15 August 2013 © NXP N.V. 2013. All rights reserved 8 / 11 PSMN057-200B NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. Legal information 12.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Document status [1][2] Product status [3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Definition Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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PSMN057-200B Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the All information provided in this document is subject to legal disclaimers. 15 August 2013 © NXP N.V. 2013. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. PSMN057-200B Product data sheet All information provided in this document is subject to legal disclaimers. 15 August 2013 © NXP N.V. 2013. All rights reserved 10 / 11 PSMN057-200B NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 13. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 4 11 Package outline ..................................................... 8 12 12.1 12.2 12.3 12.4 Legal information ...................................................9 Data sheet status ................................................. 9 Definitions .............................................................9 Disclaimers ...........................................................9 Trademarks ........................................................ 10 © NXP N.V. 2013. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 August 2013 PSMN057-200B Product data sheet All information provided in this document is subject to legal disclaimers. 15 August 2013 © NXP N.V. 2013. All rights reserved 11 / 11