Data Sheet

PHB47NQ10T
N-channel TrenchMOS standard level FET
Rev. 02 — 25 February 2010
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
„ DC-to-DC convertors
„ Switched-mode power supplies
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
100
V
ID
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1 and 2
-
-
47
A
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 3
-
-
166
W
VGS = 10 V; ID = 40 A;
VDS = 80 V; Tj = 25 °C;
see Figure 13
-
21
-
nC
VGS = 10 V; ID = 25 A;
Tj = 25 °C;
see Figure 11 and 12
-
20
28
mΩ
Dynamic characteristics
QGD
gate-drain charge
Static characteristics
RDSon
drain-source
on-state resistance
PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
2. Pinning information
Table 2.
Pinning information
Pin
Symbol
Description
1
G
gate
2
D
drain
Simplified outline
S
source
mb
D
mounting base; connected to
drain
D
mb
[1]
3
Graphic symbol
G
mbb076
S
2
1
3
SOT404 (D2PAK)
[1]
It is not possible to make a connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Type number
PHB47NQ10T
PHB47NQ10T_2
Product data sheet
Package
Name
Description
Version
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads (one
lead cropped)
SOT404
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
100
V
VDGR
drain-gate voltage
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
100
V
VGS
gate-source voltage
ID
drain current
-20
20
V
VGS = 10 V; Tmb = 100 °C; see Figure 1
-
33
A
VGS = 10 V; Tmb = 25 °C; see Figure 1 and 2
-
47
A
-
187
A
IDM
peak drain current
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 2
Ptot
total power dissipation
Tmb = 25 °C; see Figure 3
-
166
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
Source-drain diode
IS
source current
Tmb = 25 °C
-
47
A
ISM
peak source current
tp ≤ 10 µs; pulsed; Tmb = 25 °C
-
187
A
-
45
mJ
Avalanche ruggedness
non-repetitive
VGS = 5 V; Tj(init) = 25 °C; ID = 30 A; Vsup ≤ 25 V;
drain-source avalanche unclamped; tp = 0.1 ms; RGS = 50 Ω; see Figure 4
energy
EDS(AL)S
03aa24
120
003aaa097
103
ID
(A)
Ider
(%)
RDSon = VDS / ID
tp =
1 μs
102
80
10 μs
100 μs
40
10
1 ms
D.C.
10 ms
100 ms
1
0
0
50
100
150
1
200
Tmb (°C)
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
PHB47NQ10T_2
Product data sheet
10
102
103
VDS (V)
Fig 2.
Safe operating area; continuous and peak drain
currents as a function of drain-source voltage
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Rev. 02 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
03aa16
120
003aaa098
102
Pder
(%)
IAS
(A)
80
25 °C
10
40
Tj prior to avalanche = 150 °C
1
0
0
50
100
150
200
10−3
10−2
10−1
1
Tmb (°C)
Fig 3.
10
tp (ms)
Normalized total power dissipation as a
function of mounting base temperature
Fig 4.
Non-repetitive avalanche ruggedness current
as a function of pulse duration
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Rth(j-mb)
Rth(j-a)
Conditions
Min
Typ
Max
Unit
thermal resistance from see Figure 5
junction to mounting
base
-
-
0.9
K/W
thermal resistance from mounted on printed-circuit board;
junction to ambient
minimum footprint
-
50
-
K/W
003aaa099
1
δ=
0.5
Zth (j-mb)
(K/W)
0.2
10−1
0.1
0.05
0.02
10−2
P
Single pulse
δ=
tp
T
t
tp
10−3
Fig 5.
T
10−7
10−6
10−5
10−4
10−3
10−2
10−1
1
tp (s)
10
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHB47NQ10T_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
100
-
-
V
VGS(th)
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 10
1
-
-
V
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 10
2
3
4
V
VDS = 100 V; VGS = 0 V; Tj = 25 °C
-
0.05
10
µA
VDS = 100 V; VGS = 0 V; Tj = 175 °C
-
-
500
µA
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
2
100
nA
VGS = -20 V; VDS = 0 V; Tj = 25 °C
-
2
100
nA
VGS = 10 V; ID = 25 A; Tj = 175 °C;
see Figure 11 and 12
-
-
76
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 11 and 12
-
20
28
mΩ
ID = 40 A; VDS = 80 V; VGS = 10 V;
Tj = 25 °C; see Figure 13
-
66
-
nC
-
12
-
nC
-
21
-
nC
-
2320
3100
pF
-
315
378
pF
-
187
256
pF
-
15
23
ns
-
70
105
ns
IDSS
drain leakage current
IGSS
gate leakage current
RDSon
drain-source on-state
resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGD
gate-drain charge
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer
capacitance
td(on)
turn-on delay time
tr
rise time
td(off)
turn-off delay time
-
83
116
ns
tf
fall time
-
45
63
ns
VDS = 25 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 14
VDS = 30 V; RL = 1.2 Ω; VGS = 10 V;
RG(ext) = 10 Ω; Tj = 25 °C
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 15
-
0.85
1.2
V
trr
reverse recovery time
66
-
ns
recovered charge
IS = 47 A; dIS/dt = -100 A/µs; VGS = -10 V;
VDS = 30 V; Tj = 25 °C
-
Qr
-
0.24
-
µC
PHB47NQ10T_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
ID
(A)
003aaa100
180
VGS = 10 V
160
20 V
8.0 V
003aaa101
100
ID
(A)
140
7.5 V
120
7.0 V
100
6.5 V
80
60
80
40
6.0 V
60
5.5 V
40
Tj = 175 °C
20
25 °C
5.0 V
20
4.5 V
0
0
0
Fig 6.
2
4
6
8
10
VDS (V)
Output characteristics: drain current as a
function of drain-source voltage; typical values
003aaa078
10−1
ID
(A)
0
2
4
6
8
VGS (V)
Fig 7.
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
003aaa104
gfs 45
(S)
40
10−2
35
2%
10−3
typ
30
98%
25
20
10−4
15
10
10−5
5
10−6
0
0
1
2
3
4
5
0
20
Fig 8.
Sub-threshold drain current as a function of
gate-source voltage
PHB47NQ10T_2
Product data sheet
40
60
80
100
ID (A)
VGS (V)
Fig 9.
Forward transconductance as a function of
drain current; typical values
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Rev. 02 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
003aaa023
4.5
4
VGS(th)
(V)
3.5
003aaa102
65
RDSon 60
(mΩ)
55
max
6.5 V
6.0 V
VGS = 5.5 V
50
3
typ
45
2.5
7.0 V
40
2
7.5 V
min
35
8.0 V
1.5
30
1
25
0.5
20
0
−60
−20
20
60
100
140
Tj (°C)
Fig 10. Gate-source threshold voltage as a function of
junction temperature
003aaa103
2.0
a
15
180
10 V
5
25
45
65
85
105
125
ID (A)
Fig 11. Drain-source on-state resistance as a function
of drain current; typical values
003aaa107
10
VGS
(V)
1.8
1.6
8
VDD = 20 V
1.4
1.2
6
VDD = 80 V
1.0
0.8
4
0.6
0.4
2
0.2
0
−60
-20
20
60
100
140
180
Tj (°C)
Fig 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
PHB47NQ10T_2
Product data sheet
0
0
10
20
30
40
50
60
70
QG (nC)
Fig 13. Gate-source voltage as a function of gate
charge; typical values
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Rev. 02 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
003aaa105
5
Ciss, Coss,
Crss
(nF)
4
IS
(A)
Ciss
80
Coss
3
2
003aaa106
100
60
25 °C
Crss
40
1
0
10−2
Tj = 175 °C
20
10−1
1
102
10
0
0
0.2
VDS (V)
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PHB47NQ10T_2
Product data sheet
0.4
0.6
0.8
1.0
1.2
1.4
VSD (V)
Fig 15. Source current as a function of source-drain
voltage; typical values
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
7. Package outline
SOT404
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.80
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-02-11
06-03-16
SOT404
Fig 16. Package outline SOT404 (D2PAK)
PHB47NQ10T_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PHB47NQ10T_2
20100225
Product data sheet
-
PHP_PHB_47NQ10T-01
Modifications:
PHP_PHB_47NQ10T-01
(9397 750 08243)
PHB47NQ10T_2
Product data sheet
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
20010516
Product data
-
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 25 February 2010
-
© NXP B.V. 2010. All rights reserved.
10 of 13
PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
9. Legal information
9.1
Data sheet status
Document status [1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
9.3
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PHB47NQ10T_2
Product data sheet
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
Non-automotive qualified products — Unless the data sheet of an NXP
Semiconductors product expressly states that the product is automotive
qualified, the product is not suitable for automotive use. It is neither qualified
nor tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use of
the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PHB47NQ10T_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
12 of 13
PHB47NQ10T
NXP Semiconductors
N-channel TrenchMOS standard level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10
Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 February 2010
Document identifier: PHB47NQ10T_2