Description Compensating the Current Mode Boost Control Loop

Application Report
SLVA452 – July 2012
Compensating the Current-Mode-Controlled Boost
Converter
Jeff Falin, Tahar Allag, Ben Hopf ........................................................ PMP - DCDC Low-Power Converters
ABSTRACT
This application report summarizes one method for compensating a current-mode-controlled boost. A
detailed description of both the power stage and the feedback network is provided. The design procedures
are explained step by step. A design example using TPS61175 is provided. Similar design steps are used
for the TPS61199 as well.
Contents
1
Simplified Small Signal Model .............................................................................................
2
Design Steps ................................................................................................................
3
Design Example using the TPS61175 ...................................................................................
Appendix A
Additional Data .....................................................................................................
2
4
5
9
List of Figures
1
Simplified Diagram of a Current-Mode Boost Converter with gM Amplifier .......................................... 2
2
TPS61175 Design Example Schematic
3
.................................................................................
Simulated Bode Plot of Power Stage Gain and Phase ................................................................
5
6
4
Simulated Bode Plot of the Type II Compensation (Including Feedback Network) for a gm Error
Amplifier ...................................................................................................................... 7
5
Modeled Bode Plot of the Total Open Loop ............................................................................. 7
6
Loop Gain and Phase ...................................................................................................... 8
7
Full Model Diagram ......................................................................................................... 9
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Simplified Small Signal Model
1
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Simplified Small Signal Model
Figure 1 shows a simplified block diagram of a current-mode boost converter with a transconductance
amplifier providing the feedback.
Power Stage
L
VOUT
RESR
d
VIN
Slope
Comp
fSW
RSNS
K
+
Modulator & Slope
Compensation
RINJ
Sn
Se
CLK
Q R
Latch
ROUT
COUT
REA
Vc
RTOP
GEA
RC
CC2 C
C1
RBOT
VREF
gM Amplifier &
Feedback Network
Figure 1. Simplified Diagram of a Current-Mode Boost Converter with gM Amplifier
With inductor current information fed back by RSNS (and possibly gained by factor K) as well as output
voltage feedback, this boost converter's inductor and switches effectively combine into a current source
driving an RC load. By removing the inductor, the small-signal, control-loop model of the power stage
reduces from a two-pole system, created by L and COUT, to a single-pole (fP) system, created by ROUT and
COUT. The single-pole system is easily used with Type-II compensation.
The single-pole system only holds true if the slope of the external compensation signal, Se, is not too
large in relation to the ramp sensed across RSENSE, Sn or the natural slope. If the Se slope dominates Sn,
for example, when the inductance is oversized in order to give ripple current much smaller than the
recommended 0.2-0.4 times the average input current, then the converter begins behaving more like a
voltage-mode converter and the full model, included in Appendix A, must be used.
Regardless of which model is used, the right-half-plane zero (ƒRHPZ), created by lack of continuous current
flow to the output, is still present.
Including the slope compensation, the new power stage small-signal model is presented mathematically
as follows:
GPS ( S ) =
ROUT * (1 - D)
*
2 * RSENSE
(1 +
S
S
)(1 )
2p * f ESR
2p * f RHPZ
* He(s)
S2
1+
2p * f P
(1)
Where D is the duty cycle and the single pole is:
fP =
2
2p * ROUT * Cout
(2)
The zero created by the ESR of the output capacitor is:
f ESR =
2
1
2p * RESR * Cout
(3)
Compensating the Current-Mode-Controlled Boost Converter
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Simplified Small Signal Model
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For a boost converter having multiple, identical output capacitors in parallel, simply combine the capacitors
and ESR in parallel and use the result in Equation 2 and Equation 3. For boost converters with ceramic
capacitor(s) in parallel with a much larger, high-ESR capacitor, use the total capacitance in parallel for
COUT in Equation 2 but only use the high-ESR capacitor's capacitance and ESR for Equation 3.
The right-hand plane zero is:
f RHPZ =
Rout
V
* ( IN ) 2
2p * L Vout
(4)
He(s) models the inductor current sampling effect as well as the slope compensation effect on the smallsignal response.
1
He( s ) =
s* [(1 +
1+
Se
) * (1 - D) - 0.5]
s2
Sn
+
f SW
(π * f SW ) 2
(5)
The equation for Se is unique to each IC and is found in the IC's datasheet. Equation 6 gives the typical
equation for Sn regarding a peak current mode converter.
Sn =
VIN
* RSNS
L
(6)
The natural slope may change for other types of current mode converters.
Figure 3 in the design example section shows a bode plot of a typical CCM boost converter power stage,
assuming the ESR pole is at a very high frequency.
Equation 7 shows the equation for feedback resistor network and the error amplifier.
H EA = GEA * REA *
RBOT
*
RBOT + RTOP (1 +
1+
S
2p * f z
S
S
) * (1 +
)
2p * f P1
2p * f P 2
(7)
Where GEA and REA are the error amplifier’s transconductance and output resistance.
1
2p * REA * CC1
1
=
2p * RC * CC 2 (Optional)
f P1 =
f P2
(8)
(9)
CC2 is optional and is modeled as 10-pF stray capacitance.
and
fZ =
1
2p * RC * CC1
(10)
Figure 4 in the design example shows a typical shape of a bode plot for transfer function HEA(s) with TypeII compensation components.
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Design Steps
2
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Design Steps
The steps to compensate the loop are as follows:
1. Choose the desired loop crossover frequency, fc
The higher in frequency that the loop gain stays above zero before crossing over, the faster the loop
response is and, therefore, the lower the output voltage droops during a step load. It is generally
recommended that the loop-gain crossover point is no higher than the lower of either 1/5 of the
switching frequency, fSW, or 1/3 of the RHPZ frequency, fRHPZ. It is also recommended to cross over at a
frequency where the power stage gain is decreasing at approximately a -20 dB/decade slope (after the
dominant pole and well before the effects of an RHPZ).
The size of the output capacitor plays a significant role in how wide the loop bandwidth is. Once the
minimum capacitance is met, meeting the output ripple specification, Equation 11 is used to estimate
the capacitance needed to meet the application's load transient requirement for the maximum voltage
dip (VTRAN) after a given load step (ΔITRAN).
Cout =
DI TRAN
2p * f C *VTRAN
(11)
2. Properly size the compensation resistor, Rc
By placing fZ below fC, for frequencies above fC, Rc| |RREA ~= RC and so RC × GEA sets the
compensation gain. Setting the compensation gain, KCOMP-dB, at fC , results in the total loop gain, T(s) =
GPS(s) × HEA(s) × He(s) being zero at fC. Therefore, to approximate a single-pole roll-off up to fP2,
rearrange Equation 12 to solve for RC so that the compensation gain, KCOMP-dB, at fC is the negative of
the gain, KPW -dB, read at frequency fC for the power stage bode plot or more simply
K COMP- dB ( f c ) = 20 * log( G EA * RC *
RBOT
) = - K PW -dB ( f c )
RBOT + RTOP
(12)
3. Properly size the compensation capacitor, CC1
Compensation capacitor CC1 is sized so that fZ ≈ fC/10 and optional fP2 > fC × 10
4. Optionally, size the compensation capacitor, CC2.
Equation 9 is for a pole produced by RC and CC2. This pole may be necessary to ensure that the gain
continues to roll off after the crossover frequency. Alternatively, for boost circuits with high ESR output
capacitors, and therefore a low-frequency ESR zero per Equation 3, this pole is useful for canceling
unhelpful effects of the ESR zero.
The preceding steps lead to a loop with a phase margin near 45 degrees. Lowering RC, while keeping fz ≈
fBW/10, increases the phase margin without significantly changing the gain and therefore increases the
time it takes for the output voltage to settle following a step load.
4
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Design Example using the TPS61175
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3
Design Example using the TPS61175
Figure 2 shows the EVM schematic and Table 1 gives the specifications for the design example. In order
to meet the transient requirement, the output capacitance value may need to changed.
Figure 2. TPS61175 Design Example Schematic
Table 1. TPS61175EVM-326 Performance Specification Summary for VIN = 12.0 V
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
INPUT CHARACTERISTICS
VIN
Input Voltage
fSW
Switching Frequency
12
V
750
kHz
OUTPUT CHARACTERISTICS
VO
Output Voltage
23
IO
Output Current
1
24
25
V
1.2
A
TRANSIENT RESPONSE
ΔITRAN
Load Step
ΔIO/ΔT
Load slew rate
9
A/µs
ΔVTRAN
VO undershoot
500
mV
tS
Settling time
300
µs
0.35
A
Equation 13 and Equation 14 give Sn and Se for the TPS61175.
VIN
12V
* RSNS =
* 40mW
L
22 mH
0.32V
0.5uA
R4
+
Se =
16 * (1 - D) * 6 pF 6 pF
Sn =
(13)
(14)
Where R4 is the frequency setting resistor.
1. Choose the desired loop crossover frequency, fc.
One fifth of the switching frequency is
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Design Example using the TPS61175
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f SW 750kHz
=
= 150kHz
5
5
(15)
fRHPZ is calculated using Equation 4
Where:
ROUT =
VOUT 24V
=
= 20W
I OUT 1.2 A
(16)
From Equation 4
f RHPZ =
12V 2
20
) = 36.2kHz
*(
2p * 22uH 24V
(17)
one-third of fRHPZ is
f RHPZ 36.2kHz
=
= 12.1kHz
3
3
(18)
thus, try fC = 10 kHz.
2. Find the output cap value using Equation 11
Cout =
DI TRAN
350mA
=
= 11 .14 mF
2p * f C *VTRAN 2p *10kHz * 500mV
(19)
Three 4.7 µF capacitors in parallel yield a total of 14.7 µF for the output capacitance (C8, C9, and C11 in
Figure 2)
3. Properly size the compensation resistor, RC (R3 in Figure 2). Using MathCAD, plot the power stage,
GPS(s), with RSENSE = 40 mΩ (given in the datasheet)
from Equation 2
fP =
2
=
2p * ROUT * Cout
2
= 1.1kHz
2p * 20W * 3 * 4.7uF
(20)
From Equation 4, fRHPZ is 36.2 kHz. Neglecting the ESR zero produced by the ceramic output capacitors
gives the plot found in Figure 3.
60
180
Phase
Gain
40
120
20
60
0
0
–20
–60
–40
–120
–60
1
10
100
1k
10k
100k
Phase (°)
Gain (dB)
22
–180
1M
Frequency (Hz)
Figure 3. Simulated Bode Plot of Power Stage Gain and Phase
The crossover frequency, fC, was chosen as 10 kHz and from Figure 3, KPW (10 kHz) = 22 dB. With RTOP =
301 kΩ, RBOT = 16.2 kΩ (R1 and R2 respectively in Figure 2), and GEA(TYP) = 340 μmho, solving
Equation 12 for RC gives:
K COMP - dB ( f c ) = 20 * log(GEA * RC *
6
RBOT
) = - K PW - dB ( f c ) Þ
RBOT + RTOP
Compensating the Current-Mode-Controlled Boost Converter
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(21)
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K COMP-dB ( fc )
RC =
GEA *
-22
20 dB
10
RBOT
RBOT + RTOP
10 20
= 4.57 kW
=
16.2kW
340umho *
16.2kW + 301kW
(22)
4. Properly size the compensation capacitor, CC1 (C4 in Figure 2).
Solving Equation 10 for CC1 and setting fz = fc/10 = 1 kHz gives
CC 1 =
1
1
=
= 34.82nF Þ 33nF
2p * RC * f z 2p * 4.57 kW *1kHz
(23)
5. Optionally, size the compensation capacitor, CC2 (C5 in Figure 2)
A stray capacitance of 10 pF is assumed for C5.
Figure 4 displays the plot for the Type II compensated amplifier and Figure 5 shows T(s) = GPS(s) ×
HEA(s) × He(s) with RC (R3) reduced to 3.09 kΩ, getting closer to the desired 60 degree phase margin.
180
80
Phase
60
Gain (dB)
20
Gain
0
0
–20
Phase (°)
90
40
–90
–40
–60
–80
1
10
100
10k
1k
100k
–180
1M
Frequency (Hz)
Figure 4. Simulated Bode Plot of the Type II Compensation (Including Feedback Network) for a gm Error
Amplifier
180
120
135
90
90
30
45
0
0
Gain
−30
−45
−60
−90
−90
−135
−120
1
10
100
1k
10k
Frequency (Hz)
100k
Phase (°)
Gain (dB)
Phase
60
−180
1M
G003
Figure 5. Modeled Bode Plot of the Total Open Loop
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Design Example using the TPS61175
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As Figure 6 shows, the measured loop compares favorably with the simulated loop.
Figure 6. Loop Gain and Phase
8
Compensating the Current-Mode-Controlled Boost Converter
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Appendix A Additional Data
Power Stage
Gvd(S), Gid(S)
d
VO
iL
RSENSE
Fm
+ +
He(S)
VC
Kr
GGMA(S)
Figure 7. Full Model Diagram
3
R C
2 VO
(1 + O O s)
2
2
VIN
Gid (s) =
2
2
VO L
VO LCO 2
s+
s
1+
2
2
VIN R OUT
VIN
(24)
Where:
GPS (s) =
Fm =
vo
FmGvd (s)
=
v c 1 + FmR SENSEHe (s)Gid (s) - FmK r Gvd (s)
1
(S e + Sn )Ts
(26)
2
Gvd (s) =
2
V L
VO
(1 - O2
s)(1 + RESR CO s)
VIN
VIN R O
2
1+
He(s) = 1 A.1
(25)
2
VO L
V LC
s + O 2 O s2
2
VIN R O
VIN
(27)
TS
T
s + S2 s 2
p
2
(28)
References
He, Dake, and R. M. Nelms, “Peak Current-Mode for a Boost Converter Using an 8-bit Microcontroller,”
IEEE 34th Annual Power Electronics Specialist Conference 2, June 2003 Record, pp. 938–943.
Ridley, R. D., “Current-Mode Control Modeling,” Switching Power Magazine, 2006, pp. 1–12.
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