8 A PoL converter using SOT23 MOSFETs

UM10177
8 A PoL converter using SOT23 MOSFETs
Rev. 02 — 21 December 2007
User manual
Document information
Info
Content
Keywords
SOT23 MOSFET PoL PMV45EN demo board
Abstract
Point of Load (PoL) converters are at the leading edge of power supply
performance in terms of power density and efficiency, however,
performance is not everything and the $/W value is also critical. This demo
board returns benchmark efficiency and power density using industry
standard construction and operating conditions to get 8 A output using
NXP PMV45EN SOT23 MOSFETs. The user manual describes the key
features of the design to enable customers to achieve the performance
benefits in their designs. A scalable approach has been applied to allow
alternative MOSFET packages to be used for higher powers.
UM10177
NXP Semiconductors
8 A PoL converter using SOT23 MOSFET
Revision history
Rev
Date
Description
01.00
20060302
First issue
02.00
20071221
Second issue
Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
2 of 16
UM10177
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8 A PoL converter using SOT23 MOSFET
1. Introduction
The SOT23 demo board demonstrates the performance of NXP SOT23 MOSFETs in an
operational single-phase buck converter on a small 2.5 cm × 5.0 cm board. The board is
supplied with three MOSFETs with locations for adding an additional FET. When
implemented with the recommended current limit circuits, these parts deliver surprising
power loads.
The simple, low cost board is designed for operation from an input voltage of 12 V
nominal, but is capable of operation from 5 V to 13 V. As supplied, the board output
voltage, VOUT, is set to 1.2 V. VOUT can be adjusted from 0.8 V to 5 V by changing a single
resistor. The current limit resistor should also be altered with changes in output voltage.
The SOT23 devices (see Figure 1) used on this board are NXP PMV45EN. The
MOSFETs are rated at 5.4 A maximum.
For detailed specifications, refer to the respective MOSFET data sheets. The use of a pair
of these MOSFETs allows the board to provide continuous output currents up to 5 A max
with adequate airflow. As supplied, this board can achieve an 8 A output current with three
MOSFETs.
3.0
2.8
1.1
0.9
3
0.45
0.15
2.5 1.4
2.1 1.2
1
2
1.9
Dimensions in mm
0.48
0.38
0.15
0.09
04-11-04
Fig 1. Simplified outline
Figure 1 shows the FET footprint. The demo board uses large pads for the drain and
source to provide heat sinking. The MOSFET outline plus clearance will occupy less than
200 mm × 200 mm.
The TI TPS40071 controller was selected for its feature set which includes: voltage
operating range of 4.5 V to 28 V, high side current limit, source and sink drivers, and
anti-cross conduction protection. For controller technical information, see the TI data
sheet for the TPS40071.
The board was designed as a simple low cost 8 A small form factor PoL demonstrator. For
VOUT values above 2.5 V, add a fourth FET. For ease of evaluation, the design area was
not minimized.
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
3 of 16
UM10177
NXP Semiconductors
8 A PoL converter using SOT23 MOSFET
1.1 Board top and bottom views
Figure 2 shows the top and bottom view of the board. All components are located on the
topside and clearance between components is expanded so attaching meters and probes
is less difficult. Power input connections, power output connections, and mounting hole
pads are mirrored top and bottom.
Fig 2. Board top and bottom views
1.2 Connection details
Figure 3 shows the board connections. Input power and ground connection pads are at
the top of the board, and output power and ground connection pads at the bottom. The
pads are large and mirrored on the board top and bottom side for current handling
capability. You can use solder connections or alligator clips to make the power
attachment.
Soldering to the connections pads will reduce the voltage drop of the connection. Small
holes in the input and output pads are sized so conductive posts can be inserted for
oscilloscope and meter probes. Mounting holes in the corners of the board are connected
to power ground.
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
4 of 16
UM10177
NXP Semiconductors
8 A PoL converter using SOT23 MOSFET
Status LED
Input pads
VIN
GND
GND
VOUT
Output pads
Fig 3. Input - output pads
2. Design criteria
As supplied, the board is designed to provide an output voltage of 1.2 V and 8 A. The
output voltage can be changed by replacing the resistor connected to the drain. The
current limits are set by R10. The operating frequency is 500 kHz. A blue status LED at
the top of the board lights when the controller and board are operational. The LED blinks
when the high side FET is current limited.
Status LED
R10
RFP
Ro(s)
R1
RTEST
Fig 4. Ro(s) versus VOUT
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
5 of 16
UM10177
NXP Semiconductors
8 A PoL converter using SOT23 MOSFET
Table 1.
Table Ro(s) versus VOUT
VIN = 12 V
VOUT
Ro(s)
R10
Number of
syncs
FETs control
Max IO
0.8 V
60.4 kΩ
0.698 kΩ
1
1
4.5 A
0.8 V
60.4 kΩ
1.27 kΩ
2
1
9.0 A
1.2 V
11.7 kΩ
1.58 kΩ
1
1
5.0 A
1.2 V
11.7 kΩ
2.32 kΩ
2
1
8.5 A
1.51 V
7.32 kΩ
3.24 kΩ
2
1
9.0 A
2.5 V
3.32 kΩ
3.16 kΩ
1
1
5.0 A
3.3 V
2.32 kΩ
3.57 kΩ
1
1
5.0 A
3.3 V
2.32 kΩ
4.02 kΩ
2
1
6.1 A
3.3 V
2.32 kΩ
2.55 kΩ
2
2
8.5 A
5.0 V
1.40 kΩ
4.12 kΩ
1
1
5.0 A
2.1 Board features
As mentioned previously, the output voltage can be easily adjusted by changing the value
of a single resistor, Ro(s). The chart in Figure 4 lists some of the tested configurations. The
current limit can be adjusted, as described in Section 2.1.2. R10 will need to be readjusted
for a safe current limit when changing the board VOUT. The feedback path has been
designed so that phase-gain testing can be performed by removing a single resistor. The
following sections describe these features in more detail.
2.1.1 VOUT selection
Replacing Ro(s) with the values calculated in the equation below changes VOUT
Ro(s) = R1 * Vref / (VOUT - VS)
Where Vref is the reference voltage of the operational amplifier, and is fixed at 0.7 V for the
TPS40071. Resistor values for common output voltages are provided in Figure 4.
2.1.2 Control FET current limit
The TPS40071 data sheet has equations for calculating R10 for a desired current limit.
The TPS40071 compares the voltage drop across R10 with the voltage drop across the
control FET RDSon at full conduction and initiates a shut down if the control FET voltage
drop exceeds the R10 reference voltage drop.
The blue LED will flicker during cycle-to-cycle shutdown. The FET voltage drop is a
function of RDSon and is temperature dependent. The precise shutdown value depends on
the FET operating temperature. See the TPS40071 data sheet for additional information
on current limit settings.
The R10 shutdown value was selected so the FET case temperature would not exceed
90 °C in an ambient of 25 °C with airflows of 200 LFM. Higher currents are achieved by
adding more FETs. You must alter the value of R10 to allow for the increased current.
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
6 of 16
UM10177
NXP Semiconductors
8 A PoL converter using SOT23 MOSFET
2.1.3 Increasing output current capability
When the ratio of VOUT to VIN is small, the duty cycle is correspondingly small. The control
FET power loss is multiplied by the duty cycle D, and the sync FET is multiplied by (1-D).
For low output voltages, most of the power loss is in the sync FET. For lower voltages,
output current capability is significantly increased by adding an additional sync FET.
As VOUT increases, the power loss is shared more equally between the sync and control
FETs. For higher VOUT ranges, you must add an additional control and sync FET for
increased current capability.
2.1.4 Phase gain testing
Phase gain testing (Bode plots) can be performed by removing the zero ohm RFP resistor
and injecting a test signal across RTEST, a 50 W resistor as shown in Figure 5. By
monitoring the response at TP2 to the injected signal at TP1, you can generate a phase
gain plot by varying the frequency of the test signal.
The full details of this test are beyond the scope of this manual, but the measurements are
easily done using a Vector Network Analyzer (VNA). Please refer to the TPS40071 data
sheet for loop compensation techniques. The zero ohm RFP resistor should remain in the
circuit for normal operation.
R10
VIN
boost
C20
R30
OSC
L1 VOUT
CTL
choke
comp
R9
R_load
Cout
C9
generator
ref
50 Ω
fb
TP1
C2
C1
R2
R1
TP2
RTEST
R3
RFP
003aab989
Fig 5. Phase gain test setup
2.2 Board schematic
The board schematic is shown in Figure 6 (current limit shown for two FETs).
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
7 of 16
UM10177
NXP Semiconductors
8 A PoL converter using SOT23 MOSFET
12 V
R5
820 kΩ
R20
46.4 kΩ
C14
0.1 μF
R10
2.32 kΩ
C10
10 pF
C6
22 μF
C11
22 μF
R30
90.9 kΩ
C30
10 μF
D1
R4
332 kΩ
C5
22 nF
1
2
3
16
15
14
4
5
6
7
8
13
12
11
10
9
TPS40071
C1
R2
5.6 nF 10 kΩ
C2
330 pF
R3
D
C20
10 μF
Q1
PMV45EN
C
L1
S
1.0 μH
D
C4
1 μF
Q2
PMV45EN
C
C7
100 μF
S
C3
150 kΩ 3.3 nF
R1
R9
2.2 kΩ
D
8.66 kΩ
Q3
PMV45EN
C
R50
12.1 kΩ
C8
100 μF
C9
2.2 nF
S
D
Q4
PMV45EN
C
S
TP1
RTEST
49.9 Ω
RFB
TP2
C12
0.1 μF
C13
0.1 μF
003aab990
Fig 6. Board schematic
2.3 Layout
The demo board is a four-layer board, all 1 oz. copper. All signals are routed top and
bottom with the inner layers dedicated to power and ground with one exception, the gate
signals are wide traces in the inner layers (see Figure 7). The board was designed to
minimize high current induced noise in the input drive and controller circuit areas. The
input current flows in a tight loop between the input pads, the input decoupling caps and
the MOSFETs.
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
8 of 16
UM10177
NXP Semiconductors
8 A PoL converter using SOT23 MOSFET
Top layer
Power layer
Bottom layer
Ground layer
Fig 7. Board layouts
3. Electrical and thermal performance
The demo board, with two FETS, is capable of 5 A output currents for VOUT values ranging
from 1.2 V to 5 V. Three FETS raises this to 8 A. Below 1.2 V, Iout drops to 4.5 A. This
rating is based on a 90 οC case temperature limit, a 25 οC ambient temperature, and
airflow of 200 LFM.
3.1 Efficiency sweeps
Efficiency is plotted in Figure 8 for VOUT voltages of 1.2 V and 3.3 V. The input voltage is
12 V for both sweeps. The maximum current swept is the level that produces 90 οC FET
case temperatures. Higher currents can be achieved with greater airflow.
Efficiency (%)
Efficiency
95
90
95
85
80
85
80
75
75
Efficiency
90
1.2 V_Eff
70
70
1 Control FET
1 Sync FET
65
60
Vout = 1.2 V
Vout = 3.3 V
55
55
Load current A
50
0
1
2
3
Load current A
50
4
5
Vout = 1.2 V
1 Control FET
2 Sync FETs
3.3 V_Eff
65
60
0
2
4
6
Vout = 3.3 V
2 Control FETs
2 Sync FETs
8
10
Fig 8. Efficiency sweep for 1.2 V and 3.3 V output voltages
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
9 of 16
UM10177
NXP Semiconductors
8 A PoL converter using SOT23 MOSFET
3.2 Thermal sweeps
Figure 9 shows the thermal case temperature of the control and sync FETs for the
efficiency sweeps in Figure 8. The load current is swept from zero amps to a maximum
level which is defined when the average of the two case temperatures equals 90 οC.
90
Ambient compensated thermals
80
Vin = 12 V
Vout = 1.2 V
Temperature °C
70
cntl
sync
avg
60
50
40
30
20
Amps
0
1
2
3
4
Ambient compensated thermals
90
80
Vin = 12 V
Vout = 3.3 V
Temperature °C
70
cntl
sync
avg
60
50
40
30
Amps
20
0
1
2
3
4
Fig 9. Thermal measurement
3.3 Electrical waveforms
The scope shots in Figure 10 and Figure 11 show the sync FET gate, control FET gate,
switch node, and boost voltage simultaneously for a no load and a 5 A load respectively.
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
10 of 16
UM10177
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8 A PoL converter using SOT23 MOSFET
Control gate
12 V Vin
SW
Sync gate
(Control_gate-SW)
Ch 1 5.00 V
Ch 3 5.00 V
Math1 4.00 V 200 ns
Ch 2 5.00 V
Ch 4 5.00 V
M 200 ns Ch 2
5.5 V
BW
Fig 10. Waveforms no load
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
11 of 16
UM10177
NXP Semiconductors
8 A PoL converter using SOT23 MOSFET
Control gate
12 V Vin
SW
Sync gate
(Control_gate-SW)
Ch 1 5.00 V
Ch 3 5.00 V
Math1 4.00 V 200 ns
Ch 2 5.00 V
Ch 4 5.00 V
M 200 ns Ch 2
5.5 V
BW
Fig 11. Waveforms at 5 A
3.4 Loop gain phase plot
Figure 12 shows the loop gain and phase versus frequency for VOUT = 3.3 V. The
compensation was very nearly the same for VOUT ranges of 0.8 V to 3.3 V. The test setup
is shown in Figure 6.
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
12 of 16
UM10177
NXP Semiconductors
8 A PoL converter using SOT23 MOSFET
50
180
40
144
30
108
20
72
10
36
0
0
−10
−36
−20
−30
−40
gain
−72
phase
−108
−144
phase shift (0 dB)
−50
100
1000
phase (degrees)
gain (dB)
Phase gain
Vout = 3.30 V 2.5 A load
10 000
−180
1 000 000
100 000
frequency (Hz)
Fig 12. Phase gain plot of demo board
4. Bill of materials
Table 2.
Pilsner rev 1.0 - 1-phase
Item
Qnt
Value
Package Tolerance Rating Manufacturer Manufacturer
P/N
Designation
1
1
3.3 nF
603
± 10 %
50 V
TDK
-
C3
2
1
10 pF
603
± 10 %
50 V
TDK
-
C 10
3
1
220 pF
603
± 10 %
50 V
TDK
-
C2
4
1
2.2 nF
603
± 10 %
50 V
TDK
-
C9
5
1
22 nF
603
± 10 %
50 V
TDK
-
C5
6
1
5.6 nF
603
± 10 %
50 V
TDK
-
C1
7
3
0.1 μF
603
± 10 %
50 V
TDK
-
C 12, C 20, C 30,
(C 13, C 14 empty)
8
1
1 μF
603
± 10 %
16 V
TDK
-
C4
9
1
22 μF
1210
+ 80 %, −
20 %
16 V
TDK
-
C 6 (C 11 empty)
10
2
100 μF
1812
+ 80 %, −
20 %
6.3 V
TDK
-
C 7, C 8
11
1
90.0 k
603
±1%
-
-
-
R 30
12
1
8.66 k
603
±1%
-
-
-
R1
13
1
332 k
603
±1%
-
-
-
R4
14
1
2.49 k
603
±1%
-
-
-
R 10
15
1
10 k
603
±1%
-
-
-
R2
16
1
12.1 k
603
±1%
-
-
-
ROS
17
1
46.4 k
603
±1%
-
-
-
R 20
18
1
150
603
±1%
-
-
-
R3
19
1
49.9
603
±1%
-
-
-
RTEST
20
1
2.2
603
±5%
-
-
-
R9
UM10177_2
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 21 December 2007
13 of 16
UM10177
NXP Semiconductors
8 A PoL converter using SOT23 MOSFET
Table 2.
Pilsner rev 1.0 - 1-phase
Item
Qnt
Value
Package Tolerance Rating Manufacturer Manufacturer
P/N
21
1
820
603
±5%
-
-
-
Designation
R5
22
1
1
603
±1%
-
-
-
RFB
23
1
TPS40071
SOP
-
-
TI
TPS40071PWP
U1
24
1
PMV45EN
SOT23
-
-
NXP
PMV45EN
Q 1, Q2 (Q3. Q4 empty)
25
1
Blue LED
603
-
3.8 V
Lite-On
LTST-C190UBKT
D1
26
1
HM73-101R0 -
± 20 %
1 μH,
8.5 A
BI
HM73-101R0
L1
UM10177_2
User manual
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Rev. 02 — 21 December 2007
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8 A PoL converter using SOT23 MOSFET
5. Legal information
5.1
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
5.2
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
5.3
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
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UM10177
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8 A PoL converter using SOT23 MOSFET
6. Contents
1
1.1
1.2
2
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.2
2.3
3
3.1
3.2
3.3
3.4
4
5
5.1
5.2
5.3
6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Board top and bottom views . . . . . . . . . . . . . . . 4
Connection details . . . . . . . . . . . . . . . . . . . . . . 4
Design criteria . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Board features . . . . . . . . . . . . . . . . . . . . . . . . . 6
VOUT selection . . . . . . . . . . . . . . . . . . . . . . . . . 6
Control FET current limit. . . . . . . . . . . . . . . . . . 6
Increasing output current capability . . . . . . . . . 7
Phase gain testing . . . . . . . . . . . . . . . . . . . . . . 7
Board schematic . . . . . . . . . . . . . . . . . . . . . . . . 7
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical and thermal performance. . . . . . . . . 9
Efficiency sweeps . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal sweeps . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical waveforms. . . . . . . . . . . . . . . . . . . . 10
Loop gain phase plot . . . . . . . . . . . . . . . . . . . 12
Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 21 December 2007
Document identifier: UM10177_2
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