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TDA7492
50 W + 50 W dual BTL class-D amplifier
Datasheet - production data
Description
The TDA7492 is a dual BTL class-D audio
amplifier with single power supply designed for
LCD TVs and monitors.
Thanks to the high efficiency and exposed-pad-up
(EPU) package, only a simple heatsink is
required.
PowerSSO-36
with exposed pad up
Features
 50 W + 50 W continuous output power at
THD = 10% with RL = 6  and VCC = 25 V
 40 W + 40 W continuous output power at
THD = 10% with RL = 8  and VCC = 25 V
 Wide-range single-supply operation (8 - 26 V)
 High efficiency ( = 90%)
 Four selectable, fixed gain settings of
nominally 21.6 dB, 27.6 dB, 31.1 dB and
33.6 dB
 Differential inputs minimize common-mode
noise
 Standby and mute features
 Short-circuit protection
 Thermal overload protection
 Externally synchronizable
 ECOPACK®, environmentally friendly package
Table 1. Device summary
Order code
Operating temp. range
Package
Packaging
TDA7492
-40 to +85 °C
PowerSSO-36 EPU
Tube
TDA749213TR
-40 to +85 °C
PowerSSO-36 EPU
Tape and reel
January 2015
This is information on a product in full production.
DocID014926 Rev 6
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www.st.com
Contents
TDA7492
Contents
1
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
2.1
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Characterizations for 6- loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Characterizations for 8- loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3
Characterizations for 4- loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4
Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
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6.1
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2
Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3
Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4
Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4.1
Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4.2
Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.5
Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6
Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.7
Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.8
Heatsink requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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TDA7492
8
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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32
List of tables
TDA7492
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
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Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
How to set up SYNCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PowerSSO-36 EPU dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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TDA7492
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Internal block diagram (showing one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output power vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
THD vs. output power (1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
THD vs. output power (100 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FFT performance (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FFT performance (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output power vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
THD vs. output power (1 kHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
THD vs. output (100 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FFT performance (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FFT performance (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output power vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
THD vs. output power (1 kHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
THD vs. output (100 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FFT performance (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FFT performance (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Test board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Applications circuit for class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Turn on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Typical LC filter for a 8- speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Typical LC filter for a 4- speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-36 EPU outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Device block diagram
1
TDA7492
Device block diagram
Figure 1 shows the block diagram of one of the two identical channels of the TDA7492.
Figure 1. Internal block diagram (showing one channel only)
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TDA7492
Pin description
2
Pin description
2.1
Pinout
Figure 2. Pin connections (top view, PCB view)
SUB GND
1
SVCC
OUTPB
2
34 VREF
OUTPB
3
33 INNB
PGNDB
4
32 INPB
PGNDB
5
31 GAIN1
PVCCB
6
30 GAIN0
PVCCB
7
29 SVR
OUTNB
8
28 DIAG
OUTNB
9
27 SGND
OUTNA 10
26 VDDS
OUTNA 11
25 SYNCLK
PVCCA 12
24 ROSC
PVCCA 13
23 INNA
PGNDA 14
36 VSS
35
22 INPA
EP
exposed pad up
Connect to ground
21 MUTE
PGNDA 15
OUTPA 16
OUTPA 17
20 STBY
19 VDDPW
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32
Pin description
2.2
TDA7492
Pin list
Table 2. Pin description list
Number
8/32
Name
Type
Description
1
SUB_GND
PWR
Connect to the frame
2,3
OUTPB
O
Positive PWM for right channel
4,5
PGNDB
PWR
Power stage ground for right channel
6,7
PVCCB
PWR
Power supply for right channel
8,9
OUTNB
O
Negative PWM output for right channel
10,11
OUTNA
O
Negative PWM output for left channel
12,13
PVCCA
PWR
Power supply for left channel
14,15
PGNDA
PWR
Power stage ground for left channel
16,17
OUTPA
O
Positive PWM output for left channel
18
PGND
PWR
Power stage ground
19
VDDPW
O
3.3-V (nominal) regulator output referred to ground for
power stage
20
STBY
I
Standby mode control
21
MUTE
I
Mute mode control
22
INPA
I
Positive differential input of left channel
23
INNA
I
Negative differential input of left channel
24
ROSC
O
Master oscillator frequency-setting pin
25
SYNCLK
I/O
Clock in/out for external oscillator
26
VDDS
O
3.3-V (nominal) regulator output referred to ground for signal
blocks
27
SGND
PWR
Signal ground
28
DIAG
O
Open-drain diagnostic output
29
SVR
O
Supply voltage rejection
30
GAIN0
I
Gain setting input 1
31
GAIN1
I
Gain setting input 2
32
INPB
I
Positive differential input of right channel
33
INNB
I
Negative differential input of right channel
34
VREF
O
Half VDDS (nominal) referred to ground
35
SVCC
PWR
Signal power supply
36
VSS
O
3.3-V (nominal) regulator output referred to power supply
-
EP
-
Exposed pad for heatsink, to be connected to GND
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TDA7492
Electrical specifications
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
3.2
Parameter
Value
Unit
VCC
DC supply voltage for pins PVCCA, PVCCB, SVCC
30
V
VI
Voltage limits for input pins STBY, MUTE, INNA, INPA,
INNB, INPB, GAIN0, GAIN1
-0.3 - 3.6
V
Top
Operating temperature
-40 to +85
°C
Tj
Junction temperature
-40 to 150
°C
Tstg
Storage temperature
-40 to 150
°C
Thermal data
Table 4. Thermal data
3.3
Symbol
Parameter
Rth j-case
Thermal resistance, junction to case
Min
-
Typ
2
Max
3
Unit
°C/W
Electrical specifications
Unless otherwise stated, the results in Table 5 below are given for the conditions:
VCC = 25 V, RL (load) = 8 , ROSC = R3 = 39 k, C8 = 100 nF, f = 1 kHz, GV = 21.6 dB and
Tamb = 25 °C.
Table 5. Electrical specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VCC
Supply voltage for
pins PVCCA, PVCCB, SVCC
-
8
-
26
V
Iq
Total quiescent current
Without LC
-
26
35
mA
IqSTBY
Quiescent current in standby
-
-
2.5
5.0
μA
VOS
Output offset voltage
Play mode
-
-
±100
Mute mode
-
-
±60
IOCP
Overcurrent protection threshold RL = 0 
4.8
6.0
-
A
Tj
Junction temperature at thermal
shutdown
-
-
150
-
°C
Ri
Input resistance
Differential input
48
60
-
k
VOVP
Overvoltage protection threshold -
28
29
-
V
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Electrical specifications
TDA7492
Table 5. Electrical specifications (continued)
Symbol
Parameter
VUVP
Undervoltage protection
threshold
RdsON
Power transistor on resistance
Po
Output power
Po
Output power
Condition
Min
Typ
-
-
-
7
High side
-
0.2
-
Low side
-
0.2
-
THD = 10%
-
40
-
THD = 1%
-
32
-
RL = 6 , THD = 10%,
VCC = 25V
-
50
-
RL = 6 , THD = 1%
VCC = 25V
-
40
-
Unit
V

W
W
PD
Dissipated power
Po =40W +40 W,
THD = 10%
-
8.0
-
W

Efficiency
Po = 40 W + 40W
80
90
-
%
THD
Total harmonic distortion
Po = 1 W
-
0.1
0.4
%
GAIN0 = L, GAIN1 = L
20.6
21.6
22.6
GAIN0 = L, GAIN1 = H
26.6
27.6
28.6
GAIN0 = H, GAIN1 = L
30.1
31.1
32.1
GAIN0 = H, GAIN1 = H
32.6
33.6
34.6
GV
Closed-loop gain
dB
GV
Gain matching
-
-
-
±1
dB
CT
Cross talk
f = 1 kHz
-
50
-
dB
eN
Total input noise
A Curve, GV = 20 dB
-
20
-
f = 22 Hz to 22 kHz
-
25
35
SVRR
Supply voltage rejection ratio
fr = 100 Hz, Vr = 0.5 V,
CSVR = 10 μF
40
50
-
dB
Tr, Tf
Rise and fall times
-
-
50
-
ns
fSW
Switching frequency
Internal oscillator
290
310
330
kHz
250
-
400
With external oscillator (2) 250
-
400
2.3
-
-
-
-
0.8
60
80
-
fSWR
Output switching frequency
Range
VinH
Digital input high (H)
VinL
Digital input low (L)
AMUTE
Mute attenuation
With internal oscillator
VMUTE = 1 V
(1)
1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 k (see Figure 28.).
2. fSW = fSYNCLK / 2 with the frequency of the external oscillator.
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kHz
V
dB
TDA7492
4
Characterization curves
Characterization curves
The general test conditions used for producing the characterization curves can be
summarized as follows:
Test board: SZ LAB TDA7492 slug-up demo board
Test frequency: 1 kHz (also 100 Hz for THD vs. output power only)
Output power: 1 W

For 6-loads
–
test voltage: 25 V
–
LC filter: L = 22 μH and C = 220 nF

For 8-loads
–
test voltage: 25 V
–
LC filter: L = 33 μH and C = 220 nF

For 4-loads
–
test voltage: 20 V
–
LC filter: L = 15 μH and C = 470 nF.
Figure 28 on page 22 shows the circuit with which the characterization curves, shown in the
next sections, were measured. Figure 27 on page 21 shows the PCB layout.
Characterizations for 6- loads
Figure 3. Output power vs. supply voltage
3RXWYV9FF
Test conditions:
Vcc = 15 - 25 V,
RL = 6 Ω,
Rosc = 39 kΩ, Cosc = 100 nF,
f = 1 kHz,
Gv = 30 dB,
Tamb = 25r C
3RXW:
4.1
10% THD
1% THD
Specification limit:
Typical:
Vs = 25 V, RL = 6 Ω,
Po = 50 W atTHD = 10%,
9FF9
Po = 40 W atTHD = 1%
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Characterization curves
TDA7492
Figure 4. THD vs. output power (1 kHz)
10
5
Test conditions:
THD %
Vcc = 25 V,
2
RL = 6 Ω,
Rosc = 39 kΩ, Cosc = 100 nF,
f = 1 kHz,
1
0.5
Gv = 30 dB,
0.2
Tamb = 25r C
0.1
0.05
Specification limit:
Typical:
0.02
Po = 50 W at THD = 10%
0.01
100m
200m
500m
1
2
5
10
20
60
Output Power (W)
Figure 5. THD vs. output power (100 Hz)
10
Test conditions:
Vcc = 25 V,
RL = 6 Ω,
Rosc = 39 kΩ, Cosc = 100 nF,
f = 100 Hz,
5
THD %
2
1
0.5
Gv = 30 dB,
0.2
Tamb = 25r C
0.1
Specification limit:
Typical:
0.05
0.02
Po = 50 W at THD = 10%
0.01
100m
200m
500m
1
2
5
10
Output power (W)
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60
TDA7492
Characterization curves
Figure 6. THD vs. frequency
0.5
0.4
Test conditions:
0.3
Vcc = 25 V,
RL = 6 Ω,
Rosc = 39 kΩ, Cosc = 100 nF,
0.2
THD %
f = 1 kHz,
0.1
Gv = 30 dB,
0.07
0.06
Po = 1 W,
0.05
0.04
Tamb = 25r C
0.03
0.02
Specification limit:
Typical: THD < 0.4%
0.01
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Figure 7. Frequency response
+1
Test conditions:
Vcc = 25 V,
RL = 6 Ω,
+0.5
-0
dBrA
-0.5
-1
Rosc = 39 kΩ, Cosc = 100 nF,
-1.5
f = 1 kHz,
-2
Gv = 30 dB,
-2.5
Po = 1 W,
-3
Tamb = 25r C
-3.5
-4
Specification limit:
-4.5
-5
Max: +/-3 dB (20 Hz to 20 kHz)
-5.5
-6
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Figure 8. Crosstalk
-60 T
Test conditions:
Vcc = 25 V,
RL = 6 Ω,
Crosstalk
dB
T TT
-75
-80
f = 1 kHz,
-85
Gv = 30 dB,
-90
Tamb = 25r C
T
-70
Rosc = 39 kΩ, Cosc = 100 nF,
Po = 1 W
T
-65
-95
-100
-105
Specification limit:
-110
Typical: > 50 dB (at f = 1 kHz)
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
DocID014926 Rev 6
13/32
32
Characterization curves
TDA7492
Figure 9. FFT performance (0 dB)
+10
+0
Test conditions:
-10
Vcc = 25 V,
-20
dBrA
RL = 6 Ω,
-30
-40
Rosc = 39 kΩ, Cosc = 100 nF,
-50
f = 1 kHz,
-60
Gv = 30 dB,
-70
Po = 1 W,
-80
-90
Tamb = 25r C
-100
-110
Specification limit:
-120
Typical: > 60 dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
2k
5k
10k
20k
2k
5k
10k
20k
Frequency (Hz)
Figure 10. FFT performance (-60 dB)
+10
+0
Test conditions:
-10
Vcc = 25 V,
RL = 6 Ω,
Rosc = 39 kΩ, Cosc = 100 nF,
-20
dBrA
-30
-40
-50
f = 1 kHz,
Gv = 30 dB,
Po = -60 dB (at 1 W = 0 dB)
Tamb = 25r C
-60
-70
-80
-90
-100
-110
Specification limit:
-120
Typical: > 90 dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
Frequency (Hz)
14/32
DocID014926 Rev 6
TDA7492
Characterizations for 8- loads
Figure 11. Output power vs. supply voltage
Test conditions:
3RXWYV9FF
Vcc = 5 - 25 V,
RL = 8 Ω,
Rosc = 39 kΩ, Cosc = 100 nF,
f = 1 kHz,
3RXW:
4.2
Characterization curves
Gv = 30 dB,
Tamb = 25r C
10% THD
1% THD
Specification limit:
Typical:
Vs = 25 V, RL = 8 Ω,
Po = 40 W at THD = 10%,
9FF9
Po = 32 W at THD = 1%
Figure 12. THD vs. output power (1 kHz)
10
Test conditions:
5
Vcc = 25 V,
THD
RL = 8 Ω,
%
Rosc = 39 kΩ, Cosc = 100 nF,
f = 1 kHz,
2
1
0.5
Gv = 30 dB,
Tamb = 25r C
0.2
0.1
Specification limit:
0.05
Typical:
0.02
Po = 40 W at THD = 10%
0.01
100m
200m
500m
1
2
5
10
20
50
Output power (W)
DocID014926 Rev 6
15/32
32
Characterization curves
TDA7492
Figure 13. THD vs. output (100 Hz)
10
Test conditions:
Vcc = 25 V,
RL = 8 Ω,
5
THD
%
2
Rosc = 39 kΩ, Cosc = 100 nF,
1
f = 100 Hz,
0.5
Gv = 30 dB,
Tamb = 25r C
0.2
0.1
Specification limit:
0.05
Typical:
Po = 40 W at THD = 10%
0.02
0.01
100m
200m
500m
1
2
5
10
20
50
Output power (W)
Figure 14. THD vs. frequency
0.5
0.4
Test conditions:
0.3
Vcc = 25 V,
THD
RL = 8 Ω,
%
0.2
Rosc = 39 kΩ, Cosc = 100 nF,
0.1
f = 1 kHz,
Gv = 30 dB,
0.07
0.06
Po = 1 W,
0.05
Tamb = 25r C
0.04
0.03
Specification limit:
0.02
Typical: THD < 0.4%
0.01
20
50
100
200
500
1k
2k
5k
10k
Frequency (Hz)
Figure 15. Frequency response
+1
+0.5
Test conditions:
Vcc = 25 V,
RL = 8 Ω,
Rosc = 39 kΩ, Cosc = 100 nF,
f = 1 kHz,
Gv = 30 dB,
Po = 1 W,
-0
dBrA
-0.5
-1
-1.5
-2
-2.5
-3
Tamb = 25r C
-3.5
Specification limit:
-4.5
-4
Max: +/-3 dB (20 Hz to 20 kHz)
-5
-5.5
-6
20
50
100
200
500
1k
Frequency (Hz)
16/32
DocID014926 Rev 6
2k
5k
10k
20k
20k
TDA7492
Characterization curves
Figure 16. Crosstalk
-60
Test conditions:
Vcc = 25 V,
RL = 8 Ω,
T
T
T T TT T
T
-65
Crosstalk
-70
dB
-75
Rosc = 39 kΩ, Cosc = 100 nF,
-80
f = 1 kHz,
-85
Gv = 30 dB,
-90
Po = 1 W,
-95
Tamb = 25r C
-100
-105
Specification limit:
-110
Typical: > 50 dB (at f = 1 kHz)
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Figure 17. FFT performance (0 dB)
+10
+0
Test conditions:
Vcc = 25 V,
-10
dBrA
RL = 8 Ω,
-20
-30
Rosc = 39 kΩ, Cosc = 100 nF,
-40
f = 1 kHz,
-50
Gv = 30 dB,
-60
-70
Po = 1 W,
-80
Tamb = 25r C
-90
-100
-110
Specification limit:
-120
Typical: > 60 dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Figure 18. FFT performance (-60 dB)
+10
+0
Test conditions:
-10
Vcc = 25 V,
dBrA
-20
RL = 8 Ω,
-30
Rosc = 39 kΩ, Cosc = 100 nF,
-40
f = 1 kHz,
-50
Gv = 30 dB,
-60
-70
Po = -60 dB (at 1 W = 0 dB)
Tamb = 25r C
-80
-90
-100
-110
Specification limit:
-120
Typical: > 90 dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
DocID014926 Rev 6
17/32
32
Characterization curves
4.3
TDA7492
Characterizations for 4- loads
Figure 19. Output power vs. supply voltage
Test conditions:
3RXWYV9FF
Vcc = 15 - 22 V,
RL = 4 Ω,
Rosc = 39 kΩ, Cosc = 100 nF,
3RXW:
f = 1 kHz,
Gv = 20 dB,
Tamb = 25r C
Specification limit:
Typical:
10% THD
1% THD
Vs = 20 V, RL = 4 Ω,
Po = 47 W at THD = 10%,
9FF9
Po = 38 W at THD = 1%
Figure 20. THD vs. output power (1 kHz)
10
Test conditions:
5
Vcc = 20 V,
THD + N
RL = 4 Ω,
%
Rosc = 39 kΩ, Cosc = 100 nF,
f = 1 kHz,
2
1
0.5
Gv = 20 dB,
Tamb = 25r C
0.2
0.1
Specification limit:
0.05
Typical:
Po = 38 W at THD = 1%
0.02
0.01
100m
200m
500m
1
2
5
Output power (W)
18/32
DocID014926 Rev 6
10
20
50
TDA7492
Characterization curves
Figure 21. THD vs. output (100 Hz)
10
Test conditions:
5
Vcc = 20 V,
THD + N
RL = 4 Ω,
%
2
Rosc = 39 kΩ, Cosc = 100 nF,
1
f = 100 Hz,
0.5
Gv = 20 dB,
Tamb = 25r C
0.2
0.1
Specification limit:
0.05
Typical:
Po = 38 W at THD = 1%
0.02
0.01
100m
200m
500m
1
2
5
10
20
50
Output power (W)
Figure 22. THD vs. frequency
0.5
0.4
Test conditions:
0.3
Vcc = 20 V,
RL = 4 Ω,
THD + N
0.2
%
Rosc = 39 kΩ, Cosc = 100 nF,
f = 1 kHz,
0.1
Gv = 20 dB,
0 dB at f = 1 kHz,
0.07
0.06
Po = 1 W,
0.05
Tamb = 25r C
0.04
0.03
Specification limit:
0.02
Typical: THD < 0.4%
0.01
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Figure 23. Frequency response
+1
Test conditions:
+0.75
+0.5
Vcc = 20 V,
RL = 4 Ω,
Rosc = 39 kΩ, Cosc = 100 nF,
f = 1 kHz,
Gv = 20 dB,
0 dB at f = 1 kHz,
Po = 1 W,
Tamb = 25r C
+0.25
dBrA
-0
-0.25
-0.5
-0.75
-1
-1.25
-1.5
-1.75
-2
Specification limit:
Typical:
Max: +/-3 dB (20 Hz to 20 kHz)
-2.25
-2.5
-2.75
-3
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
DocID014926 Rev 6
19/32
32
Characterization curves
TDA7492
Figure 24. Crosstalk
-60
T
Vcc = 20 V,
RL = 4 Ω,
T T
T
T
-65
Test conditions:
-70
Crosstalk
-75
dB
Rosc = 39 kΩ, Cosc = 100 nF,
-80
f = 1 kHz,
-85
Gv = 20 dB,
-90
0 dB at f = 1 kHz,
-95
Po = 1 W,
-100
Tamb = 25r C
-105
Specification limit:
-110
Typical: > 50 dB (at f = 1 kHz)
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
2k
5k
10k
20k
Frequency (Hz)
Figure 25. FFT performance (0 dB)
+10
+0
Test conditions:
Vcc = 20 V,
-10
dBrA
RL = 4 Ω,
-20
-30
Rosc = 39 kΩ, Cosc = 100 nF,
-40
f = 1 kHz,
-50
Gv = 20 dB,
-60
0 dB at f = 1 kHz,
-70
-80
Po = 1 W,
-90
Tamb = 25r C
-100
-110
Specification limit:
-120
Typical: > 60 dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
Frequency (Hz)
Figure 26. FFT performance (-60 dB)
+10
+0
Test conditions:
-10
Vcc = 20 V,
RL = 4 Ω,
-20
dBrA
-30
Rosc = 39 kΩ, Cosc = 100 nF,
-40
f = 1 kHz,
-50
Gv = 20 dB,
-60
0 dB at f = 1 kHz,
-70
-80
Po = 1 W,
Tamb = 25r C
-90
-100
-110
Specification limit:
-120
Typical: > 90 dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
Frequency (Hz)
20/32
DocID014926 Rev 6
2k
5k
10k
20k
TDA7492
Test board
Figure 27. Test board layout
2. Test board
4.4
Characterization curves
DocID014926 Rev 6
21/32
32
Applications circuit
5
TDA7492
Applications circuit
Figure 28. Applications circuit for class-D amplifier
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Input settings for standby, mute and play:
Input settings for gain:
STBY : MUTE
Mode
GAIN0 : GAIN1
Nominal gain
Standby
Standby
Mute
Play
0V:0V
0 V : 3.3 V
3.3 V : 0 V
3.3 V : 3.3 V
21.6 dB
27.6 dB
31.1 dB
33.6 dB
0V:0V
0 V : 3.3 V
3.3 V : 0 V
3.3 V : 3.3 V
22/32
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DocID014926 Rev 6
Q)
TDA7492
Applications information
6
Applications information
6.1
Mode selection
The three operating modes of the TDA7492 are set by the two inputs, STBY (pin 20) and
MUTE (pin 21).

Standby mode: all circuits are turned off, very low current consumption.

Mute mode: inputs are connected to ground and the positive and negative PWM
outputs are at 50% duty cycle.

Play mode: the amplifiers are active.
The protection functions of the TDA7492 are enabled by pulling down the voltages of the
STBY and MUTE inputs shown in Figure 29. The input current of the corresponding pins
must be limited to 200 μA.
Table 6. Mode settings
Mode
STBY
MUTE
L (1)
Standby
Mute
H
Play
H
X (don’t care)
(1)
L
H
1. Drive levels defined in Table 5: Electrical specifications on page 9
Figure 29. Standby and mute circuits
Standby
3.3 V
0V
STBY
R2
30 k
C7
2.2 μF
R4
30 k
C15
2.2 μF
Mute
3.3 V
0V
TDA7492
MUTE
Figure 30. Turn on/off sequence for minimizing speaker “pop”
DocID014926 Rev 6
23/32
32
Applications information
6.2
TDA7492
Gain setting
The gain of the TDA7492 is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31).
Internally, the gain is set by changing the feedback resistors of the amplifier.
Table 7. Gain settings
GAIN0
6.3
GAIN1
Nominal gain, Gv (dB)
0
0
21.6
0
1
27.6
1
0
31.1
1
1
33.6
Input resistance and capacitance
The input impedance is set by an internal resistor Ri = 60 k (typical). An input capacitor
(Ci) is required to couple the AC input signal.
The equivalent circuit and frequency response of the input components are shown in
Figure 31. For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz:
fc = 1 / (2 *  * Ri * Ci)
Figure 31. Device input circuit and frequency response
Rf
Input
signal
24/32
Ci
Input
pin
Ri
DocID014926 Rev 6
TDA7492
6.4
Applications information
Internal and external clocks
The clock of the class-D amplifier can be generated internally or can be driven by an
external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all
devices operate at the same clock frequency. This can be implemented by using one
TDA7492 as master clock, while the other devices are in slave mode, that is, externally
clocked. The clock interconnect is via pin SYNCLK of each device. As explained below,
SYNCLK is an output in master mode and an input in slave mode.
6.4.1
Master mode (internal clock)
Using the internal oscillator, the output switching frequency, fSW, is controlled by the
resistor, ROSC, connected to pin ROSC:
fSW = 106 / ((ROSC * 16 + 182) * 4) kHz
where ROSC is in k.
In master mode, pin SYNCLK is used as a clock output pin whose frequency is:
fSYNCLK = 2 * fSW
For master mode to operate correctly, then resistor ROSC must be less than 60 k as given
below in Table 8.
6.4.2
Slave mode (external clock)
In order to accept an external clock input the pin ROSC must be left open, that is, floating.
This forces pin SYNCLK to be internally configured as an input as given in Table 8.
The output switching frequency of the slave devices is:
fSW = fSYNCLK / 2
Table 8. How to set up SYNCLK
Mode
ROSC
SYNCLK
Master
ROSC < 60 k
Output
Slave
Floating (not connected)
Input
Figure 32. Master and slave connection
Master
Slave
TDA7492
TDA7492
ROSC
SYNCLK
Output
Cosc
100 nF
SYNCLK
ROSC
Input
Rosc
39 k
DocID014926 Rev 6
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32
Applications information
6.5
TDA7492
Output low-pass filter
To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The
cutoff frequency should be larger than 22 kHz and much lower than the output switching
frequency. It is necessary to choose the L-C component values depending on the loud
speaker impedance. Some typical values, which give a cutoff frequency of 27 kHz, are
shown in Figure 33 and Figure 34 below.
Figure 33. Typical LC filter for a 8- speaker
Figure 34. Typical LC filter for a 4- speaker
26/32
DocID014926 Rev 6
TDA7492
6.6
Applications information
Protection functions
The TDA7492 is fully protected against overvoltages, undervoltages, overcurrents and
thermal overloads as explained here.
Overvoltage protection (OVP)
If the supply voltage exceeds the value for VOVP given in Table 5: Electrical specifications
on page 9 the overvoltage protection is activated which forces the outputs to the
high-impedance state. When the supply voltage drops to below the threshold value the
device restarts.
Undervoltage protection (UVP)
If the supply voltage drops below the value for VUVP given in Table 5: Electrical
specifications on page 9 the undervoltage protection is activated which forces the outputs to
the high-impedance state. When the supply voltage recovers the device restarts.
Overcurrent protection (OCP)
If the output current exceeds the value for IOCP given in Table 5: Electrical specifications on
page 9 the overcurrent protection is activated which forces the outputs to the
high-impedance state. Periodically, the device attempts to restart. If the overcurrent
condition is still present then the OCP remains active. The restart time, TOC, is determined
by the R-C components connected to pin STBY.
Thermal protection (OTP)
If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode
and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction
temperature reaches the value for Tj given in Table 5: Electrical specifications on page 9 the
device shuts down and the output is forced to the high-impedance state. When the device
cools sufficiently the device restarts.
6.7
Diagnostic output
The output pin DIAG is an open drain transistor. When the protection is activated it is in the
high-impedance state. The pin can be connected to a power supply (<26 V) by a pull-up
resistor whose value is limited by the maximum sinking current (200 μA) of the pin.
Figure 35. Behavior of pin DIAG for various protection conditions
VDD
TDA7492
R1
DIAG
Protection logic
VDD
Restart
Restart
Overcurrent
protection
OV, UV, OT
protection
DocID014926 Rev 6
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32
Applications information
6.8
TDA7492
Heatsink requirements
As with most amplifiers, the power dissipated within the device depends primarily on the
supply voltage, the load impedance and the output modulation level.
The maximum estimated power dissipation for the TDA7492 is around 7 W. At 25 °C
ambient a heatsink having Rth =15 °C/W is sufficient for sine-wave testing at maximum
power. A musical program, however, dissipates about 40% less power than this and a
heatsink with Rth = 25 °C/W is thus recommended. Even at the maximum recommended
ambient temperature for consumer applications of 50 °C there is still a clear safety margin
before the maximum junction temperature (150 °C) is reached.
28/32
DocID014926 Rev 6
TDA7492
Package mechanical data
The TDA7492 comes in a 36-pin PowerSSO package with exposed pad up (EPU).
Figure 36 shows the package outline and Table 9 gives the dimensions.
Figure 36. PowerSSO-36 EPU outline drawing
h x 45°
7
Package mechanical data
DocID014926 Rev 6
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32
Package mechanical data
TDA7492
Table 9. PowerSSO-36 EPU dimensions
Dimensions in mm
Dimensions in inches
Symbol
Min
Typ
Max
Min
Typ
Max
A
2.15
-
2.45
0.085
-
0.096
A2
2.15
-
2.35
0.085
-
0.093
a1
0
-
0.10
0
-
0.004
b
0.18
-
0.36
0.007
-
0.014
c
0.23
-
0.32
0.009
-
0.013
D
10.10
-
10.50
0.398
-
0.413
E
7.40
-
7.60
0.291
-
0.299
e
-
0.5
-
-
0.020
-
e3
-
8.5
-
-
0.335
-
F
-
2.3
-
-
0.091
-
G
-
-
0.10
-
-
0.004
H
10.10
-
10.50
0.398
-
0.413
h
-
-
0.40
-
-
0.016
k
0
-
8 degrees
-
-
8 degrees
L
0.60
-
1.00
0.024
-
0.039
M
-
4.30
-
-
0.169
-
N
-
-
10 degrees
-
-
10 degrees
O
-
1.20
-
-
0.047
-
Q
-
0.80
-
-
0.031
-
S
-
2.90
-
-
0.114
-
T
-
3.65
-
-
0.144
-
U
-
1.00
-
-
0.039
-
X
4.10
-
4.70
0.161
-
0.185
Y
6.50
-
7.10
0.256
-
0.280
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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Revision history
Revision history
Table 10. Document revision history
Date
Revision
30-Jul-2008
1
Initial release.
4-Nov-2008
2
Updated VOS details in Table 5
Updated Chapter 4: Characterization curves on page 11.
3
Updated supply operating range to 8 V - 26 V on page 1
Changed C1 to C8 at beginning of Section 3.3 on page 9
Updated Table 5: Electrical specifications on page 9 for VCC min, Iq
condition, VOS min/max, IOC, and added new parameter VUV
Updated Figure 3: Test circuit for characterizations on page 10
Updated Figure 28: Applications circuit for class-D amplifier on page 22
Inserted brackets in equation in Table 5, footnote and in Section 6.4.1
on page 25
Updated values in UVP and OCP in Section 6.6 on page 27
Updated package presentation in Chapter 7 on page 29 and max
vaules for A and A2 in Table 9: PowerSSO-36 EPU dimensions on
page 30.
03-Sep-2009
4
Added text for exposed pad in Figure 2 on page 7
Added text for exposed pad in Table 2 on page 8
Removed Figure 3: Test circuit for characterizations since it is identical
to apps circuit in Figure 28 on page 22
Moved section Test board on page 21 to end of chapter
Updated package Y (Min) dimension in Table 9 on page 30
12-Sep-2011
5
Updated OUTNA in Table 2: Pin description list
22-Jan-2015
6
Updated operative temperature range to -40 to +85 °C in Table 1:
Device summary and Table 3: Absolute maximum ratings
Updated Y dimension in Table 9: PowerSSO-36 EPU dimensions
15-Apr-2009
Changes
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