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STA516B
65 V, 7.5 A quad power half bridge
Datasheet - production data
Description
STA516B is a monolithic quad half-bridge stage in
multipower BCD technology. The device can be
used as dual bridge or reconfigured, by
connecting pin CONFIG to pins VDD, as a single
bridge with double-current capability or as a half
bridge (binary mode) with half current capability.
The device is designed, particularly, to be the
output stage of a stereo all digital high efficiency
amplifier. It is capable of delivering 200 W +
200 W into 6  loads with THD = 10% at
VCC = 51 V or, in single BTL configuration, 400 W
into a 3 load with THD = 10% at VCC = 52 V.
PowerSO36 package
with exposed pad up
The input pins have a threshold proportional to
the voltage on pin VL.
Features
 Low input/output pulse width distortion
 200 m RdsON complementary DMOS output
stage
 CMOS compatible logic inputs
The STA516B is aimed at audio amplifiers in hi-fi
applications, such as home theatre systems,
active speakers and docking stations.
It comes in a 36 pin PowerSO package with
exposed pad up (EPU).
 Thermal protection
 Thermal warning output
 Undervoltage protection
Table 1. Device summary
Order code
Temperature range
Package
Packaging
STA516B13TR
0 to 90 °C
PowerSO36 EPU
Tape and reel
February 2014
This is information on a product in full production.
DocID13183 Rev 6
1/18
www.st.com
Introduction
1
STA516B
Introduction
Figure 1. Application circuit (dual BTL)
+VCC
VCC1A
IN1A
29
M3
IN1A
VL
+3.3V
CONFIG
PWRDN
R57
10K
R59
10K
16
24
25
FAULT
27
26
M2
PROTECTIONS
&
LOGIC
TRI-STATE
C58
100nF
TH_WAR
M5
TH_WAR
28
IN1B
30
VDD
21
VDD
22
VSS
33
VSS
34
C53
100nF
C60
100nF
VCCSIGN
IN2A
GND-Reg
GND-Clean
IN2B
GND1A
12
VCC1B
REGULATORS
13
GND1B
7
VCC2A
IN2B
GNDSUB
M15
31
20
19
M16
VCC2B
OUT2B
OUT2B
M14
C110
100nF
5
C109
330pF
C33
1 F
3
2
32
1
4
8
L113 22 H
OUT2A
GND2A
R100
6
C99
100nF
C23
470nF
C101
100nF
C21
100nF
OUT2A
6
R98
6
L19 22 H
C32
1 F
8
9
R63
20
OUT1B
OUT1B
M4
35
36
C20
100nF
C52
330pF
C31
1 F
11
M17
VCCSIGN
IN2A
OUT1A
14
C55
1000 F
L18 22 H
OUT1A
10
IN1B
C58
100nF
C30
1 F
17
23
PWRDN
15
R104
20
R103
6
R102
6
C107
100nF
C108
470nF
C106
100nF
8
C111
100nF
L112 22 H
GND2B
D00AU1148B
2/18
DocID13183 Rev 6
STA516B
2
Pin description
Pin description
Figure 2. Pin out
VCC_SIGN
36
1
SUB_GND
VCC_SIGN
35
2
OUT2B
VSS
34
3
OUT2B
VSS
33
4
VCC2B
IN2B
32
5
GND2B
IN2A
31
6
GND2A
IN1B
30
7
VCC2A
IN1A
29
STA516B
8
OUT2A
9
OUT2A
10
OUT1B
TH_WARN
28
FAULT
27
TRISTATE
26
11
OUT1B
PWRDN
25
12
VCC1B
CONFIG
24
13
GND1B
VL
23
14
GND1A
VDD
22
15
VCC1A
VDD
21
16
OUT1A
GND_REG
20
17
OUT1A
GND_CLEAN
19
18
N.C.
Table 2. Pin function
Pin
Name
Type
Description
1
GND_SUB
PWR
2, 3
OUT2B
O
4
VCC2B
PWR
Positive supply
5
GND2B
PWR
Negative supply
6
GND2A
PWR
Negative supply
7
VCC2A
PWR
Positive supply
8, 9
OUT2A
O
Output half bridge 2A
10, 11
OUT1B
O
Output half bridge 1B
12
VCC1B
PWR
Positive supply
13
GND1B
PWR
Negative supply
14
GND1A
PWR
Negative supply
15
VCC1A
PWR
Positive supply
16, 17
OUT1A
O
Output half bridge 1A
18
N.C.
-
No internal connection
19
GND_CLEAN
PWR
Logical ground
20
GND_REG
PWR
Ground for regulator VDD
21, 22
VDD
PWR
5-V regulator referred to ground
23
VL
PWR
High logical state setting voltage, VL
Substrate ground
Output half bridge 2B
DocID13183 Rev 6
3/18
18
Pin description
STA516B
Table 2. Pin function (continued)
Pin
4/18
Name
Type
Description
24
CONFIG
I
Configuration pin:
0: normal operation
1: bridges in parallel (OUT1A = OUT1B, OUT2A = OUT2B (If
IN1A = IN1B, IN2A = IN2B))
25
PWRDN
I
Standby pin:
0: low-power mode
1: normal operation
26
TRISTATE
I
Hi-Z pin:
0: all power amplifier outputs in high impedance state
1: normal operation
27
FAULT
O
Fault pin advisor (open-drain device, needs pull-up resistor):
0: fault detected (short circuit or thermal, for example)
1: normal operation
28
TH_WARN
O
Thermal warning advisor (open-drain device, needs pull-up
resistor):
0: temperature of the IC >130 °C
1: normal operation
29
IN1A
I
Input of half bridge 1A
30
IN1B
I
Input of half bridge 1B
31
IN2A
I
Input of half bridge 2A
32
IN2B
I
Input of half bridge 2B
33, 34
VSS
PWR
5-V regulator referred to +VCC
35, 36
VCC_SIGN
PWR
Signal positive supply
DocID13183 Rev 6
STA516B
3
Electrical characteristics
Electrical characteristics
Table 3. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC_MAX DC supply voltage (pins 4, 7, 12, 15)
65
V
Vmax
Maximum voltage on pins 23 to 32
5.5
V
Tj_MAX
Operating junction temperature
0 to 150
°C
Tstg
Storage temperature
-40 to 150
°C
Warning:
Stresses beyond those listed under “Absolute maximum
ratings” make cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated
under “Recommended operating condition” are not implied.
Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. In the real
application, power supply with nominal value rated inside
recommended operating conditions, may experience some
rising beyond the maximum operating condition for short
time when no or very low current is sinked (amplifier in mute
state). In this case the reliability of the device is guaranteed,
provided that the absolute maximum rating is not exceeded.
Table 4. Thermal data
Symbol
Parameter
Min.
Typ.
Max.
Unit
Tj-case
Thermal resistance junction to case (thermal pad)
-
1
2.5
°C/W
Twarn
Thermal warning temperature
-
130
-
°C
TjSD
Thermal shut-down junction temperature
-
150
-
°C
thSD
Thermal shut-down hysteresis
-
25
-
°C
Table 5. Recommended operating conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply voltage for pins PVCCA, PVCCB
10
-
58
V
Tamb
Ambient operating temperature
0
-
90
°C
DocID13183 Rev 6
5/18
18
Electrical characteristics
STA516B
Unless otherwise stated, the test conditions for Table 6 below are VL = 3.3 V, VCC = 50 V
and Tamb = 25 °C
Table 6. Electrical characteristics
Symbol
Test conditions
Min.
Typ.
Max.
Unit
RdsON
Power P-channel/N-channel
MOSFET RdsON
Idd = 1 A
-
200
240
m
Idss
Power P-channel/N-channel
leakage Idss
-
-
-
50
µA
gN
Power P-channel RdsON
matching
Idd = 1 A
95
-
-
%
gP
Power N-channel RdsON
matching
Idd = 1 A
95
-
-
%
Dt_s
Low current dead time (static)
see Figure 3
-
10
20
ns
Dt_d
High current dead time
(dynamic)
L = 22 µH, C = 470 nF
RL = 8 , Idd = 4.5 A
see Figure 4
-
50
ns
td ON
Turn-on delay time
Resistive load
-
-
100
ns
td OFF
Turn-off delay time
Resistive load
-
-
100
ns
tr
Rise time
Resistive load
see Figure 3
-
-
25
ns
tf
Fall time
Resistive load
see Figure 3
-
-
25
ns
VIN-High
High level input voltage
-
-
-
VL / 2 +
V
300 mV
VIN-Low
Low level input voltage
-
VL / 2 300 mV
-
V
IIN-H
High level input current
VIN = VL
-
1
-
µA
IIN-L
Low level input current
VIN = 0.3 V
-
1
-
µA
IPWRDN-H
High level PWRDN pin input
current
VL = 3.3 V
-
35
-
µA
VLow
Low logical state voltage
(pins PWRDN, TRISTATE)
(seeTable 7)
VL = 3.3 V
0.8
-
VHigh
High logical state voltage
(pins PWRDN, TRISTATE)
(seeTable 7)
VL = 3.3 V
Supply current from VCC in
power down
VPWRDN = 0 V
IFAULT
Output current on pins
FAULT, TH_WARN with fault
condition
IVCC-HiZ
Supply current from VCC in
tristate
IVCCPWRDN
6/18
Parameter
V
-
1.7
V
-
-
2.4
mA
Vpin = 3.3 V
-
1
-
mA
VTRISTATE = 0 V
-
22
-
mA
DocID13183 Rev 6
STA516B
Electrical characteristics
Table 6. Electrical characteristics (continued)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IVCC
Supply current from VCC in
operation, both channels
switching)
Input pulse width
= 50% duty,
switching frequency
= 384 kHz,
no LC filters
IOCP
Overcurrent protection
threshold Isc (short-circuit
current limit) (1)
-
7.5
8.5
10
A
VUVP
Undervoltage protection
threshold
-
-
7
-
V
VOVP
Overvoltage protection
threshold
-
61
62.5
tpw_min
Output minimum pulse width
No load
50
-
-
70
-
mA
V
110
ns
1. See specific application note number: AN1994
Table 7. Threshold switching voltage variation with voltage on pin VL
Voltage on pin VL, VL
VLOW max.
VHIGH min.
Unit
2.7
1.05
1.65
V
3.3
1.4
1.95
V
5.0
2.2
2.8
V
Table 8. Logic truth table
Pin
TRISTATE
Inputs as per Figure 4
Transistors as per Figure 4
Output mode
INxA
INxB
Q1
Q2
Q3
Q4
0
x
x
Off
Off
Off
Off
Hi Z
1
0
0
Off
Off
On
On
Dump
1
0
1
Off
On
On
Off
Negative
1
1
0
On
Off
Off
On
Positive
1
1
1
On
On
Off
Off
Not used
DocID13183 Rev 6
7/18
18
Electrical characteristics
3.1
STA516B
Test circuits
Figure 3. Test circuit
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf )
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
Duty cycle = 50%
DTf
M58
OUTxY
INxY
R8
M57
V67 =
vdc = Vcc/2
+
-
gnd
D03AU1458
Figure 4. Current dead-time test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
DTin(A)
Q1
Q2
Rload=8
OUTxA
INxA
Iout=4.5A
M57
Q3
DTout(B)
L67 22
C69
470nF
L68 22
C71 470nF
DocID13183 Rev 6
DTin(B)
OUTxB
INxB
Iout=4.5A
C70
470nF
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
8/18
M64
Q4
M63
D00AU1162
STA516B
4
Power supply and control sequencing
Power supply and control sequencing
To guarantee correct operation and reliability, the recommended power-on sequence as
given below should be followed:

Apply VCC and VL, in any order, keeping PWRDN low in this phase

Release PWRDN from low to high, keeping TRISTATE low (until VDD and VSS are
stable)

Release TRISTATE from low to high
Always maintain PWM inputs INxy < VL.
Figure 5. Power-ON sequence
Power-OFF sequence:
– When TRISTATE or PWRDN go low, the outputs go into HiZ state
– Inputs INxy are removed before VL is removed
– VL can be removed before or after VCC
DocID13183 Rev 6
9/18
18
Power supply and control sequencing
STA516B
Figure 6. Power-OFF sequence
10/18
DocID13183 Rev 6
STA516B
5
Technical information
Technical information
The STA516B is a dual channel H-bridge that is able to deliver 200 W per channel (into
RL = 6  with THD = 10% and VCC = 51 V) of audio output power very efficiently. It operates
in conjunction with a pulse-width modulator driver such as the STA321 or STA309A.
The STA516B converts ternary, phase-shift or binary-controlled PWM signals into audio
power at the load. It includes a logic interface, integrated bridge drivers, high efficiency
MOSFET outputs and thermal and short-circuit protection circuitry.
In differential mode (ternary, phase-shift or binary differential), two logic level signals per
channel are used to control high-speed MOSFET switches to connect the speaker load to
the input supply or to ground in a bridge configuration, according to the damped ternary
modulation operation.
In binary mode, both full bridge and half bridge modes are supported. The STA516B
includes overcurrent and thermal protection as well as an undervoltage lockout with
automatic recovery. A thermal warning status is also provided.
Figure 7. Block diagram of full-bridge DDX® or binary mode
INL[1,2]
INR[1,2]
VL
PWRDN
TRISTATE
FAULT
Logic
interface
and
decode
Protection
THWARN
OUTPL
Left
H-bridge
Right
H-bridge
OUTNL
OUTPR
OUTNR
Regulators
Figure 8. Block diagram of binary half-bridge mode
INA(1,2)
INB(1,2)
VL
PWRDN
TRISTATE
FAULT
Left A
1/2-Bridge
OUT 1A
Left A
1/2-Bridge
OUT 1B
Protection
Left A
1/2-Bridge
OUT 2A
Regulators
Left A
1/2-Bridge
OUT 2B
Logic
interface
and
decode
THWARN
5.1
Logic interface and decode
The STA516B power outputs are controlled using one or two logic-level timing signals. In
order to provide a proper logic interface, the VL input must operate at the same voltage as
the DDX control logic supply.
DocID13183 Rev 6
11/18
18
Technical information
5.2
STA516B
Protection circuitry
The STA516B includes protection circuitry for overcurrent and thermal overload conditions.
A thermal warning pin (THWARN, pin 28, open drain MOSFET) is activated low when the IC
temperature exceeds 130 °C, just in advance of thermal shutdown. When a fault condition is
detected an internal fault signal immediately disables the output power MOSFETs, placing
both H-bridges in a high-impedance state. At the same time the open-drain MOSFET of pin
FAULT (pin 27) is switched on.
There are two possible modes subsequent to activating a fault.
5.3

Shutdown mode: with pins FAULT (with pull-up resistor) and TRISTATE separate, an
activated fault disables the device, signaling a low at pin FAULT output.
The device may subsequently be reset to normal operation by toggling pin TRISTATE
from high to low to high using an external logic signal.

Automatic recovery mode: This is shown in the applications circuits below where pins
FAULT and TRISTATE are connected together to a time-constant circuit (R59 and
C58).
An activated fault forces a reset on pin TRISTATE causing normal operation to resume
following a delay determined by the time constant of the circuit.
If the fault condition persists, the circuit operation repeats until the fault condition is
cleared.
An increase in the time constant of the circuit produces a longer recovery interval. Care
must be taken in the overall system design not to exceed the protection threshold
under normal operation.
Power outputs
The STA516B power and output pins are duplicated to provide a low-impedance path for the
device bridged outputs. All duplicate power, ground and output pins must be connected for
proper operation.
The PWRDN or TRISTATE pin should be used to set all power MOSFETs to the
high-impedance state during power-up until the logic power supply, VL, has settled.
5.4
Parallel output / high current operation
When using the DDX mode output, the STA516B outputs can be connected in parallel in
order to increase the output current capability to a load. In this configuration the STA516B
can provide up to 240 W into a 3  load.
This mode of operation is enabled with the pin CONFIG (pin 24) connected to pin VDD. The
inputs are joined so that IN1A = IN1B, IN2A = IN2B and similarly the outputs
OUT1A = OUT1B, OUT2A = OUT2B as shown in Figure 9 on page 13
5.5
Output filtering
A passive 2nd order filter is used on the STA516B power outputs to reconstruct the analog
audio signal. System performance can be significantly affected by the output filter design
and choice of passive components. A filter design for 6 or 8  loads is shown in the
application circuit of Figure 8, and for 3 or 4  loads in Figure 9 and Figure 10.
12/18
DocID13183 Rev 6
STA516B
6
Applications
Applications
Figure 9 below shows a single-BLT configuration capable of giving 400 W into a 3  load at
10% THD with VCC = 52 V. This result was obtained using the STA30X+STA50X demo
board. Note that a PWM modulator as driver is required.
Figure 9. Typical single-BTL configuration for 400 W
VL
+3.3V
GND-Clean
GND-Reg
100nF
X7R
10K
23
18
N.C.
12 H
100nF
VDD
VDD
CONFIG
TH_WAR
TH_WAR
PWRDN
nPWRDN
FAULT
10K
IN1A
IN1B
IN1A
IN2A
IN2B
IN1B
VSS
VSS
100nF
X7R
19
16
20
11
10
21
VCCSIGN
100nF
X7R
VCCSIGN
Add.
GNDSUB
OUT1A
100nF
FILM
OUT1A
22
1/2W
OUT1B
OUT1B
9
OUT2A
6.2
1/2W
330pF
8
100nF
X7R
680nF
FILM
100nF
X7R
6.2
1/2W
OUT2A
22
24
OUT2B
28
3
15
26
29
12
30
7
31
12 H
VCC1A
+36V
1 F
X7R
VCC1B
4
2200 F
63V
VCC2A
+36V
1 F
X7R
32
33
4
100nF
FILM
OUT2B
2
25
27
TRI-STATE
100nF
17
VCC2B
GND1A
34
14
GND1B
35
13
36
6
1
5
GND2A
GND2B
D04AU1545
Figure 10. Typical quad half-bridge configuration
+VCC
VCC1P
IN1A
29
VL
23
M3
IN1A
+3.3V
PWRDN
R57
10K
R59
10K
CONFIG
24
PWRDN
25
FAULT
27
26
16
M2
PROTECTIONS
&
LOGIC
TH_WAR
M5
TH_WAR
28
IN1B
30
C58
100nF
C53
100nF
C60
100nF
VDD
21
22
VSS
33
VSS
34
VCCSIGN
IN2A
GND-Reg
GND-Clean
IN2B
PGND1P
12
VCC1N
C51
1 F
11
M4
REGULATORS
13
7
R41
20
R51
6
C41
330pF
R42
20
C72
100nF
R52
6
C82
100nF
IN2B
GNDSUB
9
36
M15
31
20
19
M16
1
OUTPR
6
PGND2P
4
VCC2N
3
2
32
OUTPR
C52
1 F
5
PGND2N
D03AU1474
C73
100nF
R53
6
C43
330pF
C83
100nF
C62
100nF
OUTNR
OUTNR
M14
R43
20
R66
5K
R67
5K
L14 22 H
R44
20
R64
5K
R65
5K
L13 22 H
8
35
R62
5K
R63
5K
L12 22 H
C42
330pF
VCC2P
C81
100nF
C61
100nF
OUTNL
PGND1N
C71
100nF
M17
VCCSIGN
IN2A
OUTPL
OUTNL
IN1B
VDD
OUTPL
14
10
R61
5K
L11 22 H
17
TRI-STATE
C58
100nF
15
C74
100nF
C44
330pF
R54
6
C84
100nF
R68
5K
C21
2200 F
C31 820 F
C91
1 F
4
C32 820 F
C92
1 F
4
C33 820 F
C93
1 F
4
C34 820 F
C94
1 F
4
For more information, refer to the application note AN1994.
DocID13183 Rev 6
13/18
18
Package mechanical data
7
STA516B
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark
14/18
DocID13183 Rev 6
STA516B
Figure 11. PowerSO36 exposed pad up outline drawing
DocID13183 Rev 6
Package mechanical data
15/18
Package mechanical data
STA516B
Table 9. PowerSO36 exposed pad up dimensions
mm.
inch.
Symbol
Min.
16/18
Typ.
Max.
Min.
Typ.
Max.
A
3.25
-
3.43
0.128
-
0.135
A2
3.10
-
3.20
0.122
-
0.126
A4
0.80
-
1.00
0.031
-
0.039
A5
-
0.20
-
-
0.008
-
a1
0.03
-
-0.04
0.001
-
-0.002
b
0.22
-
0.38
0.009
-
0.015
c
0.23
-
0.32
0.009
-
0.013
D
15.80
-
16.00
0.622
-
0.630
D1
9.40
-
9.80
0.370
-
0.386
D2
-
1.00
-
-
0.039
-
E
13.90
-
14.50
0.547
-
0.571
E1
10.90
-
11.10
0.429
-
0.437
E2
-
-
2.90
-
-
0.114
E3
5.80
-
6.20
0.228
-
0.244
E4
2.90
-
3.20
0.114
-
0.126
e
-
0.65
-
-
0.026
-
e3
-
11.05
-
-
0.435
-
G
0
-
0.08
0
-
0.003
H
15.50
-
15.90
0.610
-
0.626
h
-
-
1.10
-
-
0.043
L
0.80
-
1.10
0.031
-
0.043
M
2.25
-
2.60
0.089
-
0.102
N
-
-
10 degrees
-
-
10 degrees
R
-
0.6
-
-
0.024
-
s
-
-
8 degrees
-
-
8 degrees
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8
Revision history
Revision history
Table 10. Document revision history
Date
Revision
Changes
01-Feb-2007
1
Initial release.
19-Mar-2007
2
Update to reflect product maturity.
11-Aug-2009
3
Updated section Description on cover page.
16-Nov-2010
4
Modified presentation
Updated Chapter 3: Electrical specifications on page 5
Added Chapter 5: Applications information on page 10
15-Jan-2014
5
Modified Section 4: Power supply and control sequencing on page 9
11-Feb-2014
6
Updated order code Table 1 on page 1
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STA516B
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