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STA518
40 V, 3.5 A quad power half-bridge
Datasheet - production data
Description
The STA518 is a monolithic quad half-bridge
stage in multipower BCD technology. The device
can be used also as dual bridge or reconfigured,
by connecting the CONFIG pin to the Vdd pin, as
a single bridge with double current capacity.
The device is particularly designed to make the
output stage of a stereo all-digital high-efficiency
(DDX™) amplifier capable of delivering an output
power of 24 W x 4 channels @ THD = 10% at
VCC 30 V into a 4  load in single-ended
configuration.
PowerSSO36
with exposed pad (or slug) up
It can also deliver 50 + 50 W @ THD = 10% at
VCC 29 V as output power into an 8 load in BTL
configuration and 70 W @ THD = 10% at VCC
34 V into 8 in a single paralleled BTL
configuration.
Features
 Multipower BCD technology
 Minimum input output pulse width distortion
 200 m RdsON complementary DMOS output
stage
The input pins have a threshold proportional to
the VL pin voltage.
 CMOS-compatible logic inputs
 Thermal protection
 Thermal warning output
 Undervoltage protection
 Short-circuit protection
Table 1. Device summary
Order code
Temperature range °C
Package
Packaging
STA51813TR
-40 to 90
PowerSSO36 (slug up)
Tape & reel
September 2014
This is information on a product in full production.
DocID010708 Rev 6
1/21
www.st.com
Contents
STA518
Contents
1
Audio application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4
Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Technical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Logic interface and decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
Power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Parallel output / high current operation . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
DocID010708 Rev 6
STA518
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VLOW, VHIGH variation with Ibias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Logic truth table (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PowerSO36 exposed pad up dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DocID010708 Rev 6
3/21
21
List of figures
STA518
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
4/21
Audio application circuit (quad single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Low-current dead time for single-ended application: test circuit. . . . . . . . . . . . . . . . . . . . . 11
High-current dead time for bridge application: block diagram. . . . . . . . . . . . . . . . . . . . . . . 11
High-current dead time for bridge application: test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . 11
STA518 block diagralm full-bridge DDX® or binary modes . . . . . . . . . . . . . . . . . . . . . . . . 12
STA518 bock diagram binary half-bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical stereo full-bridge configuration to obtain 50 + 50 W @ THD = 10%, RL = 8 ,
VCC = 29 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typical single BTL configuration to obtain 70 W @ THD 10%, RL = 8 , VCC = 34 V . . . 14
Power dissipation vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
THD+N vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
THD+N vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power dissipation vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
THD+N vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PSSO36 (slug up) mechanical outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DocID010708 Rev 6
DocID010708 Rev 6
R57
10K
C58
100nF
TH_WAR
+3.3V
C60
100nF
IN2B
IN2A
C53
100nF
IN1B
C58
100nF
R59
10K
PWRDN
IN1A
33
34
VSS
VSS
GNDSUB
IN2B
GND-Clean
GND-Reg
IN2A
VCCSIGN
1
32
19
20
31
36
35
22
VDD
VCCSIGN
21
30
IN1B
VDD
28
TH_WAR
TRI-STATE
27
FAULT
26
25
24
PWRDN
23
VL
29
CONFIG
IN1A
REGULATORS
PROTECTIONS
&
LOGIC
M14
M16
M15
M17
M4
M5
M2
M3
5
2
3
4
6
9
8
7
13
10
11
12
14
16
17
D03AU1474
PGND2N
OUTNR
OUTNR
C52
1μF
VCC2N
PGND2P
OUTPR
OUTPR
VCC2P
PGND1N
OUTNL
OUTNL
C51
1μF
VCC1N
PGND1P
OUTPL
OUTPL
VCC1P
C44
330pF
R44
20
C62
100nF
C43
330pF
R43
20
C42
330pF
R42
20
C61
100nF
C41
330pF
R41
20
R54
6
C74
100nF
L14 22μH
R53
6
C73
100nF
L13 22μH
R52
6
C72
100nF
L12 22μH
R51
6
C71
100nF
L11 22μH
C84
100nF
C83
100nF
C82
100nF
C81
100nF
R68
5K
R67
5K
R66
5K
R65
5K
R64
5K
R63
5K
R62
5K
R61
5K
C94
1μF
C34 820μF
C93
1μF
C33 820μF
C92
1μF
C32 820μF
C91
1μF
C31 820μF
4Ω
4Ω
4Ω
4Ω
C21
2200μF
+VCC
1
15
STA518
Audio application circuit
Audio application circuit
Figure 1. Audio application circuit (quad single-ended)
5/21
21
Pin description
2
STA518
Pin description
Figure 2. Pin connections (top view)
VCCSign
36
1
GND-SUB
VCCSign
35
2
OUT2B
VSS
34
3
OUT2B
VSS
33
4
VCC2B
IN2B
32
5
GND2B
IN2A
31
6
GND2A
IN1B
30
7
VCC2A
IN1A
29
8
OUT2A
TH_WAR
28
9
OUT2A
FAULT
27
10
OUT1B
TRI-STATE
26
11
OUT1B
PWRDN
25
12
VCC1B
CONFIG
24
13
GND1B
VL
23
14
GND1A
VDD
22
15
VCC1A
VDD
21
16
OUT1A
GND-Reg
20
17
OUT1A
GND-Clean
19
18
N.C.
D01AU1273
Table 2. Pin function
6/21
Pin n°
Name
Description
1
GND-SUB
2, 3
OUT2B
Output half-bridge 2B
4
Vcc2B
Positive supply
5
GND2B
Negative supply
6
GND2A
Negative supply
7
Vcc2A
Positive supply
8, 9
OUT2A
Output half-bridge 2A
10, 11
OUT1B
Output half-bridge 1B
12
Vcc1B
Positive supply
13
GND1B
Negative supply
14
GND1A
Negative supply
15
Vcc1A
Positive supply
16, 17
OUT1A
Output half-bridge 1A
18
NC
Substrate ground
Not connected
DocID010708 Rev 6
STA518
Pin description
Table 2. Pin function (continued)
Pin n°
Name
Description
19
GND-clean
Logical ground
20
GND-Reg
Ground for regulator Vdd
21, 22
Vdd
5 V regulator referred to ground
23
VL
Logic reference voltage
24
CONFIG
Configuration pin
25
PWRDN
Short-circuit pin
26
TRI-STATE
27
FAULT
28
TH_WAR
29
IN1A
Input of half-bridge 1A
30
IN1B
Input of half-bridge 1B
31
IN2A
Input of half-bridge 2A
32
IN2B
Input of half-bridge 2B
33, 34
Vss
35, 36
VCC Sign
Hi-Z pin
Fault pin advisor
Thermal warning advisor
5 V regulator referred to +VCC
Signal positive supply
Table 3. Functional pin status
Pin name
Pin n°
Logical value
FAULT
27
0
Fault detected (short-circuit, or thermal)
FAULT *
27
1
Normal operation
TRI-STATE
26
0
All powers in Hi-Z state
TRI-STATE
26
1
Normal operation
PWRDN
25
0
Low consumption
PWRDN
25
1
Normal operation
TH_WAR
28
0
Temperature of the IC = 130 °C
28
1
Normal operation
TH_WAR
(1)
IC - status
1. The pin is an open collector. To have a high logic value, it needs to be pulled up by a resistor.
DocID010708 Rev 6
7/21
21
Electrical specifications
STA518
3
Electrical specifications
3.1
Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol
3.2
Parameter
Value
Unit
VCC
DC supply voltage (pin 4, 7, 12, 15)
40
V
Vmax
Maximum voltage on pins 23 to 32
5.5
V
-40 to 90
°C
Top
Operating temperature range
Ptot
Power dissipation (Tcase = 70 °C)
21
W
Tstg, Tj
Storage and junction temperature
-40 to 150
°C
Recommended operating conditions
Table 5. Recommended operating conditions (1)
Symbol
VCC
Parameter
Min.
DC supply voltage
10
VL
Input logic reference
2.7
Tamb
Ambient temperature
0
Typ.
3.3
Max.
Unit
36.0
V
5.0
V
70
°C
Max.
Unit
1.5
°C/W
1. Performance not guaranteed beyond recommended operating conditions
3.3
Thermal data
Table 6. Thermal data (1)
Symbol
Tj-case
Parameter
Min.
Typ.
Thermal resistance junction to case (thermal pad)
TjSD
Thermal shut-down junction temperature
150
°C
Twarn
Thermal warning temperature
130
°C
thSD
Thermal shut-down hysteresis
25
°C
1. See thermal information
3.4
Thermal information
The power dissipated within the device depends primarily on the supply voltage, load
impedance and output modulation level. The PSSO36 package of the STA518 includes an
exposed thermal slug on the top of the device to provide a direct thermal path from the IC to
the heatsink. For the quad single-ended application the dissipated power vs. output power is
shown in Figure 10.
8/21
DocID010708 Rev 6
STA518
Electrical specifications
Considering that for the STA518 the thermal resistance junction to slug is 1.5 °C/W and the
estimated thermal resistance due to the grease placed between slug and heat sink is
2.3 °C/W (the use of thermal pads for this package is not recommended), the suitable heat
sink Rth to be used can be drawn from the following graph Figure 11, where is shown the
derating power vs. tamb for different heat sinks.
3.5
Electrical characteristics
Refer to the circuit in Figure 3 (VL = 3.3 V; VCC = 30 V; RL = 8 ; fsw = 384 kHz; Tamb = 25
°C unless otherwise specified)
Table 7. Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
200
270
m
50
μA
RdsON
Power P-channel / N-channel
MOSFET RdsON
Id = 1 A
Idss
Power P-channel / N-channel
leakage Idss
VCC = 35 V
gN
Power P-channel RdsON
matching
Id = 1 A
95
%
gP
Power N-channel RdsON
matching
Id = 1 A
95
%
Dt_s
Low current dead time (static)
see test circuit Figure 3
Dt_d
High current dead time (dynamic)
td ON
td OFF
20
ns
L = 22 μH; C = 470 nF; RL = 8 
Id = 3 A; seeFigure 5
50
ns
Turn-on delay time
Resistive load; VCC = 30 V
100
ns
Turn-off delay time
Resistive load; VCC = 30 V
100
ns
25
ns
25
ns
36
V
VL/2
+300mV
V
tr
Rise time
tf
Fall time
10
Resistive load; as Figure 3
VCC
Supply voltage operating voltage
VIN-H
High-level input voltage
VIN-L
Low-level input voltage
IIN-H
High-level input current
Pin voltage = VL
1
A
IIN-L
Low-level input current
Pin voltage = 0.3 V
1
A
High-level PWRDN pin input
current
VL = 3.3 V
35
A
VLOW
Low logical state voltage VLOW
(pin PWRDN, TRISTATE) (1)
VL = 3.3 V
VHIGH
High logical state voltage VHIGH
(pin PWRDN, TRISTATE) (1)
VL = 3.3 V
IPWRDN-H
IVCCPWRDN
10
VL/2 300mV
Supply current from VCC in power
PWRDN = 0
down
DocID010708 Rev 6
V
0.8
V
1.7
V
3
mA
9/21
21
Electrical specifications
STA518
Table 7. Electrical characteristics (continued)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IFAULT
Output current pins
FAULT, TH_WAR when
fault conditions
Vpin = 3.3 V
1
mA
IVCC-hiz
Supply current from VCC in Tristate
VCC = 30 V; Tri-state = 0
22
mA
Supply current from VCC in
operation
(both channels switching)
VCC = 30V;
Input pulse width = 50% Duty;
Switching frequency = 384 kHz;
No LC filters;
50
mA
Isc (short-circuit current limit) (2)
VCC = 30 V
6
A
7
V
IVCC
IVCC-q
VUV
tpw_min
3.5
Undervoltage protection
threshold
Output minimum pulse width
No load
70
150
ns
1. Table 8 explains the VLOW, VHIGH variation with Ibias.
2. See relevant Application Note AN1994
Table 8. VLOW, VHIGH variation with Ibias
VL
VLow min
VHigh max
Unit
2.7
0.7
1.5
V
3.3
0.8
1.7
V
5
0.85
1.85
V
Table 9. Logic truth table (see Figure 4)
TRI-STATE
INxA
INxB
Q1
Q2
Q3
Q4
Output
mode
0
x
x
OFF
OFF
OFF
OFF
Hi-Z
1
0
0
OFF
OFF
ON
ON
DUMP
1
0
1
OFF
ON
ON
OFF
NEGATIVE
1
1
0
ON
OFF
OFF
ON
POSITIVE
1
1
1
ON
ON
OFF
OFF
Not used
10/21
DocID010708 Rev 6
STA518
Electrical specifications
Figure 3. Low-current dead time for single-ended application: test circuit
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
Duty cycle = 50%
DTf
M58
OUTxY
INxY
R 8Ω
M57
V67 =
vdc = Vcc/2
+
-
gnd
D03AU1458
Figure 4. High-current dead time for bridge application: block diagram
+VCC
Q1
Q2
OUTxA
INxA
OUTxB
Q3
INxB
Q4
GND
D00AU1134
Figure 5. High-current dead time for bridge application: test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
DTin(A)
Q1
Q2
Rload=8Ω
OUTA
INA
Iout=4.5A
M57
Q3
DTout(B)
L67 22μ
C69
470nF
L68 22μ
C71 470nF
C70
470nF
DTin(B)
OUTB
INB
Iout=4.5A
Q4
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
DocID010708 Rev 6
M64
M63
D03AU1517
11/21
21
Technical information
4
STA518
Technical information
The STA518 is a high-efficiency dual-channel H-Bridge that is able to deliver 50 W per
channel (@ THD = 10% RL = 8 , VCC = 29 V) of audio output power.
The STA518 converts both DDX and binary-controlled PWM signals into audio power at the
load. It includes a logic interface, integrated bridge drivers, high-efficiency MOSFET outputs
and thermal and short-circuit protection circuitry.
In DDX mode, two logic level signals per channel are used to control high-speed MOSFET
switches to connect the speaker load to the input supply or to ground in a bridge
configuration, according to the damped ternary modulation operation.
In binary mode operation, both full-bridge and half-bridge modes are supported. The
STA518 includes overcurrent and thermal protection as well as an undervoltage lockout with
automatic recovery. A thermal warning status is also provided.
Figure 6. STA518 block diagram full-bridge DDX® or binary modes
INL 1:2
INR 1:2
VL
PWRDN
OUTPL
Logic I/F
and Decode
Left
H-Bridge
OUTNL
TRI-STATE
FAULT
TWARN
Protection
Circuitry
OUTPR
Right
H-Bridge
Regulators
OUTNR
Figure 7. STA518 block diagram binary half-bridge mode
LeftA
-Bridge
OUTPL
LeftB
-Bridge
OUTNL
Protection
Circuitry
RightA
-Bridge
OUTPR
Regulators
RightB
-Bridge
OUTNR
INL 1:2
INR 1:2
VL
Logic I/F
and Decode
PWRDN
TRI-STATE
FAULT
TWARN
4.1
Logic interface and decode
The STA518 power outputs are controlled using one or two logic level timing signals. In
order to provide a proper logic interface, the Vbias input must operate at the same voltage as
the DDX control logic supply.
Protection circuitry:
The STA518 includes protection circuitry for overcurrent and thermal overload conditions. A
thermal warning pin (pin 28) is activated low (open-drain MOSFET) when the IC
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STA518
Technical information
temperature exceeds 130 °C, in advance of the thermal shutdown protection. When a fault
condition is detected, an internal fault signal acts to immediately disable the output power
MOSFETs, placing both H-Bridges in high impedance state. At the same time an open-drain
MOSFET connected to the FAULT pin (pin 27) is switched on.
There are two possible modes subsequent to activating a fault:
1. SHUTDOWN mode: with FAULT (pull-up resistor) and TRI-STATE pins independent,
an activated fault will disable the device, signaling low at the FAULT output.
The device may subsequently be reset to normal operation by toggling the TRI-STATE
pin from high to low to high using an external logic signal.
2. AUTOMATIC recovery mode: This is shown in the audio application circuit of quad
single-ended. The FAULT and TRI-STATE pins are shorted together and connected to
a time constant circuit comprising R59 and C58.
An activated FAULT will force a reset on the TRI-STATE pin causing normal operation
to resume following a delay determined by the time constant of the circuit.
If the fault condition is still present, the circuit operation will continue repeating until the
fault condition is removed.
An increase in the time constant of the circuit will produce a longer recovery interval.
Care must be taken in the overall system design as not to exceed the protection
thresholds under normal operation.
4.2
Power outputs
The STA518 power and output pins are duplicated to provide a low impedance path for the
device's bridged outputs. All duplicate power, ground and output pins must be connected for
proper operation.
The PWRDN or TRI-STATE pins should be used to set all MOSFETS to the Hi-Z state
during power-up until the logic power supply, VL, is settled.
4.3
Parallel output / high current operation
When using DDX mode output, the STA518 outputs can be connected in parallel in order to
increase the output current capability to a load. In this configuration the STA518 can provide
70 W into 8 ohm.
This mode of operation is enabled with the CONFIG pin (pin 24) connected to VREG1 and
the inputs combined INLA=INLB, INRA=INRB and the outputs combined OUTLA=OTLB,
OUTRA=OUTRB.
4.4
Additional information
Output Filter: A passive 2nd order passive filter is used on the STA518 power outputs to
reconstruct an analog audio signal. System performance can be significantly affected by the
output filter design and choice of passive components. A filter design for 6 ohm / 8 ohm
loads is shown in the typical application circuit of Figure 9.
Quad single-ended circuit (Figure 1) shows a filter for half-bridge mode, 4 ohm loads.
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Technical information
STA518
Figure 8. Typical stereo full-bridge configuration to obtain 50 + 50 W @ THD = 10%,
RL = 8 , VCC = 29 V
+VCC
VCC1A
IN1A
29
VL
23
CONFIG
24
PWRDN
25
FAULT
27
M3
IN1A
+3.3V
PWRDN
R57
10K
R59
10K
16
M2
PROTECTIONS
&
LOGIC
26
TH_WAR
M5
TH_WAR
28
IN1B
30
VDD
21
VDD
22
VSS
33
VSS
34
OUT1A
14
GND1A
12
VCC1B
OUT1B
M4
REGULATORS
VCCSIGN
13
GND1B
7
VCC2A
C60
100nF
VCCSIGN
IN2A
IN2A
GND-Reg
GND-Clean
IN2B
IN2B
GNDSUB
9
36
M15
31
20
19
M16
4
VCC2B
2
32
C33
1μF
3
OUT2B
OUT2B
M14
1
5
8Ω
C21
100nF
C110
100nF
C109
330pF R103
6
OUT2A
GND2A
R100
6
L113 22μH
OUT2A
6
C99
100nF
C23
470nF
C101
100nF
R98
6
L19 22μH
C32
1μF
8
35
R63
20
OUT1B
M17
C53
100nF
C20
100nF
C52
330pF
C31
1μF
11
C55
1000μF
L18 22μH
OUT1A
10
IN1B
C58
100nF
C30
1μF
17
TRI-STATE
C58
100nF
15
R104
20
C107
100nF
C108
470nF
C106
100nF
R102
6
8Ω
C111
100nF
L112 22μH
GND2B
D00AU1148B
Figure 9. Typical single BTL configuration to obtain 70 W @ THD 10%, RL = 8 ,
VCC = 34 V(a)
VL
+3.3V
GND-Clean
GND-Reg
10K
23
18
N.C.
22μH
100nF
100nF
X7R
VDD
VDD
CONFIG
TH_WAR
TH_WAR
PWRDN
nPWRDN
10K
FAULT
IN1A
IN1B
IN1A
IN2A
IN2B
IN1B
VSS
VSS
100nF
X7R
20
21
VCCSIGN
100nF
X7R
VCCSIGN
Add.
GNDSUB
16
11
10
9
24
OUT1B
OUT1B
OUT2A
6.2
1/2W
330pF
6.2
1/2W
15
12
7
31
4
8Ω
22μH
VCC1A
VCC1B
32V
1μF
X7R
VCC2A
32
33
100nF
X7R
470nF
FILM
100nF
X7R
100nF
FILM
OUT2B
2
30
34
22Ω
1/2W
OUT2B
3
25
29
100nF
FILM
OUT1A
8
28
26
OUT1A
OUT2A
22
27
TRI-STATE
100nF
19
17
VCC2B
2200μF
63V
32V
1μF
X7R
GND1A
14
GND1B
35
13
36
6
1
5
GND2A
GND2B
D04AU1549
a. A PWM modulator as driver is needed. In particular, this result is achieved using the STA308 + STA518 +
STA50X demo board. Peak Power for t  1sec.
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STA518
5
Characterization curves
Characterization curves
The following characterization curves are obtained using the quad single-ended
configuration (Figure 1) with an STA308A controller.
Figure 10. Power dissipation vs. output power
Figure 11. Power derating curve
Figure 12. THD+N vs. output power
Figure 13. Output power vs. supply voltage
Figure 14. THD vs. frequency
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Characterization curves
STA518
The following characterizations are obtained using the stereo full-bridge configuration
(Figure 8) with STA308A controller.
Figure 15. Output power vs. supply voltage
Figure 16. THD+N vs. output power
Figure 17. Power dissipation vs. output power
The following characterization is obtained using a single BTL configuration (Figure 9) with
the STA308A controller.
Figure 18. THD+N vs. output power
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STA518
6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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STA518
Figure 19. PSSO36 (slug up) mechanical outline
DocID010708 Rev 6
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Package information
7618147_F
STA518
Package information
Table 10. PowerSO36 exposed pad up dimensions
Dimensions in mm.
Dimensions in inch.
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
2.15
-
2.45
0.085
-
0.096
A2
2.15
-
2.35
0.085
-
0.092
a1
0
-
0.1
0.00
-
0.004
b
0.18
-
0.36
0.007
-
0.014
c
0.23
-
0.32
0.009
-
0.013
D
10.10
-
10.50
0.398
-
0.413
E
7.4
-
7.6
0.291
-
0.299
e
-
0.5
-
-
0.020
-
e3
-
8.5
-
-
0.335
-
F
-
2.3
-
-
0.091
-
G
-
-
0.1
-
-
0.004
H
10.1
-
10.5
-
-
0.413
h
-
-
0.4
-
-
0.016
k
0 deg
-
8 deg
0 deg
-
8 deg
L
0.55
-
0.85
0.022
M
-
4.3
-
-
0.169
-
N
-
-
10 deg
-
-
10 deg
O
-
1.2
-
-
0.047
-
Q
-
0.8
-
-
0.031
-
S
-
2.9
-
-
0.114
-
T
-
3.65
-
-
0.114
-
U
-
1.0
-
-
0.039
-
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Revision history
7
STA518
Revision history
Table 11. Document revision history
20/21
Date
Revision
Changes
19-Aug-2004
1
Initial release.
11-Nov-2004
2
Changed symbol in “Electrical Characteristics”.
18-May-2006
3
Changed operating temperature range value to -40 to 90°C
(seeTable 4).
26-Feb-2014
4
Updated order code Table 1 on page 1.
11-Jul-2014
5
Updated figure in cover page.
16-Sep-2014
6
Updated package information (Figure 19, Table 10, and cover page)
Minor textual updates
DocID010708 Rev 6
STA518
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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© 2014 STMicroelectronics – All rights reserved
DocID010708 Rev 6
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