AN5106, SPI Topics: Watchdog, Serial Output & Parity Check for the Dual SOIC ...

Freescale Semiconductor, Inc.
Application Note
Document Number: AN5106
Rev. 1.0, 5/2015
SPI Topics: Watchdog, Serial Output & Parity
Check
for the Dual SOIC 24 V High-side Switch Family
1
Introduction
This application note describes SPI robustness with respect to the
Watchdog & parity check and the SPI Serial Output data of the
following devices:
•
•
•
•
•
MC06XS4200
MC10XS4200
MC20XS4200
MC22XS4200
MC50XS4200
These intelligent high-side switches are designed for use in 24 V
systems such as trucks, busses, and special engines. They are
applicable to other industrial and 12 V applications as well. The low
RDS(on) channels can be used to control incandescent lamps,
LEDs, solenoids, or DC motors. Control, device configuration, and
diagnostics are performed through a 16-bit SPI interface, allowing
easy integration into existing applications. For complete feature
descriptions, refer to the individual data sheets for the devices.
Freescale analog ICs are manufactured using the SMARTMOS
process, a combinational BiCMOS manufacturing flow that
integrates precision analog, power functions and dense CMOS
logic together on a single cost-effective die.
© Freescale Semiconductor, Inc., 2015. All rights reserved.
Contents
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 SPI Robustness Monitoring Feature. . . . . . . . . . . . . . . . . . . 4
4 SPI Unused Address 011 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI
2
SPI
2.1
Serial Output Register
The SPI interface offers full duplex, synchronous data transfers over four I/O lines: Serial Input (SI), Serial Output (SO),
Serial Clock (SCLK), and Chip Select (CSB).The SI / SO pins of the device follow a first-in first-out (D15 to D0) protocol.
Transfer of input and output words starts with the most significant bit (MSB).
CSB
SCLK
SI
SO
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
1.RSTB
RST must
Notes 1.
mustbe
beininaalogic
logic[1]
[1]state
stateduring
duringdata
datatransfer.
transfer.
Notes
pinstarting
startingwith
withD15
D15 (MSB)
(MSB)and
andending
endingwith
withbit
bit D0.
D0.
2.Data
Dataenter
enterthe
theSI
SIpin
2.
3.Data
Dataare
areavailable
availableon
onthe
theSO
SOpin
pinstarting
startingwith
withbit
bitOD15
0D15 (MSB)
(MSB)and
andending
endingwith
withbit
bit00(OD0).
(OD0).
3.
Figure 1. 16-Bit SPI Interface Timing Diagram
Table 1. SI message bit assignment
Bit n
MSB
.
.
.
.
LSB
SI Register Bit
Bit Functional Description
D15
Watchdog in (WDIN): Its state must be alternated at least once within the
timeout period
D14
Parity (P) check. P-bit must be set to 0 for an even number of 1-bits and to 1
for an odd number.
D13
Selection between SI registers from bank 0 (0 = channel 0) and bank 1
D12:D10
D9:D0
Register address bits
Used to configure the device and the protective functions and to address the
SO registers
The SO output value depends on the register previously selected by the STATR register: The first sixteen SO register bits
are set to the address previously accessed by SI word (bit D13, D2…D0 of the STATR_s input register).
Figure 2 shows an SPI sequence under various circumstances, illustrating the SI frames and the corresponding contents of
the SO register.
AN5106 Application Note Rev. 1.0 5/2015
2
Freescale Semiconductor, Inc.
SPI
Write PWMR
Register
(ex:0x05FF)
Write Register
STATR to
read PWMR
register
(0x4002)
Write OCR
Register
(ex:0x5060)
Write Register
STATR to
read OCR
register
(0x4004)
SPI frame SI
MCU to eSwitch
(n)
(n+1)
(n+2)
(n+3)
(n+4)
SPI frame SO
from eSwitch
to MCU
(X)
(X)
(Y)
(Y)
(Z)
Data on SO is
data from last
register read
selection with
STATR
Data on SO is
data from last
register read
selection with
STATR
Data on SO is
data from last
register read
selection with
STATR
Data on SO is
data from last
register read
selection with
STATR
Data on SO is
data from last
register read
selection with
STATR
Here: PWMR
SO=0x1BFF
Here: PWMR
SO=0x1BFF
Here: OCR
SO=0x1260
Figure 2. SO Message versus SI Write Commands
2.2
Control of Written SI Data
To determine in real time if the SPI communication occurred without errors, extend the frame to 32 bits. Send two identical
16-bit words consecutively on SI, with the CSB pin released for the duration of the 32 bits. The SO output will then report
the STATR selected register and the second word from SI.
CSB
SPI frame SI
MCU to eSwitch
SPI frame SO
from eSwitch
to MCU
16 bits data 0x1234
STATR Selected Register
16 bits data 0x1234
16 bits data 0x1234
Figure 3. 32-bit SPI Interface
AN5106 Application Note Rev. 1.0 5/2015
Freescale Semiconductor, Inc.
3
SPI Robustness Monitoring Feature
3
SPI Robustness Monitoring Feature
The device monitors the SPI communication robustness through the Watchdog bit and parity check. Parity check (P) must
be set so that the total number of 1-bits in the SPI word is even. The Watchdog feature monitors whether the communication
has been lost. The device monitors the state of the first bit (WDIN) of the SPI frame.
3.1
Watchdog
When the state of the WDIN bit remains unchanged within a data stream of duration tWDTO = 310 ms typ., the device
assumes SPI communication has been lost and enters Fail-safe mode. The FSOB pin then goes low. This behavior can be
disabled by setting the bit WD_DIS = 1 (register GCR, bit D4)
The Watchdog timer starts at the rising edge of RSTB. The SPI frames must be sent with the WDIN bit alternating at least
once within the 310 ms timeframe.
When the RSTB is not under control (for example, if the device happens to enter Fail-safe Mode at start up,) a sequence
must be run to exit from the aforementioned mode:
1. Send a SPI frame with WDIS bit =1 (D15), The register and contents do not matter.
2. Send a second SPI frame with WDIS bit=0 within the 310 ms timeframe.
Figure 4 describe the Watchdog timing:
SPI Frame
WDIN = 1 0x8xxx
WDIN = 0 0x0AAA
Watchdog timer
tWDTO max > 310 ms
tWDTO > 310 ms
FSOB
Fail Safe state
register reset
Register data
Default
0x0AAA
new ON/OFF state
with new register set
HS0 (or HS1)
Output controlled
with SPI
(register PWMR)
register reset implies output are
set to default values i.e. output OFF
HS0 (or HS1)
Output controlled
by IN0 or IN1
when outputs are controlled by direct inputs, entering
Fail Safe mode has no impact on outputs but device
configuration is lost, registers are set to default states
Figure 4. Watchdog Timing Diagram
AN5106 Application Note Rev. 1.0 5/2015
4
Freescale Semiconductor, Inc.
SPI Robustness Monitoring Feature
When the device enters Fail-safe mode, the output states differ depending on the control method used:
•
•
3.2
If the ON/OFF state is controlled by registers (PWMR register), the registers are reset to default values and the
outputs are switched OFF.
If the ON/OFF state is controlled by direct inputs IN0 & IN1, the outputs remain controlled by IN0 & IN1 and are not
switched OFF. The register are reset to default values.
Parity Check
Parity check (P) must be set with an even number of 1-bits in the SPI word (P = 0 for an even number of 1-bits and P = 1 for
an odd number.) The parity bit is Bit14 of the SPI frame.
If the MCU happens to erroneously set a communication fault or Parity bit, the device reports the parity error at the next SPI
frame even if the SPI frame indicates no parity error.
Figure 5 show several scenarios of an SPI sequence. The drawing illustrates the parity errors on the SI frames and the
corresponding contents on SO. The SO output bits follow the same rule described in Figure 4. In this example, the PWMR
register is selected with STATR for SO read and all register writings apply to the PWMR register.
SPI frame SI
MCU to eSwitch
PWMR
Register Write
PWMR
Register Write
with wrong
Parity bit
2nd frame
PWMR
Register Write
with wrong
Parity bit
PWMR
Register Write
with correct
Parity bit
PWMR
Register Write
with correct
Parity bit
(n)
(n+1)
(n+2)
(n+3)
(n+4)
(n)
(n)
(n)
(n+3)
(n-1)
SPI frame SO
from eSwitch
to MCU
Data on SO is
data from last
register read
selection with
STATR
Data on SO is
data from last
register read
selection with
STATR
Data on SO is
data from last
register read
selection with
STATR
Data on SO is
data from last
register read
selection with
STATR
Data on SO is
data from last
register read
selection with
STATR
PWMR
PWMR
PWMR
PWMR
PWMR
BIT PF = 0
BIT PF = 0
BIT PF = 1
BIT PF = 1
BIT PF = 0
(n + 1) data
ignored
(n + 1) & (n+2)
data
ignored
When a parity error occurs on the previous SPI SI frame,
the PF bit is raised and reported on SO regardless of
the register selected for read.
Figure 5. Parity Check
AN5106 Application Note Rev. 1.0 5/2015
Freescale Semiconductor, Inc.
5
SPI Unused Address 011
4
SPI Unused Address 011
As shown in Figure 6, the address 011, bit D12-D10 of the Serial Input register addresses is not used. Register writes to this
address are ignored and the SO data reports the content of the previous read register selected. If the STATR register selects
the 011 address as the selected register, the read and write is ignored and the result of the previous register selection is
used.
SPI frame SI
MCU to eSwitch
SPI frame SO
from eSwitch
to MCU
Write Register
STATR to read
Register X
Register write
with
address = 011
(n)
(n+1)
(W)
(X)
Data on SO is
data from
previous register
read selection
with STATR
Register write
to Register X
(n+2)
(n+3)
(X)
(n+2)
Data on SO is
data from last
register read
selection with
STATR
Data on SO is
data from last
register read
selection with
STATR
Data on SO is
data from last
register read
selection with
STATR
Register X
Register X
(n + 1) data is
Ignored
Register X
Figure 6. Addressing Address 011
AN5106 Application Note Rev. 1.0 5/2015
6
Freescale Semiconductor, Inc.
Revision History
5
Revision History
Revision
Date
1.0
5/2015
Description
• Initial release
AN5106 Application Note Rev. 1.0 5/2015
Freescale Semiconductor, Inc.
7
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© 2015 Freescale Semiconductor, Inc.
Document Number: AN5106
Rev. 1.0
5/2015
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