Data Sheet

Freescale Semiconductor
Data Sheet: Technical Data
KE02 Sub-Family Data Sheet
Document Number MKE02P64M40SF0
Rev 3, 10/2014
MKE02P64M40SF0
Supports the following:
MKE02Z16VLC4(R),
MKE02Z32VLC4(R),
MKE02Z64VLC4(R),
MKE02Z16VLD4(R),
MKE02Z32VLD4(R),
MKE02Z64VLD4(R),
MKE02Z32VLH4(R),
MKE02Z64VLH4(R),
MKE02Z32VQH4(R),
MKE02Z64VQH4(R),
MKE02Z16VFM4(R),
MKE02Z32VFM4(R), and
MKE02Z64VFM4(R)
Key features
• Operating characteristics
– Voltage range: 2.7 to 5.5 V
– Flash write voltage range: 2.7 to 5.5 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 40 MHz ARM® Cortex-M0+ core and up
to 20 MHz bus clock
– Single cycle 32-bit x 32-bit multiplier
– Single cycle I/O access port
• Memories and memory interfaces
– Up to 64 KB flash
– Up to 256 B EEPROM
– Up to 4 KB RAM
• Clocks
– Oscillator (OSC) - supports 32.768 kHz crystal
or 4 MHz to 20 MHz crystal or ceramic
resonator; choice of low power or high gain
oscillators
– Internal clock source (ICS) - internal FLL with
internal or external reference, 31.25 kHz pretrimmed internal reference for 32 MHz system
clock (able to be trimmed for up to 40 MHz
system clock)
– Internal 1 kHz low-power oscillator (LPO)
• System peripherals
– Power management module (PMC) with three
power modes: Run, Wait, Stop
– Low-voltage detection (LVD) with reset or
interrupt, selectable trip points
– Watchdog with independent clock source
(WDOG)
– Programmable cyclic redundancy check module
(CRC)
– Serial wire debug interface (SWD)
– Bit manipulation engine (BME)
• Security and integrity modules
– 64-bit unique identification (ID) number per chip
• Human-machine interface
– Up to 57 general-purpose input/output (GPIO)
– Two up to 8-bit keyboard interrupt modules
(KBI)
– External interrupt (IRQ)
• Analog modules
– One up to 16-channel 12-bit SAR ADC,
operation in Stop mode, optional hardware
trigger (ADC)
– Two analog comparators containing a 6-bit
DAC and programmable reference input
(ACMP)
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2013–2014 Freescale Semiconductor, Inc.
• Timers
– One 6-channel FlexTimer/PWM (FTM)
– Two 2-channel FlexTimer/PWM (FTM)
– One 2-channel periodic interrupt timer (PIT)
– One real-time clock (RTC)
• Communication interfaces
– Two SPI modules (SPI)
– Up to three UART modules (UART)
– One I2C module (I2C)
• Package options
– 64-pin QFP/LQFP
– 44-pin LQFP
– 32-pin LQFP
– 32-pin QFN
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
2
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts........................................................................... 4
1.1 Determining valid orderable parts......................................4
5.2.2
FTM module timing............................................... 17
5.3 Thermal specifications.......................................................18
2 Part identification...................................................................... 4
5.3.1
Thermal operating requirements........................... 18
2.1 Description.........................................................................4
5.3.2
Thermal characteristics......................................... 19
2.2 Format............................................................................... 4
6 Peripheral operating requirements and behaviors.................... 20
2.3 Fields................................................................................. 4
6.1 Core modules.................................................................... 20
2.4 Example............................................................................ 5
6.1.1
SWD electricals ....................................................20
3 Parameter classification............................................................ 5
6.2 External oscillator (OSC) and ICS characteristics............. 21
4 Ratings...................................................................................... 6
6.3 NVM specifications............................................................ 23
4.1 Thermal handling ratings................................................... 6
6.4 Analog............................................................................... 24
4.2 Moisture handling ratings.................................................. 6
6.4.1
ADC characteristics...............................................25
4.3 ESD handling ratings.........................................................6
6.4.2
Analog comparator (ACMP) electricals................. 27
4.4 Voltage and current operating ratings............................... 7
5 General..................................................................................... 7
5.1 Nonswitching electrical specifications............................... 7
6.5 Communication interfaces................................................. 28
6.5.1
SPI switching specifications.................................. 28
7 Dimensions............................................................................... 31
5.1.1
DC characteristics................................................. 7
5.1.2
Supply current characteristics............................... 14
8 Pinout........................................................................................ 32
5.1.3
EMC performance................................................. 15
8.1 Signal multiplexing and pin assignments...........................32
5.2 Switching specifications.....................................................16
8.2 Device pin assignment...................................................... 34
5.2.1
Control timing........................................................ 16
7.1 Obtaining package dimensions......................................... 31
9 Revision history.........................................................................36
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
3
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: KE02Z.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q KE## A FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
KE##
Kinetis family
• KE02
A
Key attribute
• Z = M0+ core
FFF
Program flash memory size
R
Silicon revision
• M = Fully qualified, general market flow
• P = Prequalification
• 16 = 16 KB
• 32 = 32 KB
• 64 = 64 KB
• (Blank) = Main
• A = Revision after main
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
4
Freescale Semiconductor, Inc.
Parameter classification
Field
Description
T
Temperature range (°C)
PP
Package identifier
CC
Maximum CPU frequency (MHz)
N
Packaging type
Values
• V = –40 to 105
•
•
•
•
•
LC = 32 LQFP (7 mm x 7 mm)
FM = 32 QFN (5 mm x 5 mm)
LD = 44 LQFP (10 mm x 10 mm)
QH = 64 QFP (14 mm x 14 mm)
LH = 64 LQFP (10 mm x 10 mm)
• 4 = 40 MHz
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MKE02Z64VQH4
3 Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods.
To give the customer a better understanding, the following classification is used and the
parameters are tagged accordingly in the tables where appropriate:
Table 1. Parameter classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant sample size
across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices under
typical conditions unless otherwise noted. All values shown in the typical column are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the
parameter tables where appropriate.
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
5
Ratings
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
–6000
+6000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
–500
+500
V
2
Latch-up current at ambient temperature of 125°C
–100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test.
• Test was performed at 125 °C case temperature (Class II).
• I/O pins pass ±100 mA I-test with IDD current limit at 800 mA.
• I/O pins pass +60/-100 mA I-test with IDD current limit at 1000 mA.
• Supply groups pass 1.5 Vccmax.
• RESET pin was only tested with negative I-test due to product conditioning requirement.
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
6
Freescale Semiconductor, Inc.
General
4.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in the following table may
affect device reliability or cause permanent damage to the device. For functional
operating conditions, refer to the remaining tables in this document.
This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate
logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor
associated with the pin is enabled.
Table 2. Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
6.0
V
IDD
Maximum current into VDD
—
120
mA
VIN
ID
VDDA
0.31
Input voltage except true open drain pins
–0.3
VDD +
Input voltage of true open drain pins
–0.3
6
V
Instantaneous maximum current single pin limit (applies to all
port pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
Analog supply voltage
V
1. Maximum rating of VDD also applies to VIN.
5 General
5.1 Nonswitching electrical specifications
5.1.1 DC characteristics
This section includes information about power supply requirements and I/O pin
characteristics.
Table 3. DC characteristics
Symbol
C
—
—
Descriptions
Operating voltage
—
Min
Typical1
Max
Unit
2.7
—
5.5
V
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
7
Nonswitching electrical specifications
Table 3. DC characteristics (continued)
Symbol
C
Descriptions
Min
Typical1
Max
Unit
VOH
P
Output All I/O pins, except PTA2 5 V, Iload = –5 mA
high
and PTA3, standard3 V, Iload = –2.5 mA
voltage
drive strength
VDD – 0.8
—
—
V
VDD – 0.8
—
—
V
C
P
High current drive pins,
high-drive strength2
5 V, Iload = –20 mA
VDD – 0.8
—
—
V
3 V, Iload = –10 mA
VDD – 0.8
—
—
V
Output
high
current
Max total IOH for all ports
5V
—
—
–100
mA
3V
—
—
–60
Output
low
voltage
All I/O pins, standarddrive strength
5 V, Iload = 5 mA
—
—
0.8
V
3 V, Iload = 2.5 mA
—
—
0.8
V
5 V, Iload =20 mA
—
—
0.8
V
3 V, Iload = 10 mA
—
—
0.8
V
5V
—
—
100
mA
3V
—
—
60
4.5≤VDD<5.5 V
0.65 × VDD
—
—
2.7≤VDD<4.5 V
0.70 × VDD
—
—
4.5≤VDD<5.5 V
—
—
0.35 ×
VDD
2.7≤VDD<4.5 V
—
—
0.30 ×
VDD
C
IOHT
VOL
D
P
C
P
C
IOLT
VIH
VIL
D
P
P
High current drive pins,
high-drive strength2
Output
low
current
Max total IOL for all ports
Input
high
voltage
All digital inputs
Input low
voltage
All digital inputs
V
V
Vhys
C
Input
hysteresi
s
All digital inputs
—
0.06 × VDD
—
—
mV
|IIn|
P
Input
leakage
current
Per pin (pins in high
impedance input mode)
VIN = VDD or VSS
—
0.1
1
µA
|IINTOT|
C
Total
leakage
combine
d for all
port pins
Pins in high impedance
input mode
VIN = VDD or VSS
—
—
2
µA
RPU
P
Pullup
resistors
All digital inputs, when
enabled (all I/O pins
other than PTA2 and
PTA3)
—
30.0
—
50.0
kΩ
RPU3
P
Pullup
resistors
PTA2 and PTA3 pins
—
30.0
—
60.0
kΩ
IIC
D
DC
Single pin limit
injection Total MCU limit, includes
current4, sum of all stressed pins
5, 6
VIN < VSS, VIN >
VDD
-2
—
2
mA
-5
—
25
CIn
C
Input capacitance, all pins
—
—
—
7
pF
VRAM
C
RAM retention voltage
—
2.0
—
—
V
1. Typical values are measured at 25 °C. Characterized, not tested.
2. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support high current output.
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
8
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured
externally on the pin.
4. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 are true
open drain I/O pins that are internally clamped to VSS.
5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger value.
6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than
maximum injection current when the MCU is not consuming power, such as when no system clock is present, or clock rate
is very low (which would reduce overall power consumption).
Table 4. LVD and POR specification
Symbol
C
Description
Min
Typ
Max
Unit
1.5
1.75
2.0
V
4.2
4.3
4.4
V
Level 1 falling
(LVWV = 00)
4.3
4.4
4.5
V
Level 2 falling
(LVWV = 01)
4.5
4.5
4.6
V
Level 3 falling
(LVWV = 10)
4.6
4.6
4.7
V
Level 4 falling
(LVWV = 11)
4.7
4.7
4.8
V
POR re-arm
voltage1
VPOR
D
VLVDH
C
VLVW1H
C
VLVW2H
C
VLVW3H
C
VLVW4H
C
VHYSH
C
High range low-voltage
detect/warning hysteresis
—
100
—
mV
VLVDL
C
Falling low-voltage detect
threshold—low range (LVDV
= 0)
2.56
2.61
2.66
V
VLVW1L
C
Level 1 falling
(LVWV = 00)
2.62
2.7
2.78
V
VLVW2L
C
Level 2 falling
(LVWV = 01)
2.72
2.8
2.88
V
VLVW3L
C
Falling lowvoltage
warning
threshold—
low range
Level 3 falling
(LVWV = 10)
2.82
2.9
2.98
V
VLVW4L
C
Level 4 falling
(LVWV = 11)
2.92
3.0
3.08
V
VHYSDL
C
Low range low-voltage detect
hysteresis
—
40
—
mV
VHYSWL
C
Low range low-voltage
warning hysteresis
—
80
—
mV
VBG
P
Buffered bandgap output 3
1.14
1.16
1.18
V
Falling low-voltage detect
threshold—high range (LVDV
= 1)2
Falling lowvoltage
warning
threshold—
high range
1. Maximum is highest voltage that POR is guaranteed.
2. Rising thresholds are falling threshold + hysteresis.
3. voltage Factory trimmed at VDD = 5.0 V, Temp = 25 °C
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
9
Nonswitching electrical specifications
VDD-VOH(V)
IOH(mA)
Figure 1. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 5 V)
VDD-VOH(V)
IOH(mA)
Figure 2. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
10
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
VDD-VOH(V)
IOH(mA)
Figure 3. Typical VDD-VOH Vs. IOH (high drive strength) (VDD = 5 V)
VDD-VOH(V)
IOH(mA)
Figure 4. Typical VDD-VOH Vs. IOH (high drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
11
Nonswitching electrical specifications
VOL(V)
IOL(mA)
Figure 5. Typical VOL Vs. IOL (standard drive strength) (VDD = 5 V)
VOL(V)
IOL(mA)
Figure 6. Typical VOL Vs. IOL (standard drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
12
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
VOL(V)
IOL(mA)
Figure 7. Typical VOL Vs. IOL (high drive strength) (VDD = 5 V)
VOL(V)
IOL(mA)
Figure 8. Typical VOL Vs. IOL (high drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
13
Nonswitching electrical specifications
5.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes.
Table 5. Supply current characteristics
C
Parameter
Symbol
Core/Bus
Freq
VDD (V)
Typical1
Max2
Unit
Temp
C
Run supply current FEI
mode, all modules clocks
enabled; run from flash
RIDD
40/20 MHz
5
7.8
—
mA
–40 to 105 °C
20/20 MHz
6.7
—
10/10 MHz
4.5
—
1/1 MHz
1.5
—
7.7
—
mA
–40 to 105 °C
mA
–40 to 105 °C
mA
–40 to 105 °C
C
C
C
40/20 MHz
C
20/20 MHz
6.6
—
C
10/10 MHz
4.4
—
1/1 MHz
1.45
—
6.3
—
20/20 MHz
5.3
—
10/10 MHz
3.7
—
1/1 MHz
1.5
—
6.2
—
C
C
C
Run supply current FEI
mode, all modules clocks
disabled; run from flash
RIDD
40/20 MHz
3
5
C
40/20 MHz
C
20/20 MHz
5.3
—
C
10/10 MHz
3.7
—
1/1 MHz
1.4
—
10.3
—
9
14.8
10/10 MHz
5.2
—
1/1 MHz
1.45
—
10.2
—
C
P
C
Run supply current FBE
mode, all modules clocks
enabled; run from RAM
RIDD
40/20 MHz
3
5
20/20 MHz
C
40/20 MHz
P
20/20 MHz
8.8
11.8
C
10/10 MHz
5.1
—
1/1 MHz
1.4
—
8.9
—
8
12.3
10/10 MHz
4.4
—
1/1 MHz
1.35
—
8.8
—
C
P
C
Run supply current FBE
mode, all modules clocks
disabled; run from RAM
RIDD
40/20 MHz
3
5
20/20 MHz
C
40/20 MHz
3
P
20/20 MHz
7.8
9.2
C
10/10 MHz
4.2
—
1/1 MHz
1.3
—
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
14
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Table 5. Supply current characteristics (continued)
C
Parameter
Symbol
Core/Bus
Freq
VDD (V)
Typical1
Max2
Unit
Temp
C
Wait mode current FEI
mode, all modules clocks
enabled
WIDD
40/20 MHz
5
6.4
—
mA
–40 to 105 °C
20/20 MHz
5.5
—
20/10 MHz
3.5
—
1/1 MHz
1.4
—
6.3
—
µA
–40 to 105 °C
P
C
C
40/20 MHz
C
20/20 MHz
5.4
—
10/10 MHz
3.4
—
1/1 MHz
1.4
—
P
SIDD
P
Stop mode supply current
no clocks active (except 1
kHz LPO clock)3
C
ADC adder to Stop
—
3
—
5
2
85
—
3
1.9
80
—
5
86 (64-, 44pin
packages)
—
ADLPC = 1
ADLSMP = 1
µA
–40 to 105 °C
µA
–40 to 105 °C
µA
–40 to 105 °C
42 (32-pin
package)
ADCO = 1
C
–40 to 105 °C
3
MODE = 10B
ADICLK = 11B
82 (64-, 44pin
packages)
—
41 (32-pin
package)
C
ACMP adder to Stop
—
—
C
C
LVD adder to
stop4
—
C
1.
2.
3.
4.
—
5
12
—
3
12
—
5
128
—
3
124
—
Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
The Max current is observed at high temperature of 105 °C.
RTC adder causes IDD to increase typically by less than 1 µA; RTC clock source is 1 kHz LPO clock.
LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.
5.1.3 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components as well as MCU software
operation play a significant role in EMC performance. The system designer must consult
the following Freescale applications notes, available on freescale.com for advice and
guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
15
Switching specifications
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems
5.1.3.1
EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors for 64-pin QFP
package
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
0.15–50
14
dBμV
1, 2
VRE1
Radiated emissions voltage, band 1
VRE2
Radiated emissions voltage, band 2
50–150
15
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
3
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
4
dBμV
IEC level
0.15–1000
M
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 5.0 V, TA = 25 °C, fOSC = 10 MHz (crystal), fBUS = 20 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2 Switching specifications
5.2.1 Control timing
Table 7. Control timing
Rating
Symbol
Min
Typical1
Max
Unit
fSys
DC
—
40
MHz
—
20
MHz
1.0
1.25
KHz
—
—
ns
Num
C
1
D
System and core clock
2
P
Bus frequency (tcyc = 1/fBus)
fBus
DC
3
P
Internal low power oscillator frequency
fLPO
0.67
4
D
External reset pulse width2
textrst
1.5 ×
tcyc
5
D
6
D
Reset low drive
IRQ pulse width
Asynchronous
path2
trstdrv
34 × tcyc
—
—
ns
tILIH
100
—
—
ns
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
16
Freescale Semiconductor, Inc.

Switching specifications
Table 7. Control timing (continued)
Num
Max
Unit
1.5 × tcyc
—
—
ns
tILIH
100
—
—
ns
Synchronous path
tIHIL
1.5 × tcyc
—
—
ns
Port rise and fall time Normal drive strength
(load = 50 pF)4
—
tRise
—
10.2
—
ns
tFall
—
9.5
—
ns
Port rise and fall time high drive strength (load =
50 pF)4
—
tRise
—
5.4
—
ns
tFall
—
4.6
—
ns
Rating
D
7
D
Keyboard interrupt pulse
width
D
8
C
C
C
C

Typical1
C
Symbol
Min
Synchronous path3
tIHIL
Asynchronous
path2
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization
circuitry.
Shorter pulses may or


may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
4. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.
textrst
RESET_b pin
Figure 9. Reset timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 10. KBIPx timing
5.2.2 FTM module timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the
fastest clock that can be used as the optional external source to the timer counter. These
synchronizers operate from the current bus rate clock.
Table 8. FTM input timing
C
Function
Symbol
Min
Max
Unit
D
External clock
frequency
fTCLK
0
fBus/4
Hz
D
External clock
period
tTCLK
4
—
tcyc
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
17

Thermal specifications
Table 8. FTM input timing (continued)
C
Function
Symbol
D
External clock high
time
tclkh
D
External clock low
time
D
Input capture pulse
width
Min

Max
Unit
1.5
 —
tclkl
1.5
—
tcyc
tICPW
1.5
—
tcyc


tcyc

tTCLK
tclkh
TCLK
tclkl
Figure 11. Timer external clock
tICPW
FTMCHn
FTMCHn
tICPW
Figure 12. Timer input capture pulse
5.3 Thermal specifications
5.3.1 Thermal operating requirements
Table 9. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Notes
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + θJA x chip power dissipation
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
18
Freescale Semiconductor, Inc.
Thermal specifications
5.3.2 Thermal characteristics
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is userdetermined rather than being controlled by the MCU design. To take PI/O into account in
power calculations, determine the difference between actual pin voltage and VSS or VDD
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin
current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
Table 10. Thermal attributes
Board type
Symbo
l
Description
64
LQFP
64 QFP
44
LQFP
32
LQFP
32 QFN
Unit
Notes
Single-layer (1S)
RθJA
Thermal resistance,
junction to ambient (natural
convection)
71
61
75
86
97
°C/W
1, 2
Four-layer (2s2p)
RθJA
Thermal resistance,
junction to ambient (natural
convection)
53
47
53
57
33
°C/W
1, 3
Single-layer (1S)
RθJMA
Thermal resistance,
junction to ambient (200 ft./
min. air speed)
59
50
62
72
81
°C/W
1, 3
Four-layer (2s2p)
RθJMA
Thermal resistance,
junction to ambient (200 ft./
min. air speed)
46
41
47
51
27
°C/W
1, 3
—
RθJB
Thermal resistance,
junction to board
35
32
34
33
12
°C/W
4
—
RθJC
Thermal resistance,
junction to case
20
23
20
24
1.3
°C/W
5
—
ΨJT
Thermal characterization
parameter, junction to
package top outside center
(natural convection)
5
8
5
6
3
°C/W
6
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
19
Peripheral operating requirements and behaviors
Where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts - chip internal power
PI/O = Power dissipation on input and output pins - user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship
between PD and TJ (if PI/O is neglected) is:
PD = K ÷ (TJ + 273 °C)
Solving the equations above for K gives:
K = PD × (TA + 273 °C) + θJA × (PD)2
where K is a constant pertaining to the particular part. K can be determined by measuring
PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can
be obtained by solving the above equations iteratively for any value of TA.
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 SWD electricals
Table 11. SWD full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
5.5
V
0
20
MHz
1/J1
—
ns
20
—
ns
SWD_CLK frequency of operation
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
3
—
ns
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
20
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 11. SWD full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J11
SWD_CLK high to SWD_DIO data valid
—
35
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 13. Serial wire clock input timing
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 14. Serial wire data timing
6.2 External oscillator (OSC) and ICS characteristics
Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)
Num
C
1
C
C
Symbol
Min
Typical1
Max
Unit
Low range (RANGE = 0)
flo
31.25
32.768
39.0625
kHz
High range (RANGE = 1)
fhi
4
—
20
MHz
Characteristic
Crystal or
resonator
frequency
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)
(continued)
Num
C
2
D
3
D
4
5
Symbol
Load capacitors
Feedback
resistor
Low Frequency, Low-Power
Mode3
MΩ
Low Frequency, High-Gain
Mode
—
10
—
MΩ
High Frequency, LowPower Mode
—
1
—
MΩ
High Frequency, High-Gain
Mode
—
1
—
MΩ
—
0
—
kΩ
—
200
—
kΩ
—
0
—
kΩ
4 MHz
—
0
—
kΩ
8 MHz
—
0
—
kΩ
16 MHz
—
0
—
kΩ
—
1000
—
ms
—
800
—
ms
—
3
—
ms
—
1.5
—
ms
Series resistor High Frequency
D
Series resistor High
Frequency,
High-Gain Mode
C
C
C
Crystal start-up
time low range
= 32.768 kHz
crystal; High
range = 20 MHz
crystal4,5
Unit
—
D
C
See
Max
Note2
—
Mode3
RF
Typical1
—
Low-Power Mode 3
D
Min
C1, C2
Series resistor Low Frequency
D
D
6
Characteristic
RS
High-Gain Mode
Low-Power
Low range, low power
RS
tCSTL
Low range, high gain
High range, low power
tCSTH
High range, high gain
7
T
Internal reference start-up time
tIRST
—
20
50
µs
8
P
Internal reference clock (IRC) frequency trim
range
fint_t
31.25
—
39.0625
kHz
9
P
Internal
reference clock
frequency,
factory trimmed,
T = 25 °C, VDD = 5 V
fint_ft
—
31.25
—
kHz
10
P
DCO output
frequency range
FLL reference = fint_t, flo,
or fhi/RDIV
fdco
32
—
40
MHz
11
P
Factory trimmed
internal
oscillator
accuracy
T = 25 °C, VDD = 5 V
Δfint_ft
-0.5
—
0.5
%
12
C
Deviation of IRC
over
temperature
when trimmed
at T = 25 °C,
VDD = 5 V
Over temperature range
from -40 °C to 105°C
Δfint_t
-1
—
0.5
%
Over temperature range
from 0 °C to 105°C
Δfint_t
-0.5
—
0.5
Frequency
accuracy of
DCO output
using factory
trim value
Over temperature range
from -40 °C to 105°C
Δfdco_ft
-1.5
—
1
Over temperature range
from 0 °C to 105°C
Δfdco_ft
-1
—
1
13
C
%
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)
(continued)
Num
C
14
C
15
C
Characteristic
FLL acquisition
Symbol
Min
Typical1
Max
Unit
tAcquire
—
—
2
ms
CJitter
—
0.02
0.2
%fdco
time4,6
Long term jitter of DCO output clock
(averaged over 2 ms interval)7
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. See crystal or resonator manufacturer's recommendation.
3. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
0.
4. This parameter is characterized and not tested on each device.
5. Proper PC board layout procedures must be followed to achieve specifications.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
OSC
XTAL
EXTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 15. Typical crystal or resonator circuit
6.3 NVM specifications
This section provides details about program/erase times and program/erase endurance for
the flash and EEPROM memories.
Table 13. Flash and EEPROM characteristics
C
Characteristic
Symbol
Min1
Typical2
Max3
Unit4
D
Supply voltage for program/erase –40
°C to 105 °C
Vprog/erase
2.7
—
5.5
V
D
Supply voltage for read operation
VRead
2.7
—
5.5
V
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
Table 13. Flash and EEPROM characteristics
(continued)
1.
2.
3.
4.
C
Characteristic
Symbol
Min1
Typical2
Max3
Unit4
D
NVM Bus frequency
fNVMBUS
1
—
25
MHz
D
NVM Operating frequency
fNVMOP
0.8
1
1.05
MHz
D
Erase Verify All Blocks
tVFYALL
—
—
17338
tcyc
D
Erase Verify Flash Block
tRD1BLK
—
—
16913
tcyc
D
Erase Verify EEPROM Block
tRD1BLK
—
—
810
tcyc
D
Erase Verify Flash Section
tRD1SEC
—
—
484
tcyc
D
Erase Verify EEPROM Section
tDRD1SEC
—
—
555
tcyc
D
Read Once
tRDONCE
—
—
450
tcyc
D
Program Flash (2 word)
tPGM2
0.12
0.12
0.29
ms
D
Program Flash (4 word)
tPGM4
0.20
0.21
0.46
ms
D
Program Once
tPGMONCE
0.20
0.21
0.21
ms
D
Program EEPROM (1 Byte)
tDPGM1
0.10
0.10
0.27
ms
D
Program EEPROM (2 Byte)
tDPGM2
0.17
0.18
0.43
ms
D
Program EEPROM (3 Byte)
tDPGM3
0.25
0.26
0.60
ms
D
Program EEPROM (4 Byte)
tDPGM4
0.32
0.33
0.77
ms
D
Erase All Blocks
tERSALL
96.01
100.78
101.49
ms
D
Erase Flash Block
tERSBLK
95.98
100.75
101.44
ms
D
Erase Flash Sector
tERSPG
19.10
20.05
20.08
ms
D
Erase EEPROM Sector
tDERSPG
4.81
5.05
20.57
ms
D
Unsecure Flash
tUNSECU
96.01
100.78
101.48
ms
D
Verify Backdoor Access Key
tVFYKEY
—
—
464
tcyc
D
Set User Margin Level
tMLOADU
—
—
407
tcyc
C
FLASH Program/erase endurance TL to
TH = -40 °C to 105 °C
nFLPE
10 k
100 k
—
Cycles
C
EEPROM Program/erase endurance TL
to TH = -40 °C to 105 °C
nFLPE
50 k
500 k
—
Cycles
C
Data retention at an average junction
temperature of TJavg = 85°C after up to
10,000 program/erase cycles
tD_ret
15
100
—
years
Minimum times are based on maximum fNVMOP and maximum fNVMBUS
Typical times are based on typical fNVMOP and maximum fNVMBUS
Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
tcyc = 1 / fNVMBUS
Program and erase operations do not require any special power sources other than the
normal VDD supply. For more detailed information about program/erase operations, see
the Flash Memory Module section in the reference manual.
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.4 Analog
6.4.1 ADC characteristics
Table 14. 5 V 12-bit ADC operating conditions
Symbol
Min
Typ1
Max
Unit
Comment
VREFL
VSSA
—
VSSA
V
—
VREFH
VDDA
—
VDDA
Absolute
VDDA
2.7
—
5.5
V
—
Delta to VDD (VDD-VDDA)
ΔVDDA
-100
0
+100
mV
—
Delta to VSS (VSS-VSSA)
ΔVSSA
-100
0
+100
mV
—
Input
voltage
VADIN
VREFL
—
VREFH
V
—
Input
capacitance
CADIN
—
4.5
5.5
pF
—
Input
resistance
RADIN
—
3
5
kΩ
—
RAS
—
—
2
kΩ
External to
MCU
—
—
5
—
—
5
—
—
10
—
—
10
0.4
—
8.0
MHz
—
0.4
—
4.0
Characteri
stic
Reference
potential
Supply
voltage
Ground
voltage
Analog
source
resistance
Conditions
• Low
• High
•
•
12-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
•
•
10-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
8-bit mode
(all valid fADCK)
ADC
conversion
clock
frequency
High speed (ADLPC=0)
Low power (ADLPC=1)
fADCK
1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
R AS
z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
R ADIN
v ADIN
v AS
C AS
R ADIN
INPUT PIN
R ADIN
INPUT PIN
R ADIN
INPUT PIN
C ADIN
Figure 16. ADC input impedance equivalency diagram
Table 15. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Characteristic
Conditions
Supply current
C
Symbol
Min
Typ1
Max
Unit
T
IDDA
—
133
—
µA
T
IDDA
—
218
—
µA
T
IDDA
—
327
—
µA
T
IDDA
—
582
990
µA
ADLPC = 1
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
Supply current
Stop, reset, module
off
T
IDDA
—
0.011
1
µA
ADC asynchronous
clock source
High speed (ADLPC
= 0)
P
fADACK
2
3.3
5
MHz
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 15. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Characteristic
Conditions
C
Symbol
Low power (ADLPC
= 1)
Conversion time
(including sample
time)
Short sample
(ADLSMP = 0)
Sample time
Short sample
(ADLSMP = 0)
T
tADC
Long sample
(ADLSMP = 1)
T
tADS
Long sample
(ADLSMP = 1)
Total unadjusted
Error2
Differential NonLiniarity
ETUE
Min
Typ1
Max
1.25
2
3.3
—
20
—
—
40
—
—
3.5
—
—
23.5
—
—
±5.0
—
12-bit mode
T
10-bit mode
P
—
±1.5
±2.0
8-bit mode
T
—
±0.7
±1.0
12-bit mode
T
—
±1.0
—
10-bit mode4
DNL
P
—
±0.25
±0.5
mode4
T
—
±0.15
±0.25
Integral Non-Linearity 12-bit mode
T
—
±1.0
—
10-bit mode
T
—
±0.3
±0.5
—
±0.15
±0.25
—
±2.0
—
8-bit
INL
Unit
ADCK
cycles
ADCK
cycles
LSB3
LSB3
LSB3
8-bit mode
T
12-bit mode
C
10-bit mode
P
—
±0.25
±1.0
8-bit mode
T
—
±0.65
±1.0
12-bit mode
T
—
±2.5
—
10-bit mode
T
—
±0.5
±1.0
8-bit mode
T
—
±0.5
±1.0
Quantization error
≤12 bit modes
D
EQ
—
—
±0.5
LSB3
Input leakage error7
all modes
D
EIL
Temp sensor slope
-40 °C–25 °C
D
m
mV/°C
Zero-scale error5
Full-scale
error6
EZS
EFS
25 °C–125 °C
Temp sensor voltage 25 °C
D
VTEMP25
IIn * RAS
LSB3
LSB3
mV
—
3.266
—
—
3.638
—
—
1.396
—
V
1. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. Includes quantization
3. 1 LSB = (VREFH - VREFL)/2N
4. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
5. VADIN = VSSA
6. VADIN = VDDA
7. IIn = leakage current (refer to DC characteristics)
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
6.4.2 Analog comparator (ACMP) electricals
Table 16. Comparator electrical specifications
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Supply voltage
VDDA
2.7
—
5.5
V
T
Supply current (Operation mode)
IDDA
—
10
20
µA
D
Analog input voltage
VAIN
VSS - 0.3
—
VDDA
V
P
Analog input offset voltage
VAIO
—
—
40
mV
C
Analog comparator hysteresis (HYST=0)
VH
—
15
20
mV
C
Analog comparator hysteresis (HYST=1)
VH
—
20
30
mV
T
Supply current (Off mode)
IDDAOFF
—
60
—
nA
C
Propagation Delay
tD
—
0.4
1
µs
6.5 Communication interfaces
6.5.1 SPI switching specifications
The serial peripheral interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's reference manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
VDD and 80% VDD, unless noted, and 25 pF load on all SPI pins. All timing assumes
high-drive strength is enabled for SPI output pins.
Table 17. SPI master mode timing
Nu
m.
Symbol
Description
Min.
Max.
Unit
Comment
1
fop
fBus/2048
fBus/2
Hz
fBus is the bus
clock
2
tSPSCK
2 x tBus
2048 x tBus
ns
tBus = 1/fBus
3
tLead
Enable lead time
1/2
—
tSPSCK
—
4
tLag
Enable lag time
1/2
—
tSPSCK
—
5
tWSPSCK
6
tSU
Data setup time (inputs)
tBus – 30
1024 x tBus
ns
—
8
—
ns
—
7
tHI
Data hold time (inputs)
8
—
ns
—
8
tv
Data valid (after SPSCK edge)
—
25
ns
—
9
tHO
Data hold time (outputs)
20
—
ns
—
10
tRI
Rise time input
—
tBus – 25
ns
—
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 17. SPI master mode timing (continued)
Nu
m.
11
Symbol
Description
tFI
Fall time input
tRO
Rise time output
tFO
Fall time output
Min.
Max.
Unit
Comment
—
25
ns
—
SS1
(OUTPUT)
3
2
SPSCK
(CPOL=0)
(OUTPUT)
10
11
10
11
4
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
MISO
(INPUT)
7
MSB IN2
BIT 6 . . . 1
LSB IN
8
MOSI
(OUTPUT)
MSB OUT2
9
BIT 6 . . . 1
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI master mode timing (CPHA=0)
SS1
(OUTPUT)
2
3
SPSCK
(CPOL=0)
(OUTPUT)
5
SPSCK
(CPOL=1)
(OUTPUT)
6
MISO
(INPUT)
5
11
10
11
4
7
MSB IN2
BIT 6 . . . 1
LSB IN
9
8
MOSI
(OUTPUT)
10
PORT DATA MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI master mode timing (CPHA=1)
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
Table 18. SPI slave mode timing
Nu
m.
Symbol
Description
1
fop
2
tSPSCK
3
tLead
Enable lead time
4
tLag
Enable lag time
5
tWSPSCK
6
tSU
7
Min.
Max.
Unit
Comment
0
fBus/4
Hz
fBus is the bus clock as
defined in Control timing.
4 x tBus
—
ns
tBus = 1/fBus
1
—
tBus
—
Frequency of operation
SPSCK period
1
—
tBus
—
tBus - 30
—
ns
—
Data setup time (inputs)
15
—
ns
—
tHI
Data hold time (inputs)
25
—
ns
—
8
ta
Slave access time
—
tBus
ns
Time to data active from
high-impedance state
9
tdis
Slave MISO disable time
—
tBus
ns
Hold time to highimpedance state
10
tv
Data valid (after SPSCK edge)
—
25
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
Rise time input
—
tBus - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
13
Clock (SPSCK) high or low time
SS
(INPUT)
2
12
13
12
13
4
SPSCK
(CPOL=0)
(INPUT)
5
3
SPSCK
(CPOL=1)
(INPUT)
5
9
8
MISO
(OUTPUT)
see
note
SLAVE MSB
6
MOSI
(INPUT)
10
11
11
BIT 6 . . . 1
SLAVE LSB OUT
SEE
NOTE
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined
Figure 19. SPI slave mode timing (CPHA = 0)
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
30
Freescale Semiconductor, Inc.
Dimensions
SS
(INPUT)
4
2
3
SPSCK
(CPOL=0)
(INPUT)
5
SPSCK
(CPOL=1)
(INPUT)
5
see
note
SLAVE
8
MOSI
(INPUT)
13
12
13
11
10
MISO
(OUTPUT)
12
MSB OUT
6
9
BIT 6 . . . 1
SLAVE LSB OUT
BIT 6 . . . 1
LSB IN
7
MSB IN
NOTE: Not defined
Figure 20. SPI slave mode timing (CPHA=1)
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
Then use this document number
32-pin LQFP
98ASH70029A
32-pin QFN
98ASA00473D
44-pin LQFP
98ASS23225W
64-pin QFP
98ASB42844B
64-pin LQFP
98ASS23234W
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
31
Pinout
8 Pinout
8.1 Signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
Table 19. Pin availability by package pin-count
Pin Number
Lowest Priority <-- --> Highest
64-QFP/
LQFP
44-LQFP
32LQFP/QFN
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
1
1
1
PTD11
KBI1_P1
FTM2_CH3
SPI1_MOSI
—
KBI1_P0
FTM2_CH2
SPI1_SCK
—
2
2
2
PTD01
3
—
—
PTH7
—
—
—
—
4
—
—
PTH6
—
—
—
—
5
3
—
PTE7
—
FTM2_CLK
—
FTM1_CH1
6
4
—
PTH2
—
BUSOUT
—
FTM1_CH0
7
5
3
—
—
—
—
VDD
8
6
4
—
—
—
VDDA
VREFH2
9
7
5
—
—
—
—
VREFL
10
8
6
—
—
—
VSSA
VSS3
11
9
7
PTB7
—
I2C0_SCL
—
EXTAL
12
10
8
PTB6
—
I2C0_SDA
—
XTAL
13
11
—
—
—
—
—
VSS
14
—
—
PTH11
—
FTM2_CH1
—
—
15
—
—
PTH01
—
FTM2_CH0
—
—
16
—
—
PTE6
—
—
—
—
17
—
—
PTE5
—
—
—
—
9
PTB51
FTM2_CH5
SPI0_PCS0
ACMP1_OUT
—
FTM2_CH4
SPI0_MISO
NMI
ACMP1_IN2
—
—
ADC0_SE11
18
12
19
13
10
PTB41
20
14
11
PTC3
FTM2_CH3
21
15
12
PTC2
FTM2_CH2
—
—
ADC0_SE10
22
16
—
PTD7
KBI1_P7
UART2_TX
—
—
23
17
—
PTD6
KBI1_P6
UART2_RX
—
—
24
18
—
PTD5
KBI1_P5
—
—
—
25
19
13
PTC1
—
FTM2_CH1
—
ADC0_SE9
26
20
14
PTC0
—
FTM2_CH0
—
ADC0_SE8
27
—
—
PTF7
—
—
—
ADC0_SE15
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
32
Freescale Semiconductor, Inc.
Pinout
Table 19. Pin availability by package pin-count (continued)
Pin Number
Lowest Priority <-- --> Highest
64-QFP/
LQFP
44-LQFP
32LQFP/QFN
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
28
—
—
PTF6
—
—
—
ADC0_SE14
29
—
—
PTF5
—
—
—
ADC0_SE13
30
—
—
PTF4
—
—
—
ADC0_SE12
31
21
15
PTB3
KBI0_P7
SPI0_MOSI
FTM0_CH1
ADC0_SE7
32
22
16
PTB2
KBI0_P6
SPI0_SCK
FTM0_CH0
ADC0_SE6
33
23
17
PTB1
KBI0_P5
UART0_TX
—
ADC0_SE5
34
24
18
PTB0
KBI0_P4
UART0_RX
—
ADC0_SE4
35
—
—
PTF3
—
—
—
—
36
—
—
PTF2
—
—
—
—
37
25
19
PTA7
—
FTM2_FLT2
ACMP1_IN1
ADC0_SE3
38
26
20
PTA6
—
FTM2_FLT1
ACMP1_IN0
ADC0_SE2
39
—
—
PTE4
—
—
—
—
40
27
—
—
—
—
—
VSS
41
28
—
—
—
—
—
VDD
42
—
—
PTF1
—
—
—
—
43
—
—
PTF0
—
—
—
—
44
29
—
PTD4
KBI1_P4
—
—
—
45
30
21
PTD3
KBI1_P3
SPI1_PCS0
—
—
46
31
22
PTD2
KBI1_P2
SPI1_MISO
—
—
23
PTA34
KBI0_P3
UART0_TX
I2C0_SCL
—
KBI0_P2
UART0_RX
I2C0_SDA
—
47
32
48
33
24
PTA24
49
34
25
PTA1
KBI0_P1
FTM0_CH1
ACMP0_IN1
ADC0_SE1
50
35
26
PTA0
KBI0_P0
FTM0_CH0
ACMP0_IN0
ADC0_SE0
51
36
27
PTC7
—
UART1_TX
—
—
52
37
28
PTC6
—
UART1_RX
—
—
53
—
—
PTE3
—
SPI0_PCS0
—
—
54
38
—
PTE2
—
SPI0_MISO
—
—
55
—
—
PTG3
—
—
—
—
56
—
—
PTG2
—
—
—
—
57
—
—
PTG1
—
—
—
—
58
—
—
PTG0
—
—
—
—
59
39
—
PTE11
—
SPI0_MOSI
—
—
60
40
—
PTE01
—
SPI0_SCK
FTM1_CLK
—
61
41
29
PTC5
—
FTM1_CH1
—
RTCO
62
42
30
PTC4
RTCO
FTM1_CH0
ACMP0_IN2
SWD_CLK
63
43
31
PTA5
IRQ
FTM0_CLK
—
RESET
64
44
32
PTA4
—
ACMP0_OUT
—
SWD_DIO
1. This is a high-current drive pin when operated as output.
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
33
Pinout
2. VREFH and VDDA are internally connected.
3. VSSA and VSS are internally connected.
4. This is a true open-drain pin when operated as output.
Note
When an alternative function is first enabled, it is possible to
get a spurious edge to the module. User software must clear any
associated flags before interrupts are enabled. Table 19
illustrates the priority if multiple modules are enabled. The
highest priority module will have control over the pin. Selecting
a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority
module. Disable all modules that share a pin before enabling
another module.
PTE3
PTC6
PTC7
PTA0
PTA1
52
51
50
49
PTE2
PTG1
57
54
PTG0
58
53
PTE11
59
PTG2
PTE01
PTG3
PTC5
60
55
PTC4
62
61
56
PTA4
PTA5
64
63
8.2 Device pin assignment
PTD1 1
1
48
PTA22
PTD0 1
2
47
PTA32
PTD2
PTH7
3
46
PTH6
4
45
PTD3
PTE7
5
44
PTD4
PTH2
VDD
6
43
PTF0
7
42
PTF1
VDDA/VREFH
VREFL
VSSA/VSS
8
41
VDD
9
40
VSS
10
39
PTE4
PTA6
PTB7
PTB6
11
38
12
37
PTA7
VSS
13
36
PTF2
27
28
29
PTF7
PTF6
PTF5
32
26
PTC0
PTB2
25
PTC1
31
24
PTD5
30
23
PTD6
PTF4
22
PTD7
PTB3
21
PTC2
PTB1
19
33
20
16
PTB4 1
PTC3
PTB0
PTE6
17
PTF3
34
18
35
15
PTE5
14
PTB5 1
PTH11
PTH01
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 21. 64-pin QFP/LQFP packages
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
34
Freescale Semiconductor, Inc.
PTC6
PTC7
PTA0
PTA1
36
35
34
PTE2
38
37
PTE01
PTE11
PTC5
41
39
PTC4
42
40
PTA4
PTA5
43
44
Pinout
PTB0
23
PTB1
22
24
11
21
10
VSS
PTB2
PTA7
PTB3
PTA6
PTB7
PTB6
20
26
25
PTC0
8
9
19
VSS
18
VDD
27
PTC1
28
7
PTD5
6
VREFL
VSSA/VSS
17
PTD4
PTD6
29
16
5
PTD7
PTD3
VDD
VDDA/VREFH
15
30
14
4
PTC2
PTH2
PTC3
3
31
PTA32
PTE7
13
PTA22
32
12
33
2
PTB5 1
1
PTD0 1
PTB4 1
PTD1 1
PTD2
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
PTC6
PTA0
PTA1
26
25
PTC5
29
PTC7
PTC4
30
28
PTA5
31
27
PTA4
32
Figure 22. 44-pin LQFP package
PTD1 1
1
24
PTA22
PTD0 1
2
23
PTA32
VDD
VDDA/VREFH
3
22
PTD2
4
21
PTD3
13
14
15
16
PTB3
PTB2
PTB1
PTC0
17
PTC1
8
11
PTB0
PTB6
12
PTA7
18
PTC3
19
7
PTC2
6
PTB7
10
PTA6
PTB4 1
20
9
5
PTB5 1
VREFL
VSSA/VSS
1. High source/sink current pins
2. True open drain pins
Figure 23. 32-pin LQFP package
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
Freescale Semiconductor, Inc.
35
PTD1 1
PTC6
PTC7
PTA0
PTA1
26
25
PTC5
29
27
PTC4
30
28
PTA4
PTA5
32
31
Revision history
24
PTA22
2
23
PTA32
3
22
PTD2
1
16
PTB2
PTB1
15
17
PTB3
8
14
PTB0
PTB6
PTC0
PTA7
18
13
19
7
12
6
PTB7
PTC2
PTA6
PTC1
20
11
5
PTC3
PTD3
VREFL
VSSA/VSS
9
21
10
4
PTB5 1
VDD
VDDA/VREFH
PTB4 1
PTD0 1
1. High source/sink current pins
2. True open drain pins
Figure 24. 32-pin QFN package
9 Revision history
The following table provides a revision history for this document.
Table 20. Revision history
Rev. No.
Date
2
3/2014
3
10/2014
Substantial Changes
Initial public release.
•
•
•
•
•
•
•
•
•
Added new package of 32-pin QFN information
Updated pin-out
Updated key features of UART, KBI and ADC in the front page
Added a note to the Max. in Supply current characteristics
Updated footnote fOSC = 10 MHz (crystal) in EMC radiated
emissions operating behaviors
Added a new section of Thermal operating requirements
Updated NVM specifications
Added reference potential in ADC characteristics
Updated to "All timing assumes high-drive strength is enabled for
SPI output pins." in SPI switching specifications
KE02 Sub-Family Data Sheet, Rev3, 10/2014.
36
Freescale Semiconductor, Inc.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
customer's technical experts. Freescale does not convey any license
under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found
at the following address: freescale.com/SalesTermsandConditions.
Freescale, the Freescale logo, and Kinetis are trademarks of Freescale
Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or
service names are the property of their respective owners. ARM and
Cortex-M0+ are the registered trademarks of ARM Limited.
©2013-2014 Freescale Semiconductor, Inc.
Document Number MKE02P64M40SF0
Revision 3, 10/2014