SPICE Device Model Si4736DY Vishay Siliconix N-Channel 30-V (D-S) MOSFET With Schottky Diode CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71012 S-51870⎯Rev. B, 12-Sep-05 www.vishay.com 1 SPICE Device Model Si4736DY Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Condition Simulated Data Measured Data VGS(th) VDS = VGS, ID = 250 μA 1.1 ID(on) VDS ≥ 5 V, VGS = 10 V 596 VGS = 10 V, ID = 13 A 0.0079 0.0070 VGS = 4.5 V, ID = 12 A 0.0090 0.0083 Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistancea Forward Transconductancea Schottky Diode Forward Voltagea rDS(on) gfs VSD V A VDS = 15 V, ID = 13 A 62 56 IS = 3 A, VGS = 0 V 0.76 0.495 IS = 3 A, VGS = 0 V, TJ = 125°C 0.61 0.43 37 37 VDS = 15 V, VGS = 4.5 V, ID = 13 A 10 10 Ω S V Dynamicb Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd 8.8 8.8 Turn-On Delay Time td(on) 17 17 tr 6 14 83 102 37 26 34 42 Rise Time Turn-Off Delay Time td(off) Fall Time tf Source-Drain Reverse Recovery Time trr VDD = 15 V, RL = 15 Ω ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω IF = 3 A, di/dt = 100 A/μs nC ns Notes a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 71012 S-51870⎯Rev. B, 12-Sep-05 SPICE Device Model Si4736DY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 71012 S-51870⎯Rev. B, 12-Sep-05 www.vishay.com 3