SRDA3.3-6 Datasheet

SRDA3.3-6 and SRDA05-6
RailClamp
Low Capacitance TVS Diode Array
PROTECTION PRODUCTS
Description
Features
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. The SR series has
been specifically designed to protect sensitive components which are connected to data and transmission
lines from overvoltage caused by electrostatic discharge (ESD), electrical fast transients (EFT), and
lightning.
The unique design of the SRDA series devices incorporates surge rated, low capacitance steering diodes and
a TVS diode in a single package. During transient
conditions, the steering diodes direct the transient to
either the positive side of the power supply line or to
ground. The internal TVS diode prevents over-voltage
on the power line, protecting any downstream components.
The low capacitance array configuration allows the user
to protect six high-speed data or transmission lines.
The low inductance construction minimizes voltage
overshoot during high current surges.
‹ Transient protection for high-speed data lines to
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IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 24A (8/20µs)
Array of surge rated diodes with internal TVS diode
Protects six I/O lines and power supply line
Low capacitance (<15pF) for high-speed interfaces
Low operating & clamping voltages
Solid-state technology
Mechanical Characteristics
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JEDEC SO-8 package
UL 497B listed
Molding compound flammability rating: UL 94V-0
Marking : Part number, date code, logo
Packaging : Tube or Tape and Reel
Applications
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Circuit Diagram
USB Power & Data Line Protection
T1/E1 secondary IC Side Protection
Token Ring
HDSL, SDSL secondary IC Side Protection
Video Line Protection
Microcontroller Input Protection
Base stations
I2C Bus Protection
Schematic and PIN Configuration
I/O 1 1
8
GND
I/O 2 2
7
I/O 6
+VREF 3
6
I/O 5
I/O 3 4
5
I/O 4
S0-8 (Top View)
Revision 01/15/08
1
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SRDA3.3-6 and SRDA05-6
PROTECTION PRODUCTS
Absolute Maximum Rating
Rating
Symbol
Value
Units
Peak Pulse Power (tp = 8/20µs)
Pp k
500
Watts
Peak Forward Voltage (IF = 1A, tp=8/20µs)
VFP
1.5
V
Lead Soldering Temperature
TL
260 (10 sec.)
°C
Operating Temperature
TJ
-55 to +125
°C
TSTG
-55 to +150
°C
Storage Temperature
Electrical Characteristics
SR DA3.3-6
Parameter
Reverse Stand-Off Voltage
Symbol
Conditions
Minimum
Typical
VRWM
Maximum
Units
3.3
V
Punch-Through Voltage
V PT
IPT = 2µA
3.5
V
Snap-Back Voltage
VSB
ISB = 50mA
2.8
V
Reverse Leakage Current
IR
VRWM = 3.3V, T=25°C
1
µA
Clamping Voltage
VC
IPP = 1A, tp = 8/20µs
5.3
V
Clamping Voltage
VC
IPP = 10A, tp = 8/20µs
10
V
Clamping Voltage
VC
IPP = 25A, tp = 8/20µs
15
V
Peak Pulse Current
IP P
tp = 8/20µs
25
A
Junction Capacitance
Cj
Between I/O pins and
Ground
VR = 0V, f = 1MHz
8
15
pF
Between I/O pins
VR = 0V, f = 1MHz
4
pF
Note:
(1) The SRDA3.3-6 is constructed using Semtech’s proprietary EPD process technology. See applications section for
more information.
 2008 Semtech Corp.
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SRDA3.3-6 and SRDA05-6
PROTECTION PRODUCTS
Electrical Characteristics (continued)
SR DA05-6
Parameter
Symbol
Conditions
Minimum
Typical
Maximum
Units
5
V
Reverse Stand-Off Voltage
VRWM
Reverse Breakdown Voltage
V BR
It = 1mA
Reverse Leakage Current
IR
VRWM = 5V, T=25°C
10
µA
Clamp ing Voltage
VC
IPP = 1A, tp = 8/20µs
9.8
V
Clamp ing Voltage
VC
IPP = 10A, tp = 8/20µs
12
V
Clamp ing Voltage
VC
IPP = 25A, tp = 8/20µs
20
V
Peak Pulse Current
IP P
tp = 8/20µs
25
A
Junction Cap acitance
Cj
Between I/O p ins and
Ground
VR = 0V, f = 1MHz
8
15
pF
Between I/O p ins
VR = 0V, f = 1MHz
4
 2008 Semtech Corp.
3
6
V
pF
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SRDA3.3-6 and SRDA05-6
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
Power Derating Curve
10
110
% of Rated Power or PI P
Peak Pulse Power - Ppk (kW)
100
1
0.1
90
80
70
60
50
40
30
20
10
0
0.01
0.1
1
10
100
0
1000
25
50
125
150
16
110
Waveform
Parameters:
tr = 8µs
td = 20µs
90
80
70
-t
e
60
50
40
SRDA05-6
14
Clamping Voltage - VC (V)
100
Percent of IPP
100
Clamping Voltage vs. Peak Pulse Current
Pulse Waveform
td = IPP/2
30
20
12
10
SRDA3.3-6
8
6
Waveform
Parameters:
tr = 8µs
td = 20µs
4
2
10
0
0
0
5
10
15
20
25
0
30
5
10
15
20
25
30
Peak Pulse Current - IPP (A)
Time (µs)
Variation of Capacitance vs. Reverse Voltage
Forward Voltage vs. Forward Current
0
10
9
Forward Voltage - VF (V)
-2
% Change in Capacitance
75
Ambient Temperature - TA (oC)
Pulse Duration - tp (µs)
-4
-6
-8
-10
-12
8
7
6
5
4
3
Waveform
Parameters:
tr = 8µs
td = 20µs
2
1
-14
0
1
2
3
4
5
0
6
0
Reverse Voltage - VR (V)
 2008 Semtech Corp.
5
10
15
20
25
30
35
40
45
50
Forward Current - IF (A)
4
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SRDA3.3-6 and SRDA05-6
PROTECTION PRODUCTS
Applications Information
Data Line Protection Using Internal TVS Diode as
Reference
Device Connection Options for Protection of Six HighSpeed Lines
The SRDA TVS is designed to protect four data lines
from transient overvoltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode VF) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 1, 2, 4, 5, 6 and 7.
The negative reference is connected at pin 8. These
pins should be connected directly to a ground plane on
the board for best results. The path length is kept as
short as possible to minimize parasitic inductance.
The positive reference is connected at pins 2 and 3.
In the case of the SRDA3.3-6, pins 2 and 3 are
connected internally to the cathode of the low voltage
TVS. It is not recommended that these pins be directly
connected to a DC source greater than the snap-back
votlage (VSB) as the device can latch on as described
below.
EPD TVS IV Characteristic Curve
IPP
EPD TVS Characteristics
These devices are constructed using Semtech’s
proprietary EPD technology. By utilizing the EPD technology, the SRDA3.3-6 can effectively operate at 3.3V
while maintaining excellent electrical characteristics.
ISB
IPT
VBRR
VRWM
The EPD TVS employs a complex nppn structure in
contrast to the pn structure normally found in traditional silicon-avalanche TVS diodes. Since the EPD
TVS devices use a 4-layer structure, they exhibit a
slightly different IV characteristic curve when compared
to conventional devices. During normal operation, the
device represents a high-impedance to the circuit up to
the device working voltage (VRWM). During an ESD
event, the device will begin to conduct and will enter a
low impedance state when the punch through voltage
(VPT) is exceeded. Unlike a conventional device, the low
voltage TVS will exhibit a slight negative resistance
characteristic as it conducts current. This characteristic aids in lowering the clamping voltage of the device,
but must be considered in applications where DC
voltages are present.
VSB VPT VC
IBRR
curve by the snap-back voltage (VSB) and snap-back
current (ISB). To return to a non-conducting state, the
current through the device must fall below the ISB
(approximately <50mA) and the voltage must fall below
the VSB (normally 2.8 volts for a 3.3V device). If a 3.3V
TVS is connected to 3.3V DC source, it will never fall
below the snap-back voltage of 2.8V and will therefore
stay in a conducting state.
When the TVS is conducting current, it will exhibit a
slight “snap-back” or negative resistance characteristics due to its structure. This point is defined on the
 2008 Semtech Corp.
IR
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SRDA3.3-6 and SRDA05-6
PROTECTION PRODUCTS
Applications Information (continued)
approximation, the clamping voltage due to the characteristics of the protection diodes is given by:
V =V +V
C
CC
F
(for positive duration pulses)
= Descriptions
-V
(for negative duration pulses)
V
PIN
C
F
However, for fast rise time transient events, the
effects of parasitic inductance must also be considered as shown in Figure 2. Therefore, the actual
clamping voltage seen by the protected circuit will be:
V = V + V + L di
C
CC
F
V = -V - L di
C
F
G
P
ESD
/dt
ESD
/dt (for positive duration pulses)
Figure 1 - “Rail-To-Rail” Protection Topology
(First Approximation)
(for negative duration pulses)
ESD current reaches a peak amplitude of 30A in 1ns
for a level 4 ESD contact discharge per IEC 1000-4-2.
Therefore, the voltage overshoot due to 1nH of series
inductance is:
V = L di
P
ESD
/dt = 1X10-9 (30 / 1X10-9) = 30V
Example:
Consider a V = 5V, a typical V of 30V (at 30A) for the
CC
F
steering diode and a series trace inductance of 10nH.
The clamping voltage seen by the protected IC for a
positive 8kV (30A) ESD pulse will be:
Figure 2 - The Effects of Parasitic Inductance When
Using Discrete Components to Implement Rail-To-Rail
Protection
V = 5V + 30V + (10nH X 30V/nH) = 335V
C
This does not take into account that the ESD current is
directed into the supply rail, potentially damaging any
components that are attached to that rail. Also note
the high V of the discrete diode. It is not uncommon
F
for the V of discrete diodes to exceed the damage
F
threshold of the protected IC. This is due to the
relatively small junction area of typical discrete components. It is also possible that the power dissipation
capability of the discrete diode will be exceeded, thus
destroying the device.
The RailClamp is designed to overcome the inherent
disadvantages of using discrete signal diodes for ESD
suppression. The RailClamp’s integrated TVS diode
helps to mitigate the effects of parasitic inductance in
the power supply connection. During an ESD event,
 2008 Semtech Corp.
Figure 3 - Rail-To-Rail Protection Using
RailClamp TVS Arrays
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SRDA3.3-6 and SRDA05-6
PROTECTION PRODUCTS
Applications Information (continued)
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
the current will be directed through the integrated TVS
diode to ground. The total clamping voltage seen by
the protected IC due to this path will be:
V =V
C
F(RailClamp)
+V
TVS
This is given in the data sheet as the rated clamping
voltage of the device. For an SRDA05-6 the typical
clamping voltage is <16V at I =30A. The diodes
PP
internal to the RailClamp are low capacitance, fast
switching devices that are rated to handle high transient currents and maintain excellent forward voltage
characteristics.
Using the RailClamp does not negate the need for good
board layout. All other inductive paths must be considered. The connection between the positive supply and
the SRDA and from the ground plane to the SRDA
must be kept as short as possible. The path between
the SRDA and the protected line must also be minimized. The protected lines should be routed directly to
the SRDA. Placement of the SRDA on the PC board is
also critical for effective ESD protection. The device
should be placed as close as possible to the input
connector. The reason for this is twofold. First,
inductance resists change in current flow. If a significant inductance exists between the connector and the
TVS, the ESD current will be directed elsewhere (lower
resistance path) in the system. Second, the effects of
radiated emissions and transient coupling can cause
upset to other areas of the board even if there is no
direct path to the connector. By placing the TVS close
to the connector it will divert the ESD current immediately and absorb the ESD energy before it can be
coupled into nearby traces.
(Reference Semtech application note SI99-01 for
further information on board layout)
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small compared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
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SRDA3.3-6 and SRDA05-6
PROTECTION PRODUCTS
Outline Drawing - SO-8
A
h
D
e
N
h
H
2X E/2
E1 E
1
A
A1
A2
b
c
D
E1
E
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h
L
L1
N
01
aaa
bbb
ccc
c
GAGE
PLANE
2
0.25
ccc C
2X N/2 TIPS
DIM
L
(L1)
e/2
DETAIL
B
01
A
D
aaa C
SEATING
PLANE
A2 A
C
A
.053
.069
.004
.010
.049
.065
.012
.020
.010
.007
.189 .193 .197
.150 .154 .157
.236 BSC
.050 BSC
.010
.020
.016 .028 .041
(.041)
8
8°
0°
.004
.010
.008
1.75
1.35
0.10
0.25
1.25
1.65
0.31
0.51
0.17
0.25
4.80 4.90 5.00
3.80 3.90 4.00
6.00 BSC
1.27 BSC
0.25
0.50
0.40 0.72 1.04
(1.04)
8
0°
8°
0.10
0.25
0.20
SIDE VIEW
A1
bxN
bbb
SEE DETAIL
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
C A-B D
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-012, VARIATION AA.
Land Pattern - SO-8
X
DIM
(C)
G
C
G
P
X
Y
Z
Z
Y
DIMENSIONS
INCHES
MILLIMETERS
(.205)
.118
.050
.024
.087
.291
(5.20)
3.00
1.27
0.60
2.20
7.40
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 300A.
 2008 Semtech Corp.
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SRDA3.3-6 and SRDA05-6
PROTECTION PRODUCTS
Ordering Information
Part Number
Lead Finish
Qty/Pkg
Reel Size
SRDA3.3-6.TB
SnPb
500/Reel
7 Inch
SRDA05-6.TB
SnPb
500/Reel
7 Inch
SRDA3.3-6.TBT
Pb free
500/Reel
7 Inch
SRDA05-6.TBT
Pb free
500/Reel
7 Inch
SRDA3.3-6
SnPb
95/Tube
N/A
SRDA05-6
SnPb
95/Tube
N/A
SRDA3.3-6.T
Pb free
95/Tube
N/A
SRDA05-6.T
Pb free
95/Tube
N/A
Note: Lead-free devices are RoHS/WEEE Compliant
Contact Information
Semtech Corporation
Protection Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
 2008 Semtech Corp.
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