"Through Silicon Via (TSV) Product Technology Presentation" - Presented to the IMAPS N. California Chapter on February 1, 2012

Through Silicon Via (TSV) Product Technology
IMAPS North California Chapter
R. Huemoeller
SVP, Adv. 3DIC Platform Develop
February 1, 2012
Agenda
• Product Offerings & Timing
• Wafer Processing Challenges & Solutions
• Assembly Challenges & Solutions
• Reliability & Future
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
2
R.Huemoeller Feb-12
Industry TSV Product Roadmap
“Drivers and Timing”
© 2012 Amkor Technology, Inc.
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3
R.Huemoeller Feb-12
Stacked CSP (SCSP) – Migration
Migration to TSV
Performance Driven
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
4
R.Huemoeller Feb-12
FCBGA – Migration
Migration to TSV
Performance & Cost Driven
© 2012 Amkor Technology, Inc.
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R.Huemoeller Feb-12
TSV Product Segments
• 3D Vertical Stacking
─ Memory and Application Processor Driven
─ Today CSP focused on 28nm CMOS… scaling to 20/22nm
─ Application Processors almost exclusively moving to pre-finished wafer process
flows
• 2.5D Interposer – Side by Side Stacking
─ Network, GPU and CPU driven
─ All large package body focused
─ All large silicon interposer focused (near retical size)
─ Both wafer finishing and pre-finished wafer process flows being used
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
6
R.Huemoeller Feb-12
TSV Wafer Logistics
Wafer Finish –
Can be at either
Foundry or
OSAT
Customer Preferred Path
All Amkor customers endorsing this path now
© 2012 Amkor Technology, Inc.
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R.Huemoeller Feb-12
2.5D TSV Product Opportunities
New !!
Logic 1
Monolithic
SOC
Type 1
Monolithic
SOC
Type 2
Analog
Cache
Logic
1
Cache
Logic
2
Analog
Logic
Logic
Logic
Logic
Multi-Die
Interposer
SOC
Logic 2
Logic 1
Logic 1 Logic 2
Multi-Die
Interposer
SOC
Logic
•
Focus process node development on specific application functionalities
•
Reduces complexity and mask layer count of process node
•
Reduces advanced process node ‘Time to Market’
•
Improves wafer yield
•
Reduces wafer start cost
•
Improves performance, power, and area of each application functionality
© 2012 Amkor Technology, Inc.
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8
R.Huemoeller Feb-12
System
Level
Reduction
Gate to
Gate
Routing
between
Die
Deconstruct
into
Smaller Die
Fab Yield
Improve
= Cost
Reduction
Departition
(e-DRAM)
System
Level
Reduction
Top Die
Cost
Departition
Fewer
SoC Layers
Reduction in
Fab Yield
Wide
Parallel
Busses
Stress
Lower Power
Speed
Memory Bus
Primary Drivers for Interposers
Si InterpT + DDRT + Logic
Wide
Parallel
Busses
Si InterpT + Logic
Si InterpT + Logic + SERDES
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
9
R.Huemoeller Feb-12
TSV Production Intercepts
Si InterpT + DDR3T + Logic
Interposer Required
GPU, CPU (28nm)
Apps ProcessorT + SDR
Interposer Required for some platforms
Smart Phone / Tablet (28nm)
Memory (DDRT)
Server, Custom Mem.
45 & 32nm
Si InterposerT + Logic
Interp. Req’d
ASIC, FPGA (28nm)
RFPA’s & Image Sensors
Production
Since 2010
2012
2012
2013
2014
2015
Die with TSV indicated by = T
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
10
R.Huemoeller Feb-12
TSV Consortia Activity
• Thin Wafer Handling
─ 3DIC task force to accommodate pre-finished wafer flow
─ Momentum & activity slowing significantly
• Test and Design
─ Design :
•
GSA EDA consortia
─ Test : Mitigate downstream loss of ‘Bill of Materials’
•
3D CSP products : Interim test after logic to substrate assembly
•
2.5D Interposer products : Interim test after logic to interposer assembly
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
11
R.Huemoeller Feb-12
TSV Wafer & Assembly Challenges
© 2012 Amkor Technology, Inc.
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R.Huemoeller Feb-12
TSV Product Challenges
Technology Integration
Micro Copper
Pillar Bumping
Thermal
Micro Joining
Silico
n
Interposer
Substrate
Underfill
Thin Wafer
Handling
Interposer Thinning
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
Subassembly
&
Package
Warpage
13
R.Huemoeller Feb-12
General TSV Processing
Foundry / IDM
Wafer Fabrication
Front Side
Wafer Finish
B a ck Side
Ba
W
Wafer
Finish
a
ss
Assembly
A
“P”
“M”
“M”
High Volume
Production
Development
‘Prototype Capable’
Development
‘Prototype Capable’
"P" High Volume Production Capable
Production Rel qual passed, CpK >= 1.3
Production
Readiness
"L" Limited Production Capable
Eng supervision req'd ; Eng, Rel Data = pass
"M" Prototype Capable
Eng supervision req'd ; Process under develop, Limited Rel Data
"H" High Risk / No Capability
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
14
R.Huemoeller Feb-12
TSV Wafer Finishing Challenges
“MEOL (middle end of line)”
© 2012 Amkor Technology, Inc.
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R.Huemoeller Feb-12
Wafer Finishing of TSV Devices
•
Back Side of Wafer Processing
– Equipment required includes :
1. Wafer thickness measurement device
2. 300mm Wafer Support tools (200mm for some markets)
»
Bond and De-bond
3. Wafer back grind equipment
4. Wafer back side silicon etch tools
5. Organic or Inorganic passivation capability
6. CMP tools
7. Wafer Sputtering tools
8. Nickel-gold and/or SnPb / SnAg bump capability
– Ability to handle varying TSV wafer quality
– Ability to thin to 50µm
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
16
R.Huemoeller Feb-12
Wafer Finishing of TSV Devices, cont.
• Formation of Back-side / Front-side µBumps
– Most development focused at 40µm pitch today
– 30µm pitch in some cases
– 20µm pitch requires stepper (registration) & high speed photoresist (resolution)
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
17
R.Huemoeller Feb-12
Wafer Finishing of TSV Devices, cont.
• 200/300mm Thin Wafer Support System
– Bond up to 40µm front side µbumps in adhesives
Requires excellent TTV at < 2µm
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
18
R.Huemoeller Feb-12
Wafer Finishing of TSV Devices, cont.
• TSV Reveal, Isolation and Organic Passivation
– Key : No damage to silicon, liner or tip
– Critical : No copper residue on surface via TOF Sims
Grind – Expose TSV
Ni – Au on Copper Via
Silicon Etch Recess
© 2012 Amkor Technology, Inc.
Business
Proprietary
Amkor InfoAmkor
for Controlled
Release
at IMAPS North
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R.Huemoeller Feb-12
Wafer Finishing of TSV Devices, cont.
• TSV Reveal, Isolation and Inorganic Passivation
– Key : No damage to silicon, liner or tip
– Critical : No copper residue on surface via TOF Sims
PRE CMP
© 2012 Amkor Technology, Inc.
POLISH A
POLISH B
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R.Huemoeller Feb-12
Liner Intact
Organic
Passivation
© 2012 Amkor Technology, Inc.
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R.Huemoeller Feb-12
Wafer Finishing of TSV Devices, cont.
• 200/300mm Thin Wafer Handling – De-bonding
– De-bonding wafers with large C4 bumps on back side
Can be very challenging
– No wafer breakage, bump deformation or foreign material
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
22
R.Huemoeller Feb-12
TSV Assembly Challenges
“Die Stacking”
© 2012 Amkor Technology, Inc.
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R.Huemoeller Feb-12
Top TSV Assembly Challenges
•
Die-Die / Die-Substrate Joining
– Micro bump uniformity ; Method of Join ; Materials
•
Die-Die X-Y Spacing
– Underfill fillet sizes and pad metallurgy
– Process assy sequence ; Micro-join method & Mat’ls
•
Assembly
Process Flexibility
is
REQUIRED
Thermal, Power Management & Reliability
– Use of Lids, Stiffeners & Passives
– Underfill & adhesive material compatibility
•
Warpage Control
Die to Die
Die to Substrate
Die to Wafer
– Interposer, Substrate & Top Die warpage
– Die area density / distribution at each level
•
Intermediate e-Test Points
– Process assembly sequence
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
24
R.Huemoeller Feb-12
Assembly of TSV Devices
•
Joining Technology
– Compression technology provides many advantages over mass reflow
– Mass reflow begins to reach limit at 40µm pitch due to shorting potential
– White bump (high-K dielectric layer delamination) eliminated with TC Bonding
Bump Pitch
50um
40um
30um
20um
Bonding
Method
Reflow
Reflow/
Compression Compression
Compression
Bump
Structure
Solder
Cu-Solder
2010
Process
2012
2012
Cu-Solder
2013
Chip to Substrate ( Organic / Si interposer)
Chip to Chip
© 2012 Amkor Technology, Inc.
Cu-Solder
Chip to Wafer
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R.Huemoeller Feb-12
TSV CSP Vertical Assembly
• Thermo-Compression Bond + Non Conductive Paste (NCP)
– Thin die handling capability to 50µm
– Material dispense critical
Chip
Chip
Pitch ≥ 40µm today ; 30µm future
Pillar to NiNi-Au Pad as standard
© 2012 Amkor Technology, Inc.
Cu Pillar with SnAg µBumps
40
40µm today
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R.Huemoeller Feb-12
TSV Silicon Interposer Assembly
•
Assembly Experience on Interposer
– Substrates range from 35mm up to 90mm / side
– Interposer thickness as thin as 60um, but
typically at100um
GPU
DRAM
DRAM
Chip
Chip
Pitch ≥ 40µm today ; 35µm 2012
© 2012 Amkor Technology, Inc.
80µm Tall Plated SnAg Bumps
Pitch ≥ 150µm today ; ≥ 130µm 2012
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R.Huemoeller Feb-12
TSV Product Reliability & Future
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
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R.Huemoeller Feb-12
TSV Product Reliability Data – General
• 2.5D TSV – FCBGA (die to die = face to face)
– Multiple Die on Interposer ; 100µm thick, 10µm TSV at 210µm pitch
– Logic at 40µm pitch µbump with 25µm dia. ; over 200k micro-bumps
– Passed Level 4 MRT ; TC Condition B 1000 cycles ; HTS 1000 hrs
and HAST 110C, 85% RH, 500 Hours
• 3D TSV – CSP (die to die = face to back)
– Memory ~ 100µm thick
– Logic ~ 50µm thick with 10µm TSV at 40um pitch ; either peripheral or
area array bump pitch to substrate
– Passed MRT L3 260’C (3x reflow) ; T/C-B 1000 cycles ; HTS 1000 hrs
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
29
R.Huemoeller Feb-12
TSV Product Future is ‘Very Bright’
•
Form Factor Improvement
•
Reduces Complexity
Reduces mask layer count of process node
Reduces advanced process node ‘Time to Market’
Improves wafer yield
Reduces wafer start cost
•
Improves Performance & Reduces Power Requirement
© 2012 Amkor Technology, Inc.
Amkor Info for Controlled Release at IMAPS North
30
R.Huemoeller Feb-12
Thank You!
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