IDT ICS9E4101

DATASHEET
Programmable Timing Control HubTM for Intel Systems
Features/Benefits:
•
Supports tight ppm accuracy clocks for Serial-ATA and
PCI-Express
•
Supports spread spectrum modulation, 0 to -0.5%
down spread
Recommended Application:
I-temp CK410 clock, Intel Yellow Cover part
Output Features:
•
2 - 0.7V current-mode differential CPU pairs
•
6 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
•
1 - 0.7V current-mode differential CPU/SRC selectable
pair
•
6 - PCI (33MHz)
•
3 - PCICLK_F, (33MHz) free-running
•
1 - USB, 48MHz
•
1 - DOT, 96MHz, 0.7V current differential pair
•
1 - REF, 14.318MHz
2
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CPU
MHz
266.66
133.33
200.00
SRC
MHz
100.00
100.00
100.00
100.00
100.00
PCI
REF
MHz
MHz
33.33
14.318
33.33
14.318
33.33
14.318
RESERVED
RESERVED
33.33
14.318
RESERVED
RESERVED
USB
MHz
48.00
48.00
48.00
DOT
MHz
96.00
96.00
96.00
48.00
96.00
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
Supports undriven differential CPU, SRC pair in PD#
for power management.
1. FS_C is a three-level input. Please see V IL_FS and V IH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_B and FS_A are low-threshold inputs. Please see the V IL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ICS9E4101
0
0
0
0
1
1
1
1
2
FS_B FS_A
Supports CPU clks up to 400MHz
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
ITP_EN/PCICLK_F0
PCICLK_F1
PCICLK_F2
VDD48
USB_48MHz
GND
DOTT_96MHz
DOTC_96MHz
FS_B/TEST_MODE
Vtt_PwrGd#/PD
FS_A_410
SRCCLKT1
SRCCLKC1
VDDSRC
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
Functionality
1
•
Pin Configuration
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC output cycle-cycle jitter <125ps
•
PCI outputs cycle-cycle jitter < 500ps
•
+/- 300ppm frequency accuracy on CPU & SRC clocks
FS_C
ICS9E4101
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCICLK2
PCICLK1
PCICLK0
FS_C/TEST_SEL
REFOUT
GND
X1
X2
VDDREF
SDATA
SCLK
GND
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
IREF
GNDA
VDDA
CPUCLKT2_ITP/SRCCLKT_7
CPUCLKC2_ITP/SRCCLKC_7
VDDSRC
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
GND
56-pin SSOP
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
1
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
Pin Description
Pin #
1
2
3
4
5
6
7
PIN NAME
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PIN TYPE
PWR
PWR
OUT
OUT
OUT
PWR
PWR
8
ITP_EN/PCICLK_F0
I/O
9
10
11
12
13
14
15
PCICLK_F1
PCICLK_F2
VDD48
USB_48MHz
GND
DOTT_96MHz
DOTC_96MHz
16
FS_B/TEST_MODE
IN
17
Vtt_PwrGd#/PD
IN
18
FS_A_410
IN
19
20
21
22
23
24
25
26
27
28
SRCCLKT1
SRCCLKC1
VDDSRC
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
OUT
OUT
PWR
OUT
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power pin for the 48MHz output.3.3V
48.00MHz USB clock
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE
is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
Vtt_PwrGd# is an active low input used to determine when latched
inputs are ready to be sampled. PD is an asynchronous active high
input pin used to put the device into a low power state. The internal
clocks, PLLs and the crystal oscillator are stopped.
3.3V tolerant low threshold input for CPU frequency selection. This
pin requires CK410 FSA. Refer to input electrical characteristics for
Vil_FS and Vih_FS threshold values.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC/SATA pair.
Complement clock of differential SRC/SATA pair.
Supply for SRC clocks, 3.3V nominal
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
2
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
Pin Description (continued)
Pin #
29
30
31
32
33
34
PIN NAME
GND
SRCCLKC5
SRCCLKT5
SRCCLKC6
SRCCLKT6
VDDSRC
TYPE
PWR
OUT
OUT
OUT
OUT
PWR
35
CPUCLKC2_ITP/SRCCLKC_7
OUT
36
CPUCLKT2_ITP/SRCCLKT_7
OUT
37
38
VDDA
GNDA
PWR
PWR
39
IREF
OUT
40
CPUCLKC1
OUT
41
CPUCLKT1
OUT
42
VDDCPU
PWR
43
CPUCLKC0
OUT
44
CPUCLKT0
OUT
45
46
47
48
49
50
51
52
GND
SCLK
SDATA
VDDREF
X2
X1
GND
REFOUT
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
53
FS_C/TEST_SEL
54
55
56
PCICLK0
PCICLK1
PCICLK2
IN
OUT
OUT
OUT
DESCRIPTION
Ground pin.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Complimentary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are
required for voltage bias. Selected by ITP_EN input.
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output.
These are current mode outputs. External resistors are required for
voltage bias. Selected by ITP_EN input.
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
Reference Clock output
3.3V tolerant input for CPU frequency selection. Low voltage
threshold inputs, see input electrical characteristics for Vil_FS and
Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
PCI clock output.
PCI clock output.
PCI clock output.
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
3
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
General Description
ICS9E4101 follows Intel CK410 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS9E4101 is driven with a 14.318MHz crystal. It generates CPU outputs
up to 400MHz. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support.
Block Diagram
48MHz, USB
Frequency
Dividers
PLL2
96MHz_DOTT_0
96MHz_DOTC_0
X1
X2
XTAL
REFOUT
CPUCLKT (2:0)
CPUCLKC (2:0)
SCLK
SDATA
Vtt_PWRGD#/PD
FS_A
FS_B
FS_C
ITP_EN
TEST_MODE
TEST_SEL
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
Control
Logic
STOP
Logic
SRCCLKT (7:1)
SRCCLKC (7:1)
PCICLK (5:0)
PCICLKF (2:0)
I REF
Power Groups
Pin Number
VDD
GND
48
51
1,7
2,6
21,28,34
29
37
38
11
13
42
45
Description
Xtal, Ref
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
DOT, USB, PLL_48
CPUCLK clocks
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
4
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
General I2C serial interface information for the ICS9E4101
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDTTM Programmable Timing Control HubTM for Intel Systems
Not acknowledge
stoP bit
1408A—01/25/10
5
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
2
I C Table: Read-Back Register
Pin #
Name
Byte 0
35,36
CPUCLK2/RCCLK7 Enable
Bit 7
32,33
SRCCLK6 Enable
Bit 6
30,31
SRCCLK5 Enable
Bit 5
26,27
SRCCLK4 Enable
Bit 4
SRCCLK3 Enable
24,25
Bit 3
22,23
SRCCLK2 Enable
Bit 2
19,20
SRCCLK1 Enable
Bit 1
Bit 0
Control Function
Type
Output Enable
RW
Output Enable
RW
Output Enable
RW
Output Enable
RW
Output Enable
RW
Output Enable
RW
Output Enable
RW
RESERVED
0
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
1
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
PWD
1
1
1
1
1
1
1
Type
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
RW
RW
Disable
Disable
Spread Off
RW
SPREAD OFF
Enable
Enable
SPREAD
ON
PWD
1
1
1
1
1
1
1
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
0
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
1
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
PWD
0
0
0
0
0
0
0
0
Type
0
1
RW
RW
RW
RW
Driven
Free-Running
Free-Running
Free-Running
Hi-Z
Stoppable
Stoppable
Stoppable
PWD
1
1
1
1
1
1
1
1
2
I C Table: Spreading and Device Behavior Control Register
Pin #
Name
Byte 1
54
PCI_F0 Enable
Bit 7
14,15
DOT_96MHz
Bit 6
12
USB_48MHz Enable
Bit 5
52
REFOUT Enable
Bit 4
Bit 3
40,41
CPUT1/CPUC1
Bit 2
43,44
CPUT0/CPUC0
Bit 1
Bit 0
-
Spread Spectrum Mode
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
RESERVED
Output Enable
Output Enable
0
2
I C Table: Output Control Register
Pin #
Byte 2
5
Bit 7
4
Bit 6
3
Bit 5
56
Bit 4
55
Bit 3
54
Bit 2
10
Bit 1
9
Bit 0
Name
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCI_F2 Enable
PCI_F1 Enable
I 2C Table: Output Control Register
Pin #
Name
Byte 3
35,35
CPU_ITP/SRCCLK7
Bit 7
SRCCLK6
32,33
Bit 6
SRCCLK5
30,31
Bit 5
SRCCLK4
26,27
Bit 4
24,25
SRCCLK3
Bit 3
22,23
SRCCLK2
Bit 2
19,20
SRCCLK1
Bit 1
Bit 0
Free-Running
Control
default:
not affected by
PCI/SRC_STOP
(Byte 6, bit 3)
RESERVED
2
I C Table: Output Control Register
Byte 4
Pin #
Bit 7
14,15
Bit 6
10
Bit 5
9
Bit 4
8
Bit 3
Bit 2
Bit 1
Bit 0
Name
DOT_96MHz
PCI_F2
PCI_F1
PCI_F0
Control Function
RESERVED
Driven in PD
Free-Running
Control
not affected by
RESERVED
RESERVED
RESERVED
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
6
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
2
I C Table: Output Control Register
Byte 5
Pin #
Name
19,20,22,23,
SRC Stop Drive Mode
Bit 7 24,25,26,27,30,31,
32,33,35,36
Bit 6
Bit 5
Bit 4
19,20,22,23,
SRC PD Drive Mode
Bit 3 24,25,26,27,30,31,
32,33,35,36
35,36
40,41
43,44
CPUCLK_ITP
CPUCLK1
CPUCLK0
I C Table: Output Control Register
Byte 6
Pin #
Name
Bit 7
-
Test Mode Selection
Bit 6
Bit 5
Bit 4
52
17,18,19,20,22,23,
24,25,26,27,30,31,
32,33,35,36
54,55,56,3,4,5,8,9,
10
-
Test Clock Mode Entry
Bit 2
Bit 1
Bit 0
Control Function
Type
0
1
PWD
Drive Mode in
PCI_Stop
RW
Driven
Hi-Z
0
0
0
0
RESERVED
RESERVED
RESERVED
Drive Mode in PD
RW
Driven
Hi-Z
0
Drive Mode in PD
Drive mode in PD
Drive mode in PD
RW
RW
RW
Driven
Driven
Driven
Hi-Z
Hi-Z
Hi-Z
0
0
0
Type
0
1
PWD
RW
Hi-Z
REF/N
0
RW
Disable
Enable
0
0
1
2
Bit 3
Bit 2
Bit 1
Bit 0
REFOUT Strength
Control Function
Test Mode
Selection
Test Mode
RESERVED
Strength Prog
RW
1X
2X
Enabled, all
Disabled, all
stoppable PCI
stoppable PCI
and SRC
and SRC clocks
clocks are
are running
stopped.
-
PCI/SRC_STOP
Stop all PCI and
SRC clocks
RW
FS_C
FS_B
FS_A
readback
readback
readback
R
R
R
Control Function
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
0
0
0
0
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
0
0
0
0
1
0
0
0
1
LATCHED
LATCHED
LATCHED
2
I C Table: Vendor & Revision ID Register
Pin #
Name
Byte 7
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
REVISION ID
VENDOR ID
2
I C Table: Byte Count Register
Byte 8
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function
Writing to this
register will
configure how
many bytes will be
read back, default
is 08 = 8 bytes.
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
7
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
2
I C Table: Watchdog Timer Register
Pin #
Byte 9
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
WD4
WD3
WD2
WD1
WD0
Control Function
RESERVED
RESERVED
RESERVED
Type
0
1
RW
RW
RW
RW
RW
-
-
PWD
0
0
0
0
0
0
0
0
Type
0
1
PWD
RW
R
Disable
Disable
Enable
Enable
0
1
0
0
0
0
0
0
Control Function
N Divider Bit 8
The decimal
representation of M
Div (6:0) is equal to
reference divider
value. Default at
power up = latch-in
or Byte 0 Rom
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
X
X
X
X
X
X
X
X
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
X
X
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
X
X
X
X
X
X
X
X
Enables
prograaming bytes
10-19
2
I C Table: VCO Control Select Bit & WD Timer Control Register
Control Function
Byte 10
Pin #
Name
M/N Programming
M/NEN
Enable
Bit 7
WDEN
Watchdog Enable
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
RESERVED
Bit 3
RESERVED
Bit 2
RESERVED
Bit 1
RESERVED
Bit 0
2
I C Table: VCO Frequency Control Register
Byte 11
Pin #
Name
N Div8
Bit 7
M Div6
Bit 6
M Div5
Bit 5
M Div4
Bit 4
M Div3
Bit 3
M Div2
Bit 2
M Div1
Bit 1
M Div0
Bit 0
2
I C Table: VCO Frequency Control Register
Byte 12
Pin #
Name
N Div7
Bit 7
N Div6
Bit 6
N Div5
Bit 5
N Div4
Bit 4
N Div3
Bit 3
N Div2
Bit 2
N Div1
Bit 1
N Div0
Bit 0
The decimal
representation of N
Div (8:0) is equal to
VCO divider value.
Default at power up
= latch-in or Byte 0
Rom table.
2
I C Table: Spread Spectrum Control Register
Byte 13
Pin #
Name
SSP7
Bit 7
SSP6
Bit 6
SSP5
Bit 5
SSP4
Bit 4
SSP3
Bit 3
SSP2
Bit 2
SSP1
Bit 1
SSP0
Bit 0
Control Function
These Spread
Spectrum bits will
program the spread
pecentage. It is
recommended to
use ICS Spread %
table for spread
programming.
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
8
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
2
I C Table: Spread Spectrum Control Register
Byte 14
Pin #
Name
Bit 7
Bit 6
SSP13
Bit 5
SSP12
Bit 4
SSP11
Bit 3
SSP10
Bit 2
SSP9
Bit 1
SSP8
Bit 0
Control Function
RESERVED
RESERVED
Type
0
1
It is recommended
to use ICS Spread
% table for spread
programming.
RW
RW
RW
RW
RW
RW
-
-
Control Function
SRC divider ratio
can be configured
via these 4 bits
individually.
CPU divider ratio
can be configured
via these 4 bits
individually.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
PCI divider ratio
can be configured
via these 4 bits
individually.
Type
Control Function
RESERVED
PCI Phase Invert
SRC Phase Invert
CPU Phase Invert
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
RW
RW
RW
Default
Default
Default
Inverse
Inverse
Inverse
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
0
0
X
X
X
X
X
X
2
I C Table: Output Divider Control Register
Byte 15
Pin #
Name
SRC Div3
Bit 7
SRC Div2
Bit 6
SRC Div1
Bit 5
SRC Div0
Bit 4
CPU Div3
Bit 3
CPU Div2
Bit 2
CPU Div1
Bit 1
CPU Div0
Bit 0
See Table: Divider Ratio
Combination Table
See Table: Divider Ratio
Combination Table
PWD
X
X
X
X
X
X
X
X
2
I C Table: Output Divider Control Register
Byte 16
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
PCI Div3
Bit 3
PCI Div2
Bit 2
PCI Div1
Bit 1
PCI Div0
Bit 0
RW
RW
RW
RW
0
1
See Table: Divider Ratio
Combination Table
PWD
0
0
0
0
X
X
X
X
2
I C Table: Vendor & Revision ID Register
Pin #
Name
Byte 17
Bit 7
PCIINV
Bit 6
SRCINV
Bit 5
CPUINV
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2
I C Table: Group
Byte 18
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Skew Control Register
Pin #
Name
SRC_Skw3
SRC_Skw2
SRC_Skw1
SRC_Skw0
CPU_Skw3
CPU_Skw2
CPU_Skw1
CPU_Skw0
-
SRC Skew Control
CPU Skew Control
IDTTM Programmable Timing Control HubTM for Intel Systems
See Table: 7-Steps Skew
Programming Table
See Table: 7-Steps Skew
Programming Table
PWD
0
0
0
0
0
0
0
0
PWD
0
0
0
0
0
0
0
0
1408A—01/25/10
9
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
2
I C Table: Group
Byte 19
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Skew Control Register
Pin #
Name
-
PCI_Skw3
PCI_Skw2
PCI_Skw1
PCI_Skw0
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
PCI Skew Control
Type
RW
RW
RW
RW
0
1
See Table: 7-Steps Skew
Programming Table
PWD
0
0
0
0
0
0
0
0
2
I C Table: Slew Rate Control Register
Pin #
Byte 20
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
2
I C Table: Slew Rate Control Register
Byte 21
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2
I C Table: Slew Rate Control Register
Pin #
Byte 22
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2
I C Table: Slew Rate Control Register
Pin #
Byte 23
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
10
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
2
I C Table: Slew Rate Control Register
Pin #
Byte 24
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
2
I C Table: Test Byte Register
Byte 25
Test
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Test Function
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
IDTTM Programmable Timing Control HubTM for Intel Systems
Test Result
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
1408A—01/25/10
11
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
Absolute Max
Symbol
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
ΘJA
ΘJC
Parameter
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Min
Typ
Max
VDD + 0.5V
VDD + 0.5V
150
85
115
GND - 0.5
-65
-40
Units
V
V
°
C
°C
°C
2000
V
°C/W
°C/W
57.4
38.8
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = -40 to 85°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
Input Low Voltage
Input High Current
VIL
IIH
3.3 V +/-5%
VIN = VDD
VIN = 0 V; Inputs with no pullup resistors
VIN = 0 V; Inputs with pull-up
resistors
VSS - 0.3
-5
0.8
5
V
uA
I IL1
Input Low Current
I IL2
MIN
TYP
MAX
UNITS NOTES
-5
uA
-200
uA
Low Threshold Input High
Voltage
VIH_FS
3.3 V +/-5%
0.7
VDD + 0.3
V
Low Threshold Input Low
Voltage
VIL_FS
3.3 V +/-5%
VSS - 0.3
0.35
V
Operating Supply Current
I DD3.3OP
3.3 V +/-5%, Full Load
500
mA
Powerdown Current
I DD3.3PD
70
12
Input Frequency 3
Pin Inductance1
Fi
Lpin
CIN
COUT
CINX
7
5
6
5
mA
mA
MHz
nH
pF
pF
pF
3
1
1
1
1
1.8
ms
1,2
Input Capacitance1
Clk Stabilization1,2
TSTAB
Modulation Frequency
Tdrive_PD#
Tfall_Pd#
Trise_Pd#
SMBus Voltage
VDD
Low-level Output Voltage
VOLSMBUS
Current sinking at VOL = 0.4 V I PULLUP
SCLK/SDATA
TRI2C
Clock/Data Rise Time
SCLK/SDATA
TFI2C
Clock/Data Fall Time
350
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or deassertion of PD# to 1st clock
Triangular Modulation
CPU output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
14.31818
30
33
kHz
1
300
us
1
5
5
5.5
0.4
ns
ns
V
V
mA
1
2
1
1
1
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
(Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
2.7
@ I PULLUP
4
1
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
2
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm accuracy on PLL
outputs.
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
12
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = -40 to 85°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source Output
Impedance
SYMBOL
CONDITIONS
MIN
Zo
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on single
ended signal using oscilloscope
math function.
Measurement on single ended
signal using absolute value.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Variation of crossing over all edges
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-tr
d-tf
see Tperiod min-max values
400MHz nominal
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
Duty Cycle
dt3
Skew
tsk3
Measurement from differential
wavefrom
CPU (1:0) VT = 50%
Skew
tsk4
CPU (1:0) to CPU_ITP, VT = 50%
TYP
MAX
UNITS
NOTES
Ω
1
850
1
mV
-150
150
1150
1
550
mV
1
1
1
140
mV
1
-300
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
175
300
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
700
700
125
125
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
45
55
%
1
100
ps
1
150
ps
1
-300
250
mV
Measurement from differential
85
ps
wavefrom
1
Guaranteed by design, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
Jitter, Cycle to cycle
tjcyc-cyc
IDTTM Programmable Timing Control HubTM for Intel Systems
1
1408A—01/25/10
13
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = -40 to 85°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Zo
VO = Vx
3000
VHigh
VLow
Vovs
Vuds
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
660
-150
Crossing Voltage (abs)
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Tabsmin
tr
tf
d-tr
d-tf
MAX
850
150
1150
-300
250
Variation of crossing over all
edges
see Tperiod min-max values
100.00MHz nominal
100.00MHz spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
UNITS
NOTES
Ω
1
mV
mV
350
550
mV
1
12
140
mV
1
300
10.0030
10.0533
ppm
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
1,2
1
1
1
1
-300
9.9970
9.9970
9.8720
175
175
30
30
700
700
125
125
Measurement from differential
45
55
%
wavefrom
tsk3
SRC(7:0), VT = 50%
Skew
250
ps
Measurement from differential
tjcyc-cyc
Jitter, Cycle to cycle
125
ps
wavefrom
1
Guaranteed by design, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
Duty Cycle
dt3
IDTTM Programmable Timing Control HubTM for Intel Systems
1
1
1
1
1
1
1
1408A—01/25/10
14
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
Electrical Characteristics - PCICLK/PCICLK_F
TA = -40 to 85°C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
Clock period
Tperiod
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
33.33MHz output nominal
33.33MHz output spread
-300
29.99100
29.99100
29.49100
29.49100
12
12
2.4
Absolute Min/Max Clock
period
Clk High Time
Clock Low Time
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
1
2
Tabs
th1
tl1
VOH
VOL
IOH
IOL
tr1
tf1
dt1
tsk1
tjcyc-cyc
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
TYP
MAX
UNITS
Notes
300
30.00900
30.15980
30.50900
30.65980
N/A
N/A
ppm
ns
ns
ns
ns
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
ns
ns
%
ps
ps
1,2
2
2
2
2
1
1
0.55
-33
-33
30
38
4
4
2
2
55
500
500
1
1
0.5
0.5
45
1
1
1
1
1
1
1
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
Electrical Characteristics - USB_48MHz
TA = -40 to 85°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
Clock period
Absolute Min/Max Clock
period
Clk High Time
Clock Low Time
ppm
Tperiod
see Tperiod min-max values
48.0000MHz output nominal
-100
20.82570
100
20.83400
ppm
ns
1,2
2
Tabs
Nominal
20.48125
21.18542
ns
2
10.036
9.836
IOH
38
2
2
ns
ns
mA
mA
mA
mA
V/ns
V/ns
1
1
Output High Current
8.094
7.694
-33
1
1
2
2
55
350
ns
ns
%
ps
1
1
1
1
Output Low Current
th1
tl1
IOL
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Jitter, Cycle to cycle
1
2
tr1
tf1
dt1
tjcyc-cyc
V OH @ MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
TYP
MAX
-33
30
1
1
1
1
45
1.43
1.33
48
UNITS Notes
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
15
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
Electrical Characteristics - DOT, 96MHz 0.7V Current Mode Differential Pair
TA = -40 to 85°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source
Output Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage
(abs)
Crossing Voltage
(var)
SYMBOL
CONDITIONS
MIN
Zo
VO = Vx
3000
VHigh
VLow
Vovs
Vuds
Statistical measurement
on single ended signal
Measurement on single
ended signal using
660
-150
Vcross(abs)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
tr
Fall Time
tf
Rise Time Variation
Fall Time Variation
d-tr
d-tf
TYP
UNITS
NOTES
Ω
1
850
150
1150
Variation of crossing over
all edges
see Tperiod min-max
-100
values
96.00MHz nominal
10.4135
mV
550
mV
1
140
mV
1
100
ppm
1,2
10.4198
ns
2
ns
1,2
10.1635
VOL = 0.175V, VOH =
0.525V
VOH = 0.525V VOL =
0.175V
1
1
1
1
mV
-300
250
96.00MHz nominal
MAX
175
700
ps
1
175
700
ps
1
125
125
ps
ps
1
1
Measurement from
45
55
%
1
differential wavefrom
Measurement from
tjcyc-cyc
Jitter, Cycle to cycle
250
ps
1
differential wavefrom
1
Guaranteed by design, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
Duty Cycle
dt3
Electrical Characteristics - REF-14.318MHz
TA = -40 to 85°C; V DD = 3.3 V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
Clock period
Absolute Min/Max Clock
period
Output High Voltage
Output Low Voltage
ppm
Tperiod
see Tperiod min-max values
14.318MHz output nominal
Tabs
V OH
V OL
Output High Current
IOH
Output Low Current
IOL
Rise Time
Fall Time
Skew
t r1
t f1
MAX
UNITS
NOTES
-300
69.82700
300
69.85500
ppm
ns
1
1
Nominal
68.82033
70.86224
ns
2
2.4
0.4
V
V
1
1
-29
-23
mA
1
29
27
mA
1
1
1
tsk1
IOH = -1 mA
I OL = 1 mA
V OH @MIN = 1.0 V,
V OH@MAX = 3.135 V
V OL @MIN = 1.95 V,
VOL @MAX = 0.4 V
V OL = 0.4 V, V OH = 2.4 V
V OH = 2.4 V, VOL = 0.4 V
V T = 1.5 V
2
2
500
ns
ns
ps
1
1
1
Duty Cycle
dt1
V T = 1.5 V
Jitter
tjcyc-cyc
V T = 1.5 V
45
TYP
55
%
1
1000
ps
1
1
Guaranteed by design, not 100% tested in production.
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
16
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
Test Clarification Table
HW
Comments
· FS_C/TEST_SEL is a 3-level latched input.
o Power-up w/ V >= 2.0V to select TEST
o Power-up w/ V < 2.0V to have pin function as
FS_C.
· When pin is FS_C, VIH_FS and VIL_FS levels
apply.
· FS_B/TEST_MODE is a low-threshold input
o VIH_FS and VIL_FS levels apply.
o TEST_MODE is a real time input
· TEST_SEL can be invoked after power up through
SMBus B6b6.
o If TEST is selected by B6b6, only B6b7 controls
TEST_MODE. The FS_B/TEST_Mode pin is not
used.
· Power must be cycled to exit TEST.
SW
TEST
FS_C/TEST FS_B/TEST ENTRY
BIT
_SEL
_MODE
HW PIN HW PIN
B6b6
0
X
0
1
0
X
1
0
X
1
1
X
REF/N or
HI-Z
B6b7
OUTPUT
X
NORMAL
0
HI-Z
1
REF/N
0
REF/N
1
1
X
1
REF/N
0
X
1
0
HI-Z
0
X
1
1
REF/N
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
17
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
c
N
56-Lead, 300 mil Body, 25 mil, SSOP
L
E1
INDEX
AREA
E
1 2
α
h x 45°
D
A
A1
A
A1
b
c
D
E
E1
e
h
L
N
a
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
-C-
e
SYMBOL
SEATING
PLANE
b
N
56
D mm.
MIN
18.31
D (inch)
MAX
18.55
MIN
.720
MAX
.730
.10 (.004) C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
9E4101yFILFT
Example:
XXXX y F I LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Industrial Temperature Range
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
IDTTM Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
18
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
Revision History
Rev.
0.1
Issue Date
10/25/07
0.2
07/11/08
0.3
0.4
0.5
A
10/06/08
01/07/09
02/17/09
01/25/10
Description
Initial Release
Corrected operating temperature range on "Absolute Max" electrical
characteristics table.
Corrected typo on ordering information.
Removed "Advanced Information" from document header.
Added thermal chars.
Released to final. Updated document template.
Page #
12
19
Various
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© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
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19