ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/ LVCMOS-TO-0.7V HCSL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS85105I is a low skew, high performance 1ICS to-5 Differential-to-0.7V HCSL Fanout Buffer and HiPerClockS™ a member of the HiPerClockS™ family of High Perfor mance Clock Solutions from IDT. The ICS85105I has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • Five 0.7V differential HCSL outputs • Selectable differential CLK0, nCLK0 or LVCMOS inputs • CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 500MHz • Translates any single-ended input signal to 3.3V HCSL levels with resistor bias on nCLK input Guaranteed output and part-to-part skew characteristics make the ICS85105I ideal for those applications demanding well defined performance and repeatability. • Output skew: 100ps (maximum) • Part-to-part skew: 600ps (maximum) • Propagation delay: 3.2ns (maximuml) • Additive phase jitter, RMS: 0.24ps (typical) • 3.3V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM CLK_EN Pullup PIN ASSIGNMENT GND CLK_EN CLK_SEL CLK0 nCLK0 CLK1 Q4 nQ4 IREF VDD D Q CLK0 Pulldown nCLK0 Pullup/Pulldown CLK1 Pulldown LE 0 Q0 nQ0 1 CLK_SEL Pulldown Q1 nQ1 Q2 nQ2 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDD Q1 nQ1 Q2 nQ2 VDD Q3 nQ3 ICS85105I IREF 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm Package Body G Package Top View Q3 nQ3 Q4 nQ4 IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 1 2 3 4 5 6 7 8 9 10 1 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 GND Power 2 CLK_EN Input 3 CLK_SEL Input 4 CLK0 Input 5 nCLK0 Input 6 CLK1 Input 7, 8 Q4, nQ4 Output 9 IREF Input 10, 13, 18 VDD Power Differential output pair. HCSL interface levels. An external fixed precision resistor (475Ω) from this pin to ground provides a reference current used for differential current-mode Qx/nQx outputs. Positive supply pins. 1 1, 1 2 nQ3, Q3 Output Differential output pair. HCSL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. HCSL interface levels. Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. Pullup When LOW, Qx outputs are forced low, nQx outputs are forced high. LVTTL / LVCMOS interface levels. Clock select input. When HIGH, selects CLK1 input. Pulldown When LOW, selects CLK0, nCLK0 inputs. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. Pulldown Pulldown Single-ended clock input. LVTTL / LVCMOS interface levels. 16, 17 nQ1, Q1 Output Differential output pair. HCSL interface levels. nQ0, Q0 Output Differential output pair. HCSL interface levels. 19, 20 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER Test Conditions Minimum 2 Typical Maximum Units ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs CLK_EN CLK_SEL Selected Source Q0:Q4 nQ0:nQ4 0 0 CLK0, nCLK0 Disabled; LOW Disabled; HIGH 0 1 CLK1 Disabled; LOW Disabled; HIGH 1 0 CLK0, nCLK0 Enabled Enabled 1 1 CLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. Enabled Disabled nCLK0 CLK0, CLK1 CLK_EN nQ0:nQ4 Q0:Q4 FIGURE 1. CLK_EN TIMING DIAGRAM IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 3 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the -0.5V to VDD + 0.5V Inputs, VI device. These ratings are stress specifications only. Functional op- Outputs, IO Continuous Current Surge Current 50mA 100mA eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not Package Thermal Impedance, θJA 20 Lead TSSOP 91.1°C/W (0 mps) Storage Temperature, TSTG implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 2.97 3.3 3.63 V 27 mA Unterminated TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter Maximum Units V IH Input High Voltage Test Conditions Minimum 2 Typical VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK1, CLK_SEL VIN = VDD = 3.63V 150 µA CLK_EN VIN = VDD = 3.63V 5 µA IIL Input Low Current CLK1, CLK_SEL VIN = 0V, VDD = 3.63V -5 µA CLK_EN VIN = 0V, VDD = 3.63V -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions CLK0/nCLK0 Minimum VDD = VIN = 3.63V CLK0 VDD = 3.63V, VIN = 0V -5 nCLK0 VDD = 3.63V, VIN = 0V -150 Peak-to-Peak Input Voltage; NOTE 1 Common Mode Input Voltage; VCMR NOTE 1, 2 NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. VPP IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 4 Typical Maximum Units 150 µA µA µA 0.15 1.3 V GND + 0.5 VDD - 0.85 V ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Maximum Units CLK_SEL = 0 Minimum Typical 500 MHz CLK_SEL = 1 250 MHz 3.2 ns fMAX Output Frequency tPD Propagation Delay; NOTE 1 2.8 ns t sk(o) Output Skew; NOTE 2, 4 100 ps t sk(pp) 600 ps VRB Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Absolute Maximum Output Voltage; NOTE 5, 10 Absolute Minimum Output Voltage; NOTE 5, 11 Ringback Voltage; NOTE 6, 13 tSTABLE Time before VRB is allowed; NOTE 6, 13 500 VCROSS Absolute Crossing Voltage; NOTE 5, 8, 9 Total Variation of VCROSS over all edges; NOTE 5, 8, 12 250 t jit VMAX VMIN ΔVCROSS Rise/Fall Edge Rate; NOTE 6, 7 CLK_SEL = 0 2.0 CLK_SEL = 1 2.0 100MHz (12kHz - 20MHz) 0.24 ps 1150 -300 -100 Measured between -150mV to +150mV 0.6 mV mV 100 V ps 550 mV 140 mV 5.5 V/ns Output Duty Cycle; NOTE 14 45 55 % odc All parameters measured at ƒ≤ 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Measurement taken from single-ended waveform. NOTE 6: Measurement taken from differential waveform. NOTE 7: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. See Parameter Measurement Information Section. NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. See Parameter Measurement Information Section. NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 12: Defined as the total variation of all crossing voltage of Rising Qx and Falling nQx. This is the maximum allowed variance in the VCROSS for any par ticular system. See Parameter Measurement Information Section. NOTE: 13. TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to droop back into the VRB ±100mV differential range. See Parameter Measurement Information Section. NOTE 14: Input duty cycle must be 50%. IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 5 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz SSB PHASE NOISE dBc/HZ Additive Phase Jitter, Integration Range: 12kHz - 20MHz at 100MHz = 0.22ps (typical) OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 6 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V±10% 3.3V±10% SCOPE VDD 50Ω VDD 50Ω 33Ω Qx 49.9Ω 2pF HCSL HCSL 50Ω 33Ω 50Ω GND GND nQx 49.9Ω 2pF 475Ω IREF 475Ω IREF 0V 0V This load condition is used for IDD, tsk(o), t PD, and t jit measurements. HCSL OUTPUT LOAD AC TEST CIRCUIT HCSL OUTPUT LOAD AC TEST CIRCUIT PART 1 nQx VDD Qx nCLK0 V Cross Points PP PART 2 nQy V CMR CLK0 Qy tsk(pp) GND DIFFERENTIAL INPUT LEVELS PART-TO-PART SKEW nQx nCLK0 Qx CLK0 nQy nQ0:nQ4 Q0:Q4 Qy tPD tsk(o) OUTPUT SKEW (DIFFERENTIAL INPUT) PROPAGATION DELAY (DIFFERENTIAL INPUTS) Rise Edge Rate Fall Edge Rate CLK1 +150mV 0.0V nQ0:nQ4 -150mV Q0:Q4 Q - nQ tPD DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME PROPAGATION DELAY (LVCMOS INPUT) IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 7 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION, CONTINUED Clock Period (Differential) Positive Duty Cycle (Differential) nQ Negative Duty Cycle (Differential) VCROSS_DELTA = 140mV 0.0V Q Q - nQ DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD SE MEASUREMENT POINTS FOR DELTA CROSS POINT TSTABLE VRB +150mV VRB = +100mV 0.0V VRB = -100mV -150mV Q - nQ VRB TSTABLE DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK VMAX = 1.15V nQ VCROSS_MAX = 550mV VCROSS_MIN = 250mV Q VMIN = -0.30V SE MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 8 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUT For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. DIFFERENTIAL OUTPUTs All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_BIAS = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_BIAS in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_BIAS should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_Bias nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 9 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 2.5V FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK HCSL *R4 33 R1 50 R2 50 nCLK HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional – R3 and R4 can be 0Ω FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 10 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER RECOMMENDED TERMINATION Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. FIGURE 4A. RECOMMENDED TERMINATION Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ù impedance. FIGURE 4B. RECOMMENDED TERMINATION IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 11 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85105I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85105I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.63V * 27mA = 98.01mW Power (outputs)MAX = 47.3mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 47.3mW = 236.5mW Total Power_MAX (3.63V, with all outputs switching) = 98.01mW + 236.5mW = 334.51mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 91.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.335W * 91.1°C/W = 115.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 20-LEADN TSSOP, FORCED CONVECTION θ by Velocity (Meters per Second) JA Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 0 1 2.5 91.1°C/W 86.7°C/W 84.6°C/W 12 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 5. VDD IOUT = 17mA ➤ VOUT RREF = 475Ω ± 1% RL 50Ω IC FIGURE 5. HCSL DRIVER CIRCUIT AND TERMINATION HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50Ω load to ground. The highest power dissipation occurs when VDD is HIGH. Power = (VDD_HIGH – VOUT ) * IOUT, since VOUT = IOUT * RL = (VDD_HIGH – IOUT * RL) * IOUT = (3.63V – 17mA * 50Ω) * 17mA Total Power Dissipation per output pair = 47.3mW IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 13 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θ by Velocity (Meters per Second) JA Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 91.1°C/W 86.7°C/W 84.6°C/W TRANSISTOR COUNT The transistor count for ICS85105I is: 614 PACKAGE OUTLINE AND DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 8A. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 20 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 α 0° 8° aaa -- 0.10 0.75 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 14 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 85105AGI ICS85105AGI 20 lead TSSOP tube -40°C to 85°C 85105AGIT ICS85105AGI 20 lead TSSOP 2500 tape & reel -40°C to 85°C 85105AGILF ICS85105AGIL 20 lead "Lead-Free" TSSOP tube -40°C to 85°C 85105AGILFT ICS85105AGIL 20 lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ 0.7V HCSL FANOUT BUFFER 15 ICS85105AGI REV. A JUNE 5, 2008 ICS85105I LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support Corporate Headquarters 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA