Appl. Manual

RV-2251-C3
Application Manual
Date: January 2016
Headquarters:
Micro Crystal AG
Mühlestrasse 14
CH-2540 Grenchen
Switzerland
Tel.
Fax
Internet
Email
Revision N°: 1.0
1/71
+41 32 655 82 82
+41 32 655 82 83
www.microcrystal.com
[email protected]
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
TABLE OF CONTENTS
1.
OVERVIEW ..................................................................................................................................................... 4
1.1. GENERAL DESCRIPTION......................................................................................................................... 4
1.2. APPLICATIONS ......................................................................................................................................... 5
2.
BLOCK DIAGRAM ......................................................................................................................................... 6
2.1. PINOUT ...................................................................................................................................................... 7
2.2. PIN DESCRIPTION .................................................................................................................................... 7
2.3. FUNCTIONAL DESCRIPTION ................................................................................................................... 8
2.4. DEVICE PROTECTION DIAGRAM ........................................................................................................... 8
3.
REGISTER ORGANIZATION ......................................................................................................................... 9
3.1. REGISTER OVERVIEW ............................................................................................................................. 9
3.1.1. AUTO-INCREMENTING AND STOP CONDITION ............................................................................ 9
3.2. TIME AND DATE REGISTERS ................................................................................................................ 10
3.3. OFFSET REGISTER ................................................................................................................................ 13
3.4. ALARM_W REGISTERS.......................................................................................................................... 14
3.5. ALARM_D REGISTERS .......................................................................................................................... 16
3.6. RAM REGISTER ...................................................................................................................................... 17
3.7. CONTROL REGISTERS .......................................................................................................................... 17
3.8. REGISTER RESET VALUES SUMMARY ............................................................................................... 19
4.
DETAILED FUNCTIONAL DESCRIPTION .................................................................................................. 20
4.1. AUTOMATIC BACKUP SWITCHOVER FUNCTION............................................................................... 20
4.1.1. PRIMARY BATTERY ........................................................................................................................ 21
4.1.2. CAPACITOR OR SECONDARY BATTERY 3.0 V CHARGE ........................................................... 23
4.1.3. CAPACITOR OR SECONDARY BATTERY 5.5 V CHARGE ........................................................... 25
4.2. POWER-ON RESET ................................................................................................................................. 27
4.3. SUPPLY VOLTAGE MONITORING FUNCTIONS .................................................................................. 27
4.3.1. VDD MONITORING CIRCUIT ........................................................................................................... 28
4.3.2. VIO MONITORING CIRCUIT ............................................................................................................ 30
4.3.3. VIO LEVEL SHIFTER........................................................................................................................ 31
4.3.4. VBAT MONITORING CIRCUIT ......................................................................................................... 32
4.4. RTC COUNTER ACCESS........................................................................................................................ 33
4.5. INTERRUPT SUMMARY.......................................................................................................................... 34
4.6. PERIODIC TIME UPDATE INTERRUPT FUNCTION ............................................................................. 35
4.6.1. PULSE MODE ................................................................................................................................... 36
4.6.2. LEVEL MODE ................................................................................................................................... 37
4.6.3. USE OF THE PERIODIC TIME UPDATE INTERRUPT ................................................................... 38
4.7. ALARM FUNCTIONS ............................................................................................................................... 39
4.7.1. ALARM DIAGRAM ............................................................................................................................ 39
4.7.2. USE OF THE ALARM INTERRUPTS ............................................................................................... 40
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4.8. SERVICING INTERRUPTS ...................................................................................................................... 40
4.9. FREQUENCY OFFSET COMPENSATION ............................................................................................. 41
4.9.1. OFFSET COMPENSATION CALCULATION WORKFLOW ............................................................. 42
4.9.2. MEASURING TIME ACCURACY AT INT PIN .................................................................................. 44
4.10. OSCILLATOR FAILURE DETECTION .................................................................................................... 45
4.11. 32-KHZ CLOCK OUTPUT ........................................................................................................................ 46
4.12. ECO MODE .............................................................................................................................................. 46
2
5.
I C-BUS INTERFACE ................................................................................................................................... 47
5.1. BIT TRANSFER ....................................................................................................................................... 47
5.2. START AND STOP CONDITIONS .......................................................................................................... 47
5.3. DATA VALID ............................................................................................................................................ 48
5.4. SYSTEM CONFIGURATION.................................................................................................................... 48
5.5. ACKNOWLEDGE ..................................................................................................................................... 49
5.6. SLAVE ADDRESS ................................................................................................................................... 50
5.7. REGISTER ADDRESS ............................................................................................................................. 50
5.8. WRITE OPERATION ................................................................................................................................ 51
5.9. READ OPERATION ................................................................................................................................. 52
5.9.1. NORMAL READ AT SPECIFIC ADDRESS ...................................................................................... 52
5.9.2. POWER SAVING READ AT SPECIFIC ADDRESS ......................................................................... 53
5.9.3. READ IMMEDIATELY ....................................................................................................................... 54
6.
ELECTRICAL SPECIFICATIONS ................................................................................................................ 55
6.1. ABSOLUTE MAXIMUM RATINGS .......................................................................................................... 55
6.2. OPERATING PARAMETERS .................................................................................................................. 56
6.3. TYPICAL CHARACTERISTICS ............................................................................................................... 58
6.4. OSCILLATOR PARAMETERS ................................................................................................................ 64
6.4.1. XTAL FREQUENCY VS. TEMPERATURE CHARACTERISTICS ................................................... 64
2
6.5. I C-BUS INTERFACE AC ELECTRICAL CHARACTERISTICS ............................................................. 65
7.
RECOMMENDED REFLOW TEMPERATURE (LEAD-FREE SOLDERING) ............................................. 66
8.
PACKAGE .................................................................................................................................................... 67
8.1. DIMENSIONS AND SOLDER PAD LAYOUT .......................................................................................... 67
8.2. MARKING AND PIN #1 INDEX ................................................................................................................ 67
9.
PACKING INFORMATION ........................................................................................................................... 68
9.1. CARRIER TAPE ....................................................................................................................................... 68
9.2. PARTS PER REEL ................................................................................................................................... 68
9.3. REEL 7 INCH FOR 12 mm TAPE ............................................................................................................ 69
9.4. HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED CRYSTALS ........ 70
10.
DOCUMENT REVISION HISTORY .............................................................................................................. 71
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RV-2251-C3
Real-Time Clock / Calendar Module with I2C-bus interface
1. OVERVIEW
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RTC Module with built-in “Tuning Fork” crystal oscillating at 32.768 kHz
Counters for seconds, minutes, hours, date, weekday, month and year
Programmable Offset register for frequency adjustment
Automatic leap year calculation (2000 to 2099)
Two Alarm Interrupt circuits:
o Alarm_W for weekday, hour and minutes settings
o Alarm_D for hour and minutes setting
Periodic Time Update Interrupt function (2 Hz, 1 Hz, 1/60 Hz, 1/3600 Hz and monthly)
Automatic Backup switchover function (VDD monitoring)
3.0 V Regulated Output for ML rechargeable batteries (VREG)
Monitoring function of backup power supply voltage (VBAT monitoring)
2
Built-in I C-bus interface voltage detector with delayed access enable output (VIO monitoring)
2
Level shifter for I C-bus interface and CLKOUT (VIO)
Oscillator failure sensing function
Internal Power-On Reset (POR)
Power-On Reset Flag to prove that the power supply was started from 0V (VOUT)
32.768 kHz Clock Output
2
I C bus interface (up to 400 kHz)
Wide Timekeeping voltage range: 0.9 V to 5.5 V
Wide interface operating voltage: 1.9 to 5.5 V
Low current consumption: 270 nA (VBAT = 3.0 V)
o Very low current consumption in ECO mode: 210 nA (VBAT = 3.0 V)
Operating temperature range: -40 to +85°C
Small and compact C3 package size, RoHS-compliant and 100% lead-free: 3.7 x 2.5 x 0.9 mm
1.1. GENERAL DESCRIPTION
The RV-2251-C3 is a CMOS Real-Time Clock/Calendar Module with an automatic backup switchover circuit and a
voltage detector. An Offset register allows compensating the frequency deviation of the 32.768 kHz clock. All
2
addresses and data are transferred over an I C-bus interface for communication with a host controller. The
Address Pointer is incremented automatically after each written or read data byte. The low power consumption can
even be lowered by selecting the ECO mode. 3.0 V ML rechargeable batteries can be directly connected to the RV2251-C3.
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Real-Time Clock / Calendar Module
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1.2. APPLICATIONS
The RV-2251-C3 RTC Module contains a backup switchover circuit to change automatically from main power
source to back up power source according to needs.
This unique feature makes this product perfectly suitable for many applications:
 Communication: IoT / Wearables / Wireless Sensors and Tags / Handsets
 Automotive:
M2M / Navigation & Tracking Systems / Dashboard / Tachometers / Engine Controller
Car Audio & Entertainment Systems
 Metering:
E-Meter / Heating Counter / Smart Meters / PV Converter
 Outdoor:
ATM & POS systems / Surveillance & Safety systems / Ticketing Systems
 Medical:
Glucose Meter / Health Monitoring Systems
 Safety:
DSLR / Security & Camera Systems / Door Lock & Access Control
 Consumer:
Gambling Machines / TV & Set Top Boxes / White Goods
 Automation:
DSC / Data Logger / Home & Factory Automation / Industrial and Consumer Electronics
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2. BLOCK DIAGRAM
VOLTAGE
DETECTOR1
VDD
VREG
12
10
VOLTAGE
REGULATOR
SW1
VOUT
INTERNAL
POWER
SUPPLY
& POR
11
SW2
VBAT
VSS
ECO
9
BATTERY
MONITOR
7
4
XTAL
OSC
FREQUENCY DIVIDER
&
OFFSET COMPENSATION
VIO
VIOL
SCL
SDA
CLKOUT
5
VOLTAGE
DETECTOR2
1
VIOL
CONTROL
0
F
6
3
8
2
INT
SYSTEM
CONTROL
LOGIC
Seconds
Minutes
Hours
Weekdays
Date
Months
Years
Offset
Alarm_W Minutes
Alarm_W Hours
Alarm_W Weekday
Alarm_D Minutes
Alarm_D Hours
RAM
Control1
Control2
LEVEL
SHIFTER
I2C-BUS
INTERFACE
INT
CONTROL
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2.1. PINOUT
C3 Package: (top view)
#11
#7
2251
#12
#1
#6
#5
#1
VIOL
#2
INT
#3
SDA
#4
ECO
#5
VIO
#6
SCL
#7
VSS
#8
CLKOUT
#9
VBAT
#10
VREG
#11
VOUT
#12
VDD
2.2. PIN DESCRIPTION
Symbol
Pin #
Description
VIOL
1
VIO Peripheral Supply Monitoring Result Output; open-drain; active LOW; requires pull-up resistor. If
VIO voltage is equal or lower than VDET2F, the VIOL output level is LOW.
INT
2
Interrupt Output; open-drain; active LOW; requires pull-up resistor. Used to output Alarm (Alarm_W
and Alarm_D) and Periodic Time Update Interrupt signals.
SDA
3
I2C Serial Data Input-Output; requires pull-up resistor. Is tolerant to 5.5 V regardless of power
supply voltage.
ECO
4
Input to select Oscillator mode. If ECO is HIGH, ECO mode is off. If ECO is tied to Ground, ECO
mode is on. This pin must not be left floating or the RTC may consume higher current.
VIO
5
Peripheral Supply Voltage Input (for I2C interface and CLKOUT). Is tolerant to 5.5 V regardless of
power supply voltage. If VIO voltage is equal or lower than VDET2F, the VIOL output becomes LOW.
SCL
6
I2C Serial Clock Input; requires pull-up resistor. Is tolerant to 5.5 V regardless of power supply
voltage.
VSS
CLKOUT
7
8
Ground.
32.768 kHz Clock Output; push-pull. Voltage of high level is equal to VIO. Output always active.
VBAT
9
Backup Power Supply Input. VBAT can handle primary or secondary batteries or capacitors as
backup sources. If VDD level is equal or lower than VDET1F, power is supplied from this pin.
If VBAT is not used, connect it to VOUT. Do not connect VBAT to VSS (else VDD is short circuited when
VDD < VDET1F).
VREG
10
Voltage regulator output. 3.0 V if VDD ≥ 3.3 V. Connect a 0.1 µF capacitor between VREG and VSS.
VOUT
11
Internal Supply Voltage Output or Input. VOUT is the switch-over output of VDD and VBAT. Directly
input internal supply voltage over this pin is possible. Connect at least a 0.1 µF capacitor between
VOUT and VSS when a secondary battery is connected to the pin VBAT.
12
Main Power Supply Input.
If the voltage VDD is equal or higher than VDET1R, SW1 is closed, and SW2 is opened. As a result,
power is supplied by VDD pin.
If the voltage VDD is equal or lower than VDET1F, SW1 is open, and SW2 turns on. As a result, power
is supplied from VBAT pin.
VDD
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2.3. FUNCTIONAL DESCRIPTION
The RV-2251-C3 is a low power CMOS based Real-Time Clock Module with embedded 32.768 kHz Crystal.
The RTC module is specially designed for versatile backup solutions. The multi-functionality of the RV-2251-C3 is
reached with the Automatic Backup switchover function, a separate Peripheral Supply Voltage Input with level
shifter, a monitoring function of the backup power supply voltage and a 3.0 V Regulated Output for charging ML
rechargeable batteries (e.g. Renata LMR 2016) or capacitors.
Additionally, there is an Offset Register customer use for aging correction.
The RTC Module provides standard Clock & Calendar function including seconds, minutes, hours (12 or 24 h),
weekday, date, months, years (with automatic leap year calculation) and an interrupt function with two
programmable Alarm settings and a Periodic Time Update Interrupt function. Beside the standard RTC functions it
2
includes 1 Byte of User RAM and offers an I C-bus (2-wire interface).
The registers are accessed by selecting a register address with the Address Pointer and the Transmission Format
and then performing read or write operations. Multiple reads or writes may be executed in a single access, with the
Address Pointer automatically incrementing after each byte.
2.4. DEVICE PROTECTION DIAGRAM
VDD
12
VIOL
INT
SDA
ECO
VIO
1
11
2
10
3
9
4
8
5
7
VOUT
VREG
VBAT
CLKOUT
VSS
6
SCL
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3. REGISTER ORGANIZATION
Registers are accessed by selecting a register address including the 4-bit Address Pointer and the 4-bit
Transmission Format and then performing read or write operations (see REGISTER ADDRESS). Multiple reads or
writes may be executed in a single access, with the Address Pointer automatically incrementing after each byte.
16 registers (Address Pointer 0h – Fh) are available. The time registers are encoded in the Binary Coded Decimal
format (BCD) to simplify application use. Other registers are either bit-wise or standard binary format. When one of
the RTC registers is written or read, the contents of all time counters are frozen for up to 0.5 second. Therefore,
faulty writing or reading of the clock and calendar during a carry condition is prevented.
3.1. REGISTER OVERVIEW
After reset, all registers are set according to Table in section REGISTER RESET VALUES SUMMARY.
Address Pointer
Function
Bit 7
Bit 6
Bit 5
Bit 4
0h
1h
Seconds
Minutes
○
○
40
40
2h
Hours
○
○
3h
4h
5h
6h
7h
8h
Weekday
Date
Months
Years
Offset
Alarm_W Minutes
○
○
○
○
○
○
40
20
20
AMPM
20
○
20
○
20
10
10
10
10
○
10
10
10
9h
Alarm_W Hours
○
○
Ah
Bh
Alarm_W Weekdays
Alarm_D Minutes
○
○
6
40
Ch
Alarm_D Hours
○
○
Dh
Eh
Fh
RAM
Control1
Control2
AE_W
GP1
AE_D
BLF
80
MODE
○
40
20
AMPM
20
5
20
AMPM
20
12_24
OF
Bit 3
8
8
8
8
○
8
8
8
OFFSET
10
8
10
8
10
8
4
3
10
8
10
8
10
8
RAM data
GP0
TEST
PON
GP2
Bit 2
Bit 1
Bit 0
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
4
4
4
2
4
4
4
2
2
2
1
2
2
2
1
1
1
0
1
1
1
UF
USEL
WF
DF
○ Bit not implemented. Will return a 0 when read.
3.1.1.AUTO-INCREMENTING AND STOP CONDITION
When address is automatically incremented, wrap around occurs from the Address Pointer value Fh to value 0h
2
(see figure below). Note that the Address Pointer is set to Fh when sending an I C STOP condition (see START
AND STOP CONDITIONS).
2
Auto-incrementing of the Address Pointer, and I C STOP condition:
Address Pointer
0h
wrap around
1h
2h
3h
autoincrement
:
Dh
Eh
STOP condition
Fh
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3.2. TIME AND DATE REGISTERS
0h - Seconds
This register holds the count of seconds, in two binary coded decimal (BCD) digits. Values will be from 00 to 59.
Address Pointer
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0h
Seconds
Reset
○
0
40
X
20
X
10
X
8
X
4
X
2
X
1
X
Bit
Symbol
Value
7
6:0
○
Seconds
0
00 to 59
Description
Unused
Holds the count of seconds, coded in BCD format.
1h - Minutes
This register holds the count of minutes, in two binary coded decimal (BCD) digits. Values will be from 00 to 59.
Address Pointer
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1h
Minutes
Reset
○
0
40
X
20
X
10
X
8
X
4
X
2
X
1
X
Bit
Symbol
Value
7
6:0
○
Minutes
0
00 to 59
Description
Unused
Holds the count of minutes, coded in BCD format.
2h - Hours
This register holds the count of hours, in two binary coded decimal (BCD) digits. If the 12_24 bit is clear (see
CONTROL REGISTERS, Eh - Control1) the values will be from 1 to 12 and the AMPM bit will be 0 for AM hours
and 1 for PM hours. If the 12_24 bit is set, the hour values will range from 0 to 23.
Address Pointer
2h
Function
Hours (12 hour mode)
Hours (24 hour mode)
Reset
Bit 7
Bit 6
○
○
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AMPM
20
X
10
10
X
8
8
X
4
4
X
2
2
X
1
1
X
Hours (12 hour mode)
Bit
Symbol
Value
7:6
○
0
0
1
1 to 12
5
4:0
AMPM
Hours (12 hour mode)
Description
Unused
AM hours.
PM hours.
Holds the count of hours, coded in BCD format.
Hours (24 hour mode)
Bit
Symbol
Value
7:6
5:0
○
Hours (24 hour mode)
0
0 to 23
Description
Unused
Holds the count of hours, coded in BCD format.
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3h - Weekday
This register holds the current day of the week. Each value represents one weekday that is assigned by the user.
Values will range from 0 to 6.
Address Pointer
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3h
Weekday
Reset
○
0
○
0
○
0
○
0
○
0
4
X
2
X
1
X
Bit
Symbol
Value
7:3
2:0
○
Weekday
0
0 to 6
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Weekday
Bit 7
Weekday 1
Weekday 2
Weekday 3
Weekday 4
Weekday 5
Weekday 6
Weekday 7
0
Description
Unused
Holds the weekday counter value.
Bit 6
0
Bit 5
0
Bit 4
0
4h – Date
This register holds the current date of the month, in two binary coded decimal (BCD) digits. Values will range from
01 to 31. Leap years are correctly handled from 2000 to 2099.
Address Pointer
Function
4h
Date
Reset
Bit
Symbol
7:6
5:0
○
Date
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
○
0
○
0
20
X
10
X
8
X
4
X
2
X
1
X
Value
0
01 to 31
Description
Unused
Holds the current date of the month, coded in BCD format.
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5h - Months
This register holds the current month, in two binary coded decimal (BCD) digits. Values will range from 01 to 12.
Address Pointer
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
5h
Months
Reset
○
0
○
0
○
0
10
X
8
X
4
X
2
X
1
X
Bit
Symbol
Value
7:5
4:0
○
Months
0
01 to 12
Months
Bit 7
January
February
March
April
May
June
July
August
September
October
November
December
0
Description
Unused
Holds the current month, coded in BCD format.
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
6h - Years
This register holds the current year, in two binary coded decimal (BCD) digits. Values will range from 00 to 99.
Leap years are correctly handled from 2000 to 2099.
Address Pointer
Function
6h
Years
Reset
Bit
Symbol
7:0
Years
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80
X
40
X
20
X
10
X
8
X
4
X
2
X
1
X
Value
00 to 99
Description
Holds the current year, coded in BCD format.
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3.3. OFFSET REGISTER
7h – Offset Register
This register holds the OFFSET value to digitally compensate the initial frequency deviation of the 32.768 kHz
oscillator or for aging adjustment (see FREQUENCY OFFSET COMPENSATION).
Address Pointer
Function
Bit 7
Bit 6
7h
Offset
Reset
MODE
0
Bit
Symbol
Value
7
MODE
6:0
0
1
-62 to
+62
OFFSET
OFFSET
0111111
0111110
:
0000011
0000010
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
OFFSET
0
0
0
0
0
Description
Offset Mode
Normal Mode: Offset is compensated every 20 seconds (at 00, 20 and 40).
Slow Mode: Offset is compensated every minute (at seconds = 00).
Defines compensation pulses in steps.
For MODE = 0, each pulse introduces a deviation of 3.052 ppm, the
maximum range is ±189 ppm.
For MODE = 1, each pulse introduces a deviation of 1.017 ppm, the
maximum range is ±63 ppm.
The values of 3.052 ppm and 1.017 ppm are based on a nominal 32.768
kHz clock (see FREQUENCY OFFSET COMPENSATION).
CLKOUT frequency deviation
in ppm(2)
Normal Mode
Slow Mode
MODE = 0
MODE = 1
+189.209
+63.070
+186.157
+62.052
:
:
+6.104
+2.035
+3.052
+1.017
OFFSET
compensation value
in decimal
Converting
(mathematical
operation)
Compensation
pulses
in steps
-1
-1
:
-1
-1
+62
+61
:
+2
+1
×0
0
0
0
Two’s complement
Two’s complement
:
Two’s complement
Two’s complement
-1
-2
:
-61
-62
-3.052
-6.104
:
-186.157
-189.209
-1.017
-2.035
:
-62.052
-63.070
×0
0
0
0
0000001
0000000
1111111
1111110
:
1000011
1000010
(1)
(1)
+63
+62
:
+3
+2
+1
0
1000001
(1)
+127
+126
:
+67
+66
+65
1000000
(1)
+64
(1) The OFFSET values X00000X mean no correction steps are done (X representing 0 or 1) and the offset circuit is disabled. With this
converting method a symmetrical structure of ±62 correction steps can be guaranteed.
(2) For MODE = 0, each compensation pulse corresponds to 1/(32768×10) = 3.052 ppm. For MODE = 1 it is 1/(32768×30) = 1.017 ppm.
The frequency deviation measured at CLKOUT pin can be compensated by computing the compensation value OFFSET and writing it into
the Offset register (see OFFSET COMPENSATION CALCULATION WORKFLOW).
13/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
3.4. ALARM_W REGISTERS
8h – Alarm_W Minutes
This register holds the alarm value for minutes for Alarm_W, in two binary coded decimal (BCD) digits. Values will
range from 00 to 59.
Address Pointer
Function
8h
Alarm_W Minutes
Reset
Bit
Symbol
7
6:0
○
Alarm_W Minutes
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
○
0
40
X
20
X
10
X
8
X
4
X
2
X
1
X
Value
0
00 to 59
Description
Unused
Holds the alarm value for minutes for Alarm_W, coded in BCD format.
9h – Alarm_W Hours
This register holds the alarm value for hours for Alarm_W, in two binary coded decimal (BCD) digits. If the 12_24
bit is clear (see CONTROL REGISTERS, Eh - Control1) the values will be from 1 to 12 and the AMPM bit will be 0
for AM hours and 1 for PM hours. If the 12_24 bit is set, the hour values will range from 0 to 23.
Address Pointer
9h
Function
Alarm_W Hours (12 hour
mode)
Alarm_W Hours (24 hour
mode)
Reset
Bit 7
Bit 6
○
○
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AMPM
10
8
4
2
1
20
10
8
4
2
1
X
X
X
X
X
X
Alarm_W Hours (12 hour mode)
Bit
Symbol
7:6
○
5
4:0
AMPM
Alarm_W Hours (12 hour
mode)
Value
0
0
1
1 to 12
Description
Unused
AM hours.
PM hours.
Holds the alarm value for hours for Alarm_W, coded in BCD format.
Alarm_W Hours (24 hour mode)
Bit
Symbol
7:6
○
Alarm_W Hours (24 hour
mode)
5:0
Value
0
0 to 23
Description
Unused
Holds the alarm value for hours for Alarm_W, coded in BCD format.
14/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
Ah – Alarm_W Weekdays
This register holds the alarm value for the weekdays for Alarm_W (weekdays assigned by the user). Multiple days
can be selected. Values will range from 0000001 to 1111111.
Address Pointer
Function
Ah
Alarm_W Weekdays
Reset
Bit
Symbol
7
6:0
Alarm_W Weekdays
Alarm_W Weekday 1
Alarm_W Weekday 2
Alarm_W Weekday 3
Alarm_W Weekday 4
Alarm_W Weekday 5
Alarm_W Weekday 6
Alarm_W Weekday 7
○
Alarm_W Weekdays
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
○
0
6
X
5
X
4
X
3
X
2
X
1
X
0
X
Value
0
0000001
to
1111111
Description
Unused
Holds the weekday alarm value for Alarm_W. Multiple days can be
selected.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
15/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
3.5. ALARM_D REGISTERS
Bh – Alarm_D Minutes
This register holds the alarm value for minutes for Alarm_D, in two binary coded decimal (BCD) digits. Values will
range from 00 to 59.
Address Pointer
Function
Bh
Alarm_D Minutes
Reset
Bit
Symbol
7
6:0
○
Alarm_D Minutes
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
○
0
40
X
20
X
10
X
8
X
4
X
2
X
1
X
Value
0
00 to 59
Description
Unused
Holds the alarm value for minutes for Alarm_D, coded in BCD format.
Ch – Alarm_D Hours
This register holds the alarm value for hours for Alarm_D, in two binary coded decimal (BCD) digits. If the 12_24 bit
is clear (see CONTROL REGISTERS, Eh - Control1) the values will be from 1 to 12 and the AMPM bit will be 0 for
AM hours and 1 for PM hours. If the 12_24 bit is set, the hour values will range from 0 to 23.
Address Pointer
Ch
Function
Alarm_D Hours (12 hour
mode)
Alarm_D Hours (24 hour
mode)
Reset
Bit 7
Bit 6
○
○
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AMPM
10
8
4
2
1
20
10
8
4
2
1
X
X
X
X
X
X
Alarm_D Hours (12 hour mode)
Bit
Symbol
7:6
○
5
4:0
AMPM
Alarm_D Hours (12 hour
mode)
Value
0
0
1
1 to 12
Description
Unused
AM hours.
PM hours.
Holds the alarm value for hours for Alarm_D, coded in BCD format.
Alarm_D Hours (24 hour mode)
Bit
Symbol
7:6
○
Alarm_D Hours (24 hour
mode)
5:0
Value
0
0 to 23
Description
Unused
Holds the alarm value for hours for Alarm_D, coded in BCD format.
16/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
3.6. RAM REGISTER
Dh - RAM
Free RAM byte, which can be used for any purpose, for example, status byte of the system.
Address Pointer
Function
Dh
RAM
Reset
Bit
Symbol
7:0
RAM
Bit 7
0
Value
00h to
FFh
Bit 6
0
Bit 5
0
Bit 4
Bit 3
RAM data
0
0
Bit 2
Bit 1
Bit 0
0
0
0
Description
User RAM
3.7. CONTROL REGISTERS
Eh - Control1
Control and status register 1.
Address Pointer
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Eh
Control1
Reset
AE_W
0
AE_D
0
12_24
0
GP0
0
TEST
0
0
USEL
0
0
Bit
Symbol
Value
Description
Alarm_W Interrupt Enable (see ALARM FUNCTION and INTERRUPT SUMMARY)
7
AE_W
6
AE_D
5
12_24
4
GP0
3
TEST
2:0
USEL
0
Disabled
1
Enabled
Alarm_D Interrupt Enable (see ALARM FUNCTION and INTERRUPT SUMMARY)
0
Disabled
1
Enabled
12 or 24 hour mode (see TIME AND DATE REGISTERS, ALARM_W REGISTERS
and ALARM_D REGISTERS)
0
12 hour mode is selected (1 to 12).
1
24 hour mode is selected (0 to 23).
0 or 1
Register bit for general purpose use.
0
Normal mode.
1
Test mode. Do not use.
000 to
Periodic Time Update Interrupt selection (see PERIODIC TIME UPDATE
111
INTERRUPT FUNCTION and INTERRUPT SUMMARY)
USEL
USEL-Mode
000
001
010
011
100
101
110
111
Pulse
Pulse
Level
Level
Level
Level
INT Frequency
OFF (INT = HIGH) – Default value
Always ON (INT = LOW) (1)
2 Hz (2) (3)
1 Hz (2) (3)
Every second (3)
Every minute
Every hour
Every month
(1) When USEL = 001b the flag UF cannot be reset to 0.
(2) Duty cycle = 50%
(3) In Pulse Mode the 2 Hz and 1 Hz clock pulses and in Level Mode the 1 Hz signal can be affected by compensation pulses
(see FREQUENCY OFFSET COMPENSATION).
17/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
Fh – Control2
Control and status register 2.
Address Pointer
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Fh
Control2
Reset
GP1
0
BLF
1
OF
1
PON
1
GP2
0
UF
0
WF
0
DF
0
Bit
Symbol
Value
7
GP1
0 or 1
6
BLF
5
OF
4
PON
3
GP2
2
UF
1
0
1
WF
1
0
0
Description
Register bit for general purpose use.
Battery Low Flag (see VBAT MONITORING CIRCUIT)
0
Backup Power Supply voltage VBAT is above the threshold value VBLF.
Backup Power Supply voltage VBAT dropped below the threshold value
1
VBLF. It can be cleared by writing a 0 to the bit. This bit is also set on a
power on reset (POR) and can be cleared by writing a 0 to the bit.
Oscillator Failure Flag (see OSCILLATOR FAILURE DETECTION
0
No oscillator failure has occurred.
Oscillator Failure. This bit is set if an oscillator failure occurs. It can be
1
cleared by writing a 0 to the bit. This bit is also set on a power on reset
(POR) and can be cleared by writing a 0 to the bit.
Power-On reset Flag (see POWER-ON RESET)
0
No Power-On reset state detected.
VOUT Power-On reset state (POR) detected. All registers are initialized to
1
their reset values. It can be cleared by writing a 0 to the bit.
0 or 1
Register bit for general purpose use.
Periodic Time Update Interrupt Flag (see PERIODIC TIME UPDATE INTERRUPT
FUNCTION and INTERRUPT SUMMARY)
0
Periodic Time Update Interrupt output INT is inactive (HIGH).
DF
1
Periodic Time Update Interrupt output INT is active (LOW). It can be
cleared by writing a 0 to the bit only in the Level Mode (see LEVEL
MODE), which deactivates the INT pin (goes HIGH) until it is activated (tied
LOW) again in the next interrupt cycle.
Alarm_W Flag (see ALARM FUNCTION and INTERRUPT SUMMARY)
No match detected.
Indicating a match between current time and preset alarm time. The WF bit
is only valid when AE_W = 1 and approximately 15 µs after the Alarm_W
registers match their respective counters. It can be cleared by writing a 0 to
the bit.
Alarm_D Flag (see ALARM FUNCTION and INTERRUPT SUMMARY)
No match detected.
Indicating a match between current time and preset alarm time. The DF bit
is only valid when AE_D = 1 and approximately 15 µs after the Alarm_D
registers match their respective counters. It can be cleared by writing a 0 to
the bit.
18/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
3.8. REGISTER RESET VALUES SUMMARY
Address Pointer
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
Seconds
Minutes
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
X
X
0
0
0
0
X
0
X
0
X
X
0
0
0
1
X
X
X
0
X
0
X
0
X
X
X
X
X
0
0
1
X
X
X
0
X
X
X
0
X
X
X
X
X
0
0
1
X
X
X
0
X
X
X
0
X
X
X
X
X
0
0
0
X
X
X
X
X
X
X
0
X
X
X
X
X
0
0
0
X
X
X
X
X
X
X
0
X
X
X
X
X
0
0
0
X
X
X
X
X
X
X
0
X
X
X
X
X
0
0
0
Hours
Weekday
Date
Months
Years
Offset
Alarm_W Minutes
Alarm_W Hours
Alarm_W Weekdays
Alarm_D Minutes
Alarm_D Hours
RAM
Control1
Control2
X means undefined.
RV-2251-C3 after power-on reset:
Time (hh:mm:ss)
=
Date (YY-MM-DD)
=
Weekday
=
Hour mode
=
Offset
=
Periodic Interrupt
=
Alarms
=
Battery Low Flag
=
Oscillator Failure Flag =
Power-On reset Flag
=
XX:XX:XX
XX-XX-XX
X
12 hour mode (AM/PM)
Offset register is set to 0
disabled
disabled
1 (can be cleared by writing a 0 to the bit)
1 (can be cleared by writing a 0 to the bit)
1 (can be cleared by writing a 0 to the bit)
19/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
4. DETAILED FUNCTIONAL DESCRIPTION
4.1. AUTOMATIC BACKUP SWITCHOVER FUNCTION
The RV-2251-C3 has two power supply inputs, VDD and VBAT, to supply the RTC circuit with the XTAL. By
monitoring the input voltage VDD with the internal Voltage Detector 1, it is selected which of the two power supplies
is used for the internal power source VOUT. When VDD voltage is lower than VDET1, VBAT supplies the power to VOUT,
and when higher than VDET1, VDD supplies the power to VOUT (see also VDD MONITORING CIRCUIT).
The following table shows the power state of the IC as a function of the VDD supply voltage.
Automatic Backup Switchover:
Condition
Power state
VDD > VDET1
VDD Power
VDD ≤ VDET1
VBAT Power
Description
VOUT connected to VDD.
SW1 is closed, and SW2 is open.
VOUT connected to VBAT.
SW1 is open, and SW2 is closed.
As a backup source not only a primary battery such as CR2025, LR44, or a secondary battery such as ML614, but
also an electric double layer capacitor or an aluminum electrolytic capacitor can be applied. Since the switchover
point is judged with the voltage level of the main power supply VDD, it allows the RV-2251-C3 to minimize the
current drawn from the VBAT supply by switching to VBAT only at the point where VDD is no longer able to power the
device. See following timing chart for VDD, VBAT, and VOUT.
Backup switchover timing example: VREG = VDD = 4.5 V
VDET1R
VREG = VDD
VDET1R
VDET1R
VDET1F
4.5 V
VDET1F
0V
0V
5.5 V
VBAT
1.2 V
0V
5.5 V
4.5 V
VOUT
0V
1
Power state
1
2
3
POR VBAT
1.2 V
VOF
2
3
2
3
2
VDD Power
VBAT
VDD Power
VBAT Power
VDD
When VBAT is 0 V and VDD is rising from 0 V, VOUT follows about the half of VDD voltage level (over SW1
protective diode). Once VOUT has reached VOF, RV-2251-C3 switches to VBAT (SW1 = OFF, SW2 = ON).
However, because VOUT > VBAT, VOUT is supplied by VREG = VDD over SW1 protective diode. After VDD rising
over VDET1R, VOUT follows VDD voltage level.
When VDD is higher than VDET1R, VOUT is connected to VDD (SW1 = ON, SW2 = OFF).
After VDD falling beyond VDET1F, VOUT is connected to VBAT (SW1 = OFF, SW2 = ON).
Note: In this circuit where backup is done with primary battery and VBAT is not hard-wired to VOUT, the switchover to
VBAT (SW2 closed) can only occur after a previous startup of VDD. A voltage VDD of 1.0 V is sufficient, and it can be
turned off again after start-up time tSTART. With this circuit, it is not possible to power on from VBAT only (see
PRIMARY BATTERY).
20/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
4.1.1.PRIMARY BATTERY
Backup with primary battery: Conditions VMCU, VBAT
With primary battery e.g. CR2025 or LR44 (VBAT = 3.0 V).
MCU power
supply VMCU
RV-2251-C3
VDD
VREG
C3
C2
VIO
VOUT
VBAT
R1
Primary
battery
C1
VSS
Power state and interface access:
 VOUT powered from 0 V to 0.7 V with VMCU from
0 V to 1.0 V (with VBAT NOT POSSIBLE!)
o POR state
o Interface access disabled
 VMCU between 1.0 V and VDET2R (typ. 1.77 V):
o VBAT Power state
o Interface access disabled
 VMCU between VDET2R (typ. 1.77 V) and VDET1R
(typ. 2.78 V) AND VBAT between 1.0 V and 5.5
V:
o VBAT Power state
o Interface access enabled
 VMCU between VDET1R (typ. 2.78 V) and 5.5 V
o VDD Power state
o Interface access enabled
Note: In this circuit where backup is done with primary battery and VBAT is not hard-wired to VOUT, the switchover to
VBAT (SW2 closed) can only occur after a previous startup of VDD. A voltage VDD of 1.0 V is sufficient, and it can be
turned off again after the start-up time tSTART. With this circuit, it is not possible to power on from VBAT only.
21/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
Backup with primary battery: All components
C2
C1
3
VOUT
VBAT SW2
C3
VREG
SW1
VDD
VREG
4
VDET1
2
R1
VBLF
RV-2251-C3
MCU power supply
VIO
VDET2
VB
5
RTC
with
XTAL
1
VIOL
DELAY
CLKOUT
VSS
2
3
4
5
6
SCL
SDA
INT
ECO
1
VIOL
SCL
LEVEL
SHIFTER
Primary
battery
VMCU
VMCU
MCU
SDA
6
INT
VSS
Primary battery e.g. CR2025 or LR44 (VBAT = 3.0 V).
When using a primary battery, a series resistor R1 is used to limit battery current and to prevent damage in
case of soldering issues causing short between supply pins.
A 100 nF decoupling capacitor (C1, C2 and C3) is recommended close to the device for every power
supply pin (here VREG, VDD and VIO together).
Main RTC Power Supply. If the voltage is equal or lower than VDET1F, SW1 is open, and SW2 turns on. As
a result, power is supplied from VBAT pin. When VDD is equal or higher than VDET1R, SW1 is closed, and
SW2 is opened.
Interface lines SCL, SDA and the outputs VIOL and INT are open drain and require pull-up resistors to VIO.
32.768 kHz Clock Output; push-pull. Voltage of high level is equal to VIO. Output always active.
22/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
4.1.2.CAPACITOR OR SECONDARY BATTERY 3.0 V CHARGE
Backup with capacitor or secondary battery, 3.0 V charge: Conditions VDD, VBAT, VIO
E.g. with secondary battery ML614 Manganese Rechargeable Lithium Battery (ML series).
Charging voltage is VREG = 3.0 V.
3 V to 5.5 V
RV-2251-C3
VDD
(3.0 V)
VREG
C3
C2
MCU interface
(1.9 V to 5.5 V)
VIO
VOUT
C4
VREG = 3.0 V charge
VBAT
R1
Capacitor
or
secondary
battery
C1
VSS
Power state:
 VOUT powered from 0 V to 0.7 V with VDD from
0 V to 1.0 V OR with VBAT from 0 V to 0.7 V
o POR state
 VDD between 1.0 V and VDET1R (typ. 2.78 V):
o VBAT Power state
o Discharging secondary battery down
to VDD
 VDD between VDET1R (typ. 2.78 V) and 3.0 V:
o VDD Power state
o Charging secondary battery to VDD
 VDD between 3.0 V and 5.5 V
o VDD Power state
o Charging secondary battery with
regulated voltage VREG = 3.0 V
MCU interface access:
 VIO between 0 V and VDET2R (typ. 1.77 V):
o Interface access disabled
 VIO between VDET2R (typ. 1.77 V) and 5.5 V
AND VOUT between 1.0 V and 5.5 V (powered
from VDD or VBAT):
o Interface access enabled
23/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
Backup with capacitor or secondary battery, 3.0 V charge: All components
C1
3
VREG = 3.0 V charge
(3 V)
VREG
VOUT
VBAT SW2
C2
C3
SW1
VDD
VREG
4
VDD (3 V to 5.5 V)
VDET1
R1
VBLF
C4
RV-2251-C3
5
RTC
with
XTAL
1
3
4
5
6
VIOL
SCL
SCL
SDA
CLKOUT
INT
VSS
2
VIOL
DELAY
ECO
1
MCU Interface (1.9 V to 5.5 V)
VIO
VDET2
Capacitor VB
or
secondary
battery
LEVEL
SHIFTER
2
VIO
VIO
MCU
SDA
6
INT
VSS
Supercapacitor (e.g. 1 farad) or secondary battery. e.g. ML614 Manganese Rechargeable Lithium Battery
(ML series). Charging voltage is VREG = 3.0 V.
When using a supercapacitor, a series resistor R1 is used to limit the inrush current into the supercapacitor
at power-on. E.g. to comply with the maximum output current of the RV-2251-C3 (IOmax = 10 mA).
To limit the current to comply with the specification of the backup device.
And to fulfill the condition R1 > RMCU * (VB – (VDET1F)) / VDET1F) that after switch off the MCU the voltage VDD
is falling below VDET1F for shore and RV-2251-C3 can switch SW1 OFF.
A 100 nF decoupling capacitor (C1, C2, C3 and C4) is recommended close to the device for every power
supply pin (VBAT and VOUT together).
Main RTC Power Supply. If the voltage is equal or lower than VDET1F, SW1 is open, and SW2 turns on. As
a result, power is supplied from VBAT pin. When VDD is equal or higher than VDET1R, SW1 is closed, and
SW2 is opened.
Interface lines SCL, SDA and the outputs VIOL and INT are open drain and require pull-up resistors to VIO.
32.768 kHz Clock Output; push-pull. Voltage of high level is equal to VIO. Output always active.
24/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
4.1.3.CAPACITOR OR SECONDARY BATTERY 5.5 V CHARGE
Backup with capacitor or secondary battery, 5.5 V charge: Conditions VDD, VBAT, VIO
With capacitor. E.g. electric double layer capacitor (VBAT = 5.5 V).
Charging voltage is more than VREG output voltage.
5.5 V
C2
MCU interface
(1.9 V to 5.5 V)
RV-2251-C3
VDD
VREG
VIO
VOUT
C3
5.5 V charge
VBAT
R1
Capacitor
or
secondary
battery
C1
VSS
Power state:
 VOUT powered from 0 V to 0.7 V with VDD from
0 V to 1.0 V OR with VBAT from 0 V to 0.7 V
o POR state
 VDD between 1.0 V and VDET1R (typ. 2.78 V):
o VBAT Power state
o Discharging capacitor down to VDD
 VDD between VDET1R (typ. 2.78 V) and 5.5 V:
o VDD Power state
o Charging capacitor to VDD
MCU interface access:
 VIO between 0 V and VDET2R (typ. 1.77 V):
o Interface access disabled
 VIO between VDET2R (typ. 1.77 V) and 5.5 V
AND VOUT between 1.0 V and 5.5 V (powered
from VDD or VBAT):
o Interface access enabled
25/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
Backup with capacitor or secondary battery, 5.5 V charge: All components
C1
3
5.5 V charge
VOUT
VBAT SW2
C2
VREG
SW1
VDD
VREG
4
5.5 V
VDET1
Capacitor
or
secondary
battery
R1
VBLF
C3
RV-2251-C3
5
RTC
with
XTAL
1
VIOL
DELAY
3
4
5
6
SCL
SDA
CLKOUT
INT
VSS
2
VIOL
SCL
ECO
1
MCU Interface (1.9 V to 5.5 V)
VIO
VDET2
VB
LEVEL
SHIFTER
2
VIO
VIO
MCU
SDA
6
INT
VSS
Supercapacitor (e.g. 1 farad). Charging voltage is 5.5 V.
When using a supercapacitor, a series resistor R1 is used to limit the inrush current into the supercapacitor
at power-on. E.g. to comply with the maximum output current of the RV-2251-C3 (IOmax = 10 mA).
To limit the current to comply with the specification of the backup device.
And to fulfill the condition R1 > RMCU * (VB – (VDET1F)) / VDET1F) that after switch off the MCU the voltage VDD
is falling below VDET1F for shore and RV-2251-C3 can switch SW1 OFF.
A 100 nF decoupling capacitor (C1, C2 and C3) is recommended close to the device for every power
supply pin (VBAT with VOUT and VREG with VDD together).
Main RTC Power Supply. If the voltage is equal or lower than VDET1F, SW1 is open, and SW2 turns on. As
a result, power is supplied from VBAT pin. When VDD is equal or higher than VDET1R, SW1 is closed, and
SW2 is opened.
Interface lines SCL, SDA and the outputs VIOL and INT are open drain and require pull-up resistors to VIO.
32.768 kHz Clock Output; push-pull. Voltage of high level is equal to VIO. Output always active.
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4.2. POWER-ON RESET
The power-on reset (POR) is generated at start-up when VOUT is powered on from 0 V. The Offset and RAM
register are set to 00h and the Control1 and Control2 registers are initialized to their reset values (see REGISTER
RESET VALUES SUMMARY). The values of the other registers stay undefined. At the same time, the power on
state is stored to dedicated flags, thereby it can be identified whether VOUT was powered on from 0 V (BLF = 1) or if
the RV-2251-C3 was backed-up by battery (BLF = 0).
Two conditions can be differentiated:
 The Oscillation Failure Flag OF and the Power-On reset Flag PON confirm the invalidation of time data.
 While the Battery Low Flag BLF indicates only a potential invalidation of time data.
4.3. SUPPLY VOLTAGE MONITORING FUNCTIONS
The VDD, VIO and VBAT pin have their own voltage monitoring functions.
VDD power supply monitoring circuit automatically selects which of the two power supplies, VDD or VBAT, is used for
the internal power source VOUT. When VDD voltage is lower than VDET1, VBAT supplies the power to VOUT, and when
higher than VDET1, VDD supplies the power to VOUT (see AUTOMATIC BACKUP SWITCHOVER FUNCTION and
VDD MONITORING CIRCUIT).
Note that in a circuit where VBAT is not hard-wired to VOUT, the switchover to VBAT (SW2 closed) can only occur after
a previous startup of VDD. A voltage VDD of 1.0 V is sufficient, and it can be turned off again after start-up time tSTART.
In such a case, it is not possible to power on from VBAT only (see PRIMARY BATTERY).
VIO peripheral supply monitoring circuit makes VIOL pin LOW when VIO peripheral supply pin becomes equal or
lower than VDET2F. At the power-on of VIO, this circuit switches off VIOL pin (HIGH) after the delay time tDELAY from
when the VIO peripheral supply pin becomes equal or more than VDET2R (see VIO MONITORING CIRCUIT).
Note that the VIO monitoring function is only available if VOUT is between 1.0 V and 5.5 V.
VBAT power supply monitoring circuit is equipped with BLF flag in register Control2 that is configured to record any
drop in battery supply voltage below the threshold value VBLF (see VBAT MONITORING CIRCUIT).
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4.3.1.VDD MONITORING CIRCUIT
The VDD supply voltage monitor circuit is part of the automatic backup switchover function and operates always.
When VDD rising over VDET1R, SW1 turns on, and SW2 turns off, RTC is in VDD Power state. When VDD is falling
beyond VDET1F, SW1 turns off, and SW2 turns on, RTC is in VBAT Power state. In the following example backup is
done with a capacitor charged to 3.0 V (see CAPACITOR OR SECONDARY BATTERY 3.0 V CHARGE).
Power states:
VDD Power
VBAT Power
POR
SW1 = ON, SW2 = OFF
SW1 = OFF, SW2 = ON
SW1 = OFF, SW2 = OFF
VDD monitoring:
5V
3 V reg.
VDET1R
VDD
VDET1R
VDET1F
VDET1R
VDET1F
3V
VOUT = VBAT
VBLF
VOF
CLKOUT
1
PON
3
OF
7
BLF
5
VDD Power
VBAT
6
VDD
VBAT
POR
VBAT
Power state
4
POR
VBAT
2
Internal initialization
period (1 to 2 sec.)
VDD Power
Write operation
1
2
3
4
5
6
7
The flags PON and OF are set to 1 when VOUT was started from 0 V and the 32.768 kHz oscillator is running.
The BLF flag is set to 1 and valid after internal initialization period (1 to 2 seconds) doe to sampling VBAT.
After the internal initialization period all flags (PON, OF and BLF) can be cleared to 0 by software.
The VBLF monitoring circuit detects that VBAT is lower than VBLF and sets the BLF flag to 1.
When VBAT is over VBLF again the BLF flag can be cleared to 0 by software.
Once VOUT is not available the RTC is in POR Power state.
An oscillator failure is indicated by the OF flag although VOUT was assumed to be stable and higher than VOF
(can be cleared to 0 by software).
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Hint:



RV-2251-C3
When VDD is rising from 0 V, VOUT follows about the half of VDD voltage level (over SW1 protective diode).
Once VOUT has reached VOF, RV-2251-C3 switches to VBAT (SW1 = OFF, SW2 = ON) and VOUT follows
VBAT. After VDD rising over VDET1R, VOUT follows VDD voltage level.
During POR, flags can be read, but the read values are not valid!
Be aware that the oscillation halt sensing circuit OF will detect also very short voltage drop on VOUT pin:
o In some cases 1 µF to VOUT pin if needed.
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4.3.2.VIO MONITORING CIRCUIT
The VIOL is the VIO Peripheral Supply Monitoring Result Output pin that is informing the MCU about the state of the
2
I C interface. The VIO supply voltage monitor circuit is always in operation. When VIO is rising over VDET2R and after
2
2
tDELAY, VIOL outputs HIGH and I C access is enabled. When VIO falling beyond VDET2F, VIOL outputs LOW and the I C
access is disabled.
Note that the VIO monitoring function is only available if VOUT is between 1.0 V and 5.5 V.
VIO monitoring:
VDET2R
VDET2R
VDET2R
VDET2F
VDET2F
VIO
0V
0V
VIOL
0V
0V
tDELAY
tDELAY
I2C access
disabled
tDELAY
2
1
enabled
disabled
en.
disabled
enabled
Condition:
VOUT is between 1.0 V and 5.5 V.
1
2
2
When VIO is higher than VDET2R (typically 1.77 V) and after a typical delay time tDELAY = 105 ms the I C access
is enabled and VIOL is off (HIGH).
2
When VIO is lower than VDET2F, I C access is disabled immediately and VIOL is tied LOW.
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4.3.3.VIO LEVEL SHIFTER
Due to the level shifter the MCU interface access using the VIO peripheral supply is independent from the internal
2
supply output voltage VOUT for the RTC in timekeeping mode. The VIO voltage supplies the two I C lines and the
output pins VIOL and INT over pull up resistors and the push-pull output pin CLKOUT (32.768 kHz).
Note that the VIO monitoring function is only available if VOUT is between 1.0 V and 5.5 V.
2
I C-bus interface accessibility:
6
5.5 V
VIO:ACC
5
VIO [V]
4
3
2
VDET2
1
0
0
1
1.0 V
2
3
VOUT [V]
4
5
6
5.5 V
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4.3.4.VBAT MONITORING CIRCUIT
The VBAT backup supply voltage monitoring circuit is configured to conduct sampling operation during an interval of
7.8 ms per second to check for a drop in battery supply voltage below a threshold voltage VBLF (typ. = 1.35 V), thus
minimizing supply current requirements as illustrated in the timing chart below. This circuit suspends a sampling
operation once the BLF flag is set to 1 (register Control2). The VBAT supply voltage monitor is useful for back-up
battery checking.
VBAT monitoring:
VOUT = VBAT
VBLF
VOF
1
PON
3
1s
sampling VBAT
5
7.8 ms
BLF
4
Internal initialization
period (1 to 2 sec.)
Power state
6
2
POR
VDD Power or VBAT Power
Write operation
1
2
3
4
5
6
The PON flag is set to 1 when VOUT was started from 0 V and the 32.768 kHz oscillator is running.
The BLF flag is set to 1 and valid after internal initialization period (1 to 2 seconds) doe to sampling VBAT.
After the internal initialization period both flags (PON and BLF) can be cleared to 0 by software.
The backup monitoring circuit detects that VBAT is lower than VBLF and sets the BLF flag to 1.
As long as BLF is set, VBAT is not sampled by the monitoring circuit to minimize supply current.
After the BLF flag is cleared to 0 by software the monitoring circuit begins with sampling VBAT again.
Hint:
During the interval of 7.8 ms the typical current sensing peak is I VBAT:VSP = 900 nA. The typical IVBAT average current
when VBAT is sampled can be calculated as follows:
IVBAT_Average = ((IVBAT:VSP * 7.8 ms) + (IVBAT_Sampling OFF * (1 s – 7.8 ms))) / 1 s
= ((900 nA * 7.8 ms) + (210 nA * 992.2 ms )) / 1 s
= 215 nA
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4.4. RTC COUNTER ACCESS
The following Figure shows the data flow and data dependencies starting from the 1 Hz clock tick.
Data flow for the time function:
1 Hz tick
SECONDS
MINUTES
12_24 hour mode
HOURS
LEAP YEAR
CALCULATION
DATE
WEEKDAY
MONTHS
YEARS
Caution:
When one of the RTC registers is written or read, the contents of all time counters are frozen for up to 0.5 second.
To guarantee that either read or write timer value is consistent, a single burst should be limited to < 0.5 seconds.
Therefore, when communicating with the RV-2251-C3 module, the series of operations from transmitting the
START (or repeated START) condition to transmitting the STOP (or repeated START) condition should occur
2
within 0.5 second. If this series of operations requires 0.5 second or more, the I C bus interface will be
automatically cleared and set to standby mode by the bus timeout function of the RV-2251-C3 module.
Note with caution that both write and read operations have to be regarded as invalid when occurred during or
after this auto clearing operation.
Restarting of communications begins with transfer of the START condition again.
Access time for read/write operations:
t < 0.5 s
P
SDA
SDA
Sr
SCL
SCL
S
or
Sr
P
or
Sr
START or
repeated START
condition
STOP or
repeated START
condition
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4.5. INTERRUPT SUMMARY
The interrupt pin ̅̅̅̅̅
INT can be triggered by the Periodic Time Update Interrupt signal and by the Alarm_W and
Alarm_D signals:
 PERIODIC TIME UPDATE INTERRUPT FUNCTION
 ALARM FUNCTIONS
Interrupt scheme:
USEL
PERIODIC TIME
UPDATE
GENERATOR
CLEAR
check now signal
to interface:
read UF
UPDATE FLAG
UF
SET
0/1
PULSE
GENERATOR
TRIGGER
from interface:
clear UF
MIN. ALARM_W
=
MINUTE TIME
HR. ALARM_W
=
0
AND
&
1
0
HOUR TIME
1
from interface:
clear WF
=
WEEKDAY
ALARM_W
FLAG WF
SET
MIN. ALARM_D
=
0
AND
&
1
0
MINUTE TIME
1
OR
≥1
to interface:
read DF
ALARM_D
FLAG DF
SET
CLEAR
1
HR. ALARM_D
=
INT
CLEAR
AE_D
check now signal
OR
≥1
1
WD. ALARM_W
HOUR TIME
to interface:
read WF
AE_W
from interface:
clear DF
OR
≥1
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4.6. PERIODIC TIME UPDATE INTERRUPT FUNCTION
The RV-2251-C3 incorporates the Periodic Time Update Interrupt circuit configured to generate periodic interrupt
signals on pin INT. In the Pulse Mode the frequencies of 2 Hz and 1 Hz can be selected. In Level Mode the
frequencies of 1 Hz, 1/60 Hz (once per 1 minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every
month) can be selected. The condition of periodic time update interrupt signals can be monitored by reading
(polling) the update flag UF (see CONTROL REGISTERS, Fh – Control2).
Periodic Time Update Interrupt selection field USEL:
USEL
USEL-Mode
000
001
010
011
100
101
110
111
Pulse
Pulse
Level
Level
Level
Level
INT Frequency
OFF (INT = HIGH) – Default value
Always ON (INT = LOW) (1)
2 Hz (2) (3)
1 Hz (2) (3)
Every second (3)
Every minute
Every hour
Every month
(1) When USEL = 001b the flag UF cannot be reset to 0.
(2) Duty cycle = 50%
(3) In Pulse Mode the 2 Hz and 1 Hz clock pulses and in Level Mode the 1 Hz signal can be affected by compensation pulses
(see FREQUENCY OFFSET COMPENSATION).
When the offset adjustment is used, the interrupt cycle will fluctuate once per 20 seconds or 60 seconds as follows:
 Pulse Mode: The HIGH period of the INT output pulses will increment or decrement by a maximum of
±3.784 ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.
 Level Mode: A periodic time update interrupt of 1 second will increment or decrement by a maximum of
±3.784 ms.
Hint:
Maximum correction once per 20 seconds or 60 seconds:
 Offset Mode = 0 (maximum range = ±189 ppm):

 Offset Mode = 1 (maximum range = ±63 ppm):

20 s * ±189 ppm = ±3.784 ms
60 s * ±63 ppm = ±3.784 ms
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4.6.1.PULSE MODE
Pulse Mode: 2-Hz and 1-Hz clock pulses are outputted in synchronization with the increment of the seconds
counter as illustrated in the timing chart below.
Diagram of the Periodic Time Update Interrupt function in Pulse Mode (example with 1 Hz):
USEL
1
INT
4
UF
3
event
2
increment of
seconds counter
5
period
tDELAY
Seconds register
approx.
46 µs
Write operation
1
2
3
4
5
6
period
6
period
tDELAY
approx.
46 µs
rewriting
Seconds
register
tDELAY
approx.
46 µs
Set USEL field to 010b or 011b to enable 2-Hz respective 1-Hz periodic time update interrupt function in
pulse mode.
A Periodic Time Update Interrupt event occurs when the internal clock value matches either the seconds or
0.5 seconds update time. Note, that the increment of the Seconds register is delayed be approximately
46 µs.
When a Periodic Time Update Interrupt occurs, the UF bit is set to 1.
If the USEL field is in pulse mode and a Periodic Time Update Interrupt occurs, the INT pin output goes low.
Rewriting the seconds counter will reset the other time counters of less than 1 second, driving the INT pin
low.
If the USEL field value is set to 000b, the INT pin is disabled (stay/goes HIGH).
In the pulse mode, the increment of the Seconds register value is delayed by approximately 46 µs from the falling
edge of INT pulses. Consequently, time readings immediately after the falling edge of the INT pulses may appear
with a lag of 1 second behind the real-time counts. Rewriting the seconds counter will reset the other time counters
of less than 1 second, driving the INT pin low.
Note:
In Pulse Mode the 2 Hz and 1 Hz clock pulses can be affected by compensation pulses (see FREQUENCY
OFFSET COMPENSATION).
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4.6.2.LEVEL MODE
Level Mode: Periodic Time Update Interrupt signals are output with selectable interrupt cycle settings of 1 second,
1 minute, 1 hour, and 1 month. The increment of the seconds counter is synchronized with the falling edge of
periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are
output in synchronization with the increment of the seconds counter as illustrated in the timing chart below.
Diagram of the Periodic Time Update Interrupt function in Level Mode:
USEL
1
INT
4
UF
3
event
2
increment of
seconds counter
5
7
6
period
period
8
period
Write operation
1
2
3
4
5
6
7
8
Set USEL field to 100b, 101b, 110b or 111b to enable second, minute, hour or monthly Periodic Time Update
Interrupt function in level mode. Note, that the moment right after writing to USEL, INT pin can become LOW
in a very short time. In such a case, ignore it or confirm it by clearing UF flag.
A Periodic Time Update Interrupt event occurs when the internal clock value matches either seconds,
minutes, hours or month update time.
When a Periodic Time Update Interrupt occurs, the UF bit is set to 1.
When UF bit is set, the INT pin output goes low.
If the INT pin is low, its status changes as soon as the UF flag is cleared from 1 to 0.
No interrupt occurs because the UF flag was not set back to 0.
The UF flag retains 1 until it is cleared to 0 by software.
If the USEL field value is set to 000b, the INT pin is disabled (stay/goes HIGH).
Note:
In Level Mode the 1 Hz signal can be affected by compensation pulses (see FREQUENCY OFFSET
COMPENSATION).
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4.6.3.USE OF THE PERIODIC TIME UPDATE INTERRUPT
Field and bit related to the Periodic Time Update Interrupt function:


USEL field (see CONTROL REGISTERS, Eh - Control1)
UF bit (see (see CONTROL REGISTERS, Fh – Control2)
Prior to entering any other settings, it is recommended to write a 000b to the USEL field to prevent inadvertent
interrupts on INT pin.
Procedure to use the Periodic Time Update Interrupt function:
1. Initialize field USEL to 000b and bit UF to 0.
2. Choose and enable the frequency and mode by writing the corresponding value to the USEL field.
a. In Pulse Mode the first interrupt occurs when the internal clock value matches either the seconds
or the 0.5 seconds update time.
b. In Level Mode the first interrupt occurs when the internal clock value matches either seconds,
minutes, hours or month update time. Confirm it by writing 0 to the UF flag to be prepared for a
next event.
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4.7. ALARM FUNCTIONS
The RV-2251-C3 incorporates the Alarm Interrupt circuit configured to generate interrupt signals to the MCU at
preset times. The Alarm Interrupt circuit allows two types of alarm settings specified by the Alarm_W registers
(pointers 8h, 9h and Ah, see ALARM_W REGISTERS) and the Alarm_D registers (pointers Bh and Ch, see
ALARM_D REGISTERS). The Alarm_W registers allow weekdays, hours, and minutes alarm settings including
combinations of multiple weekday settings such as Monday, Wednesday and Friday, Saturday and Sunday. The
Alarm_D registers allow hour and minute alarm settings. The Alarms output to INT pin. Each alarm function can be
checked from the MCU by reading (polling) the alarm flags WF and DF (see CONTROL REGISTERS, Fh –
Control2). When the comparisons first match, the flags are set logic 1.




The INT pin always follows the conditions of the flags WF and DF linked with logic OR.
The WF and DF flags accept only the writing of 0.
If the bits AE_W and AE_D are set to 1 the WF and DF flags indicate alarm events. The events are
generated approximately 15 µs after any match between current time and preset alarm time specified by
the Alarm_W and Alarm_D registers. Once WF and DF have been cleared, they will only be set again
when the time increments to match an alarm condition once more.
If the bits AE_W and AE_D are reset to 0 the alarm interrupt circuits are disabled and the flags WF and DF
always read out 0 (see following ALARM DIAGRAM).
4.7.1.ALARM DIAGRAM
Diagram of the Alarm Interrupt functions:
AE_W (AE_D)
1
INT
4
WF (DF)
3
event
5
7
6
2
alarm
alarm
tDELAY
approx.
15 µs
alarm
8
alarm
tDELAY
approx.
15 µs
Write operation
1
2
3
4
5
6
7
8
Set AE_W (AE_D) to 1 to enable the corresponding Alarm Interrupt function.
An Alarm Interrupt event occurs when the selected Alarm registers match the respective counters.
When an Alarm Interrupt event occurs, the WF (DF) flag is set to 1.
̅̅̅̅̅ pin output goes low.
If the AE_W (AE_D) bit is 1 and an Alarm Interrupt occurs, the INT
̅̅̅̅̅
If the INT pin is low, its status changes as soon as the WF (DF) flag is cleared from 1 to 0.
No interrupt occurs because the WF (DF) flag was not set back to 0.
The WF (DF) flag retains 1 until it is cleared to 0 by software.
If the AE_W (AE_D) bit value is 0 when an Alarm event occurs, the ̅̅̅̅̅
INT pin status does not go low.
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4.7.2.USE OF THE ALARM INTERRUPTS
Registers and bits related to the two Alarm Interrupt functions Alarm_W and Alarm_D:
Alarm_W:
 Minutes Register (1h) (see TIME AND DATE REGISTERS)
 Hours Register (2h) (see TIME AND DATE REGISTERS)
 Weekday Register (3h) (see TIME AND DATE REGISTERS)
 Alarm_W Minutes (8h) (see ALARM_W REGISTERS)
 Alarm_W Hours (9h) (see ALARM_W REGISTERS)
 Alarm_W Weekdays (Ah) (see ALARM_W REGISTERS)
 AE_W bit (see CONTROL REGISTERS, Eh - Control1)
 WF flag (see (see CONTROL REGISTERS, Fh – Control2)
Alarm_D:
 Minutes Register (1h) (see TIME AND DATE REGISTERS)
 Hours Register (2h) (see TIME AND DATE REGISTERS)
 Alarm_D Minutes (Bh) (see ALARM_D REGISTERS)
 Alarm_D Hours (Ch) (see ALARM_D REGISTERS)
 AE_D bit (see CONTROL REGISTERS, Eh - Control1)
 DF flag (see (see CONTROL REGISTERS, Fh – Control2)
Prior to entering any timer settings for an Alarm Interrupt, it is recommended to write a 0 to the AE_W (AE_D) bit to
prevent inadvertent interrupts on INT pin.
Procedure to use the Alarm Interrupt functions:
1. Initialize bit AE_W (AE_D) and flag WF (DF) to 0.
2. Write the desired alarm settings in registers with pointers 8h, 9h and Ah (Bh and Ch).
3. Set the AE_W (AE_D) bit to 1 to enable the corresponding Alarm Interrupt function.
4.8. SERVICING INTERRUPTS
The INT pin can indicate three types of interrupts. It outputs the logic OR operation result of these interrupt outputs.
When an interrupt is detected, (when the INT pin is at low level), the UF, WF and DF flags can be read to
determine which interrupt event has occurred.
The INT pin is always connected to the OR’ed flag signals and cannot be disconnected separately. To check
whether an event has occurred without monitoring the INT pin, software can read the UF, WF and DF interrupt
flags (polling).
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4.9. FREQUENCY OFFSET COMPENSATION
The RV-2251-C3 incorporates an Offset register (see OFFSET REGISTER, 7h – Offset Register) which can be
used by customer to compensate the frequency offset of the 32.768 kHz oscillator which allows implementing
functions, such as:
 Improve time accuracy
 Aging compensation
7h – Offset Register:
Address Pointer
Function
Bit 7
Bit 6
7h
Offset
Reset
MODE
0
Bit
Symbol
Value
7
MODE
6:0
0
1
-62 to
+62
OFFSET
OFFSET
0111111
0111110
:
0000011
0000010
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
OFFSET
0
0
0
0
0
Description
Offset Mode
Normal Mode: Offset is compensated every 20 seconds (at 00, 20 and 40).
Slow Mode: Offset is compensated every minute (at seconds = 00).
Defines compensation pulses in steps.
For MODE = 0, each pulse introduces a deviation of 3.052 ppm, the
maximum range is ±189 ppm.
For MODE = 1, each pulse introduces a deviation of 1.017 ppm, the
maximum range is ±63 ppm.
The values of 3.052 ppm and 1.017 ppm are based on a nominal 32.768
kHz clock (see FREQUENCY OFFSET COMPENSATION).
CLKOUT frequency deviation
in ppm(2)
Normal Mode
Slow Mode
MODE = 0
MODE = 1
+189.209
+63.070
+186.157
+62.052
:
:
+6.104
+2.035
+3.052
+1.017
OFFSET
compensation value
in decimal
Converting
(mathematical
operation)
Compensation
pulses
in steps
-1
-1
:
-1
-1
+62
+61
:
+2
+1
×0
0
0
0
Two’s complement
Two’s complement
:
Two’s complement
Two’s complement
-1
-2
:
-61
-62
-3.052
-6.104
:
-186.157
-189.209
-1.017
-2.035
:
-62.052
-63.070
×0
0
0
0
0000001
0000000
1111111
1111110
:
1000011
1000010
(1)
(1)
+63
+62
:
+3
+2
+1
0
1000001
(1)
+127
+126
:
+67
+66
+65
1000000
(1)
+64
(1) The OFFSET values X00000X mean no correction steps are done (X representing 0 or 1) and the offset circuit is disabled. With this
converting method a symmetrical structure of ±62 correction steps can be guaranteed.
(2) For MODE = 0, each compensation pulse corresponds to 1/(32768×10) = 3.052 ppm. For MODE = 1 it is 1/(32768×30) = 1.017 ppm.
The frequency deviation measured at CLKOUT pin can be compensated by computing the compensation value OFFSET and writing it into
the Offset register (see OFFSET COMPENSATION CALCULATION WORKFLOW).
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4.9.1.OFFSET COMPENSATION CALCULATION WORKFLOW
Offset compensation calculation workflow:
Example
Measure the frequency on pin CLKOUT:
fCLKOUT
32768.48 Hz
Compute the CLKOUT frequency deviation in ppm:
∆f/f [ppm] = ((fCLKOUT – 32768) / 32768) * 1’000’000
+14.648 ppm
Compute the CLKOUT offset pulses in steps:
MODE = 0 (Normal Mode):
Pulses = ∆f/f [ppm] / 3.052 ppm
+4.8

or
MODE = 1 (Slow Mode):
Pulses = ∆f/f [ppm] / 1.017 ppm
+14.4 
+5 compensation pulses
are needed
+14 compensation pulses
are needed
Compute the OFFSET compensation value:
If Pulses > +62 or < -62, fCLKOUT is out of range to be
corrected.
Else if 0 ≤ Pulses ≤ +62, set OFFSET = Pulses + 1
(1)
OFFSET = +5 + 1 = +6 (MODE = 0)
= +14 + 1 = +15 (MODE = 1)
Else if -62 ≤ Pulses ≤ -1, set OFFSET = Pulses + 128
(1)
See table column ‘Converting (mathematical operation)’ in section FREQUENCY OFFSET COMPENSATION.
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Result of the offset compensation (Example):
(1)
(2)
-2
0
2
4
6
8
10
12
14
16 ∆f/f [ppm]
Mode 1
Mode 0
Reachable accuracy zone
Measured/calculated
∆f/f [ppm] = 14.648 ppm
(32768.48 Hz)
With the offset compensation the accuracy of ±1.53 ppm (Mode 0) and ±0.51 ppm (Mode 1) (0.5 * offset per
puls) can be reached (see OFFSET REGISTER).
 ±1.53 ppm corresponds to a time deviation of 0.132 seconds per day.
 ±0.51 ppm corresponds to a time deviation of 0.044 seconds per day.
MODE = 0: Deviation after compensation = ∆f/f [ppm] – compensation pulses * 3.052 ppm
= 14.648 ppm – 5 * 3.052 ppm = -0.61 ppm
(2) MODE = 1: Deviation after compensation = ∆f/f [ppm] – compensation pulses * 1.017 ppm
= 14.648 ppm – 14 * 1.017 ppm = +0.41 ppm
(1)
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4.9.2.MEASURING TIME ACCURACY AT INT PIN
The offset circuit is configured to change time counts of 1 second on the basis of the settings of the Offset register
once in 20 seconds or 60 seconds. The offset circuit does not affect the frequency of 32.768 kHz-clock pulse
output from the CLKOUT pin. Therefore, after writing the Offset register, the clock deviation cannot be measured
with probing CLKOUT clock pulses. The way to measure the clock deviation is the following:
1. Select the Periodic Time Update Interrupt function with the frequency 1 Hz in Pulse Mode at the INT output
pin:
a. Initialize field USEL to 000b and bit UF to 0.
b. Choose and enable the frequency of 1 Hz in Pulse Mode by writing 011b to USEL.
c. The first interrupt occurs when the internal clock value matches the seconds update time.
2. After setting the Offset register, the 1Hz clock period changes every 20 seconds (or every 60 seconds) as
shown below.
1 Hz clock pulse on INT pin:
1
INT
T0
T0
T0
19 periods (MODE = 0) or 59 periods (MODE = 1)
1
T1
1 period
The HIGH level of the T1 pulse will increment or decrement by a maximum of ±3.784 ms.
3. Measure the T0 and T1 periods with a high-precision universal counter on INT output pin.
4. Calculate the average period TAVER to receive the time accuracy:
a. When MODE = 0:
TAVER = (19 * T0 + 1 * T1) / 20 s
b. When MODE = 1:
TAVER = (59 * T0 + 1 * T1) / 60 s
5. Calculate the new achieved frequency offset:
Frequency offset [ppm] = (
1
TAVER
- 1) * 1'000'000
Note:
If following three conditions are true, the actual offset value could be different from the target offset value that is set
in the Offset register:
1. Offset function is used.
2
2. I C read access to RV-2251-C3 at random, or synchronized with external clock that has no relation to RV2251-C3, or synchronized with Periodic Time Update Interrupt in pulse mode.
3. Access to RV-2251-C3 more than two times per each second on average.
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4.10. OSCILLATOR FAILURE DETECTION
When the oscillator of the RV-2251-C3 is stopped, the Oscillator failure flag OF is set. The oscillator is considered
to be stopped between power up and stable crystal oscillation (start-up time tSTART). This time can be in a range of
typical 100 ms to maximal 500 ms depending on temperature and supply voltage.
The flag remains set until cleared by command (see following Figure). If the flag cannot be cleared, then the
oscillator is not running. This method can be used to monitor the oscillator and to determine if the supply voltage
has reduced to the point where oscillation fails.
OF flag:
VIO
backup
supply
power up
main
supply
VOUT
VOF
VIOL
2
1
CLKOUT
OF
3
tSTART
Power state
POR
4
5
tDELAY
VDD Power or VBAT Power
POR
Write operation
1
2
3
4
5
VIOL goes HIGH but is not yet valid since VOUT is still 0 V.
At power up of VOUT, VIOL is tied low and indicating POR during the time tSTART + tDELAY
(typically 100 ms + 105 ms = 205 ms).
After tSTART the oscillation is stable and the flags OF (and POR) can be read, but the read values are not
valid.
After tSTART + tDELAY the flags are valid and can be cleared to 0 by software.
When VOUT is lower than VOF, the oscillator is stopped and RV-2251-C3 is again in POR power state.
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4.11. 32-KHZ CLOCK OUTPUT
The RV-2251-C3 includes a crystal oscillator which runs at 32.768 kHz. This frequency is always output to the
CLKOUT pin (CMOS push-pull) and the high level of the signal is equal to the VIO voltage.
4.12. ECO MODE
The ECO mode permits to lower the power consumption. When the ECO mode is activated (ECO pin is tied to
Ground) the timekeeping current consumption (in VDD and VBAT mode) is reduced and the oscillation frequency
might change slightly. The full time accuracy is guaranteed for the temperature range of 0 to 50°C.
If the ECO mode is deactivated (ECO is HIGH) the timekeeping current is little increased and the full time accuracy
is guaranteed over the complete temperature and voltage range.
Applications:
 ECO pin tied to Ground: The RV-2251-C3 is permanently in ECO mode.
 ECO pin connected to VOUT: The RV-2251-C3 is permanently in Non-ECO mode.
 ECO pin connected to VDD: The RV-2251-C3 is changing from Non-ECO to ECO mode when VDD is
shutting down and the RV-2251-C3 is supplied from VBAT. Depending of the circuitry a pull down resistor
(100 kΩ) for ECO pin may be needed.
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RV-2251-C3
5. I2C-BUS INTERFACE
2
The I C interface is for bidirectional, two-line communication between different ICs or modules. The RV-2251-C3 is
2
accessed at addresses 64h/65h, and supports Fast Mode (up to 400 kHz). The I C interface consists of two lines:
one bi-directional data line (SDA) and one clock line (SCL). Both lines are open drain and connected to the positive
peripheral supply VIO via pull-up resistors. Data transfer is initiated only when the interface is not busy. When VIO is
lower than VDET2F, access is disabled.
5.1. BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line remains stable during the HIGH
period of the clock pulse, as changes in the data line at this time are interpreted as a control signals. Data changes
should be executed during the LOW period of the clock pulse (see Figure below).
Bit transfer:
SDA
SCL
data line
stable;
data valid
change of
data
allowed
5.2. START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while
the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH transition of the data line, while the clock
is HIGH, is defined as the STOP condition (P) (see Figure below).
Definition of START and STOP conditions:
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
A START condition which occurs after a previous START but before a STOP is called a Repeated START
condition.
Hint:
To realize a Repeated START condition with RV-2251-C3, do not insert a STOP before a START condition;
otherwise the Address Pointer is automatically set to Fh.
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RV-2251-C3
5.3. DATA VALID
After a START condition, SDA is stable for the duration of the high period of SCL. The data on SDA may be
changed during the low period of SCL. There is one clock pulse per bit of data. Each data transfer is initiated with a
START condition and terminated with a STOP condition. The number of data bytes transferred between the
START and STOP conditions is not limited. The information is transmitted byte-wise and each receiver
acknowledges with a ninth bit.
5.4. SYSTEM CONFIGURATION
2
2
Since multiple devices can be connected with the I C bus, all I C bus devices have a fixed and unique device
address built-in to allow individual addressing of each device.
2
The device that controls the I C bus is the Master; the devices which are controlled by the Master are the Slaves. A
device generating a message is a Transmitter; a device receiving a message is the Receiver. The RV-2251-C3
acts as a Slave-Receiver or Slave-Transmitter.
2
Before any data is transmitted on the I C bus, the device which should respond is addressed first. The addressing
is always carried out with the first byte transmitted after the START procedure. The clock signal SCL is only an
input signal and only generated by a Master, but the data signal SDA is a bidirectional line.
System configuration:
SDA
SCL
MASTER
TRANSMITTER
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER
RECEIVER
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RV-2251-C3
5.5. ACKNOWLEDGE
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an acknowledge cycle.
 A slave receiver, which is addressed, must generate an acknowledge cycle after the reception of each
byte.
 Also a master receiver must generate an acknowledge cycle after the reception of each byte that has been
clocked out of the slave transmitter.
 The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and
hold times must be taken into consideration).
 A master receiver must signal an end of data to the transmitter by not generating an acknowledge cycle on
the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line
HIGH to enable the master to generate a STOP condition.
2
Data transfer and acknowledge on the I C bus:
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
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RV-2251-C3
5.6. SLAVE ADDRESS
2
2
On the I C-bus the 7-bit slave address 0110010b is reserved for the RV-2251-C3. The entire I C-bus slave address
byte is shown in the following table.
Slave address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
1
1
0
0
1
0
R/W
Bit 0
Transfer data
1(R)
0 (W)
65h (read)
64h (write)
2
After a START condition, the I C-bus slave address has to be sent to the RV-2251-C3 device. The R/W bit defines
the direction of the following single or multiple byte data transfer. The 7-bit address is transmitted MSB first. If this
address is 0110010b, the RV-2251-C3 is selected, the eighth bit indicates a read (R/W = 1) or a write (R/W = 0)
operation (results in 65h or 64h) and the RV-2251-C3 supplies the ACK. The RV-2251-C3 ignores all other address
values and does not respond with an ACK.
In the write operation, a data transfer is terminated by sending either the STOP condition or the START condition of
the next data transfer.
5.7. REGISTER ADDRESS
The 8-bit Register Address value that defines which register is to be accessed next is a combination of the 4-bit
Address Pointer and the 4-bit Transmission Format.
Address Pointer
Bit 7
Bit 6
Bit 5
Transmission Format
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
0
0
0
1
0
1
0h to Fh
Usage
The Transmission Format is always 0000b
(see WRITE OPERATION and
NORMAL READ AT SPECIFIC ADDRESS)
The Transmission Format is 0100b or 0101b.
Both values are equivalent (see POWER
SAVING READ AT SPECIFIC ADDRESS)
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RV-2251-C3
5.8. WRITE OPERATION
Master transmits to Slave-Receiver at specified address. The 8-bit Register Address value that defines which
register is to be accessed next is a combination of the 4-bit Address Pointer and the 4-bit Transmission Format. For
the write operation the Transmission Format must always be 0000b. After writing one byte, the Address Pointer is
automatically incremented by 1.
Master writes to slave RV-2251-C3 at specific address:
5)
6)
7)
8)
9)
Master sends out the START condition.
Master sends out Slave Address, 64h for the RV-2251-C3; the R/W bit is a 0 indicating a write operation.
Acknowledgement from RV-2251-C3.
Master sends out the 4-bit Address Pointer and the 4-bit Transmission Format to RV-2251-C3.
For the write operation the Transmission Format must always be 0000b.
Acknowledgement from RV-2251-C3.
Master sends out the Data to write to the specified address in step 4).
Acknowledgement from RV-2251-C3.
Steps 6) and 7) can be repeated if necessary.
The Address Pointer is automatically incremented in the RV-2251-C3.
Master sends out the STOP Condition.
1
2
S
SLAVE ADDRESS
3
0 A
R/W
1)
2)
3)
4)
4
ADDRESS
POINTER
TRANSMI.
FORMAT
5
6
7
8
A
DATA
A
DATA
9
A
P
Acknowledge from RV-2251-C3
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5.9. READ OPERATION
5.9.1.NORMAL READ AT SPECIFIC ADDRESS
Master reads data from slave RV-2251-C3 at specific address:
1)
2)
3)
4)
Master sends out the START condition.
Master sends out Slave Address, 64h for the RV-2251-C3; the R/W bit is a 0 indicating a write operation.
Acknowledgement from RV-2251-C3.
Master sends out the 4-bit Address Pointer and the 4-bit Transmission Format to RV-2251-C3.
For the normal write operation the Transmission Format must always be 0000b.
5) Acknowledgement from RV-2251-C3.
6) Master sends out the Repeated START condition. Do not insert a STOP before a START condition;
otherwise the Address Pointer is automatically set to Fh.
7) Master sends out Slave Address, 65h for the RV-2251-C3; the R/W bit is a 1 indicating a read operation.
8) Acknowledgement from RV-2251-C3.
At this point, the Master becomes a Receiver and the Slave becomes the Transmitter.
9) The Slave sends out the Data from the Address specified in step 4).
10) Acknowledgement from Master.
11) Steps 9) and 10) can be repeated if necessary.
The Address Pointer is automatically incremented in the RV-2251-C3.
12) The Master, addressed as Receiver, can stop data transmission by not generating acknowledge on the last
byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the
data line HIGH to enable the Master to generate a STOP condition.
13) Master sends out the STOP condition.
SLAVE ADDRESS
3
0 A
4
ADDRESS
POINTER
TRANSMI.
FORMAT
5
6
7
A
Sr
SLAVE ADDRESS
Repeated
START
Acknowledge from RV-2251-C3
8
1 A
9
10
11
DATA
A
DATA
12 13
A
P
R/W
S
2
R/W
1
Acknowledge from Master
No acknowledge from Master
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5.9.2.POWER SAVING READ AT SPECIFIC ADDRESS
This method of reading data from the internal register is started by reading immediately at specific address after
writing to the 4-bit Address Pointer and the 4-bit Transmission Format field. Although this method is not based on
2
I C-bus standard in a strict sense it is very effective to shorten read time and so to minimize MCU workload. Write
4h or 5h (010Xb) to the Transmission Format when this method is used.
Master reads data from slave RV-2251-C3 at specific address in power saving method:
1)
2)
3)
4)
Master sends out the START condition.
Master sends out Slave Address, 64h for the RV-2251-C3; the R/W bit is a 0 indicating a write operation.
Acknowledgement from RV-2251-C3.
Master sends out the 4-bit Address Pointer and the 4-bit Transmission Format to RV-2251-C3.
For the power saving write operation the Transmission Format must always be 0100b or 0101b.
5) Acknowledgement from RV-2251-C3.
At this point, the Master becomes a Receiver and the Slave becomes the Transmitter.
6) The Slave sends out the Data from the Address specified in step 4).
7) Acknowledgement from Master.
8) Steps 6) and 7) can be repeated if necessary.
The Address Pointer is automatically incremented in the RV-2251-C3.
9) The Master, addressed as Receiver, can stop data transmission by not generating acknowledge on the last
byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the
data line HIGH to enable the Master to generate a STOP condition.
10) Master sends out the STOP condition.
S
2
SLAVE ADDRESS
3
0 A
4
ADDRESS
POINTER
TRANSMI.
FORMAT
5
6
7
8
9
10
A
DATA
A
DATA
A
P
R/W
1
Acknowledge from RV-2251-C3
Acknowledge from Master
No acknowledge from Master
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5.9.3.READ IMMEDIATELY
This method of reading data from the internal register is to start reading immediately after writing the Slave Address
and setting R/W bit to 1. Since the Address Pointer is set to Fh by default because of a previous STOP condition,
this method is only effective when reading is started from Address Fh.
Master reads data from slave RV-2251-C3 immediately after first byte:
1) Master sends out the START condition.
2) Master sends out Slave Address, 65h for the RV-2251-C3; the R/W bit is a 1 indicating a read operation.
3) Acknowledgement from RV-2251-C3.
At this point, the Master becomes a Receiver and the Slave becomes the Transmitter.
4) The RV-2251-C3 sends out the Data from the last accessed Register Address incremented by 1.
5) Acknowledgement from Master.
6) Steps 4) and 5) can be repeated if necessary.
The address is automatically incremented in the RV-2251-C3.
7) The Master, addressed as Receiver, can stop data transmission by not generating acknowledge on the
last byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the
data line HIGH to enable the Master to generate a STOP condition.
8) Master sends out the STOP condition.
2
3
S
SLAVE ADDRESS
1 A
4
5
DATA
A
6
DATA
7
8
A
P
R/W
1
Acknowledge from RV-2251-C3
Acknowledge from Master
No acknowledge from Master
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6. ELECTRICAL SPECIFICATIONS
6.1. ABSOLUTE MAXIMUM RATINGS
The following Table lists the absolute maximum ratings.
Absolute Maximum Ratings according to IEC 60134:
SYMBOL
PARAMETER
CONDITIONS
Peripheral Supply (I2C, CLKOUT)
Backup Power Supply
Main RTC Power Supply
Power supply current
Input voltage
Output voltage 1
Output voltage 2
Output voltage 3
Output current
Input current
Total power dissipation
Pins SCL, SDA and ECO
Pins SDA, INT and VIOL
Pin CLKOUT
Pins VOUT and VREG
VOUT and VREG
At any input
TOPR = 25°C
VESD
Electrostatic discharge
Voltage
HBM
CDM
ILU
TOPR
TSTO
TPEAK
Latch-up current
Operating temperature
Storage temperature
Maximum reflow condition
VIO
VBAT
VDD
IDD
VI
VO
IO
II
PTOT
MIN
MAX
UNIT
-0.3
-0.3
-0.3
-50
-0.3
-0.3
-0.3
-0.3
6.5
6.5
6.5
50
6.5
6.5
VIO +0.3
VDD +0.3
10
10
300
±1500
±1000
100
85
125
265
V
V
V
mA
V
V
V
V
mA
mA
mW
V
V
mA
°C
°C
°C
-10
(1)
(2)
(3)
Stored as bare product
JEDEC J-STD-020C
-40
-55
(1) HBM:
Human Body Model, according to JESD22-A114.
Charged-Device Model, according to JESD22-C101.
(3) Latch-up testing, according to JESD78, at maximum ambient temperature (T
A(max))
(2) CDM:
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RV-2251-C3
6.2. OPERATING PARAMETERS
For this Table, VSS = 0 V; VIO = 3.0 V; VDD = 3.3 V; VBAT = 3.0 V; TA = -40 °C to +85 °C; fOSC= 32.768 kHz; TYP
values at 25 °C; unless otherwise indicated.
Operating Parameters:
SYMBOL
Supplies
VDD:SUP
VIO:ACC
VOUT:TK
VOUT:TKM
VOF
VPUP
VBLF
VDET1R
VDET1F
VDET1H
VDET2R
VDET2F
VDET2H
tDELAY
VREG
∆VDET1,2
∆TA
∆VREG
∆TA
IBAT:TK1
IBAT:TK2
IDD
IIO
IDD:I2C
IIO:I2C
(1)
(2)
PARAMETER
VDD Power Supply
VIO Peripheral Supply
Timekeeping voltage
Minimum timekeeping voltage
Oscillation failure voltage
Pull-up voltage
Backup voltage threshold
Voltage detector 1 threshold;
rising edge
Voltage detector 1 threshold;
falling edge
Voltage detector 1 threshold;
hysteresis
Voltage detector 2 threshold;
rising edge
Voltage detector 2 threshold;
falling edge
Voltage detector 2 threshold;
hysteresis
Output Delay Time of
Voltage detector 2
Voltage regulator output
Voltage detector threshold
temperature coefficients
Regulated voltage temperature
coefficient
VBAT timekeeping current 1;
ECO mode on (ECO = LOW),
BLF = 1 (monitoring off)
VBAT timekeeping current 2;
ECO mode off (ECO = HIGH)
BLF = 1 (monitoring off)
VDD stand-by current
VIO stand-by current
VDD supply current during I2C
burst read/write
VIO supply current during I2C
burst read/write
CONDITIONS
MIN
RTC supplied by VDD
Interface accessible
TYP
VDET1F
VDET2F
0.9
UNIT
V
V
V
V
V
V
V
1.20
1.35
5.5
5.5
5.5
0.9
0.9
5.5
1.50
2.69
2.78
2.87
2.62
2.70
2.78
0.7
0.7
VOUT ≤ VOF, OF flag is set to 1
Pins INT and VIOL
Pin VBAT; TA = -30 to +70°C
MAX
V
Pin VDD; TA = 25°C
80
mV
1.67
1.77
1.86
1.61
1.70
1.79
V
Pin VIO; TA = 25°C
VOUT = 1.0 V to 5.5 V
65
Pin VIOL; VOUT = 1.0 V to 5.5 V
Pin VREG; TA = 25°C;
VDD = 3.3 V; IO = 1.0 mA
Pins VDD and VIO;
TA = -40 °C to +85 °C
Pin VREG;
TA = -40 °C to +85 °C
VBAT = 3.0 V; VDD = VIO = 0 V;
TA = -40 °C to +85 °C
VBAT = 3.0 V; VDD = VIO = 0 V;
TA = -30 °C to +70 °C
VBAT = 3.0 V; VDD = VIO = 0 V;
TA = -40 °C to +85 °C
VBAT = 3.0 V; VDD = VIO = 0 V;
TA = -30 °C to +70 °C
VDD = 3.3 V
VIO = 3.0 V
mV
100
105
110
ms
2.92
3.00
3.08
V
±100
ppm/°C
±100
ppm/°C
650
(1)
210
nA
500
(1)
800
(1)
270
VDD = 3.3 V, VIO = 3.0 V
400 kHz bus speed, 2.2k pull-up
(2)
resistors on SCL/SDA
nA
650
(1)
1.3
2.7
µA
µA
14
25
3
10
µA
SCL = SDA = 0 V; CLKOUT = OPEN
2.2k pull-up resistors on SCL/SDA, excluding external peripherals and pull-up resistor current. All other inputs (besides SDA and SCL) are
at 0 V or VDD. Test conditions: Continuous burst read/write, 55h data pattern, 25 μs between each data byte, 20 pF load on each bus pin.
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For this Table, VSS = 0 V; VIO = 3.0 V; VDD = 3.3 V; VBAT = 3.0 V; TA = -40 °C to +85 °C; fOSC= 32.768 kHz; TYP
values at 25 °C; unless otherwise indicated.
Operating Parameters (continued):
SYMBOL
PARAMETER
Inputs
VIL:I2C
VIH:I2C
VIL:ECO
VIH:ECO
LOW level input voltage
HIGH level input voltage
LOW level input voltage
HIGH level input voltage
ILEAK
Input leakage current
CI
Outputs
Input capacitance
IOH:CLKOUT
IOL:CLKOUT
IOL:INT
IOL:SDA
IOL:VIOL
IOZ
(3)
HIGH level output current;
Pin CLKOUT
LOW level output current;
Pin CLKOUT
LOW level output current;
Pin INT
LOW level output current;
Pin SDA
LOW level output current;
Pin VIOL
Output Off-state current
CONDITIONS
Pins SCL and SDA;
VIO = VDET2F to 5.5 V
Pin ECO
Pins SCL, SDA; VIO = 5.5 V
Pin ECO; VI = VSS or 5.5 V
Pins SCL, SDA and ECO
VOH:CLKOUT = VIO - 0.5 V
MIN
TYP
MAX
UNIT
-0.3
0.8 VIO
-0.3
VOUT - 0.3
0.2 VIO
VIO
0.3
5.5
V
V
V
V
-0.2
0.2
µA
7
pF
-0.5
mA
0.5
VOL = 0.4 V
2.0
mA
3.0
(3)
VIO = VDD = VBAT = 1.5 V
VOL = 0.4 V
Pin SDA; VIO = 5.5 V
Pins INT and VIOL ; VO = VSS or
5.5 V
0.5
-0.2
0.2
µA
VIO < VDET2F
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Real-Time Clock / Calendar Module
RV-2251-C3
6.3. TYPICAL CHARACTERISTICS
Figure 1. Timekeeping current IBAT vs. Supply voltage VBAT: BLF not set back (no VBAT sampling), TA = 25°C
Test circuit
350
300
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
V
CLKOUT
BAT
VOUT
SCL
SCA
VSS
ECO off
IBAT [nA]
250
200
ECO on
150
100
ECO on
ECO off
A
0.1 µF
50
0
0
1
2
4
3
5
6
VBAT [V]
Figure 2. Stand-by current IDD vs. Supply voltage VDD: TA = 25°C
2.0
Test circuit
1.8
1.6
IDD [µA]
1.4
A
1.2
0.1 µF
1.0
0.8
VREG = VDD , ECO off
VREG = VDD , ECO on
0.6
0.4
VREG = open, ECO off
VREG = open, ECO on
0.2
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
ECO off
ECO on
0.1 µF
0
0
1
2
3
4
5
6
VDD [V]
Figure 3. Stand-by current IIO vs. Supply voltage VIO: VDD = 3.3 V (for VIO monitoring and 32 kHz), TA = 25°C
6
Test circuit
5
3.3 V
IIO [µA]
4
3
A
2
1
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
V
SCL
OUT
SCA
VSS
0.1 µF
0.1 µF
0
0
1
2
3
4
5
6
VIO [V]
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
Figure 4. Timekeeping current IBAT vs. Ambient temperature TA: VBAT = 3 V, VDD = 0 V
Test circuit
400
350
3.3 V
ECO off
IBAT [nA]
300
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
POR
250
200
ECO on
150
100
ECO on
ECO off
A
3V
0.1 µF
50
0
-50
-25
0
25
50
75
100
TA [°C]
Figure 5. Stand-by current IDD vs. Ambient temperature TA: VDD = 3.3 V, VBAT = open
2.0
Test circuit
1.8
1.6
3.3 V
IDD [µA]
1.4
A
1.2
0.1 µF
1.0
0.8
0.6
0.4
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
0.1 µF
0.2
0
-50
-25
0
25
50
75
100
TA [°C]
Figure 6. Stand-by current IIO vs. Ambient temperature TA: VIO = 3.0 V, VDD = 3.3 V (for VIO monitor.), VBAT = open
2.0
Test circuit
1.8
1.6
3.3 V
IIO [µA]
1.4
1.2
3V
1.0
A
0.8
0.6
0.4
0.2
0
-50
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
0.1 µF
0.1 µF
-25
0
25
50
75
100
TA [°C]
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
Figure 7. MCU access current IIO/IDD vs. SCL clock frequency fSCL: See conditions in section 6.2, TA = 25°C
16
Test circuit
14
IIO, IDD [µA]
12
V IO
DD
=V
.
=3
10
3V
IDD
A
5V
8
A
5V
6
MCU
IIO
4
2.2 kΩ
2
2.2 kΩ
3V
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
0.1 µF
0.1 µF
0
0
50
100 150 200 250 300 350 400 450
fSCL [kHz]
Figure 8. Frequency deviation Δf/f vs. Supply voltage VDD = VBAT (normalized ECO on, 3 V): VIO = 3 V, TA = 25 °C
4
Test circuit
∆f/f [ppm]
2
ECO off
0
0.1 µF
ECO on
3V
-2
FREQUENCY
COUNTER
-4
-6
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
ECO off
ECO on
VIO
0.1 µF
0.1 µF
-8
0
1
2
3
4
5
6
VDD = VBAT [V]
VDET1 [V]
Figure 9. Detector threshold voltage (VDET1R/VDET1F) vs. Ambient temperature TA (VDD monitoring):
2.90
Test circuit
2.85
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
V
SCL
OUT
SCA
VSS
VDET1R
2.80
0.1 µF
V
3V
2.75
VDET1F
2.70
2.65
2.60
-50
VIO
A
3V
0.1 µF
0.1 µF
-25
0
25
50
75
100
TA [°C]
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
Figure 10. Detector threshold voltage (VDET2R/VDET2F) vs. Ambient temperature TA (VIO monitoring):
1.90
Test circuit
1.85
VDET2 [V]
3.3 V
1.80
0.1 µF
VDET2R
1.75
V
VDET2F
1.70
1.65
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
V
0.1 µF
0.1 µF
1.60
-50
-25
0
50
25
75
100
TA [°C]
Figure 11. Detector threshold voltage VBLF vs. Ambient temperature TA (VBAT monitoring):
1.50
Test circuit
1.45
3.3 V
0.1 µF
VBLF [V]
1.40
3V
1.35
MCU
1.30
1.25
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
VIO
0.1 µF
V
0.1 µF
0.1 µF
1.20
-50
-25
0
50
25
75
100
TA [°C]
Figure 12. VOUT vs. Output load current IOUT (voltage after regulator and SW1): VDD = 3.3 V, TA = 25 °C
3.05
Test circuit
3.3 V
3.00
VOUT [V]
0.1 µF
3V
2.95
2.90
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
VIO
0.1 µF
A
0.1 µF
V
0.1 µF
2.85
0
1
2
3
4
5
6
7
8
9
10
IOUT [mA]
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
Figure 13. VOUT - (VREG = VDD) vs. Output load current IOUT (voltage drop SW1, VDD > VDET1): TA = 25 °C
VOUT – (VREG = VDD) [V]
0
Test circuit
-0.02
V
-0.04
VREG = VDD = 5 V
0.1 µF
-0.06
3V
-0.08
3V
-0.10
-0.12
-0.14
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
VIO
0.1 µF
A
V
0.1 µF
-0.16
0
1
2
3
4
5
6
8
7
9
10
IOUT [mA]
Figure 14. VOUT - VBAT vs. Output load current IOUT (voltage drop SW2): TA = 25 °C
0
Test circuit
-0.05
VOUT – VBAT [V]
-0.10
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
VBAT = 3 V
-0.15
2V
-0.20
3V
-0.25
-0.30
1V
-0.35
-0.40
VIO
V
A
V
0.1 µF
-0.45
-0.50
0
1
2
3
4
5
6
8
7
9
10
IOUT [mA]
Figure 15. VOUT vs. VDD: Measured on falling edge of VDD (VDET1F = 2.70 V), VREG floating, TA = 25°C
3.5
Test circuit
3.0
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
0.1 µF
VOUT [V]
2.5
IOUT = 0 mA
3V
2.0
1.5
1 mA
5 mA
1.0
VIO
A
0.1 µF
V
10 mA
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VDD [V]
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
Figure 16. VOL:VIOL vs. IOL:VIOL (VIOL pin) : VIO < VDET2F (VDET2F = 1.70 V), VBAT = VDD = VIO = 1.5 V, TA = 25 °C
0.8
Test circuit
0.7
VOL:VIOL [V]
0.6
0.5
1.5 V
0.4
0.3
0.2
0.1
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
A
V
0.1 µF
0
2
1
0
4
3
5
6
IOL:VIOL [mA]
Figure 17. VOL:INT vs. IOL:INT (INT pin): VBAT = VDD = VIO, TA = 25 °C
0.8
Test circuit
VBAT = VDD = VIO = 2 V
0.7
RV-2251-C3
VDD
ECO
INT
VREG
VIOL
VIO
VBAT
CLKOUT
VOUT
SCL
SCA
VSS
0.6
VOL:INT [V]
3V
0.5
5V
0.4
0.3
0.2
0.1
A
V
0.1 µF
0
0
1
2
3
4
5
6
7
8
9
10
IOL:INT [mA]
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
6.4. OSCILLATOR PARAMETERS
For this Table, VSS = 0 V; VIO = 3.0 V; VDD = 3.3 V; VBAT = 3.0 V; TA = -40 °C to +85 °C; fOSC= 32.768 kHz; TYP
values at 25 °C; unless otherwise indicated.
Oscillator Parameters:
SYMBOL
PARAMETER
Xtal General
f
tSTART
Crystal Frequency
Oscillator start-up time
δCLKOUT
CLKOUT duty cycle
CONDITIONS
MIN
TYP
MAX
UNIT
32.768
100
500
kHz
ms
60
%
±20
ppm
-0.035ppm/°C2 (TOPR-T0)2 ±10%
ppm
20
30
±3
°C
ppm
TA = -40°C to +85°C
±3.052
±189
ppm
TA = -40°C to +85°C
±1.017
±63
ppm
-1.5
-0.13
-0.5
-0.04
+1.5
+0.13
+0.5
+0.04
ppm
s/day
ppm
s/day
VOUT = 3.0 V
fCLKOUT = 32.768 kHz
TA = 25°C
40
Xtal Frequency Characteristics
Δf/f
f = 32.768 kHz
TA = 25°C
TOPR = -40°C to +85°C
VDD = 3.3 V
Frequency accuracy
Frequency vs. temperature
Δf/fTOPR
characteristics
T0
Turnover temperature
Δf/f
Aging first year max.
Frequency Offset Compensation
OFFSET value MODE = 0
Δt/t
Min. comp. step (LSB) and
Max. comp. range
OFFSET value MODE = 1
Δt/t
Min. comp. step (LSB) and
Max. comp. range
±10
TA = 25°C, VDD = 3.3 V
Δt/t
Achievable time accuracy
MODE = 0
Calibrated at an initial
temperature
Δt/t
Achievable time accuracy
MODE = 1
Calibrated at an initial
temperature
6.4.1.XTAL FREQUENCY VS. TEMPERATURE CHARACTERISTICS
20
T0 = 25°C (± 5°C)
0
-20
∆f/f [ppm]
-40
-60
-80
-0.035 * (T-T0)2 ppm (±10%)
-100
-120
-140
-160
-180
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
6.5. I2C-BUS INTERFACE AC ELECTRICAL CHARACTERISTICS
2
The following Figure and Table describe the I C-bus interface AC electrical parameters.
2
I C-bus interface AC Parameter Definitions:
SDA
t BUF
t LOW
t HD:DAT
t SU:DAT
SCL
t HD:STA
t HIGH
t RISE
P
t FALL
S
t SU:STO
t SU:STA
SDA
Sr
P
For the following Table, TA = -40 °C to 85 °C, TYP values at 25 °C.
2
I C-bus interface AC Electrical Parameters:
SYMBOL
fSCL
tLOW
tHIGH
tRISE
tFALL
tHD:STA
tSU:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
PARAMETER
SCL input clock frequency
Low period of SCL clock
High period of SCL clock
Rise time of SDA and SCL
Fall time of SDA and SCL
START condition hold time
START condition setup time
SDA setup time
SDA hold time
STOP condition setup time
Bus free time before a new transmission
Conditions
VIO = VIO:ACC
VIO = VIO:ACC
VIO = VIO:ACC
VIO = VIO:ACC
VIO = VIO:ACC
VIO = VIO:ACC
VIO = VIO:ACC
VIO = VIO:ACC
VIO = VIO:ACC
VIO = VIO:ACC
VIO = VIO:ACC
MIN
TYP
MAX
UNIT
400
kHz
µs
µs
ns
ns
µs
µs
ns
µs
µs
µs
1.3
0.6
300
300
0.6
0.6
100
0
0.6
1.3
S = Start condition, Sr = Repeated Start condition, P = Stop condition
Caution:
When communicating with the RV-2251-C3 module, the series of operations from transmitting the START (or
repeated START) condition to transmitting the STOP (or repeated START) condition should occur within 0.5
2
second. If this series of operations requires 0.5 second or more, the I C bus interface will be automatically cleared
and set to standby mode by the bus timeout function of the RV-2251-C3 module.
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
7. RECOMMENDED REFLOW TEMPERATURE (LEAD-FREE SOLDERING)
Maximum Reflow Conditions in accordance with IPC/JEDEC J-STD-020C “Pb-free”
tP
TP
Critical Zone
TL to TP
Temperature
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Temperature Profile
Average ramp-up rate
Ramp down Rate
Time 25°C to Peak Temperature
Preheat
Temperature min
Temperature max
Time Tsmin to Tsmax
Soldering above liquidus
Temperature liquidus
Time above liquidus
Peak temperature
Peak Temperature
Time within 5°C of peak temperature
Time
Symbol
(Tsmax to TP)
Tcool
Tto-peak
Condition
3°C / second max
6°C / second max
8 minutes max
Unit
°C / s
°C / s
min
Tsmin
Tsmax
ts
150
200
60 – 180
°C
°C
sec
TL
tL
217
60 – 150
°C
sec
Tp
tp
260
20 – 40
°C
sec
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
8. PACKAGE
8.1. DIMENSIONS AND SOLDER PAD LAYOUT
C3 Package:
Package dimensions (bottom view):
Recommended solder pad layout:
3,70
1
2
3
0,3
0,55
4
5
0,8
0,8
0,8
0,8
0,8
0,8
0,7
3,0
0,7
0,5
6
11
10
9
8
7
0,8
1,25
12
0,55
2,50
0,8
0,5
0,1
max.0,9
4,2
All dimensions in mm typical.
8.2. MARKING AND PIN #1 INDEX
C3 Package: (top view)
Production Date Code
#11
#12
#7
M530A1
2251
#1
Pin 1 Index
#6
#5
Part Designation
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
9. PACKING INFORMATION
9.1. CARRIER TAPE
12 mm Carrier-Tape:
Material:
Polystyrene / Butadine or Polystyrol black, conductive
Cover Tape:
Base Material:
Adhesive Material:
Peel Method:
Polyester, conductive 0.061 mm
Pressure-sensitive Synthetic Polymer
Middle part removed, sticky sides remain on carrier
±0,1
±0,02
1,75
5,5 ±0,05
Ø1
,5
±0
,1
Ø1
,5
2 ±0,1
0,3
±0,2
3,95
±0,1
4 ±0,1
±0
,1
C3 Package:
12
2251
2251
4 ±0,1
2,7 ±0,1
1 ±0,1
User Direction of Feed
Tape Leader and Trailer: 300 mm minimum.
All dimensions in mm.
9.2. PARTS PER REEL
C3 Package:
Reels:
Diameter
7”
7”
Material
Plastic, Polystyrol
Plastic, Polystyrol
RTC’s per reel
1’000
3’000
68/71
Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
9.3. REEL 7 INCH FOR 12 mm TAPE
ø 10
60
60
°
°
1,8
ø 178
ø 61,5
min.12,4
max.17
Reel:
Diameter
7”
Material
Plastic, Polystyrol
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
9.4. HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED CRYSTALS
The built-in tuning-fork crystal consists of pure Silicon Dioxide in crystalline form. The cavity inside the package is
evacuated and hermetically sealed in order for the crystal blank to function undisturbed from air molecules,
humidity and other influences.
Shock and vibration:
Keep the crystal / module from being exposed to excessive mechanical shock and vibration. Micro Crystal
guarantees that the crystal / module will bear a mechanical shock of 5000g / 0.3 ms.
The following special situations may generate either shock or vibration:
Multiple PCB panels - Usually at the end of the pick & place process the single PCBs are cut out with a router.
These machines sometimes generate vibrations on the PCB that have a fundamental or harmonic frequency
close to 32.768 kHz. This might cause breakage of crystal blanks due to resonance. Router speed should be
adjusted to avoid resonant vibration.
Ultrasonic cleaning - Avoid cleaning processes using ultrasonic energy. These processes can damage
crystals due to mechanical resonance of the crystal blank.
Overheating, rework high temperature exposure:
Avoid overheating the package. The package is sealed with a seal ring consisting of 80% Gold and 20% Tin. The
eutectic melting temperature of this alloy is at 280°C. Heating the seal ring up to >280°C will cause melting of the
metal seal which then, due to the vacuum, is sucked into the cavity forming an air duct. This happens when using
hot-air-gun set at temperatures >300°C.
Use the following methods for rework:


Use a hot-air- gun set at 270°C.
Use 2 temperature controlled soldering irons, set at 270°C, with special-tips to contact all solder-joints from
both sides of the package at the same time, remove part with tweezers when pad solder is liquid.
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Micro Crystal
Real-Time Clock / Calendar Module
RV-2251-C3
10. DOCUMENT REVISION HISTORY
Date
Revision #
Revision Details
January 2016
1.0
First release
Information furnished is believed to be accurate and reliable. However, Micro Crystal assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other
rights of third parties which may result from its use . In accordance with our policy of continuous
development and improvement, Micro Crystal reserves the right to modify specifications mentioned in this
publication without prior notice. This product is not authorized for use as critical component in life support
devices or systems.
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