Appl. Manual

RV-8564
Application Manual
Date: July 2012
Headquarters:
Micro Crystal AG
Mühlestrasse 14
CH-2540 Grenchen
Switzerland
Tel.
Fax
Internet
Email
Revision N°: 2.0
1/40
+41 32 655 82 82
+41 32 655 82 83
www.microcrystal.com
[email protected]
Micro Crystal
Real Time Clock / Calendar Module
RV-8564
TABLE OF CONTENTS
1. OVERVIEW ........................................................................................................................................................ 4
2. GENERAL DESCRIPTION ................................................................................................................................ 4
3. BLOCK DIAGRAM ............................................................................................................................................. 5
4. PINOUT .............................................................................................................................................................. 6
5. PIN DESCRIPTION ............................................................................................................................................ 7
6. FUNCTIONAL DESCRIPTION ........................................................................................................................... 8
6.1. CLKOUT OUTPUT ..................................................................................................................................... 8
7. DEVICE PROTECTION DIAGRAM ................................................................................................................... 8
8. REGISTER ORGANIZATION ............................................................................................................................ 9
8.1. REGISTER OVERVIEW ............................................................................................................................. 9
8.2. CONTROL REGISTERS ............................................................................................................................ 9
8.2.1. CONTROL / STATUS 1 (address 00h…bits description) ................................................................... 9
8.2.2. CONTROL / STATUS 2 (address 01h…bits description) ................................................................. 10
8.3. TIME AND DATE REGISTERS ................................................................................................................ 10
8.3.1. SECONDS (address 02h…bits description) ..................................................................................... 10
8.3.2. MINUTES (address 03h…bits description) ....................................................................................... 10
8.3.3. HOURS (address 04h…bits description) .......................................................................................... 11
8.3.4. DAYS (address 05h…bits description).............................................................................................. 11
8.3.5. WEEKDAYS (address 06h…bits description) ................................................................................... 11
8.3.6. MONTHS / CENTURY (address 07h…bits description) ................................................................... 12
8.3.7. YEARS (address 08h…bits description) ........................................................................................... 13
8.4. ALARM REGISTERS ............................................................................................................................... 13
8.4.1. MINUTE ALARM (address 09h…bits description) ............................................................................ 13
8.4.2. HOUR ALARM (address 0Ah…bits description) ............................................................................... 13
8.4.3. DAY ALARM (address 0Bh…bits description) .................................................................................. 13
8.4.4. WEEKDAY ALARM (address 0Ch…bits description) ....................................................................... 14
8.5. CLKOUT REGISTER ............................................................................................................................... 14
8.5.1. CLKOUT FREQUENCY (address 0Dh…bits description) ................................................................ 14
8.6. TIMER REGISTER ................................................................................................................................... 14
8.6.1. TIMER CONTROL (address 0Eh…bits description) ......................................................................... 15
8.6.2. TIMER (address 0Fh…bits description) ............................................................................................ 15
8.7. REGISTER RESET VALUES ................................................................................................................... 16
9. DETAILED FUNCTIONAL DESCRIPTION ..................................................................................................... 17
9.1. INTERRUPT OUTPUT ............................................................................................................................. 17
9.1.1. BITS TF AND AF ............................................................................................................................... 17
9.1.2. BITS TIE AND AIE ............................................................................................................................ 17
9.1.3. COUNTDOWN TIMER INTERRUPT ................................................................................................ 17
9.2. VOLTAGE LOW DETECTOR AND CLOCK MONITOR ......................................................................... 18
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Real Time Clock / Calendar Module
RV-8564
9.3. SETTING AND READING THE TIME ...................................................................................................... 18
9.4. ALARM FLAG .......................................................................................................................................... 20
9.5. STOP BIT FUNCTION .............................................................................................................................. 21
9.5.1. FIRST INCREMENT OF TIME CIRCUITS AFTER STOP BIT RELEASE ........................................ 22
9.6. RESET ...................................................................................................................................................... 22
10. CHARACTERISTICS OF THE I2C BUS .......................................................................................................... 23
10.1. BIT TRANSFER ....................................................................................................................................... 23
10.2. START AND STOP CONDITIONS .......................................................................................................... 23
10.3. SYSTEM CONFIGURATION.................................................................................................................... 24
10.4. ACKNOWLEDGE ..................................................................................................................................... 25
2
11. I C BUS PROTOCOL ....................................................................................................................................... 26
11.1. ADDRESSING .......................................................................................................................................... 26
11.2. CLOCK AND CALENDAR READ AND WRITE CYCLES ...................................................................... 26
11.2.1. WRITE MODE ................................................................................................................................... 26
11.2.2. READ MODE AT SPECIFIC ADDRESS ........................................................................................... 27
11.2.3. READ MODE ..................................................................................................................................... 27
11.3. INTERFACE WATCHDOG TIMER .......................................................................................................... 28
12. ABSOLUTE MAXIMUM RATING .................................................................................................................... 28
13. FREQUENCY CHARACTERISTICS................................................................................................................ 29
13.1. FREQUENCY VS. TEMPERATURE CHARACTERISTICS .................................................................... 29
14. DC CHARACTERISTICS ................................................................................................................................. 30
15. I2C BUS TIMING CHARACTERISTICS ........................................................................................................... 31
15.1. TIMING CHART ........................................................................................................................................ 31
16. RECOMMENDED REFLOW TEMPERATURE (LEADFREE SOLDERING) .................................................. 32
17. PACKAGES ..................................................................................................................................................... 33
17.1. DIMENSIONS AND SOLDERPADS LAYOUT ........................................................................................ 33
17.2. MARKING AND PIN #1 INDEX ................................................................................................................ 34
18. PACKING INFORAMTION ............................................................................................................................... 35
18.1. CARRIER TAPE ....................................................................................................................................... 35
18.2. PARTS PER REEL ................................................................................................................................... 36
18.3. REEL 13 INCH FOR 12 mm TAPE .......................................................................................................... 37
18.4. REEL 7 INCH FOR 12 mm TAPE ............................................................................................................ 38
19. HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED CRYSTALS ................ 39
20. DOCUMENT REVISION HISTORY.................................................................................................................. 40
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Real Time Clock / Calendar Module
RV-8564
RV-8564
I2C-Bus Interface Real Time Clock / Calendar Module
1. OVERVIEW
•
•
•
•
•
•
•
•
•
•
•
•
RTC module with built-in crystal oscillating at 32.768 kHz
400kHz two-wire I2C interface
Wide Interface operating voltage: 1.8 – 5.5 V
Wide clock operating voltage: 1.2 – 5.5 V
Low power consumption: 250 nA typ @ 3.0V / 25°C
Provides year, month, day, weekday, hours, minutes, seconds
Alarm and Timer functions
Century flag
Low voltage detector, internal power on reset
Programmable clock output for peripheral devices (32.768 kHz, 1024 Hz, 32 Hz, 1 Hz)
I2C slave address: read A3h, write A2h
Available in 2 different small and compact package sizes, RoHS-compliant and 100% leadfree:
C2: 5.0 x 3.2 x 1.2 mm
C3: 3.7 x 2.5 x 0.9 mm
2. GENERAL DESCRIPTION
The RV-8564 is a CMOS real time clock / calendar optimized for low power consumption. A programmable clock
output, interrupt output and voltage low detector are also provided. All address and data are transferred serially via
2
a two-line bi-directional I C bus. Maximum bus speed is 400kbit/sec. The built-in word address register is
incremented automatically after each written or read data byte.
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RV-8564
3. BLOCK DIAGRAM
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RV-8564
4. PINOUT
C2 Package:
#1
VDD
#10
CLKOE
#2
CLKOUT
#9
N.C.
#3
N.C.
#8
N.C.
#4
SCL
#7
INT
#5
SDA
#6
VSS
#1
CLKOE
#10
N.C.
#2
VDD
#9
N.C.
#3
CLKOUT
#8
N.C.
#4
SCL
#7
VSS
#5
SDA
#6
INT
8564
C3 Package:
8564
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RV-8564
5. PIN DESCRIPTION
Pin #
Symbol
Description
C2
C3
VDD
CLKOUT
N.C.
SCL
SDA
VSS
1
2
3
4
5
6
2
3
8
4
5
7
Positive supply voltage
Clock Output pin; push-pull
Not Connected
Serial Clock Input pin; requires pull-up resistor
Serial Data Input-Output pin; open-drain; requires pull-up resistor
Ground
INT
N.C.
N.C.
CLKOE
7
6
Interrupt Output pin; open-drain; active LOW
8
9
10
9
10
1
Not Connected
Not Connected
CLKOUT enable/disable pin; enable is active HIGH; tie to GND when not using CLKOUT
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6. FUNCTIONAL DESCRIPTION
The RV-8564 RTC module combines a RTC IC with on chip oscillator together with a 32.768 kHz quartz crystal in a
miniature ceramic package.
The RV-8564 contains sixteen 8-bit registers with an auto-incrementing address register, a frequency divider which
provides the source clock for the Real Time Clock (RTC), a programmable clock output, a timer, a voltage low
2
detector and a 400 kHz I C bus interface.
All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first
two registers (memory address 00h and 01h) are used as control and/or status registers. The memory addresses
02h through 08h are used as counters for the clock function (seconds up to year counters). Address locations 09h
through 0Ch contain alarm registers which define the conditions for an alarm. Address 0Dh controls the CLKOUT
output frequency. 0Eh and 0Fh are the timer control and timer registers, respectively.
The seconds, minutes, hours, days, weekdays, months, years as well as the minute alarm, hour alarm, day alarm
and weekday alarm registers are all coded in BCD format.
When one of the RTC counters is read (memory locations 02h through 08h), the contents of all counters are frozen
at the beginning of a read cycle. Therefore, faulty reading of the clock / calendar during a carry condition is
prevented.
6.1. CLKOUT OUTPUT
A programmable square wave is available at the CLKOUT pin. Frequencies of 32.768 kHz, 1024 Hz, 32 Hz and 1
Hz can be generated for use as system clock, microcontroller clock or input to a charge pump. CLKOUT is a CMOS
push-pull output, and if disabled it becomes logic 0.
7. DEVICE PROTECTION DIAGRAM
CLKOE
VDD
CLKOUT
INT
SCL
VSS
SDA
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8. REGISTER ORGANIZATION
8.1. REGISTER OVERVIEW
Address
Function
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Control / Status 1
Control / Status 2
Seconds
Minutes
Hours
Days
Weekdays
Months / Century
Years
Minute Alarm
Hour Alarm
Day Alarm
Weekday Alarm
CLKOUT Frequency
Timer Control
Timer
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TEST1
N
VL
X
X
X
X
C
80
AE_M
AE_H
AE_D
AE_W
FE
TE
128
N
N
40
40
X
X
X
X
40
40
X
X
X
X
X
64
STOP
N
20
20
20
20
X
X
20
20
20
20
X
X
X
32
N
TI/TP
10
10
10
10
X
10
10
10
10
10
X
X
X
16
TESTC
AF
8
8
8
8
X
8
8
8
8
8
X
X
X
8
N
TF
4
4
4
4
4
4
4
4
4
4
4
X
X
4
N
AIE
2
2
2
2
2
2
2
2
2
2
2
FD1
TD1
2
N
TIE
1
1
1
1
1
1
1
1
1
1
1
FD0
TD0
1
Bit positions labeled as “X” are not implemented.
Bit positions labeled as “N” should always be written with logic 0.
8.2. CONTROL REGISTERS
8.2.1.CONTROL / STATUS 1 (address 00h…bits description)
1)
2)
Address
Function
00h
Control / Status 1
Bit
Symbol
7
TEST1
6
N
5
STOP
4
N
3
TESTC
2 to 0
N
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TEST1
N
STOP
N
TESTC
N
N
N
Value
Description
01)
Must be set to logic 0 for normal operations
1
Test mode
02)
Default value
01)
RTC source clock runs
1
RTC divider chain flip-flops are asynchronously set to
logic 0
The RTC clock is stopped (CLKOUT at 32.768 kHz is
still available)
02)
Default value
0
Must be set to logic 0 for normal operations
11)
Test mode
0002)
Default value
Reference
See section 9.5.
Default value.
Bits labeled as “N” should always be written with logic 0.
Note:
The two bits: TEST1 and TESTC are for device testing. Make sure TEST1 and TESTC are set to 0 during normal
operation. If accidentally set to 1, they may modify the clock data or result in abnormal time.
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8.2.2.CONTROL / STATUS 2 (address 01h…bits description)
Address
Function
01h
Control / Status 2
Bit
Symbol
Value
Description
7 to 5
N
0002)
Default value
01)
INT is active when TF is active (subject to the status
of TIE)
4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N
N
N
TI/TP
AF
TF
AIE
TIE
Reference
INT pulses active according to 9.1.3. (subject to the
status of TIE)
TI/TP
1
See sections 8.6.
and 9.1.
Remark: if AF and AIE are active then INT will be
permanently active
1)
2)
3
AF
2
TF
1
AIE
0
TIE
01)
Alarm flag inactive
1
Alarm flag active
01)
Timer flag inactive
1
Timer flag active
01)
Alarm interrupt disabled
1
Alarm interrupt enabled
01)
Timer interrupt disabled
1
Timer interrupt enabled
See section 9.1.
See section 9.1.
See section 9.1.
See section 9.1.
Default value.
Bits labeled as “N” should always be written with logic 0.
8.3. TIME AND DATE REGISTERS
8.3.1.SECONDS (address 02h…bits description)
1)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
02h
Seconds
VL
40
20
10
8
4
2
1
Bit
Symbol
7
VL
6 to 0
Seconds
Value
Description
0
Clock integrity is guaranteed
11)
Integrity of the clock information is not guaranteed
0 to 59
This register holds the current seconds coded in BCD format
Startup value.
8.3.2.MINUTES (address 03h…bits description)
Address
Function
03h
Minutes
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
40
20
10
8
4
2
1
Bit
Symbol
Value
Description
7
X
-
Unused
6 to 0
Minutes
0 to 59
This register holds the current minutes coded in BCD format
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RV-8564
8.3.3.HOURS (address 04h…bits description)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
04h
Hours
X
X
20
10
8
4
2
1
Bit
Symbol
Value
Description
7 to 6
X
-
Unused
5 to 0
Hours
0 to 23
This register holds the current hours coded in BCD format
8.3.4.DAYS (address 05h…bits description)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
Days
X
X
20
10
8
4
2
1
Bit
Symbol
Value
Description
7 to 6
X
-
Unused
5 to 0
Days
1 to 31
This register holds the current day coded in BCD format
8.3.5.WEEKDAYS (address 06h…bits description)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06h
Weekdays
X
X
20
10
8
4
2
1
Bit
Symbol
Value
Description
7 to 3
X
-
Unused
2 to 0
Weekdays
0 to 6
This register holds the current weekday
Weekdays1)
1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sunday
X
X
X
X
X
0
0
0
Monday
X
X
X
X
X
0
0
1
Tuesday
X
X
X
X
X
0
1
0
Wednesday
X
X
X
X
X
0
1
1
Thursday
X
X
X
X
X
1
0
0
Friday
X
X
X
X
X
1
0
1
Saturday
X
X
X
X
X
1
1
0
Definition may be re-assigned by the user.
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Real Time Clock / Calendar Module
RV-8564
8.3.6.MONTHS / CENTURY (address 07h…bits description)
1)
2)
Address
Function
07h
Months
Bit
Symbol
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C
X
X
10
8
4
2
1
Value
Description
02)
Indicates the century is x
7
C1)
1
Indicates the century is x + 1
6 to 5
X
-
Unused
4 to 0
Months
1 to 12
This register holds the current month coded in BCD format
Months
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
January
C
X
X
0
0
0
0
1
February
C
X
X
0
0
0
1
0
March
C
X
X
0
0
0
1
1
April
C
X
X
0
0
1
0
0
May
C
X
X
0
0
1
0
1
June
C
X
X
0
0
1
1
0
July
C
X
X
0
0
1
1
1
August
C
X
X
0
1
0
0
0
September
C
X
X
0
1
0
0
1
October
C
X
X
1
0
0
0
0
November
C
X
X
1
0
0
0
1
December
C
X
X
1
0
0
1
0
This bit may be re-assigned by the user.
This bit is toggled when the register Years overflows from 99 to 00.
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8.3.7.YEARS (address 08h…bits description)
1)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
Years
80
40
20
10
8
4
2
1
Bit
Symbol
Value
Description
7 to 0
Years
0 to 99
This register holds the current year coded in BCD format1)
When the register Years overflows from 99 to 00, the century bit C in the register Months is toggled.
Note:
th
The RV-8564 compensates for leap years by adding a 29 day to February if the year counter contains a value
which is divisible by 4, including 00.
8.4. ALARM REGISTERS
8.4.1.MINUTE ALARM (address 09h…bits description)
1)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
09h
Minute Alarm
AE_M
40
20
10
8
4
2
1
Bit
Symbol
7
AE_M
6 to 0
Minute Alarm
Value
Description
0
Minute Alarm in enabled
11)
Minute Alarm is disabled
0 to 59
Minute Alarm information coded in BCD format
Default value.
8.4.2.HOUR ALARM (address 0Ah…bits description)
1)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ah
Hour Alarm
AE_H
X
20
10
8
4
2
1
Bit
Symbol
7
AE_H
6
5 to 0
Value
Description
0
Hour Alarm in enabled
11)
Hour Alarm is disabled
X
-
Unused
Hour Alarm
0 to 23
Hour Alarm information coded in BCD format
Default value.
8.4.3.DAY ALARM (address 0Bh…bits description)
1)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh
Day Alarm
AE_D
X
20
10
8
4
2
1
Bit
Symbol
7
AE_D
6
5 to 0
Value
Description
0
Day Alarm in enabled
11)
Day Alarm is disabled
X
-
Unused
Day Alarm
1 to 31
Day Alarm information coded in BCD format
Default value.
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8.4.4.WEEKDAY ALARM (address 0Ch…bits description)
1)
Address
Function
0Ch
Weekday Alarm
Bit
Symbol
7
AE_W
6 to 3
2 to 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AE_W
X
X
X
X
4
2
1
Value
Description
0
Weekday Alarm in enabled
11)
Weekday Alarm is disabled
X
-
Unused
Weekday Alarm
0 to 6
Weekday Alarm information coded in BCD format
Default value.
8.5. CLKOUT REGISTER
A programmable square wave output is available at CLKOUT pin. Operation is controlled by the FE bit in register
CLKOUT Frequency and Clock Output Enable pin (CLKOE). To enable CLKOUT, CLKOE pin must be set HIGH.
Frequencies of 32.768 kHz (default), 1024 Hz, 32 Hz and 1 Hz can be generated for use as a system clock,
microcontroller clock, input to a charge pump, or for calibration of the oscillator.
8.5.1.CLKOUT FREQUENCY (address 0Dh…bits description)
Address
Function
0Dh
CLKOUT Frequency
Bit
Symbol
7
FE
6 to 2
1 to 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FE
X
X
X
X
X
FD1
FD0
Value
Description
0
The CLKOUT output is inhibited and set to logic 0
11)
The CLKOUT output is activated
X
-
Unused
FD[1:0]
001) to 11
CLKOUT Frequency selection
CLKOUT Frequency
1)
Bit 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
32.768 kHz
X
X
X
X
X
X
0
0
1024 Hz
X
X
X
X
X
X
0
1
32 Hz
X
X
X
X
X
X
1
0
1 Hz
X
X
X
X
X
X
1
1
Default value.
8.6. TIMER REGISTER
The 8-bit countdown timer register at address 0Fh is controlled by the timer control register at address 0Eh. The
Timer Control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 sec, or 1/60
Hz) and enables / disables the timer. The timer counts down from a software loaded 8-bit binary value. At the end
of every countdown, the timer sets the Timer Flag TF to logic 1. The TF may only be cleared using the interface.
The generation of interrupts from the timer function is controlled via bit TIE (Control / Status 2 register). If bit TIE is
enabled, the INT pin follows the condition of bit TF. The interrupt may be generated as a pulsed signal every
countdown period or as a permanent active signal which follows the condition of the Timer Flag TF. TI/TP (Control /
Status 2 register) is used for this mode control. When reading the timer, the current countdown value is returned.
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8.6.1.TIMER CONTROL (address 0Eh…bits description)
Address
Function
0Eh
Timer Control
Bit
Symbol
2)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TE
X
X
X
X
X
TD1
TD0
Value
Description
01)
Timer is disabled
7
TE
1
Timer is enabled
6 to 2
X
-
Unused
1 to 0
TD[1:0]
00 to 111)
Timer source clock frequency selection2)
Timer Frequency
1)
Bit 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
4096 Hz
X
X
X
X
X
X
0
0
64 Hz
X
X
X
X
X
X
0
1
1 Hz
X
X
X
X
X
X
1
0
1
X
X
X
X
X
X
1
1
/60 Hz
Default value.
These bits determine the source clock frequency for the countdown timer. When not in use, TD1 / TD0 should be set to 1/60 Hz for power
saving.
8.6.2.TIMER (address 0Fh…bits description)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Fh
Timer
128
64
32
16
8
4
2
1
Bit
Symbol
Value
7 to 0
Timer
00h to FFh
Description
Countdown value = n
Countdown Period =
n
Source Clock Frequency
Note:
2
For accurate read back of the countdown value, the I C bus clock (SDA) must be operating at a frequency of at
least twice the selected timer clock. Since it is not possible to freeze the countdown timer counter during read back,
it is recommended to read the register twice and check for consistent results.
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Micro Crystal
Real Time Clock / Calendar Module
RV-8564
8.7. REGISTER RESET VALUES
Address
Function
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Control / Status 1
Control / Status 2
Seconds
Minutes
Hours
Days
Weekdays
Months / Century
Years
Minute Alarm
Hour Alarm
Day Alarm
Weekday Alarm
CLKOUT Frequency
Timer Control
Timer
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
X
X
X
X
X
X
1
1
1
1
1
0
X
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
X
X
X
X
0
1
X
0
0
X
X
X
X
X
X
X
X
X
X
X
0
1
X
Bit positions labeled as “X” are undefined at power-on and unchanged by subsequent resets.
16/40
Micro Crystal
Real Time Clock / Calendar Module
RV-8564
9. DETAILED FUNCTIONAL DESCRIPTION
9.1. INTERRUPT OUTPUT
9.1.1.BITS TF AND AF
When an alarm occurs, AF is set to 1. Similarly, at the end of a timer countdown, TF is set to 1. These bits maintain
their value unit overwritten using the interface. If both timer and alarm are required in the application, the source of
the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another,
a logic AND in performed during a write access.
Note:
When bits TIE and AIE are disabled, pin INT will remain high-impedance.
9.1.2.BITS TIE AND AIE
These bits activate or deactivate the generation of an interrupt when TF or AF is asserted respectively. The
interrupt is the logical OR of these two conditions when both AIE and TIE are set.
9.1.3.COUNTDOWN TIMER INTERRUPT
The pulse generator for the countdown timer interrupt uses an internal clock and is dependent on the selected
source clock for the countdown timer and on the countdown value “n”. As a consequence, the width of the interrupt
pulse varies.
INT operation (bit TI/TP = 1)
INT period
n = 12)
n>1
4096 Hz
1
/8192 s
1
/4096 s
64 Hz
1
/128 s
1
/64 s
1 Hz
1
/64 s
1
/64 s
1
1
/64 s
1
/64 s
Source clock
1)
2)
1)
/60 Hz
TF and INT become active simultaneously.
n = loaded countdown value. Timer is stopped when n = 0.
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Micro Crystal
Real Time Clock / Calendar Module
RV-8564
9.2. VOLTAGE LOW DETECTOR AND CLOCK MONITOR
The RV-8564 has an on-chip voltage low detector. When VDD drops below VLOW, the VL (Voltage Low) flag is set to
indicate that the integrity of the clock information is no longer guaranteed. The VL flag can only be cleared by using
the interface.
The VL flag is intended to detect the situation when VDD is decreasing slowly; for example under battery operation.
Should the oscillator stop or VDD reach VLOW before power is reasserted, then the VL flag will be set. This indicates
that the time is possibly corrupted.
9.3. SETTING AND READING THE TIME
Data flow and data dependencies starting from 1 Hz clock tick
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Micro Crystal
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RV-8564
During read / write operations, the time counting circuits (memory locations 02h through 08h) are blocked, in order
to prevent the following:
• Faulty writing or reading of the clock and calendar during a carry condition
• Incrementing the time registers during the read cycle
After this read / write access is completed, the time circuit is released again and any pending request to increment
the time counters that occurred during the read access is serviced. A maximum of 1 request can be stored;
therefore, all accesses must be completed within 1 second.
As a consequence of this method, it is very important to make a read or write access in one go. This means, setting
or reading seconds through years should be made in one single access. Failing to comply with this method, could
result in the time becoming corrupted.
As an example, if the time (seconds through hours) is set in one access, and then, in a second access the date is
set, it is possible that the time may be incremented between the two accesses. A similar problem exists when
reading. A roll over may occur between reads thus giving the minutes from one moment and the hours from the
next.
Recommended method for reading the time:
1. Send a START condition and the slave address for write (A2h)
2. Set the address pointer to 2 (seconds) by sending 02h
3. Send a RE-START condition or STOP followed by START
4. Send the slave address for read (A3h)
5. Read the seconds
6. Read the minutes
7. Read the hours
8. Read the days
9. Read the weekdays
10. Read the century and months
11. Read the years
12. Send a STOP condition
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Micro Crystal
Real Time Clock / Calendar Module
RV-8564
9.4. ALARM FLAG
By clearing the MSB of one or more of the alarm registers AE_x (Alarm Enable), the corresponding alarm
condition(s) are active. When an alarm occurs, AF is set to logic 1. The asserted AF can be used to generate an
interrupt ( INT ). The AF is cleared using the interface.
The registers at addresses 09h through 0Ch contain alarm information. When one or more of these registers is
loaded with a valid minute, hour, day or weekday and its corresponding Alarm Enable bit (AE_x) is logic 0, then that
information is compared with the current minute, hour, day and weekday. When all enabled comparisons first
match, the Alarm Flag (AF in register Control / Status 2) is set to logic 1.
The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is enabled, the INT pin
follows the condition of bit AF. AF will remain set until cleared by the interface. Once AF has been cleared it will
only be set again when the time increments to match the alarm condition once more. Alarm registers which have
their AE_x bit at logic 1 are ignored.
1)
Only when all enabled alarm settings are matching. It’s only on increment to a matched case that the alarm flag is set.
20/40
Micro Crystal
Real Time Clock / Calendar Module
RV-8564
9.5. STOP BIT FUNCTION
The function of the STOP bit is to allow an accurate starting of the time circuits. The STOP bit function will cause
the upper part of the prescaler to (F2 to F14) to be held in reset and thus no 1 Hz ticks will be generated. The time
circuits can then be set and will not increment until the STOP bit is released.
1 Hz
OSCILLATOR
STOP
The STOP bit function will not affect the 32.768 kHz output on CLKOUT, but will stop the generation of 1024 Hz,
32 Hz and 1 Hz.
2
The lower two stages of the prescaler (F0 and F1) are not reset and as the I C bus is asynchronous to the crystal
oscillator, the accuracy of re-starting the time circuits will be between zero and one 8192 Hz cycle.
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Micro Crystal
Real Time Clock / Calendar Module
RV-8564
9.5.1.FIRST INCREMENT OF TIME CIRCUITS AFTER STOP BIT RELEASE
Bit
Prescaler bits1)
STOP
F0F1-F2 to F14
1 Hz Tick
Time
hh:mm:ss
Comment
Clock is running normally
0
01-0 0001 1101 0100
12:45:12
Prescaler counting normally
STOP bit is activated by user. F0 and F1 are not reset and values cannot be predicted externally
1
XX-0 0000 0000 0000
12:45:12
Prescaler is reset; time circuits are frozen
New time is set by user
1
1)
08:00:00
Prescaler is reset; time circuits are frozen
STOP bit is released by user
0
XX-0 0000 0000 0000
XX-0 0000 0000 0000
08:00:00
Prescaler is now running
XX-1 0000 0000 0000
08:00:00
-
XX-0 1000 0000 0000
08:00:00
-
XX-1 1000 0000 0000
08:00:00
-
:
:
11-1 1111 1111 1110
:
08:00:00
00-0 0000 0000 0001
08:00:01
0 to 1 transition of F14 increments the time circuits
10-0 0000 0000 0001
08:00:01
-
:
:
:
11-1 1111 1111 1111
08:00:01
-
00-0 0000 0000 0000
08:00:01
-
10-0 0000 0000 0000
08:00:01
-
:
:
-
11-1 1111 1111 1110
08:00:01
-
00-0 0000 0000 0001
08:00:02
0 to 1 transition of F14 increments the time circuits
-
F0 is clocked at 32.768 kHz.
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP bit is released. The
uncertainty is caused by the prescaler bits F0 and F1 not being reset and the unknown state of the 32.768 kHz
clock.
9.6. RESET
The RV-8564 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state,
2
2
the I C bus logic is initialized including the address pointer and all registers are set according to 8.7. I C bus
communication is not possible during reset.
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Micro Crystal
Real Time Clock / Calendar Module
RV-8564
10. CHARACTERISTICS OF THE I2C BUS
The I2C bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a
Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via pull-up
resistors. Data transfer may be initiated only when the bus is not busy.
10.1. BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH
period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal. Data
changes should be executed during the LOW period of the clock pulse.
10.2. START AND STOP CONDITIONS
Both SDA data and SCL clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the STOP condition (P).
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RV-8564
10.3. SYSTEM CONFIGURATION
Since multiple devices can be connected with the I2C bus, all I2C bus devices have a fixed and unique device
number built-in to allow individual addressing of each device.
The device that controls the I2C bus is the Master; the devices which are controlled by the Master are the Slaves.
A device generating a message is a Transmitter; a device receiving a message is the Receiver. The RV-8564 acts
as a Slave-Receiver or Slave-Transmitter.
Before any data is transmitted on the I2C bus, the device which should respond is addressed first. The addressing
is always carried out with the first byte transmitted after the start procedure. The clock signal SCL is only an input
signal, but the data signal SDA is a bidirectional line.
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Real Time Clock / Calendar Module
RV-8564
10.4. ACKNOWLEDGE
There is no limit to the numbers of data bytes transmitted between the START and STOP conditions. Each byte (of
8 bits) is followed by an acknowledge cycle. Therefore, the Master generates an extra acknowledge clock pulse.
The acknowledge bit is a HIGH level signal put on the SDA line by the Transmitter-Device, the Receiver-Device
must pull down the SDA line during the acknowledge clock pulse to confirm the correct reception of the last byte.
Either a Master-Receiver or a Slave-Receiver which is addressed must generate an acknowledge after the correct
reception of each byte. The device that acknowledges must pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (setup
and hold times must be taken into consideration).
If the Master is addressed as Receiver, it can stop data transmission by not generating an acknowledge on the last
byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the data line
HIGH to enable the Master to generate a STOP condition.
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Real Time Clock / Calendar Module
RV-8564
11. I2C BUS PROTOCOL
11.1. ADDRESSING
2
Before any data is transmitted on the I C bus, the device which should respond is addressed first. The addressing
is always carried out with the first byte transmitted after the start procedure.
The RV-8564 acts as a Slave-Receiver or Slave-Transmitter. Therefore, the clock signal SCL is only an input
signal, but the data signal SDA is a bidirectional line.
RV-8564
Slave Address
11.2. CLOCK AND CALENDAR READ AND WRITE CYCLES
11.2.1. WRITE MODE
Master transmits to Slave-Receiver at specified address. The Word Address is 4-bit value that defines which
register is to be accessed next. The upper four bits of the Word Address are not used. After reading or writing one
byte, the Word Address is automatically incremented by 1.
Master sends out the “Start Condition”.
Master sends out the “Slave Address”, A2h for the RV-8564; the R/ W bit in write mode.
Acknowledgement from the RV-8564.
Master sends out the “Word Address” to the RV-8564.
Acknowledgement from the RV-8564.
Master sends out the “data” to write to the specified address in step 4).
Acknowledgement from the RV-8564.
Steps 6) and 7) can be repeated if necessary. The address will be incremented automatically in the RV-8564.
Master sends out the “Stop Condition”.
R/W
1)
2)
3)
4)
5)
6)
7)
8)
9)
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RV-8564
11.2.2. READ MODE AT SPECIFIC ADDRESS
Master reads data after setting Word Address
1)
2)
3)
4)
5)
6)
7)
8)
Master sends out the “Start Condition”.
Master sends out the “Slave Address”, A2h for the RV-8564; the R/ W bit in write mode.
Acknowledgement from the RV-8564.
Master sends out the “Word Address” to the RV-8564.
Acknowledgement from the RV-8564.
Master sends out the “Start Condition”. “Stop Condition” has not been sent.
Master sends out the “Slave Address”, A3h for the RV-8564; the R/ W bit in read mode.
Acknowledgement from the RV-8564.
At this point, the Master becomes a Receiver, the Slave becomes the Transmitter.
9) The Slave sends out the “data” from the Word Address specified in step 4).
10) Acknowledgement from the Master.
11) Steps 9) and 10) can be repeated if necessary.
The address will be incremented automatically in the RV-8564.
12) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on the
last byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the
data line HIGH to enable the Master to generate a stop condition.
13) Master sends out the “Stop Condition”.
11.2.3. READ MODE
Master reads Slave-Transmitter immediately after first byte
1) Master sends out the “Start Condition”.
2) Master sends out the “Slave Address”, A3h for the RV-8564; the R/ W bit in read mode.
3) Acknowledgement from the RV-8564.
At this point, the Master becomes a Receiver, the Slave becomes the Transmitter
4) The RV-8564 sends out the “data” from the last accessed Word Address incremented by 1.
5) Acknowledgement from the Master.
6) Steps 4) and 5) can be repeated if necessary.
The address will be incremented automatically in the RV-8564.
7) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on the
last byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the
data line HIGH to enable the Master to generate a stop condition.
8) Master sends out the “Stop Condition”.
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Micro Crystal
Real Time Clock / Calendar Module
RV-8564
11.3. INTERFACE WATCHDOG TIMER
During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing
device becomes locked and does not clear the interface, the RV-8564 has a built in watchdog timer. Should the
interface be active for more than 1 s from the time a valid slave address is transmitted, then the RV-8564 will
automatically clear the interface and allow the time counting circuits to continue counting.
The watchdog is implemented to prevent the excessive loss of time due to interface access failure e. g. if main
power is removed from a battery backup system during an interface access.
Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The watchdog will trigger
between 1 s and 2 s after receiving a valid slave address.
12. ABSOLUTE MAXIMUM RATING
1)
2)
3)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
Supply voltage
Input voltage
VDD
VI
> GND / < VDD
Input Pin
-0.5
VSS -0.5
+6.5
VDD +0.5
V
V
Output voltage
VO
VDD +0.5
V
IDD; ISS
II
IO
INT Pin
VDD Pin
VSS -0.5
Supply current
DC Input current
DC Output current
Electrostatic discharge voltage
VESD
Latch-up current
Operating temperature range
Storage temperature range
ILU
TOPR
TSTO
-50
-10
-10
-40
-55
+50
+10
+10
+/-3500
+/-250
100
+85
+125
mA
mA
mA
V
V
mA
°C
°C
HBM1)
MM2)
All pins3)
Stored as bare product
Pass level; Human Body Model (HBM), according to JESD22-A114.
Pass level; Machine Model (MM), according to JESD22-A115.
Pass level; latch-up testing, according to JESD78 at maximum ambient temperature (Tamb(max) = +85°C).
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RV-8564
13. FREQUENCY CHARACTERISTICS
PARAMETER
SYMBOL
Frequency precision
∆F/F
Frequency vs. voltage characteristics
∆F/V
Frequency vs. temperature characteristics
∆F/FOPR
Turnover temperature
T0
Aging first year max.
VO ∆F/F
Oscillation startup time
CLKOUT duty cycle
CONDITIONS
TAMB = +25°C
VDD = 3.0 V
TAMB = +25°C
VDD = 1.8 V to 5.5 V
TREF = +25°C
VDD = 3.0 V
II
At 25°C
At 25°C
δCLKOUT
At 25°C
TYP.
MAX.
UNIT
+/-10
+/-20
ppm
+/-0.8
+/-1.5
ppm / V
-0.035ppm/°C2 (TOPR-TO)2
+/-10%
+25
+/-5
ppm
°C
+/-3
ppm
350
500
ms
50
40 / 60
%
13.1. FREQUENCY VS. TEMPERATURE CHARACTERISTICS
20.0
T0 = 25°C (±5°C)
0.0
-20.0
∆F/F [ppm]
-40.0
-60.0
2
-0.035 * (T-T0) ppm (±10%)
-80.0
-100.0
-120.0
-140.0
-160.0
-180.0
-60
-40
-20
0
20
40
60
80
100
T [°C]
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RV-8564
14. DC CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1.2
-
5.5
V
1.8
-
5.5
V
VLOW
-
5.5
V
fSCL = 400kHz
fSCL = 100kHz
VDD = 5.0V
VDD = 3.0V
-
275
250
800
200
550
500
µA
µA
nA
nA
VDD = 2.0V
-
225
450
nA
IDD
VDD = 5.0V
VDD = 3.0V
-
500
400
750
650
nA
nA
VDD = 2.0V
-
400
600
nA
IDD32k
VDD = 5.0V
VDD = 3.0V
-
2.5
1.5
3.4
2.2
µA
µA
VDD = 2.0V
-
1.1
1.6
µA
VSS -0.5
70% VDD
-1
-
0
-
30% VDD
VDD +0.5
+1
7
V
V
µA
pF
Power Supply Voltage
I2C bus inactive
TAMB = 25°C
2
Supply voltage
VDD
I C bus active
fSCL = 400 kHz
For clock data integrity
TAMB = 25°C
Power Supply Current
Current consumption
I2C bus active
Current consumption1)2)3)
I2C bus inactive (fSCL = 0 Hz)
CLKOUT disabled
TAMB = 25°C
Current consumption1)2)3)
I2C bus inactive (fSCL = 0 Hz)
CLKOUT disabled
TOPR = -40 to +85°C
Current consumption3)
I2C bus inactive (fSCL = 0 Hz)
CLKOUT enabled (32.768 kHz)
Load = 7.5 pF / TAMB = 25°C
Inputs
LOW level input voltage
HIGH level input voltage
Input leakage current
Input capacitance4)
Outputs
IDDO
IDD
VIL
VIH
ILI
CI
VI = VDD or VSS
On pin SDA
-
-
-3
mA
On pin INT
On pin CLKOUT
-
-
-1
mA
-
-
-1
mA
IOH
On pin CLKOUT
-
-
1
mA
Output leakage current
Voltage detector
ILO
VO = VDD or VSS
-1
0
+1
µA
Low voltage
VLOW
TAMB = 25°C
-
0.9
1.0
V
LOW level output current
VOL = 0.4 V; VDD = 5.0 V
HIGH level output current
VOH = 4.6 V; VDD = 5.0 V
IOL
1)
Timer source clock = 1/60 Hz.
CLKOUT disabled (FE = 0 or CLKOE = 0).
3)
VIL and VIH with an input voltage swing of VSS to VDD.
4)
Tested on sample basis.
2)
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RV-8564
15. I2C BUS TIMING CHARACTERISTICS
1)
PARAMETER1)
SYMBOL
MIN.
TYP.
MAX.
UNIT
SCL clock frequency
Hold time (repeated) START condition
Setup time for repeated START condition
LOW period of SCL clock
fSCL
tHD;STA
tSU;STA
tLOW
0.6
0.6
1.3
-
400
-
kHz
µs
µs
µs
HIGH period of SCL clock
Bus free time between STOP and START condition
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
Data setup time
Data hold time
Setup time for STOP condition
Spike pulse width
tHIGH
tBUF
tr
tf
Cb
tSU;DAT
tHD;DAT
tSU;STO
tw(spike)
0.6
1.3
100
0
0.6
-
0.3
0.3
400
50
µs
µs
µs
µs
pF
ns
ns
µs
ns
-
All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing
of VSS to VDD.
15.1. TIMING CHART
Note:
The I2C BUS access time between a START and a START condition or between a START and a STOP condition
to this device must be less than one second.
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RV-8564
16. RECOMMENDED REFLOW TEMPERATURE (LEADFREE SOLDERING)
Maximum Reflow Conditions in accordance with IPC/JEDEC J-STD-020C “Pb-free”
Temperature Profile
Average ramp-up rate
Ramp down Rate
Time 25°C to Peak Temperature
Preheat
Temperature min
Temperature max
Time Tsmin to Tsmax
Soldering above liquidus
Temperature liquidus
Time above liquidus
Peak temperature
Peak Temperature
Time within 5°C of peak temperature
Symbol
(Tsmax to Tp)
Tcool
Tto-peak
Condition
3°C / second max
6°C / second max
8 minutes max
Unit
°C / s
°C / s
m
Tsmin
Tsmax
ts
150
200
60 - 180
°C
°C
Sec
TL
tL
217
60 – 150
°C
sec
Tp
tp
260
20 - 40
°C
sec
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RV-8564
17. PACKAGES
17.1. DIMENSIONS AND SOLDERPADS LAYOUT
C2 Package:
Package dimensions (bottom view):
Recommended solderpad layout:
C3 Package:
Package dimensions (bottom view):
Recommended solderpad layout:
All dimensions in mm typical.
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Real Time Clock / Calendar Module
RV-8564
17.2. MARKING AND PIN #1 INDEX
C2 Package:
8564
C3 Package:
8564
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RV-8564
18. PACKING INFORAMTION
18.1. CARRIER TAPE
12 mm Carrier-Tape:
Material:
Polystyrene / Butadine or Polystyrol black, conductive
Cover Tape:
Base Material:
Adhesive Material:
Polyester, conductive 0.061 mm
Pressure-sensitive Synthetic Polymer
C2 Package:
C3 Package:
User Direction of Feed
Tape Leader and Trailer: 300 mm minimum.
All dimensions in mm.
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Real Time Clock / Calendar Module
RV-8564
18.2. PARTS PER REEL
C2 Package:
Reels:
Diameter
7”
13”
Material
Plastic, Polystyrol
Plastic, Polystyrol
RTC’s per reel
1’000
5’000
Diameter
7”
7”
Material
Plastic, Polystyrol
Plastic, Polystyrol
RTC’s per reel
1’000
3’000
C3 Package:
Reels:
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Micro Crystal
Real Time Clock / Calendar Module
RV-8564
18.3. REEL 13 INCH FOR 12 mm TAPE
Reel:
Diameter
13”
Material
Plastic, Polystyrol
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Micro Crystal
Real Time Clock / Calendar Module
RV-8564
18.4. REEL 7 INCH FOR 12 mm TAPE
Reel:
Diameter
7”
Material
Plastic, Polystyrol
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Micro Crystal
Real Time Clock / Calendar Module
RV-8564
19. HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED
CRYSTALS
The built-in tuning-fork crystal consists of pure Silicon Dioxide in crystalline form. The cavity inside the package is
evacuated and hermetically sealed in order for the crystal blank to function undisturbed from air molecules,
humidity and other influences.
Shock and vibration:
Keep the crystal / module from being exposed to excessive mechanical shock and vibration. Micro Crystal
guarantees that the crystal / module will bear a mechanical shock of 5000g / 0.3 ms.
The following special situations may generate either shock or vibration:
Multiple PCB panels - Usually at the end of the pick & place process the single PCBs are cut out with a router.
These machines sometimes generate vibrations on the PCB that have a fundamental or harmonic frequency
close to 32.768 kHz. This might cause breakage of crystal blanks due to resonance. Router speed should be
adjusted to avoid resonant vibration.
Ultrasonic cleaning - Avoid cleaning processes using ultrasonic energy. These processes can damages
crystals due to mechanical resonance of the crystal blank.
Overheating, rework high temperature exposure:
Avoid overheating the package. The package is sealed with a seal ring consisting of 80% Gold and 20% Tin. The
eutectic melting temperature of this alloy is at 280°C. Heating the seal ring up to >280°C will cause melting of the
metal seal which then, due to the vacuum, is sucked into the cavity forming an air duct. This happens when using
hot-air-gun set at temperatures >300°C.
Use the following methods for rework:
•
•
Use a hot-air- gun set at 270°C.
Use 2 temperature controlled soldering irons, set at 270°C, with special-tips to contact all solder-joints from
both sides of the package at the same time, remove part with tweezers when pad solder is liquid.
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Micro Crystal
Real Time Clock / Calendar Module
RV-8564
20. DOCUMENT REVISION HISTORY
Date
Revision #
Revision Details
February 2005
1.1
First release
September 2005
1.2
Add ESD protection schematic
July 2012
2.0
Add C3 package version
Information furnished is believed to be accurate and reliable. However, Micro Crystal assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other
rights of third parties which may result from its use. In accordance with our policy of continuous
development and improvement, Micro Crystal reserves the right to modify specifications mentioned in this
publication without prior notice. This product is not authorized for use as critical component in life support
devices or systems.
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