Appl. Manual

RV-8803-C7
Application Manual
Date: May 2016
Headquarters:
Micro Crystal AG
Mühlestrasse 14
CH-2540 Grenchen
Switzerland
Tel.
Fax
Internet
Email
Revision N°: 1.2
1/63
+41 32 655 82 82
+41 32 655 82 83
www.microcrystal.com
[email protected]
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
TABLE OF CONTENTS
1. OVERVIEW ....................................................................................................................................................... 5
1.1. GENERAL DESCRIPTION ......................................................................................................................... 5
1.2. APPLICATIONS ......................................................................................................................................... 6
2. BLOCK DIAGRAM ............................................................................................................................................ 7
2.1. PINOUT ...................................................................................................................................................... 8
2.2. PIN DESCRIPTION .................................................................................................................................... 8
2.3. FUNCTIONAL DESCRIPTION ................................................................................................................... 9
2.4. DEVICE PROTECTION DIAGRAM ........................................................................................................... 9
3. REGISTER ORGANIZATION ......................................................................................................................... 10
3.1. REGISTER OVERVIEW ........................................................................................................................... 10
3.1.1. AUTO-INCREMENTING ................................................................................................................... 11
3.2. CLOCK REGISTERS ............................................................................................................................... 12
3.3. CALENDAR REGISTERS ........................................................................................................................ 13
3.4. ALARM REGISTERS ............................................................................................................................... 15
3.5. PERIODIC COUNTDOWN TIMER CONTROL REGISTERS .................................................................. 17
3.6. EXTENSION REGISTER.......................................................................................................................... 18
3.7. FLAG REGISTER ..................................................................................................................................... 19
3.8. CONTROL REGISTER ............................................................................................................................. 20
3.9. OFFSET REGISTER ................................................................................................................................ 21
3.10. CAPTURE BUFFER/EVENT CONTROL REGISTERS ........................................................................... 22
3.11. REGISTER RESET VALUES SUMMARY ............................................................................................... 24
4. DETAILED FUNCTIONAL DESCRIPTION .................................................................................................... 25
4.1. POWER ON RESET (POR)...................................................................................................................... 25
4.2. POWER MANAGEMENT ......................................................................................................................... 25
4.3. CLOCK SOURCE ..................................................................................................................................... 25
4.4. PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION ................................................................. 25
4.4.1. COMPLETE PERIODIC COUNTDOWN TIMER DIAGRAM ............................................................. 26
4.4.2. USE OF THE PERIODIC COUNTDOWN TIMER ............................................................................. 27
4.5. PERIODIC TIME UPDATE INTERRUPT FUNCTION ............................................................................. 29
4.5.1. COMPLETE PERIODIC TIME UPDATE DIAGRAM ......................................................................... 29
4.5.2. USE OF THE PERIODIC TIME UPDATE INTERRUPT ................................................................... 30
4.6. ALARM INTERRUPT FUNCTION............................................................................................................ 31
4.6.1. COMPLETE ALARM DIAGRAM ....................................................................................................... 31
4.6.2. USE OF THE ALARM INTERRUPT .................................................................................................. 32
4.7. EXTERNAL EVENT FUNCTION .............................................................................................................. 33
4.7.1. COMPLETE EXTERNAL EVENT DIAGRAM.................................................................................... 33
4.7.2. USE OF THE EXTERNAL EVENT FUNCTION ................................................................................ 34
4.8. SERVICING INTERRUPTS ...................................................................................................................... 35
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
4.9. DIGITAL ARCHITECTURE SUMMARY .................................................................................................. 35
4.10. SYNCHRONICITY BETWEEN INT SIGNALS AND 1 HZ CLKOUT ..................................................... 36
4.11. TIME DATA READ-OUT .......................................................................................................................... 37
4.11.1. PROCEDURE ................................................................................................................................... 37
4.11.2. METHODE TO CONFIRM CORRECT TIME AND CALENDAR READ-OUT................................... 37
5. TEMPERATURE COMPENSATION ............................................................................................................... 38
5.1. FREQUENCIES ........................................................................................................................................ 38
5.2. FREQUENCY VS. TEMPERATURE CHARACTERISTICS .................................................................... 38
5.3. COMPENSATION VALUES ..................................................................................................................... 39
5.4. AGING CORRECTION ............................................................................................................................. 39
5.5. CLOCKING SCHEME .............................................................................................................................. 40
5.6. MEASURING TIME ACCURACY AT CLKOUT PIN................................................................................ 41
5.6.1. MEASURING 1 HZ AT CLKOUT PIN ............................................................................................... 41
5.7. MEASURING TIME ACCURACY AT INT PIN ....................................................................................... 42
5.7.1. MEASURING 1 HZ WITH THE PERIODIC TIME UPDATE INTERRUPT FUNCTION .................... 42
2
6. I C INTERFACE .............................................................................................................................................. 43
6.1. BIT TRANSFER ....................................................................................................................................... 43
6.2. START AND STOP CONDITIONS .......................................................................................................... 43
6.3. DATA VALID ............................................................................................................................................ 44
6.4. SYSTEM CONFIGURATION.................................................................................................................... 44
6.5. ACKNOWLEDGE ..................................................................................................................................... 45
6.6. SLAVE ADDRESS ................................................................................................................................... 46
6.7. WRITE OPERATION ................................................................................................................................ 46
6.8. READ OPERATION AT SPECIFIC ADDRESS ....................................................................................... 47
6.9. READ OPERATION ................................................................................................................................. 48
7. ELECTRICAL SPECIFICATIONS................................................................................................................... 49
7.1. ABSOLUTE MAXIMUM RATINGS .......................................................................................................... 49
7.2. OPERATING PARAMETERS .................................................................................................................. 50
7.2.1. TEMPERATURE COMPENSATION AND CURRENT CONSUMPTION ......................................... 51
7.3. OSCILLATOR PARAMETERS ................................................................................................................ 52
7.3.1. TIME ACCURACY 1 HZ EXAMPLE .................................................................................................. 52
7.4. POWER ON AC ELECTRICAL CHARACTERISTICS ............................................................................ 53
7.5. BACKUP AND RECOVERY .................................................................................................................... 54
2
7.6. I C AC ELECTRICAL CHARACTERISTICS ........................................................................................... 55
8. APPLICATION INFORMATION ...................................................................................................................... 57
8.1. OPERATING RV-8803-C7 WITH BACKUP CAPACITOR ...................................................................... 57
9. RECOMMENDED REFLOW TEMPERATURE (LEADFREE SOLDERING) ................................................. 58
10. PACKAGE ....................................................................................................................................................... 59
10.1. DIMENSIONS AND SOLDER PAD LAYOUT .......................................................................................... 59
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
10.2. MARKING AND PIN #1 INDEX ................................................................................................................ 59
11. PACKING INFORMATION .............................................................................................................................. 60
11.1. CARRIER TAPE ....................................................................................................................................... 60
11.2. PARTS PER REEL ................................................................................................................................... 60
11.3. REEL 7 INCH FOR 12 mm TAPE ............................................................................................................ 61
11.4. HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED CRYSTALS ........ 62
12. DOCUMENT REVISION HISTORY................................................................................................................. 63
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
RV-8803-C7
Highly accurate DTCXO Temperature Compensated Real Time Clock / Calendar Module
with I2C Interface
1. OVERVIEW
















32.768 kHz built-in “Tuning Fork” crystal oscillator
Counters for hundredths, seconds, minutes, hours, date, month, year, century and weekday
Factory calibrated temperature compensation
Very high Time Accuracy
o ± 1.5 ppm 0 to +50°C
o ± 3.0 ppm -40 to +85°C
o Aging compensation with OFFSET value
2
I C (up to 400 kHz) serial interface
Periodic Countdown Timer Interrupt function
Periodic Time Update Interrupt function (seconds, minutes)
Alarm Interrupts for date, weekday, hour and minute settings
External Event Input with Interrupt and Time Stamp function
Programmable Clock Output for peripheral devices (32.768 kHz, 1.024 kHz, 1 Hz) with enable/disable
function (CLKOE)
Automatic leap year calculation (2000 to 2099)
Wide operating voltage range: 1.5 V to 5.5 V
Very low current consumption: 240 nA (VDD = 3.0 V)
Operating temperature range: -40 to +85°C
Ultra small and compact C7 package size, RoHS-compliant and 100% leadfree: 3.2 x 1.5 x 0.8 mm
Register compatible with Epson RX-8803SA/LC
1.1. GENERAL DESCRIPTION
The RV-8803-C7 is a highly accurate real-time clock/calendar module due to its built-in Thermometer and Digital
Temperature Compensation circuitry (DTCXO). The Temperature Compensation circuitry is factory calibrated and
results in highest time accuracy of ± 3.0 ppm across the temperature range from -40 to +85°C, and additionally
offers an aging offset correction.
The RV-8803-C7 has the smallest package and the lowest current consumption among all temperature
compensated RTC modules. Due to its special architecture the RV-8803-C7 provides a very low current
consumption of 240 nA.
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
1.2. APPLICATIONS
The RV-8803-C7 RTC module combines key functions with outstanding performance in an ultra-small ceramic
package:
 Factory calibrated Temperature Compensation with temperature measuring every second
 Ultra Low Power consumption
 Smallest RTC module (embedded XTAL) in an ultra-small 3.2 x 1.5 x 0.8 mm leadfree ceramic package.
These unique features make this product perfectly suitable for many applications:
 Communication: IoT / Wireless Sensors and Tags / Handsets / Communications equipment
 Automotive:
Navigation & Tracking Systems / Dashboard / Tachometers / Engine Controller / Car
Audio & Entertainment Systems
 Metering:
E-Meter / Heating Counter / Smart Meters / PV Converter
 Outdoor:
ATM & POS systems / Surveillance & Safety systems / Ticketing Systems
 Medical:
Glucose Meter / Health Monitoring Systems
 Safety:
DSLR / Security & Camera Systems / Door Lock & Access Control
 Consumer:
Gambling Machines / TV & Set Top Boxes / White Goods
 Automation:
DSC / Data Logger / Home & Factory Automation / Industrial and Consumer Electronics
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
2. BLOCK DIAGRAM
VDD
VSS
SCL
SDA
3
Power
Control
5
8
2
1
I C-BUS
Interface
T-Sensor
Calibration Engine
Xtal Osc
CLKOUT
CLKOE
2
4
6
INT
EVI
Divider
INPUT
OUTPUT
CONTROL
7
Reset
System Control
logic
Seconds
Minutes
Hours
Weekday
Date
Month
Year
RAM
Minutes Alarm
Hours Alarm
Weekday Alarm
Date Alarm
Timer Counter 0
Timer Counter 1
Extension Register
Flag Register
Control register
100th Seconds
Seconds
Minutes
Hours
Weekday
Date
Month
Year
Minutes Alarm
Hours Alarm
Weekday Alarm
Date Alarm
Timer Counter 0
Timer Counter 1
Extension Register
Flag Register
Control Register
100th Seconds CP
Seconds CP
Offset
Event Control
00
08
0A
0F
10
18
1A
1F
20
21
2C
2F
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
2.1. PINOUT
C7 Package: (top view)
#8
#5
#1
SDA
#8
SCL
#2
CLKOUT
#7
EVI
#3
VDD
#6
̅̅̅̅̅
INT
#4
CLKOE
#5
VSS
8803
#1
#4
2.2. PIN DESCRIPTION
Symbol
Pin #
SDA
1
CLKOUT
2
VDD
3
CLKOE
4
VSS
5
̅̅̅̅̅
INT
6
EVI
SCL
7
8
Description
I2C Serial Data; open-drain; requires pull-up resistor.
Clock Output; push-pull; controlled by CLKOE. If CLKOE is active HIGH, the CLKOUT pin drives
the square wave of 32.768 kHz, 1.024 kHz or 1 Hz (Default value is 32.768 kHz). When CLKOE is
tied to Ground, the CLKOUT pin is high impedance (tri-state).
Power Supply Voltage.
Input to enable the CLKOUT pin. If CLKOE is active HIGH, the CLKOUT pin is in output mode.
When CLKOE is tied to Ground, the CLKOUT pin is stopped and is high impedance (tri-state).
Ground.
Interrupt Output; open-drain; requires pull-up resistor; Used to output Alarm, Periodic Countdown
Timer, Periodic Time Update and External Event Interrupt signals.
External Event Interrupt Input with Time Stamp function.
I2C Serial Clock Input; open-drain; requires pull-up resistor.
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
2.3. FUNCTIONAL DESCRIPTION
The RV-8803-C7 is a high accurate, ultra-low power CMOS based Real-Time-Clock Module with embedded 32.768
kHz Crystal. The Xtal 32.768 kHz clock itself is not temperature compensated.
The very high Time Accuracy and stability of ± 3.0 ppm over the full temperature range from -40°C to +85°C is
achieved by the built-in Digital Temperature Compensation circuitry (DTCXO). The factory calibrated correction
values are located in the EEPROM and are not accessible for the user. Additionally, there is an Offset Register
customer use for aging correction.
The RV-8803-C7 provides standard Clock & Calendar function including seconds, minutes, hours (24), weekdays,
date, months, years (with leap year calculation) and interrupt functions for an External Event, Periodic Countdown
Timer, Periodic Time Update and Alarm. Beside the standard RTC functions, it includes an integrated Temperature
2
Sensor, a Time Stamp function for the External Event Input and 1 Byte of User RAM and offers an I C-bus (2-wire
Interface). Further 2 Bytes can be used as User RAM when the Periodic Countdown Timer is not used (Timer
Counter registers 0Bh, 1Bh and 0Ch, 1Ch) and further 3 Bytes when the Alarm function is not used (Alarm
registers 08h, 18h; 09h, 19h and 0Ah, 1Ah).
The registers are accessed by selecting a register address and then performing read or write operations. Multiple
reads or writes may be executed in a single access, with the address automatically incrementing after each byte.
2.4. DEVICE PROTECTION DIAGRAM
SDA
CLKOUT
VDD
CLKOE
1
8
2
7
3
6
4
5
SCL
EVI
INT
VSS
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
3. REGISTER ORGANIZATION
Registers are accessed by selecting a register address and then performing read or write operations. Multiple
reads or writes may be executed in a single access, with the address automatically incrementing after each byte.
The following tables Register Definitions (00h to 0Fh), (10h to 1Fh) and (20h to 2Fh) summarize the function of
each register. In the table Register Definitions (00h to 0Fh) and (10h to 1Fh) the GPx bits (where x is between 0
and 5) are 6 register bits which may be used as general purpose storage. These bits are not described in the
sections below. All of the GPx bits are cleared when the RV-8803-C7 powers up, and they can therefore be used to
allow software to determine if a true Power On Reset has occurred or hold other initialization data.



Address 00h to 0Fh: Basic time and calendar register
Address 10h to 1Fh: Extension register 
Address 20h to 2Fh: Extension register 
Adds RAM
th
Adds 100 Seconds counter
Capture buffer and Event control
Note: When writing or reading a specific function value into/from the Address range 00h to 0Fh the value will be
automatically updated in the Address range 10h to 1Fh and vice versa.
In order to not corrupt the accuracy of the temperature compensation and the Time Stamp (Capture) function on
th
the highest 100 Seconds resolution, it is not possible to freeze the clock and calendar register during read-out
process, as it is common practice for other RTC’s.
Since the time and calendar registers cannot be frozen, there might be a condition that the time registers are
incremented while read-out. To avoid reading corrupted (partially incremented) data, special measures and
procedures need to be applied (see TIME DATA READ-OUT).
3.1. REGISTER OVERVIEW
Register Definitions, Address 00h to 0Fh (Basic time and calendar register):
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Function
Seconds
Minutes
Hours
Weekday
Date
Month
Year
RAM
Minutes Alarm
Hours Alarm
Weekday Alarm
Date Alarm
Timer Counter 0
Timer Counter 1
Extension Register
Flag Register
Control Register
Bit 7
Bit 6
Bit 5
○
○
○
○
○
○
80
40
40
○
6
○
○
40
20
20
20
5
20
○
20
AE_M
AE_H
40
GP0
6
GP1
64
GP4
WADA
○
20
20
5
20
32
GP3
USEL
UF
UIE
AE_WD
128
GP5
TEST
○
X
Bit 4
Bit 3
Bit 2
10
8
4
10
8
4
10
8
4
4
3
2
10
8
4
10
8
4
10
8
4
RAM data
10
8
4
10
8
4
4
3
2
10
8
4
16
8
4
GP2
2048
1024
TE
FD
TF
AF
EVF
TIE
AIE
EIE
Bit 1
Bit 0
2
2
2
1
2
2
2
1
1
1
0
1
1
1
2
2
1
2
2
512
1
1
0
1
1
256
TD
V2F
○
V1F
RESET
○ Read only. Always 0.
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
Register Definitions, Address 10h to 1Fh (Extension register ):
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
th
80
○
○
○
○
○
○
80
AE_M
AE_H
40
40
40
○
6
○
○
40
40
GP0
6
GP1
64
GP4
WADA
○
20
20
20
20
5
20
○
20
20
20
5
20
32
GP3
USEL
UF
UIE
10
10
10
10
4
10
10
10
10
10
4
10
16
GP2
TE
TF
TIE
8
8
8
8
3
8
8
8
8
8
3
8
8
2048
4
4
4
4
2
4
4
4
4
4
2
4
4
1024
2
2
2
2
1
2
2
2
2
2
1
2
2
512
1
1
1
1
0
1
1
1
1
1
0
1
1
256
AF
AIE
EVF
EIE
V2F
○
V1F
RESET
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
100 Seconds (Read Only)
Seconds
Minutes
Hours
Weekday
Date
Month
Year
Minutes Alarm
Hours Alarm
Weekday Alarm
Date Alarm
Timer Counter 0
Timer Counter 1
Extension Register
Flag Register
Control Register
AE_WD
128
GP5
TEST
○
X
FD
TD
Register Definitions, Address 20h to 2Fh (Extension register ):
Address
20h
21h
2Ch
2Fh
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80
40
20
10
8
4
2
1
○
○
ECP
40
○
EHL
20
10
8
4
2
1
○
○
ERST
100th Seconds CP (Read
Only)
Seconds CP (Read Only)
Offset
Event Control
OFFSET
ET
○
3.1.1.AUTO-INCREMENTING
When address is automatically incremented, wrap around occurs from the address FFh to the address 00h (see
figure below).
Auto-incrementing of the registers:
Address
00h
wrap around
01h
02h
03h
autoincrement
:
FDh
FEh
FFh
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
3.2. CLOCK REGISTERS
th
10h - 100 Seconds (Read Only)
This register holds the count of hundredths of seconds, in two binary coded decimal (BCD) digits. Values will be
from 00 to 99.
Address
Function
10h
100th Seconds (Read Only)
Reset
Bit
Symbol
7:0
100th Seconds (Read Only)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Value
00 to 99
Description
Holds the count of hundredths of seconds, coded in BCD format.
The 100th Seconds register is cleared to 00 when writing to the Seconds
register or when setting the RESET bit to 1 or when the ERST bit is 1 in
case of an External Event detection on EVI pin.
00h, 11h - Seconds
This register holds the count of seconds, in two binary coded decimal (BCD) digits. Values will be from 00 to 59.
Addresses
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00h, 11h(1)
Seconds
Reset
○
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6:0
○
Seconds
0
00 to 59
Description
Read only. Always 0.
Holds the count of seconds, coded in BCD format.
01h, 12h - Minutes
This register holds the count of minutes, in two binary coded decimal (BCD) digits. Values will be from 00 to 59.
Addresses
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h, 12h(1)
Minutes
Reset
○
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6:0
○
Minutes
0
00 to 59
Description
Read only. Always 0.
Holds the count of minutes, coded in BCD format.
02h, 13h - Hours
This register holds the count of hours, in two binary coded decimal (BCD) digits. Values will be from 00 to 23.
(1)
Addresses
Function
02h, 13h(1)
Hours
Reset
Bit
Symbol
7:6
5:0
○
Hours
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
○
0
○
0
20
0
10
0
8
0
4
0
2
0
1
0
Value
0
00 to 23
Description
Read only. Always 0.
Holds the count of hours, coded in BCD format.
This specific function accessed in Address range 00h to 0Fh is automatically updated in Address range 10h to
1Fh and vice versa.
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
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3.3. CALENDAR REGISTERS
03h, 14h - Weekday
This register holds the current day of the week. Each bit represents one weekday that is assigned by the user.
Values will range from 1 to 7. Do not set 1 to more than one bit.
Addresses
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Weekday
Reset
○
0
7
1
6
0
5
0
4
0
3
0
2
0
1
0
Bit
Symbol
Value
7
6:0
○
Weekday
0
1 to 7
03h, 14h
(1)
Weekday
Weekday 1
Weekday 2
Weekday 3
Weekday 4
Weekday 5
Weekday 6
Weekday 7 – Default value
Description
Read only. Always 0.
Holds the weekday counter value. Do not set 1 to more than one bit.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
04h, 15h – Date
This register holds the current day of the month, in two binary coded decimal (BCD) digits. Values will range from
00 to 31. The Reset value 00 after POR has to be replaced by a valid initial value (01 to 31). Leap years are
correctly handled from 2000 to 2099.
Addresses
Function
04h, 15h(1)
Date
Reset
Bit
Symbol
7:6
○
5:0
Date
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
○
0
○
0
20
0
10
0
8
0
4
0
2
0
1
0
Value
0
00 to 31
Description
Read only. Always 0.
Holds the current date of the month, coded in BCD format. The Reset
value 00 after POR has to be replaced by a valid initial value (01 to 31).
05h, 16h - Month
This register holds the current month, in two binary coded decimal (BCD) digits. Values will range from 01 to 12.
(1)
Addresses
Function
05h, 16h(1)
Month
Reset
Bit
Symbol
7:5
4:0
○
Month
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
○
0
○
0
○
0
10
0
8
0
4
0
2
0
1
1
Value
0
01 to 12
Description
Read only. Always 0.
Holds the current month, coded in BCD format.
This specific function accessed in Address range 00h to 0Fh is automatically updated in Address range 10h to
1Fh and vice versa.
13/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
06h, 17h - Year
This register holds the current year, in two binary coded decimal (BCD) digits. Values will range from 00 to 99.
Addresses
Function
06h, 17h(1)
Year
Reset
Bit
Symbol
7:0
Year
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit 2
Bit 1
Bit 0
0
0
0
Value
00 to 99
Description
Holds the current year, coded in BCD format.
07h - RAM
This register holds the bits for general purpose use.
Address
(1)
Function
07h
RAM
Reset
Bit
Symbol
7:0
RAM
Bit 7
Bit 6
Bit 5
0
0
0
Value
00h to
FFh
Bit 4
Bit 3
RAM data
0
0
Description
User RAM
This specific function accessed in Address range 00h to 0Fh is automatically updated in Address range 10h to
1Fh and vice versa.
14/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
3.4. ALARM REGISTERS
08h, 18h – Minutes Alarm
This register holds the Minutes Alarm Enable bit AE_M and the alarm value for minutes, in two binary coded
decimal (BCD) digits. Values will range from 00 to 59.
Addresses
08h, 18h
(1)
Bit
7
6:0
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Minutes Alarm
Reset
AE_M
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Symbol
AE_M
Minutes Alarm
Value
Description
Minutes Alarm Enable bit. Enables alarm together with AE_H and AE_WD (see USE
OF THE ALARM INTERRUPT).
0
Minutes Alarm is enabled.
1
Minutes Alarm is disabled.
00 to 59 Holds the alarm value for minutes, coded in BCD format.
09h, 19h – Hours Alarm
This register holds the Hours Alarm Enable bit AE_H and the alarm value for hours, in two binary coded decimal
(BCD) digits. Values will range from 00 to 23.
Addresses
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
09h, 19h(1)
Hours Alarm
Reset
AE_H
0
GP0
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit
7
6
5:0
(1)
Symbol
AE_H
GP0
Hours Alarm
Value
Description
Hours Alarm Enable bit. Enables alarm together with AE_M and AE_WD (see USE OF
THE ALARM INTERRUPT).
0
Hours Alarm is enabled.
1
Hours Alarm is disabled.
0 or 1
Register bit for general purpose use.
00 to 23 Holds the alarm value for hours, coded in BCD format.
This specific function accessed in Address range 00h to 0Fh is automatically updated in Address range 10h to
1Fh and vice versa.
15/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
0Ah, 1Ah – Weekday/Date Alarm
This register holds the Weekday/Date Alarm Enable bit AE_WD. If the WADA bit is 0 (Bit 6 in Register 0Dh, 1Dh), it
holds the alarm value for the day of the week (weekdays assigned by the user). Multiple days can be selected.
Values will range from 0000001 to 1111111. If the WADA bit is 1, it holds the alarm value for the date, in two binary
coded decimal (BCD) digits. Values will range from 01 to 31. Leap years are correctly handled from 2000 to 2099.
Weekday Alarm when WADA = 0 (Bit 6 in Register 0Dh, 1Dh)
Addresses
0Ah, 1Ah
(1)
Function
Weekday Alarm
Reset
Bit
Symbol
7
AE_WD
6:0
Weekday Alarm
Weekday Alarm
Weekday 1 Alarm
Weekday 2 Alarm
Weekday 3 Alarm
Weekday 4 Alarm
Weekday 5 Alarm
Weekday 6 Alarm
Weekday 7 Alarm
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AE_WD
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Value
Description
Weekday/Date Alarm Enable bit. Enables alarm together with AE_M and AE_H (see
USE OF THE ALARM INTERRUPT).
0
Weekday/Date Alarm is enabled.
1
Weekday/Date Alarm is disabled.
0000001
to
1111111
Holds the weekday alarm value. Multiple days can be selected.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 or 1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
Date Alarm when WADA = 1 (Bit 6 in Register 0Dh, 1Dh)
Addresses
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ah, 1Ah(1)
Date Alarm
Reset
AE_WD
0
GP1
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
7
AE_WD
Value
Description
Weekday/Date Alarm Enable bit. Enables alarm together with AE_M and AE_H (see
USE OF THE ALARM INTERRUPT).
0
Weekday/Date Alarm is enabled
1
Weekday/Date Alarm is disabled
0 or 1
Register bit for general purpose use.
01 to 31 Holds the alarm value for the date, coded in BCD format.
6
5:0
(1)
GP1
Date Alarm
This specific function accessed in Address range 00h to 0Fh is automatically updated in Address range 10h to
1Fh and vice versa.
16/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
3.5. PERIODIC COUNTDOWN TIMER CONTROL REGISTERS
0Bh, 1Bh – Timer Counter 0
This register is used to set the lower 8 bits of the preset value for the Periodic Countdown Timer.
Addresses
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 1Bh(1)
Timer Counter 0
Reset
128
0
64
0
32
0
16
0
8
0
4
0
2
0
1
0
Bit
7:0
Symbol
Timer Counter 0
Value
Description
00h to
FFh
The preset value for the Periodic Countdown Timer (lower 8 bit) (see USE
OF THE PERIODIC COUNTDOWN TIMER). When read, only the preset
value is returned and not the actual value.
0Ch, 1Ch – Timer Counter 1
This register is used to set the upper 4 bits of the preset value for the Periodic Countdown Timer.
Addresses
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch, 1Ch(1)
Timer Counter 1
Reset
GP5
0
GP4
0
GP3
0
GP2
0
2048
0
1024
0
512
0
256
0
Symbol
Value
GP2
GP3
GP4
GP5
0 or 1
0 or 1
0 or 1
0 or 1
Register bit for general purpose use.
Register bit for general purpose use.
Register bit for general purpose use.
Register bit for general purpose use.
Timer Counter 1
0h to
Fh
The preset value for the Periodic Countdown Timer (upper 4 bit) (see USE
OF THE PERIODIC COUNTDOWN TIMER). When read, only the preset
value is returned and not the actual value.
Bit
7
6
5
4
3:0
(1)
Description
This specific function accessed in Address range 00h to 0Fh is automatically updated in Address range 10h to
1Fh and vice versa.
17/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
3.6. EXTENSION REGISTER
0Dh, 1Dh – Extension Register
This register is used to specify the target for the Alarm Interrupt function and the Periodic Time Update Interrupt
function and to select or set operations for the Periodic Countdown Timer.
Addresses
0Dh, 1Dh
(1)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Extension Register
Reset
TEST
0
WADA
0
USEL
0
TE
0
Symbol
Value
7
TEST
6
WADA
5
USEL
4
TE
3:2
FD
1:0
TD
TD Value
(1)
Function
Timer source frequency
Bit 3
Bit 2
Bit 1
FD
0
Bit 0
TD
0
0
0
Description
This is a manufacturer’s test bit. Its value should always be 0. Avoid writing
0
a 1 to this bit when writing in this register. Zero for normal operation.
Weekday Alarm / Date Alarm selection bit. This bit is used to specify either the
Weekday or Date as the source for the Alarm Interrupt function.
0
Weekday is the source for the Alarm Interrupt function. – Default value
1
Date is the source for the Alarm Interrupt function.
Update Interrupt Select bit. Specifies either Second or Minute update for the Periodic
Time Update Interrupt function.
0
Second update (Auto reset time tRTN = 500 ms). – Default value
1
Minute update (Auto reset time tRTN = 15.6 ms).
Periodic Countdown Timer Enable bit. This bit controls the start/stop setting for the
Periodic Countdown Timer Interruption function.
0
Stops the Periodic Countdown Timer Interrupt function. – Default value
Starts the Periodic Countdown Timer Interrupt function (a countdown starts
1
from a preset value).
CLKOUT frequency selection. Sets the output frequency on the CLKOUT pin.
00
32.768 kHz – Default value
01
1.024 kHz
10
1 Hz
11
32.768 kHz
Timer source frequency selection. Sets the countdown source clock for the
Periodic Countdown Timer Interrupt function. With this setting the Auto
00 to 11 reset time tRTN and the effect of the RESET bit is also defined. See table
below (see also PERIODIC COUNTDOWN TIMER INTERRUPT
FUNCTION).
Countdown period
tRTN
00
4.096 kHz – Default value
244.14 μs
122 μs
01
10
11
64 Hz
1 Hz
1/60 Hz
15.625 ms
1s
60 s
7.813 ms
7.813 ms
7.813 ms
RESET bit
The RESET bit has no
effect.
If the RESET bit = 1, the
interrupt function is
stopped.
This specific function accessed in Address range 00h to 0Fh is automatically updated in Address range 10h to
1Fh and vice versa.
18/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
3.7. FLAG REGISTER
0Eh, 1Eh – Flag Register
This register holds a variety of status bits. The register may be written at any time to clear any status flag.
Addresses
Function
0Eh, 1Eh(1)
Flag Register
Reset
Bit
Symbol
7:6
○
5
UF
4
TF
3
AF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
○
0
○
0
UF
0
TF
0
AF
0
EVF
X
V2F
1
V1F
1
Value
Description
0
Read only. Always 0.
Periodic Time Update Flag (see PERIODIC TIME UPDATE INTERRUPT FUNCTION)
0
It can be cleared by writing a 0 to the bit.
If set to 0 beforehand, indicates the occurrence of a Periodic Time Update
1
Interrupt event.
Periodic Countdown Timer Flag (see PERIODIC COUNTDOWN TIMER INTERRUPT
FUNCTION)
0
It can be cleared by writing a 0 to the bit.
If set to 0 beforehand, indicates the occurrence of a Periodic Countdown
1
Timer Interrupt event.
Alarm Flag (see ALARM INTERRUPT FUNCTION)
0
It can be cleared by writing a 0 to the bit.
If set to 0 beforehand, indicates the occurrence of an Alarm Interrupt
1
event.
External Event Flag (see EXTERNAL EVENT FUNCTION).
2
EVF
X
0
1
0
1
V2F
1
0
0
V1F
1
(1)
The Reset value X depends on the voltage on the EVI pin at POR and has
to be cleared by writing a 0 to the bit. Because EHL = 0 at POR, the low
level is regarded as an External Event Interrupt.
If X =1, a LOW level was detected on EVI pin.
If X =0, no LOW level was detected on EVI pin.
It can be cleared by writing a 0 to the bit.
If set to 0 beforehand, indicates the occurrence of an External Event.
Voltage Low Flag 2
Read: No data loss detected.
Write: The V2F bit is cleared to prepare for a next low voltage detection.
V1F is also cleared.
Read: Set if the voltage crosses VLOW2 voltage and the data in the device
are no longer valid. All registers must be initialized. It can be cleared by
writing a 0 to the bit. The flag is also automatically set to 1 at power on
reset (POR) and has to be cleared by writing a 0 to the bit.
Write: The V2F bit remains unchanged.
Voltage Low Flag 1
Read: Temperature compensation is effective.
Write: The V1F bit is cleared to prepare for a next low voltage detection.
V2F is also cleared.
Read: Set if the voltage crosses VLOW1 voltage and the temperature
compensation is stopped. It can be cleared by writing a 0 to the bit. The
flag is also automatically set to 1 at power on reset (POR) and has to be
cleared by writing a 0 to the bit.
Write: The V1F bit remains unchanged.
This specific function accessed in Address range 00h to 0Fh is automatically updated in Address range 10h to
1Fh and vice versa.
19/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
3.8. CONTROL REGISTER
0Fh, 1Fh – Control Register
This register is used to control the interrupt event output from the ̅̅̅̅̅
INT pin and the stop/start status of clock and
calendar operations.
Addresses
Function
0Fh, 1Fh(1)
Control Register
Reset
Bit
Symbol
7:6
X
Bit 7
0
UIE
TIE
0
AIE
1
0
EIE
1
(1)
1
○
0
RESET
Bit 2
Bit 1
Bit 0
0
AIE
0
EIE
0
○
0
RESET
0
Description
1
2
Bit 3
TIE
0
Unused, but has to be 0 to avoid extraneous leakage.
Periodic Time Update Interrupt Enable
No interrupt signal is generated on ̅̅̅̅̅
INT pin when a Periodic Time Update
̅̅̅̅̅ pin.
event occurs or the signal is cancelled on INT
An interrupt signal is generated on ̅̅̅̅̅
INT pin when a Periodic Time Update
event occurs. The low-level output signal is automatically cleared after tRTN
= 500 ms (Second update) or tRTN = 15.6 ms (Minute update).
Periodic Countdown Timer Interrupt Enable
No interrupt signal is generated on ̅̅̅̅̅
INT pin when a Periodic Countdown
̅̅̅̅̅ pin.
Timer event occurs or the signal is cancelled on INT
An interrupt signal is generated on ̅̅̅̅̅
INT pin when a Periodic Countdown
Timer event occurs. The low-level output signal is automatically cleared
after tRTN = 122 µs (TD = 00) or tRTN = 7.813 ms (TD = 01, 10, 11).
Alarm Interrupt Enable
̅̅̅̅̅ pin when an Alarm event occurs or
No interrupt signal is generated on INT
the signal is cancelled on ̅̅̅̅̅
INT pin.
̅̅̅̅̅ pin when an Alarm event occurs.
An interrupt signal is generated on INT
This setting is retained until the AF bit value is cleared to 0 (no automatic
cancellation).
External Event Interrupt Enable
̅̅̅̅̅ pin when an External Event on EVI
No interrupt signal is generated on INT
pin occurs.
̅̅̅̅̅ pin when an External Event on EVI
An interrupt signal is generated on INT
pin occurs. This setting is retained until the EVF bit value is cleared to 0
(no automatic cancellation).
Read only. Always 0.
The reset is released.
Values less than seconds of the counter in the clock and calendar circuitry
are reset to 0 (2 Hz to 16 kHz), and the clock also stops. The 100th
Seconds register is also reset to 0.
The Periodic Countdown Timer, Periodic Time Update and Alarm
Interrupts do not occur.
0
3
Bit 4
UIE
0
0
1
4
Bit 5
Value
0
5
Bit 6
X
0
0
1
This specific function accessed in Address range 00h to 0Fh is automatically updated in Address range 10h to
1Fh and vice versa.
20/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
3.9. OFFSET REGISTER
2Ch – Offset Register
This register holds the OFFSET value for the aging correction.
Addresses
Function
2Ch
Offset
Reset
Bit
Symbol
7:6
○
5:0
OFFSET
Bit 7
Bit 6
○
0
○
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
OFFSET
0
0
0
0
Value
Description
0
Read only. Always 0.
The amount of the effective frequency offset. This is a two's complement
number with a range of -32 to +31 adjustment steps (maximum correction
range is roughly +/-7.4 ppm). The correction value of one LSB corresponds
to 1/(32768*128) = 0.2384 ppm (see AGING CORRECTION).
-32 to
+31
OFFSET
Unsigned value
Two’s complement
011111
011110
:
000001
000000
31
30
:
1
0
31
30
:
1
0
Offset value in ppm(*)
7.391
7.153
:
0.238
0.000
111111
111110
:
100001
100000
63
62
:
33
32
-1
-2
:
-31
-32
-0.238
-0.477
:
-7.391
-7.629
(*) Calculated with 5 decimal places (1/(32768*128) = 0.23842 ppm)
21/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
3.10. CAPTURE BUFFER/EVENT CONTROL REGISTERS
th
20h – 100 Seconds CP (Read Only)
th
This register holds a captured (copied) value of the 100 Seconds register (Time Stamp), in two binary coded
decimal (BCD) digits. The values are from 00 to 99.
Address
20h
Bit
7:0
Function
100th Seconds CP (Read
Only)
Reset
Symbol
100th Seconds CP (Read
Only)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80
40
20
10
8
4
2
1
0
0
0
0
0
0
0
0
Value
00 to 99
Description
Holds a captured value of the 100th Seconds register, coded in BCD
format.
21h - Seconds CP (Read Only)
This register holds a captured (copied) value of the Seconds register (Time Stamp), in two binary coded decimal
(BCD) digits. The values are from 00 to 59.
Addresses
Function
21h
Seconds CP (Read Only)
Reset
Bit
Symbol
7
6:0
○
Seconds CP (Read Only)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
○
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Value
0
00 to 59
Description
Read only. Always 0.
Holds a captured value of the Seconds register, coded in BCD format.
22/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
2Fh – Event Control
This register controls the event detection on the EVI pin. Depending of the EHL bit a high or a low signal can be
detected. Moreover a digital glitch filtering can be applied to the EVI signal by selecting a sampling period in the ET
field.
Addresses
Function
Bit 7
Bit 6
2Fh
Event Control
Reset
ECP
0
EHL
0
Bit
Symbol
Value
7
ECP
6
EHL
5:4
ET
3:1
○
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
○
0
○
0
○
0
ERST
0
ET
0
Description
Event Capture Enable (Time Stamp Enable)
0
Disables the Event Capture.
An External Event detected on pin EVI will cause a capture of the Seconds
1
and the 100th Seconds, i.e. they are copied into the Seconds CP and 100th
Seconds CP registers.
Event High/Low detection Select
0
The LOW level is regarded as the External Event Interrupt on pin EVI.
1
The HIGH level is regarded as the External Event Interrupt on pin EVI.
Event Filtering Time set. Applies a digital filtering to the EVI pin by sampling the EVI
signal. Edge and level detection when ET = 01, 10 or 11 (see USE OF THE
EXTERNAL EVENT ).
00
No filtering. Edge detection (minimal pulse time is 30.5 µs). – Default value
01
3.9 ms sampling period (256 Hz).
10
15.6 ms sampling period (64 Hz).
11
125 ms sampling period (8 Hz).
0
Read only. Always 0.
Event Reset. This bit is used for a hardware-based time adjustment (synchronizing)
(see USE OF THE EXTERNAL EVENT ).
0
No reset if an External Event is detected.
In case of an External Event detection at the EVI pin, the counters at below
the second are reset to 0 (2 Hz to 16 kHz). This means that the 100th
Seconds Register (100 Hz) is reset to 0. Moreover, the 100th Seconds CP
and Seconds CP registers are also reset to 0, whatever the ECP value is.
After the event detection, the ERST bit is reset to 0.
ERST
1
Be aware that the setting back of the counters at below the second
influences also the operation of the other three interrupt functions:
Periodic Countdown Timer Interrupt function
Periodic Time Update Interrupt function
Alarm Interrupt function
When 1, the reset function may be cancelled when the ERST bit is set
back to 0 before an event occurs.
23/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
3.11. REGISTER RESET VALUES SUMMARY
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10h
00h, 11h(1)
01h, 12h(1)
02h, 13h(1)
03h, 14h(1)
04h, 15h(1)
05h, 16h(1)
06h, 17h(1)
07h
08h, 18h(1)
09h, 19h(1)
th
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0Ah, 1Ah(1)
(1)
0Bh, 1Bh
0Ch, 1Ch(1)
0Dh, 1Dh(1)
0Eh, 1Eh(1)
0Fh, 1Fh(1)
20h
21h
2Ch
2Fh
(1)
100 Seconds (Read Only)
Seconds
Minutes
Hours
Weekday
Date
Month
Year
RAM
Minutes Alarm
Hours Alarm
Weekday Alarm / Date
Alarm
Timer Counter 0
Timer Counter 1
Extension Register
Flag Register
Control Register
100th Seconds CP (Read
Only)
Seconds CP (Read Only)
Offset
Event Control
This specific function accessed in Address range 00h to 0Fh is automatically updated in Address range 10h to
1Fh and vice versa.
24/63
Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
4. DETAILED FUNCTIONAL DESCRIPTION
4.1. POWER ON RESET (POR)
The power on reset (POR) is generated at start-up (see POWER ON AC ELECTRICAL CHARACTERISTICS). All
registers including the Counter Registers are initialized to their reset values.
4.2. POWER MANAGEMENT
The circuit is always on and each temperature sensing interval, i.e. every second, is temperature compensated.
2
The digital part is always on, but some functions are clock gated (like I C). By default, at power up, the circuit will
2
always go to the lower power consumption mode (power-off). Detecting an activity on the I C will wake-up the
digital part of the circuit. To achieve the specified time keeping current consumption, extra features like CLKOUT
2
and I C interface need to be inactive.
4.3. CLOCK SOURCE
The built-in 32.768 kHz crystal is the clock source for the digital part. After thermal compensation, the RV-8803-C7
provides a very accurate time with temperature compensation for an outstanding low current consumption.
4.4. PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION
The Periodic Countdown Timer Interrupt function generates an interrupt event periodically at any period set from
244.14 μs to 4095 minutes.
When an interrupt event is generated, the ̅̅̅̅̅
INT pin goes to the low level and the TF flag is set to 1 to indicate that an
event has occurred. The output on the ̅̅̅̅̅
INT pin is only effective if the TIE bit in the Control Register is set to 1. The
low-level output signal on the ̅̅̅̅̅
INT pin is automatically cleared after the Auto reset time tRTN. tRTN = 122 µs (TD = 00)
or tRTN = 7.813 ms (TD = 01, 10, 11).
Periodic Countdown Timer Interrupt Example:
TIE
TE
INT
t RTN
event
1. period
period
period
Write operation
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
4.4.1.COMPLETE PERIODIC COUNTDOWN TIMER DIAGRAM
Complete Diagram of the Periodic Countdown Timer Interrupt function:
TIE
TE
9
7
1
INT
5
6
t RTN
TF
3
event
4
t RTN
t RTN
t RTN
8
2
1. period
period
period
period
Write operation
1
The Periodic Countdown Timer starts from the preset value when writing a 1 to the TE bit.
2
A Periodic Countdown Timer Interrupt event starts a countdown based on the countdown source clock.
When the count value reaches 000h, an interrupt event occurs. After the interrupt, the counter is
automatically reloaded with the preset value, and starts again the countdown.
3
When a Periodic Countdown Timer Interrupt occurs, the TF bit is set to 1.
4
The TF bit retains 1 until it is cleared to 0 by software.
If the TIE bit is 1 and a Periodic Countdown Timer Interrupt occurs, the ̅̅̅̅̅
INT pin output goes low.
6
̅̅̅̅̅
The INT pin output remains low during the Auto reset time tRTN, and then it is automatically cleared to 1.
The TD field determines the source frequency and the Auto reset time tRTN.
tRTN = 122 µs (TD = 00) or tRTN = 7.813 ms (TD = 01, 10, 11).
7
When a 0 is written to the TE bit, the Periodic Countdown Timer function is stopped and the ̅̅̅̅̅
INT pin is
cleared after the Auto reset time tRTN.
8
If the ̅̅̅̅̅
INT pin is low, its status does not change when the TF bit value is cleared to 0.
5
9
̅̅̅̅̅ pin is low, its status changes as soon as the TIE bit value is cleared to 0.
If the INT
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
4.4.2.USE OF THE PERIODIC COUNTDOWN TIMER
The following registers, fields and bits are related to the Periodic Countdown Timer Interrupt function:
 Timer Counter 0 Register (0Bh, 1Bh) (see PERIODIC COUNTDOWN TIMER CONTROL REGISTERS)
 Timer Counter 1 Register (0Ch, 1Ch) (see PERIODIC COUNTDOWN TIMER CONTROL REGISTERS)
 TE bit and TD field (see EXTENSION REGISTER, 0Dh, 1Dh)
 TF bit (see FLAG REGISTER, 0Eh, 1Eh)
 TIE bit (see CONTROL REGISTER, 0Fh, 1Fh)
Prior to entering any timer settings for the Periodic Countdown Timer Interrupt, it is recommended to write a 0 to
̅̅̅̅̅ pin. When the RESET bit value is 1, the Periodic
the TIE and TE bits to prevent inadvertent interrupts on INT
Countdown Timer Interrupt function event does not occur. When the Periodic Countdown Timer Interrupt function is
not used, the 2 Bytes of the Timer Counter registers (0Bh, 1Bh and 0Ch, 1Ch) can be used as RAM bytes. The
Timer source frequency selection field TD is used to set the countdown period (source clock) for the Periodic
Countdown Timer Interrupt function (four settings are possible).
Procedure to use the Periodic Countdown Timer Interrupt function:
1. Initialize bits TIE, TE and TF to 0.
2. Choose the timer source clock and write the corresponding value in the TD field.
3. Choose the interrupt period based on the timer source clock, and write the corresponding preset value to
the registers Timer Counter 0 (0Bh, 1Bh) and Timer Counter 1 (0Ch, 1Ch). See following table.
̅̅̅̅̅ pin.
4. Set the TIE bit to 1 if you want to get a hardware interrupt on INT
5. Set the TE bit from 0 to 1 to start the Periodic Countdown Timer. The countdown starts at the rising edge of
the SCL signal after Bit 0 of the Address D is transferred. The following Figure shows the countdown start
timing.
Interrupt period:
Timer counter setting
(0Bh, 1Bh), (0Ch, 1Ch)
0
1
2
:
41
205
410
2048
:
4095 (FFFh)
TD = 00 (4.096 kHz)
244.14 μs
488.28 μs
:
10.010 ms
50.049 ms
100.10 ms
500.00 ms
:
0.9998 s
Interrupt period
TD = 01 (64 Hz)
TD = 10 (1 Hz)
15.625 ms
31.25 ms
:
640.63 ms
3.203 s
6.406 s
32.000 s
:
63.984 s
1s
2s
:
41 s
205 s
410 s
2048 s
:
4095 s
TD = 11 (1/60 Hz)
1 min
2 min
:
41 min
205 min
410 min
2048 min
:
4095 min
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
Start timing of the Periodic Countdown Timer:
Address D
SCL
TE
FD1
FD0
TD1
TD0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ACK
≈
SDA
≈
Internal Timer
INT
event
1. period
Rising edge of the SCL signal
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RV-8803-C7
4.5. PERIODIC TIME UPDATE INTERRUPT FUNCTION
The Periodic Time Update Interrupt function generates an interrupt event periodically at the One-Second or the
One-Minute update time, according to the selected timer source with bit USEL.
When an interrupt event is generated, the ̅̅̅̅̅
INT pin goes to the low level and the UF flag is set to 1 to indicate that
an event has occurred. The output on the ̅̅̅̅̅
INT pin is only effective if the UIE bit in the Control Register is set to 1.
The low-level output signal on the ̅̅̅̅̅
INT pin is automatically cleared after the Auto reset time tRTN. tRTN = 500 ms
(Second update) or tRTN = 15.6 ms (Minute update).
Periodic Time Update Interrupt Example:
UIE
INT
t RTN
event
period
period
period
Write operation
4.5.1.COMPLETE PERIODIC TIME UPDATE DIAGRAM
Complete Diagram of the Periodic Time Update Interrupt function:
UIE
INT
7
4
5
t RTN
UF
event
2
3
t RTN
t RTN
t RTN
6
1
period
period
period
Write operation
1
A Periodic Time Update Interrupt event occurs when the internal clock value matches either the second or
the minute update time. The USEL bit determines whether it is the Second or the Minute period with the
corresponding Auto reset time tRTN. tRTN = 500 ms (Second update) or tRTN = 15.6 ms (Minute update).
2
When a Periodic Time Update Interrupt occurs, the UF bit is set to 1.
3
The UF bit retains 1 until it is cleared to 0 by software.
If the UIE bit is 1 and a Periodic Time Update Interrupt occurs, the ̅̅̅̅̅
INT pin output goes low.
5
̅̅̅̅̅
The INT pin output remains low during the Auto reset time tRTN, and then it is automatically cleared to 1.
4
6
7
̅̅̅̅̅ pin is low, its status does not change when the UF bit value is cleared to 0.
If the INT
̅̅̅̅̅ pin is low, its status changes as soon as the UIE bit value is cleared to 0.
If the INT
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RV-8803-C7
4.5.2.USE OF THE PERIODIC TIME UPDATE INTERRUPT
The following bits are related to the Periodic Time Update Interrupt function:
 USEL bit (see EXTENSION REGISTER, 0Dh, 1Dh)
 UF bit (see FLAG REGISTER, 0Eh, 1Eh)
 UIE bit (see CONTROL REGISTER, 0Fh, 1Fh)
Prior to entering any other settings, it is recommended to write a 0 to the UIE bit to prevent inadvertent interrupts
̅̅̅̅̅ pin. If the RESET bit is set to 1 (see CONTROL REGISTER, 0Fh, 1Fh) the divider chain is reset and the
on INT
Periodic Time Update Interrupt function will not be triggered. The reset function only interrupts the Periodic Time
Update Interrupt function but does not turn it off.
Procedure to use the Periodic Time Update Interrupt function:
1.
2.
3.
4.
Initialize bits UIE and UF to 0.
Choose the timer source clock and write the corresponding value in the USEL bit.
Set the UIE bit to 1 if you want to get a hardware interrupt on ̅̅̅̅̅
INT pin.
The first interrupt will occur after the next event, either second or minute change.
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RV-8803-C7
4.6. ALARM INTERRUPT FUNCTION
The Alarm Interrupt function generates an interrupt for alarm settings such as date, weekday, hour or minute
settings.
When an interrupt event is generated, the ̅̅̅̅̅
INT pin goes to the low level and the AF flag is set to 1 to indicate that
an event has occurred.
Alarm Interrupt Example:
or AF
AIE
INT
event
alarm
Write operation
4.6.1.COMPLETE ALARM DIAGRAM
Complete Diagram of the Alarm Interrupt function:
AIE
5
INT
4
AF
2
event
3
6
7
1
alarm
alarm
Write operation
1
A date, weekday, hour or minute alarm interrupt event occurs when the selected Alarm register match the
respective counter. The WADA bit determines whether it is the date or weekday.
2
When an Alarm Interrupt event occurs, the AF bit value is set to 1.
3
The AF bit retains 1 until it is cleared to 0 by software.
̅̅̅̅̅ pin output goes low.
If the AIE bit is 1 and an Alarm Interrupt occurs, the INT
4
If the AIE value is changed from 1 to 0 while the ̅̅̅̅̅
INT pin output is low, the ̅̅̅̅̅
INT pin immediately
changes its status. While the AF bit value is 1, the ̅̅̅̅̅
INT status can be controlled by the AIE bit.
6
If the ̅̅̅̅̅
INT pin is low, its status changes as soon as the AF bit value is cleared from 1 to 0.
5
7
If the AIE bit value is 0 when an Alarm Interrupt occurs, the ̅̅̅̅̅
INT pin status does not go low.
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RV-8803-C7
4.6.2.USE OF THE ALARM INTERRUPT
The following registers and bits are related to the Alarm Interrupt function:
 Minutes Register (01h, 12h) (see CLOCK REGISTERS)
 Hours Register (02h, 13h) (see CLOCK REGISTERS)
 Weekday Register (03h, 14h) (see CALENDAR REGISTERS)
 Date Register (04h, 15h) (see CALENDAR REGISTERS)
 Minutes Alarm Register and AE_M bit (08h, 18h) (see ALARM REGISTERS)
 Hours Alarm Register and AE_H bit (09h, 19h) (see ALARM REGISTERS)
 Weekday/Date Alarm Register and AE_WD bit (0Ah, 1Ah) (see ALARM REGISTERS)
 WADA bit (see EXTENSION REGISTER, 0Dh, 1Dh)
 AF bit (see FLAG REGISTER, 0Eh, 1Eh)
 AIE bit (see CONTROL REGISTER, 0Fh, 1Fh)
Prior to entering any timer settings for the Alarm Interrupt, it is recommended to write a 0 to the AIE bit to prevent
inadvertent interrupts on ̅̅̅̅̅
INT pin. When the RESET bit value is 1, the Alarm Interrupt function event does not
occur. When the Alarm Interrupt function is not used, the 3 Bytes of the Alarm registers (08h, 18h; 09h, 19h and
0Ah, 1Ah) can be used as RAM bytes. In such case, be sure to write a 0 to the AIE bit (if the AIE bit value is 1 and
̅̅̅̅̅ may change to low level unintentionally).
the Alarm registers are used as RAM registers, INT
Procedure to use the Alarm Interrupt function:
1. Initialize bits AIE and AF to 0.
2. Choose the weekday alarm or date alarm by setting the WADA bit.
3. Write the desired alarm settings in registers 08h, 18h to 0Ah, 1Ah. The three alarm enable bits, AE_M,
AE_H and AE_WD, are used to select the corresponding register that has to be taken into account for
match or not. See the following table.
4. Set the AIE bit to 1 if you want to get a hardware interrupt on ̅̅̅̅̅
INT pin.
Alarm Interrupt:
AE_WD
Alarm enable bits
AE_H
AE_M
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Alarm event
When minutes, hours and weekday/date match (once per weekday/date)(1) – Default value
When hours and weekday/date match (once per weekday/date)(1)
When minutes and weekday/date match (once per hour per weekday/date)(1)
When weekday/date match (once per weekday/date)(1)
When hours and minutes match (once per day)(1)
When hours match (once per day)(1)
When minutes match (once per hour)(1)
Every minute(2)
(1) AE_x
bits (where x is M, H and WD)
AE_x = 0: Alarm is enabled
AE_x = 1: Alarm is disabled
(2) If all AE_x = 1: Alarm event every minute
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4.7. EXTERNAL EVENT FUNCTION
The External Event Interrupt and Time Stamp function is enabled by the control bits EIE and ECP. Depending of
the EHL bit a high or low level signal can be regarded as an event and furthermore a digital glitch filtering is applied
to the EVI signal when selecting a sampling period in the ET field.
th
If enabled and an External Event on EVI pin is detected, the seconds and 100 seconds are captured and copied
th
̅̅̅̅̅ is issued and the EVF flag is set to 1 to indicate that
into the Seconds CP and 100 Seconds CP registers, the INT
an external event has occurred.
4.7.1.COMPLETE EXTERNAL EVENT DIAGRAM
Complete Diagram of the External Event function:
EIE
8
1
INT
4
EVF
3
EVI
2
5
CP registers
Set Time to A
All = 0
7
6
event
event
Time
9
A+1
A+2
A+1
event
A+3
All = 0
event
A+4
A+3
Write operation
1
̅̅̅̅̅ pin and to prepare the
Initialize time and set EIE bit to 1. The EVF flag need to be cleared to reset the INT
system for an event.
2
An External Event on EVI pin is detected. Pay attention to the debounce time when using the filtering.
3
When an External Event Interrupt occurs, the EVF flag is set to 1.
If the EIE bit is 1 and an External Event Interrupt occurs, the ̅̅̅̅̅
INT pin output goes low.
4
5
The EVF flag retains 1 until it is cleared to 0 by software.
6
7
No interrupt occurs because the EVF flag was not set back to 0. The CP register values do not change.
If the ̅̅̅̅̅
INT pin is low, its status changes as soon as the EVF flag is cleared to 0.
8
If the EIE bit value is 0 when an External Event occurs, the ̅̅̅̅̅
INT pin status does not go low.
9
If the EVI input is 1 (steady state) and the EIE bit is set from 0 to 1 no event is detected.
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4.7.2.USE OF THE EXTERNAL EVENT FUNCTION
The following registers and bits are related to the External Event Interrupt and Time Stamp function:







th
100 Seconds Register (10h) (see CLOCK REGISTERS)
Seconds Register (00h, 11h) (see CLOCK REGISTERS)
th
100 Seconds CP Register (20h) (see CLOCK REGISTERS)
Seconds CP Register (21h) (see CLOCK REGISTERS)
ECP bit, EHL bit, ET field and ERST bit (see CAPTURE BUFFER/EVENT CONTROL REGISTERS, 2Fh)
EVF bit (see FLAG REGISTER, 0Eh, 1Eh)
EIE bit (see CONTROL REGISTER, 0Fh, 1Fh)
Prior to entering any timer settings for the event interrupt, it is recommended to write a 0 to the EIE bit to prevent
̅̅̅̅̅ pin.
inadvertent interrupts on INT
Procedure to use the External Event Interrupt and Time Stamp function:
1.
2.
3.
4.
5.
Initialize bits EIE and EVF to 0.
th
Set the ECP bit to 1 if you want to capture the seconds and 100 seconds.
Set the EHL bit to 1 or 0 to choose high or low level detection on pin EVI
Set the ET field to apply filtering to the EVI pin. See following two diagrams.
th
th
Set the ERST bit to 1 if you want to reset the100 seconds, Seconds CP and 100 Seconds CP registers
to 0 in case of an event detection. After the event detection, the ERST bit is reset to 0.
̅̅̅̅̅ pin.
6. Set the EIE bit to 1 if you want to get a hardware interrupt on INT
No filtering: ET = 00. Example with positive edge detection:
EVI
min. 30.5 µs
INT
tDELAY
Between 0 and
30.5 µs (random)
With digital filtering: ET = 01, 10 or 11 (sampling period tSP = 3.9 ms, 15.6 ms or 125 ms). Example with positive
edge/level detection:
EVI
sampling
1
1
tSP
1
tSP
2
tSP
INT
tDELAY
tSP < tDELAY < (2 x tSP)
1
Up to this sampling pulse a positive edge was detected but no steady state.
2
If a positive edge was detected and a steady state (high level) was detected between 1 and 2 the ̅̅̅̅̅
INT
pin output goes low. The delay time tDELAY varies between tSP and (2 x tSP) depending on the bouncing signal
on the EVI pin.
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RV-8803-C7
4.8. SERVICING INTERRUPTS
The ̅̅̅̅̅
INT pin can indicate four types of interrupts. It outputs the logic OR operation result of these interrupt outputs.
When an interrupt is detected, (when the ̅̅̅̅̅
INT pin is at low level), the EVF, TF, UF and AF flags can be read to
determine which interrupt event has occurred.
To keep the ̅̅̅̅̅
INT pin from changing to low level, clear the EIE, TIE, UIE and AIE bits. To check whether an event
has occurred without outputting any interrupts via the ̅̅̅̅̅
INT pin, software can read the EVF, TF, UF and AF interrupt
flags (polling).
4.9. DIGITAL ARCHITECTURE SUMMARY
The following Figure illustrates the overall architecture of the pin inputs and outputs of the RV-8803-C7.
Digital Architecture Summary:
Power
On
V2F
Temp.
Comp.
V1F
Clkout
Controller
CLKOUT
CLKOE
Clocks
Capture
Registers
Calendar
EVI
EIE
External
Event
EVF
TIE
Periodic
Countdown
Timer
TF
UIE
Periodic
Time
Update
UF
AIE
Alarm
Interrupt
Interrupt
OR +
Mask
INT
AF
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
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4.10. SYNCHRONICITY BETWEEN INT SIGNALS AND 1 HZ CLKOUT
̅̅̅̅̅ signals from the Periodic Time Update Interrupt
The following Figure illustrates the synchronicity between the INT
function and Periodic Countdown Timer Interrupt function to the 1 Hz CLKOUT signal.
̅̅̅̅̅ signals and the 1 Hz CLKOUT:
Synchronicity between the INT
CLKOUT
1 Hz clock output
INT
Periodic Time Update Interrupt function
1
INT
Alarm Interrupt function
2
1
At the exact same time.
2
Delay between 0 and 30.52 µs (random).
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
4.11. TIME DATA READ-OUT
In order to not corrupt the accuracy of the temperature compensation and the Time Capture (Time Stamp) function
th
on the highest 100 Seconds resolution, it is not possible to freeze the clock and calendar register during read-out
process, as it is common practice for other RTC’s.
Since the time and calendar registers cannot be frozen, there might be a condition that the time registers are
incremented while read-out. To avoid reading corrupted (partially incremented) data, special measures and
procedures need to be applied.
4.11.1. PROCEDURE
If a time read-out sequence starts at the end of a minute there is a special condition that subsequent registers
might be incremented by the time update. To prevent using corrupted data from partially incremented time and
calendar registers, it is recommended to repeat and confirm time and calendar data when reading Seconds = 59
(see METHODE TO CONFIRM CORRECT TIME AND CALENDAR READ-OUT).
2
Note that the device itself has an automatic timeout function which cuts the I C interface after 950 ms (see START
AND STOP CONDITIONS).
4.11.2. METHODE TO CONFIRM CORRECT TIME AND CALENDAR READ-OUT
When reading Seconds = 59, it is recommended to repeat and compare the read-out of the Seconds register. If the
Seconds register data matches, it confirms that the time and calendar data are valid (no time increment occurred
during data read-out). If the Seconds value has changed to 00, the second set of time and calendar data is valid.
1.
2.
3.
4.
Read required time and calendar information.
If Seconds data = 59, a repeated reading is required.
If Seconds data is again 59 seconds, then the first data from the first reading is confirmed to be valid.
If the Seconds register was incremented (not 59 seconds anymore), then the time and calendar information
has been incremented and the second set of data is confirmed to be valid (the first set of data is supposed
to be partially incremented during the read-out sequence and therefore is invalid).
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
5. TEMPERATURE COMPENSATION
5.1. FREQUENCIES
Xtal 32.768 kHz
The Xtal 32.768 kHz clock is not temperature compensated. Due to its negative temperature coefficient with a
parabolic frequency deviation, a change of up to -150 ppm across the entire operating temperature range of -40°C
to 85°C can result. The oscillator frequency on all devices is tested not to exceed a time deviation of ± 20 ppm
(parts per million) at 25°C.
Frequencies from 4.096 kHz to 64 Hz
These frequencies are digitally temperature compensated with a Time Accuracy of +/- 3 ppm over the whole
temperature range (-40°C to 85°C). The clock at the 16.384 kHz level of the divider chain is modified by adding or
subtracting 32.768 kHz level pulses. The pulses are added or subtracted according to the expected frequency
deviation computed by the temperature compensation algorithm. The digital compensation method (adding and
subtracting clock pulses) is affecting the cycle-to-cycle jitter of the digitally compensated frequencies shown below.
 4.096 kHz (Periodic Countdown Timer)
 1.024 kHz (CLKOUT)
 100 Hz (External Event Interrupt)
 64 Hz (Periodic Countdown Timer Interrupt)
Aging compensation can be done with the OFFSET value (see AGING CORRECTION).
1 Hz and Clock / Calendar
The 1 Hz clock is temperature compensated and using both, digital compensation and analog fine adjustment. The
Time Accuracy and the Frequency Accuracy is +/- 3 ppm for every 1 Hz period over the whole temperature range (40°C to 85°C). The temperature compensation algorithm adjusts every 1 Hz period with a resolution of about 0.1
ppm. This precise and accurate 1 Hz clock is used to increment all subsequent clock and calendar registers.
Aging compensation can be done with the OFFSET value (see AGING CORRECTION).
5.2. FREQUENCY VS. TEMPERATURE CHARACTERISTICS
20
T0 = 25°C (± 5°C)
Δ t/t in ppm
0
-20
4096 Hz to 64 Hz
-40
1 Hz and
Clock / Calendar
-60
-80
Xtal 32.768 kHz
2
-0.035 * (T-T0) ppm (±10%)
-100
-120
-140
-160
-180
-50
-40
-30
-20
-10
0
10 20 30 40
Temperature in °C
50
60
70
80
90
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
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5.3. COMPENSATION VALUES
Each device is factory calibrated over the full temperature range, and the individual compensation values are
stored in the EEPROM of the Digital Temperature Compensation Unit (DTCU). The EEPROM is not accessible for
the user.
5.4. AGING CORRECTION
An aging adjustment or accuracy tuning can be done with the OFFSET value. The correction is purely digitally and
has only the effect of shifting the time vs. temperature curve vertically up or down. It has no effect on the time vs.
temperature characteristics of the final frequency. The OFFSET value contains a two's complement number with a
6
6
range of -2 to +2 -1 adjustment steps. The minimal correction step (one LSB) is +/-1/(32768*128) = +/-0.2384
ppm. The maximum correction range is roughly +/-7.4 ppm. Note that the signed offset value OFFSET corresponds
to the actual offset value of the measured frequency. The user has access to this field (see OFFSET REGISTER).
The OFFSET value is determined by the following process:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Set the OFFSET field to 0 to ensure correction is not occurring.
Select the 1 Hz frequency on the CLKOUT pin.
Measure the frequency Fmeas at the output pin in Hz.
Compute the offset value required in ppm: POffset = ((Fmeas – 1)*1’000’000)
Compute the offset value in steps: Offset = POffset/(1/(32768*128)) = POffset/(0.2384)
If Offset > 31, the frequency is too high to be corrected.
Else if 0 ≤ Offset ≤ 31, set OFFSET = Offset
Else if -32 ≤ Offset ≤ -1, set OFFSET = Offset + 64
Else the frequency is too low to be corrected.
Examples:
 If 1.0000012 Hz is measured when the 1 Hz clock is selected, the offset is +0.0000012 Hz, which is
-6
+0.0000012 Hz / 10 Hz = +1.2 ppm. The positive offset value is then calculated as follows: +1.2 ppm /
0.2384 ppm = +5.03, the rounded integral part is +5. In binary, OFFSET = 000101.

If 0.9999949 Hz is measured when the 1 Hz clock is selected, the offset is -0.0000051 Hz, which is
-6
-0.0000051 Hz / 10 Hz = -5.1 ppm. The negative offset value is then calculated as follows: -5.1 ppm /
0.2384 ppm = -21.39, the rounded integral part is -21. The unsigned value is then -21 +64 = +43. In binary,
OFFSET = 101011.
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RV-8803-C7
5.5. CLOCKING SCHEME
Clocking Scheme with CLKOUT and Interrupts:
32.768 kHz
Xtal
32.768 kHz
DTCU
Digital
OFFSET
4.096 kHz
1.024 kHz
Divider
&
Counter
100 Hz
Time
Accuracy
+/- 3 ppm
64 Hz
DTCU
Analog
1 Hz
CLKOUT
Periodic Countdown Timer Interrupt
CLKOUT
External Event Interrupt
Periodic Countdown Timer Interrupt
CLKOUT
External Event Interrupt
Periodic Countdown Timer Interrupt
Periodic Time Update Interrupt
Time
Accuracy
+/- 3 ppm
Minutes
Divider
&
Counter
Hours, Weekday/Date
Periodic Countdown Timer Interrupt
Periodic Time Update Interrupt
Alarm Interrupt
Alarm Interrupt
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
5.6. MEASURING TIME ACCURACY AT CLKOUT PIN
The simplest method to verify the time accuracy of the Digital Temperature Compensation Unit (DTCU) is to
measure the compensated 1 Hz frequency at the CLKOUT pin. The 1 Hz clock frequency contains digitally
temperature compensation clocks with analog fine adjustment and represents the fully time accuracy of the device.
5.6.1.MEASURING 1 HZ AT CLKOUT PIN
1. Select the 1 Hz frequency at CLKOUT:
a. Set the FD field to 10 = 1 Hz (see EXTENSION REGISTER, 0Dh, 1Dh).
b. Set the CLKOUT pin into output mode by setting the CLKOE pin to high level.
2. Measuring equipment and setup:
a. Use a high-precision universal counter to observe the 1 Hz frequency accuracy on CLKOUT pin.
b. Trigger on the rising edge of the hybrid signal (gate time ≥ 1 second). Each 1 Hz clock measured
at the rising edge fully representing the accuracy of the DTCU.
1 Hz time accuracy at CLKOUT pin (hybrid signal):
1 second
CLKOUT
1
2
500 ms
1
CLKOUT Output is active HIGH.
When measuring the time accuracy it is mandatory to trigger on the rising edge of the CLKOUT signal.
The resolution of the compensated 1 Hz period is about 0.1 ppm (minimal step).
2
The falling edge of the CLKOUT signal is generated when the RV-8803-C7 clears the signal after 500 ms.
The negative edge is created by the 32.768 kHz Xtal and must not be used to test the time accuracy.
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
5.7. MEASURING TIME ACCURACY AT INT PIN
The Periodic Time Update Interrupt function can also be used to verify the time accuracy of the Digital Temperature
̅̅̅̅̅ output pin. However this
Compensation Unit (DTCU) by measuring the compensated 1 Hz frequency at the INT
procedure is a little more sophisticated than using the method with the CLKOUT pin.
5.7.1.MEASURING 1 HZ WITH THE PERIODIC TIME UPDATE INTERRUPT FUNCTION
̅̅̅̅̅ output pin:
1. Select the Periodic Time Update Interrupt function with the frequency 1 Hz at the INT
a. Write 0 to UIE and UF bits
b. Choose USEL = 0 = 1 Hz, tRTN = 500 ms (Default value) (see EXTENSION REGISTER, 0Dh, 1Dh)
̅̅̅̅̅ pin.
c. Set UIE bit to 1 to enable the INT
d. The first interrupt will occur after the next event.
2. Measuring equipment and setup:
a. Use a high-precision universal counter to observe the frequency stability on ̅̅̅̅̅
INT output pin
b. If measuring the 1 Hz clock it suffices to measure only one period to verify the time accuracy.
Trigger on the falling edge of the hybrid signal (gate time ≥ 1 second).
1 Hz time accuracy at ̅̅̅̅̅
INT pin with the Periodic Time Update Interrupt function (hybrid signal):
1 second
INT
1
2
tRTN
500 ms
̅̅̅̅̅
INT Output is active LOW.
When measuring the time accuracy it is mandatory to trigger on the falling edge of the ̅̅̅̅̅
INT signal.
The resolution of the compensated 1 Hz period is about 0.1 ppm (minimal step).
2
The rising edge of the ̅̅̅̅̅
INT signal is generated when the RV-8803-C7 clears the signal after the auto reset
time tRTN = 500 ms. The positive edge is created by the 32.768 kHz Xtal and must not be used to test the
time accuracy.
1
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
6. I2C INTERFACE
2
The I C interface is for bidirectional, two-line communication between different ICs or modules. The RV-8803-C7 is
2
accessed at addresses 64h/65h, and supports Fast Mode (up to 400 kHz). The I C interface consists of two lines:
one bi-directional data line (SDA) and one clock line (SCL). Both lines are connected to a positive supply via pullup resistors. Data transfer is initiated only when the interface is not busy.
6.1. BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line remains stable during the HIGH
period of the clock pulse, as changes in the data line at this time are interpreted as a control signals. Data changes
should be executed during the LOW period of the clock pulse (see Figure below).
Bit transfer:
SDA
SCL
data line
stable;
data valid
change of
data
allowed
6.2. START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while
the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH transition of the data line, while the clock
is HIGH, is defined as the STOP condition (P) (see Figure below).
Definition of START and STOP conditions:
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
A START condition which occurs after a previous START but before a STOP is called a Repeated START
condition, and functions exactly like a normal STOP followed by a normal START.
Caution:
When communicating with the RV-8803-C7 module, the series of operations from transmitting the START condition
to transmitting the STOP condition should occur within 950 ms.
2
If this series of operations requires 950 ms or longer, the I C bus interface will be automatically cleared and set to
standby mode by the bus timeout function of the RV-8803-C7 module. Note with caution that both write and read
operations are invalid for communications that occur during or after this auto clearing operation (when the read
operation is invalid, all data that is read has a value of FFh).
Restarting of communications begins with transfer of the START condition again.
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
6.3. DATA VALID
After a START condition, SDA is stable for the duration of the high period of SCL. The data on SDA may be
changed during the low period of SCL. There is one clock pulse per bit of data. Each data transfer is initiated with a
START condition and terminated with a STOP condition. The number of data bytes transferred between the
START and STOP conditions is not limited (however, the transfer time must be no longer than 950 ms). The
information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
In order to not corrupt the accuracy of the temperature compensation and the Time Capture (Time Stamp) function
th
on the highest 100 Seconds resolution, it is not possible to freeze the clock and calendar register during read-out
process, as it is common practice for other RTC’s.
Since the time and calendar registers cannot be frozen, there might be a condition that the time registers are
incremented while read-out. To avoid reading corrupted (partially incremented) data, special measures and
procedures need to be applied (see TIME DATA READ-OUT).
6.4. SYSTEM CONFIGURATION
2
2
Since multiple devices can be connected with the I C bus, all I C bus devices have a fixed and unique device
number built-in to allow individual addressing of each device.
2
The device that controls the I C bus is the Master; the devices which are controlled by the Master are the Slaves. A
device generating a message is a Transmitter; a device receiving a message is the Receiver. The RV-8803-C7
acts as a Slave-Receiver or Slave-Transmitter.
2
Before any data is transmitted on the I C bus, the device which should respond is addressed first. The addressing
is always carried out with the first byte transmitted after the START procedure. The clock signal SCL is only an
input signal, but the data signal SDA is a bidirectional line.
System configuration:
SDA
SCL
MASTER
TRANSMITTER
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER
RECEIVER
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
6.5. ACKNOWLEDGE
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is
unlimited (however, the transfer time must be no longer than 950 ms). Each byte of eight bits is followed by an
acknowledge cycle.
 A slave receiver, which is addressed, must generate an acknowledge cycle after the reception of each
byte.
 Also a master receiver must generate an acknowledge cycle after the reception of each byte that has been
clocked out of the slave transmitter.
 The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and
hold times must be taken into consideration).
 A master receiver must signal an end of data to the transmitter by not generating an acknowledge cycle on
the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line
HIGH to enable the master to generate a STOP condition.
2
Data transfer and acknowledge on the I C bus:
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
6.6. SLAVE ADDRESS
2
2
On the I C bus the 7-bit slave address 0110010b is reserved for the RV-8803-C7. The entire I C bus slave address
byte is shown in the following table.
Slave address
R/ W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
1
1
0
0
1
0
Transfer data
Bit 0
1(R)
65h (read)
64h (write)
0(W)
2
After a START condition, the I C slave address has to be sent to the RV-8803-C7 device. The R/ W bit defines the
direction of the following single or multiple byte data transfer. The 7-bit address is transmitted MSB first. If this
address is 0110010b, the RV-8803-C7 is selected, the eighth bit indicates a read ( R/ W = 1) or a write ( R/ W = 0)
operation (results in 65h or 64h) and the RV-8803-C7 supplies the ACK. The RV-8803-C7 ignores all other address
values and does not respond with an ACK.
In the write operation, a data transfer is terminated by sending either the STOP condition or the START condition of
the next data transfer.
6.7. WRITE OPERATION
Master transmits to Slave-Receiver at specified address. The Register Address is an 8-bit value that defines which
register is to be accessed next. After writing one byte, the Register Address is automatically incremented by 1.
Master writes to slave RV-8803-C7 at specific address:
1)
2)
3)
4)
5)
6)
7)
8)
Master sends out the START condition.
Master sends out Slave Address, 64h for the RV-8803-C7; the R/ W bit is a 0 indicating a write operation.
Acknowledgement from RV-8803-C7.
Master sends out the Register Address to RV-8803-C7.
Acknowledgement from RV-8803-C7.
Master sends out the Data to write to the specified address in step 4).
Acknowledgement from RV-8803-C7.
Steps 6) and 7) can be repeated if necessary.
The address is automatically incremented in the RV-8803-C7.
9) Master sends out the STOP Condition.
2
S
SLAVE ADDRESS
3
0 A
R/W
1
4
5
6
7
8
REGISTER ADDRESS
A
DATA
A
DATA
9
A
P
Acknowledge from RV-8803-C7
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
6.8. READ OPERATION AT SPECIFIC ADDRESS
Master reads data from slave RV-8803-C7 at specific address:
1)
2)
3)
4)
5)
6)
7)
8)
Master sends out the START condition.
Master sends out Slave Address, 64h for the RV-8803-C7; the R/ W bit is a 0 indicating a write operation.
Acknowledgement from RV-8803-C7.
Master sends out the Register Address to RV-8803-C7.
Acknowledgement from RV-8803-C7.
Master sends out the Repeated START condition (or STOP condition followed by START condition)
Master sends out Slave Address, 65h for the RV-8803-C7; the R/ W bit is a 1 indicating a read operation.
Acknowledgement from RV-8803-C7.
At this point, the Master becomes a Receiver and the Slave becomes the Transmitter.
9) The Slave sends out the Data from the Register Address specified in step 4).
10) Acknowledgement from Master.
11) Steps 9) and 10) can be repeated if necessary.
The address is automatically incremented in the RV-8803-C7.
12) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on the
last byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the
data line HIGH to enable the Master to generate a STOP condition.
13) Master sends out the STOP condition.
SLAVE ADDRESS
3
0 A
4
5
6
7
REGISTER ADDRESS
A
S
SLAVE ADDRESS
Repeated
START
Acknowledge from RV-8803-C7
8
1 A
9
10
11
DATA
A
DATA
12 13
A
P
R/W
S
2
R/W
1
Acknowledge from Master
No acknowledge from Master
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
6.9. READ OPERATION
Master reads data from slave RV-8803-C7 immediately after first byte:
1) Master sends out the START condition.
2) Master sends out Slave Address, 65h for the RV-8803-C7; the R/ W bit is a 1 indicating a read operation.
3) Acknowledgement from RV-8803-C7.
At this point, the Master becomes a Receiver and the Slave becomes the Transmitter.
4) The RV-8803-C7 sends out the Data from the last accessed Register Address incremented by 1.
5) Acknowledgement from Master.
6) Steps 4) and 5) can be repeated if necessary.
The address is automatically incremented in the RV-8803-C7.
7) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on the
last byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the
data line HIGH to enable the Master to generate a STOP condition.
8) Master sends out the STOP condition.
2
3
S
SLAVE ADDRESS
1 A
4
5
DATA
A
6
DATA
7
8
A
P
R/W
1
Acknowledge from RV-8803-C7
Acknowledge from Master
No acknowledge from Master
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7. ELECTRICAL SPECIFICATIONS
7.1. ABSOLUTE MAXIMUM RATINGS
The following Table lists the absolute maximum ratings.
Absolute Maximum Ratings according to IEC 60134:
SYMBOL
PARAMETER
VDD
VI
VO
II
IO
Power Supply Voltage
Input voltage
Output voltage
Input current
Output current
VESD
ESD Voltage
ILU
TOPR
TSTO
TPEAK
Latch-up Current
Operating Temperature
Storage Temperature
Maximum reflow condition
CONDITIONS
Input Pin
Output Pin
MIN
-0.3
-0.3
-0.3
-10
-10
HBM(1)
MM(2)
Jedec(3)
-40
-55
JEDEC J-STD-020C
TYP
MAX
UNIT
6.0
VDD +0.3
VDD +0.3
10
10
±2000
±200
+/-100
85
125
265
V
V
V
mA
mA
V
V
mA
°C
°C
°C
(1) HBM:
Human Body Model, according to JESD22-A114.
(2) MM: Machine Model, according to JESD22-A115.
(3) Latch-up testing, according to JESD78., Class I (room temperature), level A (100 mA)
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7.2. OPERATING PARAMETERS
For this Table, TA = -40 °C to +85 °C unless otherwise indicated. VDD = 1.5 to 5.5 V, fOSC= 32.768 kHz, TYP values
at 25 °C and 3.0 V.
Operating Parameters:
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
5.5
5.5
5.5
V
Supplies
VDD
VLOW1
VLOW2
Power Supply Voltage
VDD low and POR(2) detection.
Temperature compensation
stops (flag V1F).
VDD low and POR(2) detection.
Data no longer valid (flag V2F).
IVDD
VDD supply current timekeeping.
I2C bus inactive, CLKOUT
disabled, average current
IVDD:I2C
VDD supply current during
I2C burst read/write, CLKOUT
disabled
IVDD:TSP
IVDD:CK32
IVDD:CK1024
IVDD:CK1
Time-keeping mode(1)
I2C bus (100 kHz)
I2C bus (400 kHz)
VDD supply current temperature
sensing peak
Additional VDD supply current
with CLKOUT at 32.768 kHz,
average current
Additional VDD supply current
with CLKOUT at 1.024 kHz,
average current
Additional VDD supply current
with CLKOUT at 1 Hz (duty
cycle = 500 ms), average
current
Inputs
VIL
VIH
IILEAK
LOW level input voltage
HIGH level input voltage
Input leakage current
CI
Input capacitance
1.5
1.5
2.0
1.1
1.2
1.3
V
1.1
1.2
1.3
V
VDD = 1.5
VDD = 3.0 V(3)
VDD = 5.0 V(3)
VDD = 1.5 V, SCL = 100 kHz(4)
VDD = 3.0 V, SCL = 400 kHz(4)
VDD = 5.0 V, SCL = 400 kHz(4)
240
240
250
2
5
7
600
600
1200
15
40
60
Typical duration = 1.3 ms
19
µA
VDD = 3.0 V(5)
3.25
μA
VDD = 3.0 V(5)
250
nA
VDD = 3.0 V(5)
150
nA
V(3)
VDD = 1.5 V to 5.5 V
Pins: SCL, SDA CLKOE, EVI
VSS ≤ VI ≤ VDD
VDD = 3.0 V, TA = 25°C,
f = 1MHz
0.2 VDD
0.8 VDD
-0.5
nA
µA
0.5
V
V
µA
7
pF
Outputs
VDD = 1.5 V, IOH = 0.1 mA
1.2
VDD = 3.0 V, IOH = 1.0 mA
2.5
V
VDD = 5.0 V, IOH = 1.0 mA
4.5
VDD = 1.5 V, IOL = -0.1 mA
0.2
LOW level output voltage
VOL:CLK
VDD = 3.0 V, IOL = -1.0 mA
0.5
V
CLKOUT
VDD = 5.0 V, IOL = -1.0 mA
0.5
VDD = 1.5 V, IOL = -2.0 mA
0.4
LOW level output voltage
VOL
V
=
3.0
V,
I
=
-3.0
mA
0.4
V
DD
OL
̅̅̅̅̅
Pins: SDA, INT
VDD = 5.0 V, IOL = -3.0 mA
0.3
IOLEAK
Output leakage current
VO = VDD or VSS
-0.5
0.5
µA
VDD = 3.0 V, TA = 25°C,
COUT
Output capacitance
7
pF
f = 1MHz
(1) Clocks operating and RAM and registers retained. Including temperature sensing and compensation.
(2) CLKOUT is hold LOW during the first POR delay t
POR1 and goes HIGH during the second POR delay t POR2.
(3) All inputs and outputs are at 0 V or V .
DD
(4) 2.2k pull-up resistors on SCL/SDA, excluding external peripherals and pull-up resistor current. All other inputs (besides SDA and SCL) are
at 0 V or VDD. Test conditions: Continuous burst read/write, 55h data pattern, 25 μs between each data byte, 20 pF load on each bus pin.
(5) All inputs and outputs except CLKOUT are at 0 V or V . 10 MΩ, 15 pF load on CLKOUT.
DD
VOH:CLK
HIGH level output voltage
CLKOUT
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DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
7.2.1.TEMPERATURE COMPENSATION AND CURRENT CONSUMPTION
Typical IVDD average current:
I VDD
Sensing ON
IVDD:TSP
IVDD_Average
IVDD_Sensing OFF
time
0
Sensing OFF
Compensation interval (1 second)
IVDD_Average = ((IVDD:TSP * 1.3 ms) + (IVDD_Sensing OFF * (1 s – 1.3 ms)) / 1 s
IVDD_Average = ((19 µA * 1.3 ms) + (220 nA * 998.7 ms )) / 1 s = 244 nA
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7.3. OSCILLATOR PARAMETERS
For this Table, TA = -40 °C to +85 °C unless otherwise indicated. VDD = 1.5 to 5.5 V, fOSC= 32.768 kHz, TYP values
at 25 °C and 3.0 V.
Oscillator Parameters:
SYMBOL
PARAMETER
Xtal General
F
CONDITIONS
Crystal Frequency
Oscillator start-up time
tSTART = tPOR1 + tPOR2
tSTART
δCLKOUT
CLKOE = VDD
MAX
UNIT
TA = 25°C, calibration disabled
TOPR = -40°C to +85°C
VDD = 3.0 V
kHz
80
FCLKOUT = 32.768 kHz
TA = 25°C
Xtal Frequency Characteristics
ΔF/F
Frequency accuracy
Frequency vs. temperature
ΔF/FTOPR
characteristics
T0
Turnover temperature
ΔF/F
Aging first year max.
Digital Temperature Compensated Xtal DTCXO
500
ms
50 ±10
%
±10
ppm
-0.035
/°C2
±20
ppm
(TOPR-T0) ±10%
ppm
2
+25 ±5
TA = 25°C, VDD = 3.0 V
±1.5
±0.13
±3
±0.26
TA = -40°C to +85°C
1 Hz OFFSET value
Min. corr. step (LSB) and
Max. corr. range
TA = -40°C to +85°C
°C
ppm
±3
TA = 0°C to +50°C
Time accuracy calibrated,
CLKOUT measured on rising
edge of One 1 Hz period
ΔF/F
TYP
32.768
CLKOUT duty cycle
Δf/f
MIN
±0.2384
ppm
s/day
ppm
s/day
±7.4
ppm
7.3.1.TIME ACCURACY 1 HZ EXAMPLE
Time accuracy of the temperature compensated 1 Hz signal:
Time Accuracy 1 Hz
4
3
∆t/t in ppm
2
1
0
-1
-2
-3
-4
-40
-25
0
25
Temperature in °C
50
75
85
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7.4. POWER ON AC ELECTRICAL CHARACTERISTICS
The following Figure and table describe the power on AC electrical characteristics for the CLKOUT pin.
Power On AC Electrical Characteristics:
VDD
0.6 V
VDDR1
0V
CLKOUT
t POR2
t POR1
State
Operating
POR
For this Table, TA = -40 °C to +85 °C and VDD = 1.5 to 5.5 V, TYP values at 25 °C and 3.0 V.
Power On AC Electrical Parameters:
SYMBOL
VDDR1
tPOR1
tPOR2
PARAMETER
VDD rising slew rate at initial
power on reset (POR)
First POR delay
Second POR delay
CONDITIONS
MIN
TYP
0.1
CLKOE = VDD
3
80
MAX
UNIT
1
V/ms
10
500
ms
ms
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7.5. BACKUP AND RECOVERY
During a backup event with a backup voltage VDD higher than VLOW1 (VLOW2) the CLKOUT function is operating
including the Temperature compensation and the RAM and registers are retained. Pay attention to the CLKOUT
function if the power supply voltage VDD of the RV-8803-C7 sharply goes up and down, meaning VDD is changing
between Main power voltage and Backup capacitor voltage. The CLKOUT signal can then disappear for several
milliseconds when the voltage change is to sharp.
1. Choose a valid VDD range for the CLKOUT function. E.g. 1.6 V to 3.6 V (see OPERATING PARAMETERS).
2. Ensure that the slew rates VDDF and VDDR2 fulfill their specifications.
3. Check if these required specifications are fulfilled on your system.
The following Figure and Table describe the backup and recovery AC electrical characteristics (valid example with
a backup voltage > VLOW1 (VLOW2)).
VDD Backup and recovery AC Electrical Characteristics:
VDD
V DDF
VDDR2
≈
VDD
VLOW1 (V LOW2)
0V
Backup Capacitor
For the following Table, TA = -40 °C to 85 °C.
VDD Backup and recovery AC Electrical Parameters:
SYMBOL
VDDF
VDDR2
PARAMETER
CONDITIONS
VDD falling slew rate
VDD rising slew rate
Rising from VDD = 1.5 V
to VDD ≤ 3.5 V
Rising from VDD = 1.5 V
to VDD > 3.5 V
MIN
TYP
MAX
UNIT
0.5
V/µs
0.2
V/µs
0.07
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
7.6. I2C AC ELECTRICAL CHARACTERISTICS
2
The following Figure and Table describe the I C AC electrical parameters.
2
I C AC Parameter Definitions:
SDA
t BUF
t LOW
t HD:DAT
t SU:DAT
SCL
t HD:STA
t HIGH
t RISE
P
t FALL
S
t SU:STO
t SU:STA
SDA
Sr
P
For the following Table, TA = -40 °C to 85 °C, TYP values at 25 °C.
2
I C AC Electrical Parameters:
SYMBOL
PARAMETER
Conditions
MIN
VDD ≥ 1.5 V
fSCL
SCL input clock frequency
VDD ≥ 2.0 V
VDD ≥ 1.5 V
tLOW
Low period of SCL clock
VDD ≥ 2.0 V
VDD ≥ 1.5 V
tHIGH
High period of SCL clock
VDD ≥ 2.0 V
VDD ≥ 1.5 V
tRISE
Rise time of SDA and SCL
VDD ≥ 2.0 V
VDD ≥ 1.5 V
tFALL
Fall time of SDA and SCL
VDD ≥ 2.0 V
VDD ≥ 1.5 V
tHD:STA
START condition hold time
VDD ≥ 2.0 V
VDD ≥ 1.5 V
tSU:STA
START condition setup time
VDD ≥ 2.0 V
VDD ≥ 1.5 V
tSU:DAT
SDA setup time
VDD ≥ 2.0 V
VDD ≥ 1.5 V
tHD:DAT
SDA hold time
VDD ≥ 2.0 V
VDD ≥ 1.5 V
tSU:STO
STOP condition setup time
VDD ≥ 2.0 V
VDD ≥ 1.5 V
tBUF
Bus free time before a new transmission
VDD ≥ 2.0 V
S = Start condition, Sr = Repeated Start condition, P = Stop condition
0
0
4.7
1.3
4.0
0.6
TYP
MAX
UNIT
100
400
kHz
µs
µs
1000
300
300
300
4.0
0.6
4.7
0.6
250
100
0
0
4.0
0.6
4.7
1.3
ns
ns
µs
µs
ns
µs
µs
µs
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
Bus-Timeout reset:
When accessing the RV-8803-C7, all communication from transmitting the Start condition to transmitting the Stop
condition after access should be completed within 950 ms.
2
If such communication requires 950 ms or longer, the I C bus interface is reset by the internal bus timeout function.
Special attention:
2
2
Due to the automatic initialization of the I C timeout function at I C START it is possible that the RV-8803-C7
triggers an erroneous Bus-Timeout Reset and consequently responds with “no acknowledge” for the duration of
2
maximum 61 μs. This unwanted Bus-Timeout Reset of the I C Interface occurs when a START condition is sent
950 ms + n * 1000 ms (n = 0, 1, 2, …) after a previous START condition.
2
To avoid wrong communication results check the Acknowledge. If “no acknowledge” is received, repeat the I C-bus
communication. Maximum 4 read addressing are needed. For detailed technical advice see Errata_Sheet_RV8803-C7.
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
8. APPLICATION INFORMATION
8.1. OPERATING RV-8803-C7 WITH BACKUP CAPACITOR
10nF
2
1
3
Backup
Capacitor
4
VDD
RV-8803-C7
VDD
EVI
INT
INT
SDA
SDA
SCL
SCL
CLKOE
VDD
MCU
GPIO
VSS
VSS
1
2
3
4
5
CLKOUT
5
Low-cost MLCC (*) ceramic capacitor or supercapacitor.
Schottky Diode.
A 10 nF decoupling capacitor is recommended close to the device.
̅̅̅̅̅ output are open drain and require pull-up resistors to VDD.
Interface lines SCL, SDA and the INT
CLKOUT offers the selectable frequencies 32.768 kHz, 1.024 kHz and 1 Hz for application use. If not used,
it is recommended to disable CLKOUT for optimized current consumption (tie CLKOE to Ground).
(*) Note, that low-cost MLCCs are normally used for short time keeping (minutes) and the more
expensive supercapacitors for a longer backup time (day).
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
9. RECOMMENDED REFLOW TEMPERATURE (LEADFREE SOLDERING)
Maximum Reflow Conditions in accordance with IPC/JEDEC J-STD-020C “Pb-free”
tP
TP
Critical Zone
TL to TP
Temperature
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Temperature Profile
Average ramp-up rate
Ramp down Rate
Time 25°C to Peak Temperature
Preheat
Temperature min
Temperature max
Time Tsmin to Tsmax
Soldering above liquidus
Temperature liquidus
Time above liquidus
Peak temperature
Peak Temperature
Time within 5°C of peak temperature
Time
Symbol
(Tsmax to TP)
Tcool
Tto-peak
Condition
3°C / second max
6°C / second max
8 minutes max
Unit
°C / s
°C / s
min
Tsmin
Tsmax
ts
150
200
60 – 180
°C
°C
sec
TL
tL
217
60 – 150
°C
sec
Tp
tp
260
20 – 40
°C
sec
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
10. PACKAGE
10.1. DIMENSIONS AND SOLDER PAD LAYOUT
C7 Package:
Package dimensions (bottom view):
Recommended solder pad layout:
3,2
0,9
0,9
0,5
4
8
7
6
5
0,4
0,8
2,0
3
0,5
2
1,5
1
0,8
0,9
0,9
3,2
0,1
max.0,80
0,4
All dimensions in mm typical.
10.2. MARKING AND PIN #1 INDEX
C7 Package: (top view)
Production Date Code
#8
#5
M 303 A 1
8803
#1
Pin 1 Index
#4
Part Designation
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
11. PACKING INFORMATION
11.1. CARRIER TAPE
12 mm Carrier-Tape:
Material:
Polystyrene / Butadine or Polystyrol black, conductive
Cover Tape:
Base Material:
Adhesive Material:
Peel Method:
Polyester, conductive 0.061 mm
Pressure-sensitive Synthetic Polymer
Middle part removed, sticky sides remain on carrier
Ø1
±0,1
±0,02
1,75
5,5 ±0,05
,5
±0
,1
Ø1
,5
2 ±0,1
0,3
±0,2
3,45
±0,1
4 ±0,1
±0
,1
C7 Package:
12
8803
8803
4 ±0,1
1,75
±0,1
0.9
±0,1
User Direction of Feed
Tape Leader and Trailer: 300 mm minimum.
All dimensions in mm.
11.2. PARTS PER REEL
C7 Package:
Reels:
Diameter
7”
7”
Material
Plastic, Polystyrol
Plastic, Polystyrol
RTC’s per reel
1’000
5’000
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
11.3. REEL 7 INCH FOR 12 mm TAPE
ø 10
60
60
°
°
1,8
ø 178
ø 61,5
min.12,4
max.17
Reel:
Diameter
7”
Material
Plastic, Polystyrol
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
11.4. HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED CRYSTALS
The built-in tuning-fork crystal consists of pure Silicon Dioxide in crystalline form. The cavity inside the package is
evacuated and hermetically sealed in order for the crystal blank to function undisturbed from air molecules,
humidity and other influences.
Shock and vibration:
Keep the crystal / module from being exposed to excessive mechanical shock and vibration. Micro Crystal
guarantees that the crystal / module will bear a mechanical shock of 5000g / 0.3 ms.
The following special situations may generate either shock or vibration:
Multiple PCB panels - Usually at the end of the pick & place process the single PCBs are cut out with a router.
These machines sometimes generate vibrations on the PCB that have a fundamental or harmonic frequency
close to 32.768 kHz. This might cause breakage of crystal blanks due to resonance. Router speed should be
adjusted to avoid resonant vibration.
Ultrasonic cleaning - Avoid cleaning processes using ultrasonic energy. These processes can damages
crystals due to mechanical resonance of the crystal blank.
Overheating, rework high temperature exposure:
Avoid overheating the package. The package is sealed with a seal ring consisting of 80% Gold and 20% Tin. The
eutectic melting temperature of this alloy is at 280°C. Heating the seal ring up to >280°C will cause melting of the
metal seal which then, due to the vacuum, is sucked into the cavity forming an air duct. This happens when using
hot-air-gun set at temperatures >300°C.
Use the following methods for rework:


Use a hot-air- gun set at 270°C.
Use 2 temperature controlled soldering irons, set at 270°C, with special-tips to contact all solder-joints from
both sides of the package at the same time, remove part with tweezers when pad solder is liquid.
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Micro Crystal
DTCXO Temperature Compensated Real Time Clock / Calendar Module
RV-8803-C7
12. DOCUMENT REVISION HISTORY
Date
Revision #
Revision Details
January 2015
1.0
April 2016
1.1
May 2016
1.2
First release
Added term Time Stamp. 1. pp
Added pin numbers in device protection diagram, 2.4
Added additional specification for Timer Counter 0 and 1 registers, 3.5
Corrected tRTN from 7.183 ms to 7.813 ms (Periodic Countdown Timer), 3.6
Added additional specification for flags V1F and V2F, 3.7
Corrected drawing ‘Start timing of the Periodic Countdown Timer’, 4.4.2
Corrected drawing ‘Digital Architecture Summary’, 4.9
Updated text in TIME DATA READ-OUT/PROCDURE, 4.11.1
Corrected formula to POffset = ((Fmeas – 1)*1’000’000), 5.4
̅̅̅̅̅ PIN, 5.7
Updated text in MEASURING TIME ACCURACY AT INT
Added VDDR1 maximum value, 7.4
Added detailed explanation about I2C timeout function, 7.6
Updated detailed explanation about I2C timeout function, 7.6
Information furnished is believed to be accurate and reliable. However, Micro Crystal assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other
rights of third parties which may result from its use. In accordance with our policy of continuous
development and improvement, Micro Crystal reserves the right to modify specifications mentioned in this
publication without prior notice. This product is not authorized for use as critical component in life support
devices or systems.
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