DATASHEET ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs Description Key Specifications ATI RD/RS600 series systems using AMD CPUs • • • • Output Features • • • • • • • • Integrated Series Resistors on differential outputs Greyhound Compatible CPU outputs 2 - 0.7V Low Power differential CPU pairs 6 - 0.7V Low Power differential SRC pairs 2 - 0.7V Low Power differential ATIG pairs 1 - 66 MHz HyperTransport clock 2 - 48MHz USB clocks 3 - 14.318MHz Reference clocks 9LPRS464 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Features/Benefits: • 3 - Programmable Clock Request pins for SRC and ATIG clocks ATIGCLKs are programmable for frequency Spread Spectrum for EMI reduction Outputs may be disabled via SMBus External crystal load capacitors for maximum frequency accuracy • • • • Power Groups Pin Configuration GNDREF VDDREF X1 X2 VDD48 48MHz_0 48MHz_1 GND48 SMBCLK SMBDAT RESET_IN# SRC5T_LPR SRC5C_LPR VDDSRC GNDSRC SRC4T_LPR SRC4C_LPR SRC3T_LPR SRC3C_LPR SRC2T_LPR SRC2C_LPR GNDSRC VDDSRC SRC1T_LPR SRC1C_LPR VDDSRC GNDSRC *CLKREQB# CPU outputs cycle-to-cycle jitter <150ps SRC outputs cycle-to-cycle jitter < 125ps ATIG outputs cycle-to-cycle jitter < 125ps +/- 100ppm frequency accuracy on all outputs if REF is tuned to +/-100ppm 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FS0/REF0 FS1/REF1 FS2/REF2 **PD VDDHTT HTTCLK0 GNDHTT *CLKREQA# CPUKG0T_LPR CPUKG0C_LPR VDDCPU GNDCPU CPUKG1T_LPR CPUKG1C_LPR VDDA GNDA NC SRC0T_LPR SRC0C_LPR GNDSRC VDDSRC ATIG0T_LPR ATIG0C_LPR VDDATIG GNDATIG ATIG1T_LPR ATIG1C_LPR *CLKREQC# Pin Number VDD 5 Description GND 8 14,23,26,36 15,22,27,37 USB_48 outputs SRCCLK outputs 33 32 42 41 ATIGCLK differential outputs Analog, PLL 46 45 CPUCLK8 differential outputs 52 50 HTTCLK output 2 1 REF outputs Funtionality HTT MHz Hi-Z SRC MHz 100.00 ATIG MHz 100.00 USB MHz 48.00 X/2 X/3 100.00 100.00 48.00 230.00 76.67 100.00 100.00 48.00 240.00 80.00 100.00 100.00 48.00 0 100.00 66.66 100.00 100.00 48.00 0 1 133.33 66.66 100.00 100.00 48.00 1 1 0 166.67 66.66 100.00 100.00 48.00 1 1 1 200.00 66.66 100.00 100.00 48.00 FS2 FS1 FS0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 CPU MHz Hi-Z 56-Pin SSOP/TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 1 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss Pin Description PIN # PIN NAME TYPE DESCRIPTION GND PWR IN OUT PWR OUT OUT GND IN I/O Ground pin for the REF outputs. Ref, XTAL power supply, nominal 3.3V Crystal input, nominally 14.318MHz Crystal output, nominally 14.318MHz Power pin for the 48MHz outputs and core. 3.3V 48MHz clock output. 48MHz clock output. Ground pin for the 48MHz outputs Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Real Time falling edge triggered input, When asserted, the part initiates a power up reset with the SMBus being reset to it's power up values, and all PLL derived clocks stopped for the duration of Power up Stabilization. REF outputs continue to run. True clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Complement clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Supply for SRC, 3.3V nominal Ground pin for the SRC outputs True clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Complement clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) True clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Complement clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) True clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Complement clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Ground pin for the SRC outputs Supply for SRC, 3.3V nominal True clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Complement clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Supply for SRC, 3.3V nominal Ground pin for the SRC outputs Programmable Clock Request pin for SRC/ATIG/SB_SRC outputs. If output is selected for control, then that output is controlled as follows: 0 = Enabled, 1 = Tri-state 1 2 3 4 5 6 7 8 9 10 GNDREF VDDREF X1 X2 VDD48 48MHz_0 48MHz_1 GND48 SMBCLK SMBDAT 11 RESET_IN# IN 12 SRC5T_LPR OUT 13 SRC5C_LPR OUT 14 15 VDDSRC GNDSRC PWR GND 16 SRC4T_LPR OUT 17 SRC4C_LPR OUT 18 SRC3T_LPR OUT 19 SRC3C_LPR OUT 20 SRC2T_LPR OUT 21 SRC2C_LPR OUT 22 23 GNDSRC VDDSRC GND PWR 24 SRC1T_LPR OUT 25 SRC1C_LPR OUT 26 27 VDDSRC GNDSRC PWR GND 28 *CLKREQB# IN IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 2 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss Pin Description (Continued) PIN # PIN NAME TYPE DESCRIPTION 29 *CLKREQC# IN Programmable Clock Request pin for SRC/ATIG/SB_SRC outputs. If output is selected for control, then that output is controlled as follows: 0 = Enabled, 1 = Tri-state 30 ATIG1C_LPR OUT Complementary clock of low-power differential push-pull PCI-Express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) 31 ATIG1T_LPR OUT 32 33 GNDATIG VDDATIG GND PWR 34 ATIG0C_LPR OUT 35 ATIG0T_LPR OUT 36 37 VDDSRC GNDSRC PWR GND 38 SRC0C_LPR OUT 39 SRC0T_LPR OUT 40 41 42 NC GNDA VDDA NC GND PWR 43 CPUKG1C_LPR OUT 44 CPUKG1T_LPR OUT 45 46 GNDCPU VDDCPU GND PWR 47 CPUKG0C_LPR OUT 48 CPUKG0T_LPR OUT 49 *CLKREQA# 50 51 52 GNDHTT HTTCLK0 VDDHTT 53 **PD IN 54 55 56 FS2/REF2 FS1/REF1 FS0/REF0 I/O I/O I/O IN PWR OUT PWR True clock of low-power differential push-pull PCI-Express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Ground pin for the ATIG outputs Power supply for ATIG core, nominal 3.3V Complementary clock of low-power differential push-pull PCI-Express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) True clock of low-power differential push-pull PCI-Express pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Supply for SRC, 3.3V nominal Ground pin for the SRC outputs Complement clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) True clock of low power differential SRC clock pair with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) No Connect Ground for the Analog Core 3.3V Power for the Analog Core Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Ground pin for the CPU outputs Supply for CPU, 3.3V nominal Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed) Programmable Clock Request pin for SRC/ATIG/SB_SRC outputs. If output is selected for control, then that output is controlled as follows: 0 = Enabled, 1 = Tri-state Ground pin for the HTT outputs 3.3V single ended 66MHz hyper transport clock Supply for HTT clocks, nominal 3.3V. Enter /Exit Power Down. 1 = Power Down, 0 = normal operation. Frequency select latch input pin/ 3.3V 14.318MHz reference clock Frequency select latch input pin/ 3.3V 14.318MHz reference clock Frequency select latch input pin/ 3.3V 14.318MHz reference clock IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 3 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss General Description The ICS9LPRS464 is a main clock synthesizer chip that provides all clocks required for ATI RD/RS600-based systems. An SMBus interface allows full control of the device. Funtional Block Diagram REF(2:0) X1 X2 XTAL OSC. 48MHz(1:0) FIXED PLL HTT DIV HTTCLK0 CPU DIV CPUCLK(1:0) SRC DIV SRCCLK(5:0) ATIG DIV ATIGCLK(1:0) FS(2:0) PD CLKREQA# CLKREQB# CLKREQC# CONTROL LOGIC PLL RESET_IN# SMBDAT SMBCLK IREF IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 4 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss Absolute Max PARAMETER SYMBOL CONDITIONS 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature VDD_A - VDD_In - Ts - GND 0.5 -65 Ambient Operating Temp Tambient - 0 Case Temperature Tcase - Input ESD protection HBM ESD prot - 1Guaranteed MIN TYP MAX UNITS Notes VDD + 0.5V V 1 VDD + 0.5V V 1 150 °C 1 70 °C 1 115 °C 1 V 1 2000 by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN MAX UNITS Notes Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1 Input High Current IIH VIN = VDD -5 5 uA 1 -5 uA 1 -200 uA 1 IIL1 Input Low Current IIL2 VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors TYP Low Threshold InputHigh Voltage Low Threshold InputLow Voltage VIH_FS 3.3 V +/-5% 0.7 VDD + 0.3 V 1 VIL_FS 3.3 V +/-5% VSS - 0.3 0.35 V 1 Operating Current IDD3.3OP 9LPRS462, all outputs driven 200 mA 1 9LPRS464, all outputs driven 180 mA 1 Powerdown Current IDD3.3PD all diff pairs low/low 21 mA 1 Input Frequency Fi VDD = 3.3 V Pin Inductance Lpin CIN Logic Inputs 5 pF 1 Input Capacitance COUT Output pin capacitance 6 pF 1 CINX 5 pF 1 1.8 ms 1 33 kHz 1 300 us 1 Tfall_PD X1 & X2 pins From VDD Power-Up or deassertion of PD to 1st clock Triangular Modulation CPU output enable after PD de-assertion PD fall time of Trise_PD PD rise time of Clk Stabilization TSTAB Modulation Frequency Tdrive_PD SMBus Voltage 14.31818 7 30 2.7 VDD Low-level Output Voltage VOL @ IPULLUP Current sinking at IPULLUP VOL = 0.4 V (Max VIL - 0.15) to SMBCLK/SMBDAT TRI2C (Min VIH + 0.15) Clock/Data Rise Time (Min VIH + 0.15) to SMBCLK/SMBDAT TFI2C (Max VIL - 0.15) Clock/Data Fall Time *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% MHz 2 nH 1 5 ns 1 5 ns 1 5.5 V 1 0.4 V 1 mA 1 1000 ns 1 300 ns 1 4 1 Guaranteed by design and characterization, not 100% tested in production. Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2 IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 5 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT PARAMETER SYMBOL CONDITIONS Crossing Point Variation ∆VCROSS Single-ended Measurement MIN Frequency f Spread Specturm On Long Term Accuracy ppm Rising Edge Slew Rate TYP MAX UNITS NOTES 140 mV 1,2,5 198.8 200 MHz 1,3 Spread Specturm Off -300 +300 ppm 1,11 SRISE Differential Measurement 0.5 10 V/ns 1,4 Falling Edge Slew Rate SFALL Differential Measurement 0.5 10 V/ns 1,4 Slew Rate Variation CPU, DIF HTT Jitter - Cycle to Cycle Accumulated Jitter tSLVAR Single-ended Measurement 20 % 1 CPUJC2C Differential Measurement 150 ps 1,6 tJACC See Notes 1 ns 1,7 Peak to Peak Differential Voltage VD(PK-PK) Differential Measurement 400 2400 mV 1,8 Differential Voltage VD Differential Measurement 200 1200 mV 1,9 Duty Cycle DCYC Differential Measurement 45 55 % 1 Amplitude Variation ∆VD Change in VD DC cycle to cycle -75 75 mV 1,10 CPU Skew CPUSKEW10 Differential Measurement 100 ps 1 Guaranteed by design and characterization, not 100% tested in production. Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is not important due to the blocking cap. Minimum Frequency is a result of 0.5% down spread spectrum Differential measurement through the range of ±100 mV, differential signal must remain monotonic and within slew rate spec when crossing through this region. 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. 6 Max difference of tCYCLE between any two adjacent cycles. 7 Accumulated tjc.over a 10 µs time period, measured with JIT2 TIE at 50ps interval. 8 VD(PK-PK) is the overall magnitude of the differential signal. 9 VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0V VD. VD(max) is the largest amplitude allowed. 10 The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of the signal. 11 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 6 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss AC Electrical Characteristics - Low-Power DIF Outputs: SRC and ATIG PARAMETER SYMBOL CONDITIONS MIN Rising Edge Slew Rate tSLR Differential Measurement Falling Edge Slew Rate tFLR Differential Measurement Slew Rate Variation tSLVAR Single-ended Measurement Maximum Output Voltage VHIGH Includes overshoot Minimum Output Voltage VLOW Includes undershoot -300 Differential Voltage Swing VSWING Differential Measurement 300 Crossing Point Voltage VXABS Single-ended Measurement 300 Crossing Point Variation VXABSVAR Single-ended Measurement Duty Cycle SRC, ATIG, Jitter - Cycle to Cycle SRC[5:0] Skew DCYC Differential Measurement SRCJ C2C SB_SRC[1:0] Skew ATIG[3:0] Skew TYP MAX UNITS NOTES 0.5 2 V/ns 1,2 0.5 2 V/ns 1,2 20 % 1 1150 mV 1 mV 1 mV 1 550 mV 1,3,4 140 mV 1,3,5 55 % 1 Differential Measurement 125 ps 1 SRCSKEW Differential Measurement 250 ps 1 SRCSKEW Differential Measurement 100 ps 1 SRCSKEW Differential Measurement 100 ps 1 45 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of 5 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz Electrical Characteristics - USB - 48MHz PARAMETER SYMBOL CONDITIONS* MIN MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -100 100 ppm 1,2 Clock period Tperiod 48.00MHz output nominal 20.8229 20.8344 ns 2 Clock Low Time Tlow Measure from < 0.6V 9.3750 11.4580 ns 2 11.4580 ns 2 V 1 V 1 Clock High Time Thigh Measure from > 2.0V 9.3750 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL TYP IOL = 1 mA 0.55 V OH @MIN = 1.0 V -33 mA 1 mA 1 mA 1 Output High Current IOH Output Low Current IOL 38 mA 1 Rise Time tr_USB VOL = 0.4 V, VOH = 2.4 V 0.5 1.5 ns 1 Fall Time tf_USB VOH = 2.4 V, VOL = 0.4 V 0.5 1.5 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Group Skew tskew VT = 1.5 V 250 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 130 ps 1,2 VOH@MAX = 3.135 V -33 VOL @ MIN = 1.95 V 30 VOL @ MAX = 0.4 V *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33Ω (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 2 ICS recommended and/or chipset vendor layout guidelines must be followed to meet this specification IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 7 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -100 0 100 ppm 1,2 Clock period Tperiod 14.318MHz output nominal 69.8270 69.84 69.8550 ns 2 Clock Low Time Tlow Measure from < 0.6V 30.9290 37.9130 ns 2 Clock High Time Thigh Measure from > 2.0V 30.9290 37.9130 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA 0.4 V 1 Output High Current IOH VOH @MIN = 1.0 V, VOH@MAX = 3.135 V -29 -23 mA 1 Output Low Current IOL VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 1.5 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 1.5 ns 1 Skew tsk1 VT = 1.5 V 100 ps 1 Duty Cycle dt1 VT = 1.5 V Jitter tjcyc-cyc VT = 1.5 V 45 55 % 1 300 ps 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33Ω (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 8 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss Table1: CPU and HTT Frequency Selection Table Byte 0 Bit4 Bit3 Bit2 Bit1 Bit0 CPUCLK HTT Spread Overclock (2:0) (MHz) % % CPU CPU CPU CPU CPU (MHz) SS_EN FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Hi-Z X/2 230.00 240.00 100.00 133.33 166.67 200.00 250.00 260.00 270.00 280.00 102.00 136.00 170.00 204.00 210.00 220.00 230.00 240.00 100.00 133.33 166.67 200.00 250.00 260.00 270.00 280.00 102.00 136.00 170.00 204.00 Hi-Z X/3 76.67 80.00 66.67 66.67 66.67 66.67 83.33 86.67 90.00 93.33 68.00 68.00 68.00 68.00 70.00 73.33 76.67 80.00 66.67 66.67 66.67 66.67 83.33 86.67 90.00 93.33 68.00 68.00 68.00 68.00 None None None None None None None None None None None None None None None None -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% 15% 20% 0% 25% 30% 35% 40% 2% 5% 10% 15% 20% 0% 25% 30% 35% 40% 2% IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 9 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss Table2: SRC Frequency Selection Table Byte 5 Byte 0 Bit 5 Bit3 Bit2 Bit1 Bit0 SRC(7:0) SRC SRC SRC SRC SRC (MHz) SS_EN FS3 FS2 FS1 FS0 0 0 0 0 0 100.00 0 0 0 0 1 101.00 0 0 0 1 0 102.00 0 0 0 1 1 103.00 0 0 1 0 0 104.00 0 0 1 0 1 105.00 0 0 1 1 0 106.00 0 0 1 1 1 107.00 0 1 0 0 0 100.00 0 1 0 0 1 101.00 0 1 0 1 0 102.00 0 1 0 1 1 103.00 0 1 1 0 0 104.00 0 1 1 0 1 105.00 0 1 1 1 0 106.00 0 1 1 1 1 107.00 1 0 0 0 0 100.00 1 0 0 0 1 101.00 1 0 0 1 0 102.00 1 0 0 1 1 103.00 1 0 1 0 0 104.00 1 0 1 0 1 105.00 1 0 1 1 0 106.00 1 0 1 1 1 107.00 1 1 0 0 0 100.00 1 1 0 0 1 101.00 1 1 0 1 0 102.00 1 1 0 1 1 103.00 1 1 1 0 0 104.00 1 1 1 0 1 105.00 1 1 1 1 0 106.00 1 1 1 1 1 107.00 SRC Spread OverClock % % 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% 0% 1% 2% 3% 4% 5% 6% 7% 0% 1% 2% 3% 4% 5% 6% 7% 0% 1% 2% 3% 4% 5% 6% 7% 0% 1% 2% 3% 4% 5% 6% 7% IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 10 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss Table3: ATIG Frequency Selection Table Byte 9 Byte 0 ATIG Bit 6 Bit4 Bit3 Bit1 Bit0 ATIG(2:0) Spread OverClock % ATIG ATIG ATIG ATIG ATIG (MHz) % SS_EN FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% 0% 5% 10% 15% 20% 25% 30% 35% 0% 5% 10% 15% 20% 25% 30% 35% 0% 5% 10% 15% 20% 25% 30% 35% 0% 5% 10% 15% 20% 25% 30% 35% IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 11 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss Divider (1:0) Table 4: CPU Divider Ratios B19b(7:4) 00 Bit 00 0000 01 0001 10 0010 11 0011 Address LSB Divider (1:0) Table 5: HTT Divider Ratios B20b(3:0) 00 Bit 00 0000 01 0001 10 0010 11 0011 Address LSB Divider (1:0) Table 6: ATIG Divider Ratios B19b(3:0) 00 Bit 00 0000 01 0001 10 0010 11 0011 Address LSB 2 3 5 15 Div Divider (3:2) 01 10 0100 4 1000 0101 6 1001 0110 10 1010 0111 30 1011 Address Address 4 3 5 15 Div Divider (3:2) 01 10 0100 8 1000 0101 6 1001 0110 10 1010 0111 30 1011 Address Address 8 12 20 60 Div 11 1100 1101 1110 1111 Address MSB 16 24 40 120 Div 16 12 20 60 Div 11 1100 1101 1110 1111 Address MSB 32 24 40 120 Div 8 12 20 28 Div 11 1100 1101 1110 1111 Address MSB 16 24 40 56 Div Divider (3:2) 2 3 5 7 Div 01 0100 0101 0110 0111 Address 4 6 10 14 10 1000 1001 1010 1011 Address CPU Clock Common Recommendations for Differential Routing L1 length, Route as coupled 93 ohm trace. L2 length, Route as coupled 93 ohm trace. Dimension or Value 0.5 max Contact AMD Unit inch inch Figure 1 1 Figure 1 CPU clock routing. 3900pF +/-10% 93Ω +/-10% DIFF L2 L2 93Ω +/-10% DIFF L1 169Ω +/-10% L1 3900pF +/-10% Low Power Output Buffer w/integrated series resistor AMD "Greyhound" CPU input IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 12 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non-coupled 50 ohm trace. 0.5 max L2 length, Route as non-coupled 50 ohm trace. N/A L3 length, Route as non-coupled 50 ohm trace. N/A Rs 33 Rt 49.9 Unit inch inch inch ohm ohm Figure 2 2 2 2 2 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Unit inch inch Figure 2 2 Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch Figure 3 3 Figure 2 Down device routing. L1 L4 L4’ L1’ PCI Ex Board Down Device REF_CLK Input Low Power Output Buffer w/integrated series resistor Figure 2 Figure 3 PCI Express Connector Routing. L1 L4 L4’ L1’ Low Power Output Buffer w/integrated series resistor PCI Ex Add In Board REF_CLK Input Figure 3 IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 13 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss General SMBus serial interface information for the ICS9LPRS464 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 14 Not acknowledge stoP bit 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss SMBus Table: Spread Spectrum Enable and CPU Frequency Select Register Byte 0 Pin # Name Control Function Type Latched Input or SMBus RW FS Source Bit 7 Frequency Select ATIG SS_EN ATIG Spread Spectrum Enable RW Bit 6 SRC SS_EN SRC Spread Spectrum Enable RW Bit 5 CPU SS_EN CPU Spread Spectrum Enable RW Bit 4 CPU FS3 CPU Freq Select Bit 3 RW Bit 3 CPU FS2 CPU Freq Select Bit 2 RW Bit 2 CPU FS1 CPU Freq Select Bit 1 RW Bit 1 CPU FS0 CPU Freq Select Bit 0 RW Bit 0 Note: Each Spread Spectrum Enable bit is independent from the other. Bit(6:4) must all set to "1" in order to enable spread for CPU, SRC and ATIG clocks. SMBus Table: Output Control Register Byte 1 Pin # Name 7 48MHz_1 Bit 7 6 48MHz_0 Bit 6 54 REF2 Bit 5 55 REF1 Bit 4 56 REF0 Bit 3 51 HTTCLK0 Bit 2 44,43 CPUCLK1 Bit 1 48,47 CPUCLK0 Bit 0 Control Function 48MHz_1 Output Enable 48MHz_0 Output Enable REF2 Output Enable REF1 Output Enable REF0 Output Enable HTTCLK0 Output Enable CPUCLK1 Output Enable CPUCLK0 Output Enable SMBus Table: ATIGCLK and CLKREQB# Output Control Register Byte 2 Pin # Name Control Function Reserved Bit 7 Reserved Bit 6 31,30 ATIGCLK1 ATIGCLK1 Output Enable Bit 5 35,34 ATIGCLK0 ATIGCLK0 Output Enable Bit 4 Bit 3 20,21 REQBSRC2 Bit 0 1 PWD SMBus 0 Enable Enable Enable 0 0 0 0 Latch Latch Latch See Table 1: CPU Frequency Selection Table Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 Type 0 1 RW RW Disable Disable Does not control Enable Enable PWD 0 0 1 1 Controls 0 RW Reserved Bit 2 Bit 1 CLKREQB# Controls SRC2 0 Latched Inputs Disable Disable Disable 24,25 REQBSRC1 CLKREQB# Controls SRC1 0 RW Does not control Controls Reserved SMBus Table: SRCCLK Output Control Register Byte 3 Pin # Name Control Function 12,13 SRCCLK5 Bit 7 16,17 SRCCLK4 Bit 6 18,19 SRCCLK3 Bit 5 Master Output control. Enables 20,21 SRCCLK2 Bit 4 or disables output, regardless of Reserved Bit 3 CLKREQ# inputs. 24,25 SRCCLK1 Bit 2 Reserved Bit 1 39,38 SRCCLK0 Bit 0 IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 15 0 0 Type RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss SMBus Table: CLKREQB# and CLKREQC# Output Control Register Byte 4 Pin # Name Control Function Type Bit 7 12,13 REQASRC5 CLKREQA# Controls SRC5 RW Bit 6 16,17 REQASRC4 CLKREQA# Controls SRC4 RW Bit 5 18,19 REQASRC3 CLKREQA# Controls SRC3 RW PWD Controls 0 Controls 0 Controls 0 0 0 Bit 2 31,30 REQCATIG1 CLKREQC# Controls ATIG1 RW Bit 1 35,34 REQCATIG0 CLKREQC# Controls ATIG0 RW Bit 0 39,38 REQCSRC0 CLKREQC# Controls SRC0 RW SMBus Table: CPU Stop Control and SRC Frequency Select Register Byte 5 Pin # Name Control Function IO Output Voltage Select (Most IO_VOUT2 Bit 7 Significant Bit) IO_VOUT1 IO Output Voltage Select Bit 6 IO Output Voltage Select (Least IO_VOUT0 Bit 5 Significant Bit) Reserved Bit 4 SRC FS3 SRC Freq Select Bit 3 Bit 3 Bit 1 Bit 0 1 Reserved Reserved Bit 4 Bit 3 Bit 2 0 Does not control Does not control Does not control - SRC FS2 SRC FS1 SRC FS0 SMBus Table: Device ID Register Byte 6 Pin # Name Device ID7 (MSB) Bit 7 Device ID6 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 (LSB) Bit 0 SMBus Table: Revision and Vendor ID Register Byte 7 Pin # Name RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 Type Does not control Does not control Does not control 0 Controls 0 Controls 0 Controls 0 1 PWD RW RW 1 See Table 8: V_IO Selection (Default is 0.8V) 0 RW 1 RW 0 0 See Table 2: SRC Frequency Selection Table SRC Freq Select Bit 2 SRC Freq Select Bit 1 SRC Freq Select Bit 0 RW RW RW Control Function Type R R R R R R R R 0 - 1 - PWD 0 1 1 0 0 1 0 0 Type R R R R R R R R 0 - 1 - PWD 0 0 0 0 0 0 0 1 DEVICE ID Control Function REVISION ID VENDOR ID IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 16 0 0 0 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss SMBus Table: Byte Count Register Byte 8 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Byte Count Programming b(7:0) Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 Writing to this register will congiure how many bytes will 0 be read back, default is 9 1 bytes. 0 0 1 SMBus Table: REF2, 48MHz Output Strength Control and ATIG Frequency Select Register Byte 9 Pin # Name Control Function Type 0 1 54 REF2Str REF2 Strength Control RW 1X 2X Bit 7 7 48MHz_1Str 48MHz_1 Strength Control RW 1X 2X Bit 6 6 48MHz_0Str 48MHz_0 Strength Control RW 1X 2X Bit 5 Reserved Bit 4 ATIG FS3 ATIG Freq Select Bit 3 RW Bit 3 See Table 3: ATIG ATIG FS2 ATIG Freq Select Bit 2 RW Bit 2 Frequency Selection Table ATIG FS1 ATIG Freq Select Bit 1 RW Bit 1 ATIG FS0 ATIG Freq Select Bit 0 RW Bit 0 PWD 1 1 1 0 0 0 0 0 SMBus Table: PLLs M/N Programming Enable and REF1, REF0 Output Strength Control Register Byte 10 Pin # Name Control Function Type 0 M/N_EN PLLs M/N Programming Enable RW Disable Bit 7 55 REF1Str REF1 Strength Control RW 1X Bit 6 56 REF0Str REF0 Strength Control RW 1X Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 1 Enable 2X 2X PWD 0 1 1 0 0 0 0 0 1 PWD X X X X X X X X SMBus Table: CPU PLL VCO Frequency Control Register Byte 11 Pin # Name Control Function N Div8 N Divider Prog bit 8 Bit 7 N Div 9 N Divider Prog bit 9 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Div3 Bit 3 M Divider Programming bits M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0 Type RW RW RW RW RW RW RW RW The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] SMBus Table: CPU PLL VCO Frequency Control Register Byte 12 Pin # Name Control Function N Div7 Bit 7 N Div6 Bit 6 N Div5 Bit 5 N Div4 Bit 4 N Divider Programming b(7:0) N Div3 Bit 3 N Div2 Bit 2 N Div1 Bit 1 N Div0 Bit 0 Type RW RW RW RW RW RW RW RW The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 17 0 0 1 PWD X X X X X X X X 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss SMBus Table: CPU PLL Spread Spectrum Control Register Byte 13 Pin # Name Control Function SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 SSP4 Spread Spectrum Programming Bit 4 b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 SMBus Table: CPU PLL Spread Spectrum Control Register Byte 14 Pin # Name Control Function Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum Programming SSP11 Bit 3 b(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 Type RW RW RW RW RW RW RW RW Type RW RW RW RW RW RW RW SMBus Table: ATIG PLL VCO Frequency Control Register Byte 15 Pin # Name Control Function N Div8 N Divider Prog bit 8 Bit 7 N Div9 N Divider Prog bit 9 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Div3 Bit 3 M Divider Programming bits M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0 Type RW RW RW RW RW RW RW RW SMBus Table: ATIG PLL VCO Frequency Control Register Byte 16 Pin # Name Control Function N Div7 Bit 7 N Div6 Bit 6 N Div5 Bit 5 N Div4 Bit 4 N Divider Programming b(7:0) N Div3 Bit 3 N Div2 Bit 2 N Div1 Bit 1 N Div0 Bit 0 Type RW RW RW RW RW RW RW RW SMBus Table: ATIG PLL Spread Spectrum Control Register Byte 17 Pin # Name Control Function SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 SSP4 Spread Spectrum Programming Bit 4 b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 Type RW RW RW RW RW RW RW RW IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 18 0 1 PWD X X These Spread Spectrum bits in Byte 13 and 14 will program X X the spread pecentage. It is recommended to use ICS X Spread % table for spread X programming. X X 0 1 0 1 0 1 0 1 PWD 0 X These Spread Spectrum bits X in Byte 13 and 14 will program X the spread pecentage. It is X recommended to use ICS X Spread % table for spread X programming. X PWD X The decimal representation of X M and N Divier in Byte 17 and X 18 will configure the VCO X frequency. Default at power X up = Byte 0 Rom table. VCO X Frequency = 14.318 x X [NDiv(9:0)+8] / [MDiv(5:0)+2] X PWD X The decimal representation of X M and N Divier in Byte 17 and X 18 will configure the VCO X frequency. Default at power X up = Byte 0 Rom table. VCO X Frequency = 14.318 x X [NDiv(9:0)+8] / [MDiv(5:0)+2] X PWD X X These Spread Spectrum bits in Byte 19 and 20 will program X X the spread pecentage. It is recommended to use ICS X Spread % table for spread X programming. X X 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss SMBus Table: ATIG PLL Spread Spectrum Control Register Byte 18 Pin # Name Control Function Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum Programming SSP11 Bit 3 b(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 SMBus Table: CPU and ATIG Divider Ratio Programming Bits Select Register Byte 19 Pin # Name Control Function CPU_Div3 Bit 7 CPU_Divider Ratio CPU_Div2 Bit 6 Programming Bits CPU_Div1 Bit 5 CPU_Div0 Bit 4 ATIG_Div3 Bit 3 ATIG_Divider Ratio ATIG_Div2 Bit 2 Programming Bits ATIG_Div1 Bit 1 ATIG_Div0 Bit 0 SMBus Table: HTT Divider Ratio Programming Bits Select Register Byte 20 Pin # Name Control Function Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 HTT_Div3 Bit 3 HTT_Div2 HTT_Divider Ratio Bit 2 Programming Bits HTT_Div1 Bit 1 HTT_Div0 Bit 0 IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 19 Type RW RW RW RW RW RW RW Type RW RW RW RW RW RW RW RW Type RW RW RW RW 0 1 PWD 0 X These Spread Spectrum bits X in Byte 19 and 20 will program X the spread pecentage. It is X recommended to use ICS X Spread % table for spread X programming. X 0 1 See Table 4: CPU Divider Ratios See Table 5: ATIG Divider Ratios 0 1 See Table 6: HTT Divider Ratios PWD X X X X X X X X PWD 0 0 0 0 X X X X 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss RESET_IN# - Assertion (transition from '1' to '0') Asserting RESET_IN pin stops all the outputs including CPU, SRC, ATIG, PCI and USB with the REF[2:0] running. The pin is a Schmitt trigger input with debouncing. After it is triggered, REF clocks will wait for two clock cycle to ensure the RESET_IN is asserted. Then, it will take 3uS for the clocks to stop without glitches. The clock chip will be power down and re-power up, and SMBus will be reloaded. It will take no more than 2.5mS for the clocks to come out with correct frequencies and no glitches. ** Deassertion of RESET_IN# (transition from '0' to '1') has NO effect on the clocks. 2 clock cycles 2.5mS max 3 uS max RESET_IN# REF [2:0] *CLKS IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 20 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss Shared Pin Operation Input/Output Pins The I/O pins designated by (input/output) on the ICS9LPRS464 serve as dual signal functions to the device. During initial powerup, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 21 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N α 0° 8° 0° 8° aaa -0.10 -.004 c N L E1 INDEX AREA E 1 2 a D A A2 VARIATIONS A1 N -Ce b 56 SEATING PLANE D mm. MIN 13.90 D (inch) MAX 14.10 MIN .547 MAX .555 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 aaa C Ordering Information ICS 9LPRS464yGLFT Example: ICS XXXX y G LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs 22 1377A—04/07/08 ICS9LPRS464 System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs Revision History Rev. A Issue Date Description 1. Updated IDD current. 2. Added Down device routing Diagram and PCI Express Connector Routing Diagram. 3. Going to Release. 4. Updated Rs on REF & USB to 33ohm. 4/7/2008 5. Corrected REF ppm to +/- 100ppm. Page # 5,7-8,13 This product is protected by United States Patent NO. 7,342,420 and other patents. Innovate with IDT and accelerate your future networks. Contact: www.IDT.com TM For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 [email protected] Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 23