ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER General Description Features The ICS843003I-09 is a 3 differential output LVPECL Synthesizer designed to generate Ethernet HiPerClockS™ reference clock frequencies and is a member of the HiPerClocks™ family of high performance clock solutions from IDT. Using a 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated: 156.25MHz and 125MHz. The 843003I-09 has two output banks, Bank A with one differential LVPECL output pair and Bank B with two differential LVPECL output pairs. • Three 3.3Vdifferential LVPECL output pairs on two banks: Bank A with one LVPECL output pair Bank B with two LVPECL output pairs • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended reference clock input • • VCO range: 490MHz – 680MHz ICS • • • The ICS843003I-09 uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843003I-09 is packaged in a small 24-pin TSSOP, EPad package. RMS phase jitter @ 156.25MHz (1.875MHz – 20MHz): 0.53ps (typical) Full 3.3V supply mode -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Block Diagram Pin Assignment OEA Pullup VCO_SEL Pullup QA0 REF_CLK Pulldown nQA0 0 0 ÷4 25MHz XTAL_IN OSC 1 Phase Detector VCO 1 XTAL_OUT QB0 XTAL_SEL Pullup nQB0 ÷5 ÷25 QB1 nQB1 MR Pulldown OEB Pullup IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 1 nc VCO_SEL MR VCCO_A QA0 nQA0 OEB OEA nc VCCA VCC nc 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nc VCCO_B QB0 nQB0 QB1 nQB1 XTAL_SEL REF_CLK XTAL_IN XTAL_OUT VEE nc ICS843003I-09 24-Lead TSSOP, EPad 4.4mm x 7.8mm x 0.9mm package body G Package Top View ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Table 1. Pin Descriptions Number Name 1, 9, 12, 13, 24 nc 2 Type Description Unused VCO_SEL Input No connect. Pullup VCO select pin. When Low, the PLL is bypassed and the crystal reference or REF_CLK (depending on XTAL_SEL setting) are passed directly to the output dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels. Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs QX to go low and the inverted outputs nQX to go high. When logic LOW, the internal dividers and the outputs are enabled. MR has an internal pulldown resistor so the power-up default state of the outputs and dividers are enabled. LVCMOS/LVTTL interface levels. 3 MR Input 4 VCCO_A Power Output supply pin for Bank A outputs. 5, 6 QA0, nQA0 Output Differential output pair. LVPECL interface levels. 7 OEB Input Pullup Bank B output enable pin. Active High output enable. When logic HIGH, the 2 output pairs on Bank B are enabled. When logic LOW, the output pairs drive differential Low (QBx = Low, nQBx = High). OEB has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. Pullup Bank A output enable pin. Active High output enable. When logic HIGH, the output pair on Bank A is enabled. When logic LOW, the output pair drives differential Low (QA0 = Low, nQA0 = High). OEA has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. 8 OEA Input 10 VCCA Power Analog supply pin. 11 VCC Power Core supply pin. 14 VEE Power Negative supply pin. 15, 16 XTAL_OUT, XTAL_IN Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. 17 REF_CLK Input Pulldown Pullup Single-ended reference clock input. LVCMOS/LVTTL interface levels. Crystal select pin. Selects between the single-ended REF_CLK or crystal interface. Has an internal pullup resistor so the crystal interface is selected by default. LVCMOS/LVTTL interface levels. 18 XTAL_SEL Input 19, 20 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 21, 22 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 23 VCCO_B Power Output supply pin for Bank B outputs. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER Test Conditions 2 Minimum Typical Maximum Units ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Function Tables Table 3A. Bank A Frequency Table Input Crystal Frequency (MHz) Feedback Divider Bank A Output Divider M/N Multiplication Factor QA0/nQA0 Output Frequency (MHz) 25 25 4 6.25 156.25 24 25 4 6.25 150 20 25 4 6.25 125 Crystal Frequency (MHz) Feedback Divider Bank B Output Divider M/N Multiplication Factor QB[0:1]/nQB[0:1] Output Frequency (MHz) 25 25 5 5 125 Table 3B. Bank B Frequency Table Input Table 3C. OEA Select Function Table Input Table 3D. OEB Select Function Table Outputs Input Outputs OEA QA0 nQA0 OEB QB0, QB1 nQB0, nQB1 0 LOW HIGH 0 LOW HIGH 1 Active Active 1 Active Active Enabled Disabled REF_CLK OEA, OEB nQA0, nQB0, nQB1 QA0, QB0, QB1 Figure 1. OE Timing Diagram IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 3 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 32.1°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCC Core Supply Voltage VCCA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VCC – 0.20 3.3 3.465 V VCCO_A, VCCO_B Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 150 mA ICCA Analog Supply Current 20 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V MR, REF_CLK VCC = VIN = 3.465V 150 µA OEA, OEB, VCO_SEL, XTAL_SEL VCC = VIN = 3.465V 5 µA MR, REF_CLK VCC = 3.465V, VIN = 0V -5 µA OEA, OEB, VCO_SEL, XTAL_SEL VCC = 3.465V, VIN = 0V -150 µA Input Low Current IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 4 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Table 4C. LVPECL DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Current; NOTE 1 VOL Output Low Current; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCCO_A/B – 1.4 VCCO_A/B – 0.9 µA VCCO_A/B – 2.0 VCCO_A/B – 1.7 µA 0.6 1.0 V Maximum Units 27.2 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units NOTE 1: Outputs terminated with 50Ω to VCCO_A, _B – 2V. Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 19.6 NOTE: Characterized using an 18pF parallel resonant crystal. AC Electrical Characteristics Table 6. AC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Parameter Symbol fOUT Output Frequency Range tjit(Ø) RMS Phase Jitter, (Random); NOTE 1 tsk(b) Bank Skew; NOTE 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical ÷4 122.5 170 MHz ÷5 98 136 MHz 156.25MHz, (1.875MHz – 20MHz) 0.53 ps 125MHz, (1.875MHz – 20MHz) 0.48 ps 20% to 80% 50 ps 200 600 ps 45 55 % NOTE 1: Please refer to the Phase Noise Plots. NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 5 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 156.25MHz -10 ➝ 0 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.53ps (typical) -20 10 Gigabit Ethernet Filter -30 -40 -50 -70 -80 -90 -100 ➝ Noise Power dBc Hz -60 Raw Phase Noise Data -110 -120 -130 ➝ -140 -150 -160 Phase Noise Result by adding a 10 Gigabit Ethernet filter to raw data -170 -180 -190 1k 10k 100k 1M 10M 100M Offset Frequency (Hz) IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 6 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Parameter Measurement Information 2V% Phase Noise Plot VCC, VCCO_A, V VCCO_B CCA Qx Noise Power 2V% SCOPE Phase Noise Mask LVPECL nQx f1 VEE Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot - -1.3V ± 0.165V 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter nQA0, nQB0, nQB1 nQB0 80% QB0 80% VSW I N G nQB1 QA0, QB0, QB1 QB1 20% 20% tR tF tsk(b) Bank Skew Output Rise/Fall Time nQA0, nQB0, nQB1 QA0, QB0, QB1 t PW t odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 7 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843003I-09 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, VCCO_B and VCCO_B should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01µF 10Ω .01µF 10µF VCCA Figure 2. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: Outputs: Crystal Inputs LVPECL Outputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. REF_CLK Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 8 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Crystal Input Interface The ICS843003I-09 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22p X1 18pF Parallel Crystal XTAL_OUT C2 22p Figure 3. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 4. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VCC impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VCC R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 9 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 125Ω 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω Figure 5A. 3.3V LVPECL Output Termination IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 84Ω Figure 5B. 3.3V LVPECL Output Termination 10 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are SOLDER PIN PIN PAD EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER PIN LAND PATTERN (GROUND PAD) SOLDER PIN PAD Figure 6. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale) IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 11 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS843003I-09. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843003I-09 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.75mW • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 3 * 30mW = 90mW Total Power_MAX (3.3V, with all outputs switching) = 519.75mW + 90mW = 609.75mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 32.1°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.610W * 32.1°C/W = 104.6°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 7. Thermal Resistance θJA for 24 Lead TSSOP, EPad Forced Convection θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 0 1 2.5 32.1°C/W 25.5°C/W 24°C/W 12 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 7. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO - 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCOO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW L L Pd_L = [(VOL_MAX (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW – L L Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 13 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Reliability Information Table 8. θJA vs. Air Flow Table for a 24 Lead TSSOP, EPad θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 32.1°C/W 25.5°C/W 24°C/W Transistor Count The transistor count for ICS843003I-09 is: 3822 IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 14 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP, EPad Table 9. Package Dimensions Symbol N A A1 A2 b b1 c c1 D E E1 e L P P1 α ααα bbb All Dimensions in Millimeters Minimum Nominal Maximum 24 1.10 0.05 0.15 0.85 0.90 0.95 0.19 0.30 0.19 0.22 0.25 0.09 0.20 0.09 0.127 0.16 7.70 7.90 6.40 Basic 4.30 4.40 4.50 0.65 Basic 0.50 0.60 0.70 5.0 5.5 3.0 3.2 0° 8° 0.076 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 15 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Ordering Information Table 10. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 843003BGI-09 ICS843003BI09 24 Lead TSSOP, E-Pad Tube -40°C to 85°C 843003BGI-09T ICS843003BI09 24 Lead TSSO, EPad 2500 Tape & Reel -40°C to 85°C 843003BGI-09LF ICS43003BI09L “Lead-Free” 24 Lead TSSOP, EPad Tube -40°C to 85°C 843003BGI-09LFT ICS43003BI09L “Lead-Free” 24 Lead TSSOP, EPad 2500 Tape & Reel -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 16 ICS843003BGI-09 REV. A APRIL 17, 2008 ICS843003I-09 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA