UM10736: LPC15xx User Manual

UM10736
LPC15xx User manual
Rev. 1.1 — 3 March 2014
User manual
Document information
Info
Content
Keywords
LPC1500, LPC1500 User manual , LPC15xx UM, LPC15xx User manual,
LPC1549, LPC1548, LPC1547, LPC1519, LPC1518, LPC1517
Abstract
LPC15xx User manual
UM10736
NXP Semiconductors
LPC15xx User manual
Revision history
Rev
Date
Description
1.1
20140303
LPC15xx User manual
Modifications:
1
•
Section 5.4.2 “Criterion for valid user code” corrected: If the signature is not valid, the part enumerates
as USB MSC. Also see Figure 7.
•
Number of bits corrected in Table 228 “SCT event state mask registers 0 to 15 (EV[0:15]_STATE,
addresses 0x1C01 8300 (EV0_STATE) to 0x1C01 8378 (EV15_STATE) (SCT0) and 0x1C01 C300
(EV0_STATE) to 0x1C01 C378 (EV15_STATE) (SCT1)) bit description”.
•
Figure 11 “Example: Connect function U0_RXD and U0_TXD to pins” corrected.
20140213
First LPC15xx User manual revision
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Chapter 1: LPC15xx Introductory information
Rev. 1.1 — 3 March 2014
User manual
1.1 Introduction
The LPC15xx are ARM Cortex-M3 based microcontrollers for embedded applications
featuring a rich peripheral set with very low power consumption. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as enhanced debug features
and a higher level of support block integration.
The LPC15xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The LPC15xx include up to 256 kB of flash memory, 32 kB of ROM, a 4 kB EEPROM, and
up to 36 kB of SRAM. The peripheral compliment includes one full-speed USB 2.0 device,
two SPI interfaces, three USARTs, one Fast-mode Plus I2C-bus interface, one C_CAN
module, PWM/timer subsystem with four configurable, multi-purpose State Configurable
Timers (SCTimer/PWM) with input pre-processing unit, a Real-time clock module with
independent power supply and a dedicated oscillator, two 12-channel/12-bit,
2 Msamples/sec ADCs, one 12-bit, 500 kSamples/sec DAC, four voltage comparators
with internal voltage reference, and a temperature sensor. A DMA engine can service
most peripherals.
For additional documentation, see Section 45.2 “References”.
1.2 Features
• System:
– ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.
– ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
– System tick timer.
– Serial Wire Debug (SWD) with four breakpoints and two watchpoints.
– Single-cycle multiplier supported.
– Memory Protection Unit (MPU) included.
• Memory:
– Up to 256 kB on-chip flash programming memory with 256 Byte page write and
erase.
– Up to 36 kB SRAM.
– 4 kB EEPROM.
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Chapter 1: LPC15xx Introductory information
• ROM API support:
– Boot loader with boot options from flash or external source via USART, C_CAN, or
USB
– USB drivers
– ADC drivers
– SPI drivers
– USART drivers
– I2C drivers
– Power profiles and power mode configuration with low-power mode configuration
option
– DMA drivers
– C_CAN drivers
– Flash In-Application Programming (IAP) and In-System Programming (ISP).
• Digital peripherals:
– Simple DMA engine with 18 channels and 20 programmable input triggers.
– High-speed GPIO interface with up to 76 General-Purpose I/O (GPIO) pins with
configurable pull-up/pull-down resistors, open-drain mode, input inverter, and
programmable digital glitch filter.
– GPIO interrupt generation capability with boolean pattern-matching feature on
eight external inputs.
– Two GPIO grouped port interrupts.
– Switch matrix for flexible configuration of each I/O pin function.
– CRC engine.
– Quadrature Encoder Interface (QEI).
• Configurable PWM/timer/motor control subsystem:
– Up to four 32-bit counter/timers or up to eight 16-bit counter/timers or combinations
of 16-bit and 32-bit timers.
– Up to 28 match outputs and 22 configurable capture inputs with input multiplexer.
– Dither engine for improved average resolution of pulse edges.
– Four State Configurable Timers (SCTimers) for highly flexible, event-driven timing
and PWM applications.
– SCT Input Pre-processor Unit (SCTIPU) for processing timer inputs and immediate
handling of abort situations.
– Integrated with ADC threshold compare interrupts, temperature sensor, and analog
comparator outputs for motor control feedback using analog signals.
• Special-application and simple timers:
– 24-bit, four-channel, multi-rate timer (MRT) for repetitive interrupt generation at up
to four programmable, fixed rates.
– Repetitive interrupt timer for general purpose use.
– Windowed Watchdog timer (WWDT).
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Chapter 1: LPC15xx Introductory information
– High-resolution 32-bit Real-time clock (RTC) with selectable 1 s or 1 ms time
resolution running in the always-on power domain. RTC can be used for wake-up
from all low power modes including Deep power-down.
• Analog peripherals:
– Two 12-bit ADC with up to 12 input channels per ADC and with multiple internal
and external trigger inputs and sample rates of up to 2 Msamples/s. Each ADC
supports two independent conversion sequences. ADC conversion clock can be
the system clock or an asynchronous clock derived from one of the three PLLs.
– One 12-bit DAC.
– Integrated temperature sensor and band gap internal reference voltage.
– Four comparators with external and internal voltage references (ACMP0 to 3).
Comparator outputs are internally connected to the SCTimer/PWMs and ADCs and
externally to pins. Each comparator output contains a programmable glitch filter.
• Serial interfaces:
– Three USART interfaces with DMA, RS-485 support, auto-baud, and with
synchronous mode and 32 kHz mode for wake-up from Deep-sleep and
Power-down modes. The USARTs share a fractional baud-rate generator.
– Two SPI controllers.
– One I2C-bus interface supporting fast mode and Fast-mode Plus with data rates of
up to 1Mbit/s and with multiple address recognition and monitor mode.
– One C_CAN controller.
– One USB 2.0 full-speed device controller with on-chip PHY.
• Clock generation:
– 12 MHz internal RC oscillator trimmed to 1 % accuracy for 25 C  Tamb  +85 C
that can optionally be used as a system clock.
– Crystal oscillator with an operating range of 1 MHz to 25 MHz.
– Watchdog oscillator running at the fixed frequency of 503 kHz.
– 32 kHz low-power RTC oscillator with 32 kHz, 1 kHz, and 1 Hz outputs.
– System PLL allows CPU operation up to the maximum CPU rate without the need
for a high-frequency crystal. May be run from the system oscillator or the internal
RC oscillator.
– Two additional PLLs for generating the USB and SCTimer/PWM clocks.
– Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
• Power control:
– Integrated PMU (Power Management Unit) to minimize power consumption.
– Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode.
– APIs provided for optimizing power consumption in active and sleep modes and for
configuring Deep-sleep, Power-down, and Deep power-down modes.
– Wake-up from Deep-sleep and Power-down modes on activity on USB, USART,
SPI, and I2C peripherals.
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Chapter 1: LPC15xx Introductory information
– Wake-up from Sleep, Deep-sleep, Power-down, and Deep power-down modes
from the RTC alarm or wake-up interrupts.
– Timer-controlled self wake-up from Deep power-down mode using the RTC
high-resolution/wake-up 1 kHz timer.
– Power-On Reset (POR).
– BrownOut Detect BOD).
•
•
•
•
•
UM10736
User manual
JTAG boundary scan modes supported.
Unique device serial number for identification.
Single power supply 2.4 V to 3.6 V.
Temperature range -40 °C to +105 °C.
Available as LQFP100, LQFP64, and LQFP48 packages.
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Chapter 1: LPC15xx Introductory information
1.3 Block diagram
LPC15xx
PROCESSOR CORE
ARM
CORTEX-M3
NVIC
TEST/DEBUG INTERFACE
SWD/ETM
MPU
HS GPIO
MEMORY
256/128/64 kB FLASH
PORT0/1/2
pads
AHB MULTILAYER
MATRIX
PINT/
PATTERN MATCH
n
SYSTICK
4 kB EEPROM
INPUT MUX
36/20/12 kB SRAM
GINT0/1
AHB/APB BRIDGES
32 kB ROM
ANALOG PERIPHERALS
ACMP1
ACMP0/
TEMPERATURE
SENSOR
12-bit DAC
ACMP2
ACMP3
12-bit ADC0
12-bit ADC1
TRIGGER MUX
TRIGGER MUX
INPUT MUX
INPUT MUX
SWM
pads
n
SCTIMER/PWM/MOTOR CONTROL SUBSYSTEM
DMA TRIGGER
QEI
SCTIMER0/ SCTIMER1/ SCTIMER2/ SCTIMER3/
PWM
PWM
PWM
PWM
DMA
SCTIPU
SERIAL PERIPHERALS
C_CAN
FS USB/
PHY
USART0
FM+ I2C0
SPI1
USART1
USART2
SPI0
TIMERS
CLOCK
GENERATION
MRT
RIT
PRECISION
IRC
WATCHDOG
OSCILLATOR
SYSTEM
PLL
USB
PLL
SCT
PLL
WWDT
RTC
SYSTEM
OSCILLATOR
FREQUENCY
MEASUREMENT
RTC
OSCILLATOR
INPUT MUX
SYSTEM/MEMORY CONTROL
SYSCON
IOCON
PMU
CRC
FLASH CTRL
EEPROM CTRL
aaa-010869
Grey-shaded blocks show peripherals that can provide hardware triggers for DMA transfers or have DMA request lines.
Fig 1.
Block diagram
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Chapter 1: LPC15xx Introductory information
1.4 Functional description
1.4.1 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is
dedicated for data access (D-code). The use of two core buses allows for simultaneous
operations if concurrent operations target different devices.
A multi-layer AHB matrix connects the Cortex-M3 buses and other bus masters to
peripherals in a flexible manner that optimizes performance by allowing peripherals on
different slaves ports of the matrix to be accessed simultaneously by different bus
masters. Details of the multilayer matrix connections are shown in Figure 2.
APB peripherals are connected to the CPU via two APB buses using separate slave ports
from the multilayer AHB matrix. This allows for better performance by reducing collisions
between the CPU and the DMA controller. The APB bus bridges are configured to buffer
writes so that the CPU or DMA controller can write to APB devices without always waiting
for APB write completion.
1.4.2 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The Cortex-M3 includes a Thumb-2
instruction set and provides low interrupt latency, hardware divide,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller, and multiple core buses
capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
1.4.2.1 Cortex-M3 Configuration Options
The LPC15xx uses the r2p1 version of the Cortex-M3 CPU, which includes a number of
configurable options, as noted below.
System options:
•
•
•
•
•
The Nested Vectored Interrupt Controller (NVIC) is included.
SYSTICK timer is included.
Single-cycle multiplier supported.
A Memory Protection Unit (MPU) is included.
A ROM Table in included. The ROM Table provides addresses of debug components
to external debug systems.
Debug related options:
• Serial Wire Debug is included. Serial Wire Debug allows debug operations using only
two wires, simple trace functions can be added with a third wire.
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Chapter 1: LPC15xx Introductory information
• The Data Watchpoint and Trace (DWT) unit is included. The DWT allows data
address or data value matches to be trace information or trigger other events. The
DWT includes four comparators and counters for certain internal events.
• An Instrumentation Trace Macrocell (ITM) is included. Software can write to the ITM in
order to send messages to the trace port.
• The Trace Port Interface Unit (TPIU) is included. The TPIU encodes and provides
trace information to the outside world using the serial wire output pin function.
1.4.3 PWM/timer/motor control subsystem
The SCTs (State Configurable Timers) and the analog peripherals support multiple ways
of interconnecting their inputs and outputs and of interfacing to the pins and the DMA
controller. Using the highly flexible and programmable connection scheme makes it easy
to configure various subsystems for motor control and complex timing and tracking
applications. Specifically, the inputs to the SCTs and the trigger inputs of the ADCs and
DMA are selected through the input mux which offers a choice of many possible sources
for each input or trigger. SCT outputs are assigned to pins through the switch matrix
allowing for many pinout solutions.
1.4.3.1 PWW/timer subsystem
The SCTs can be configured to build a PWM controller with multiple outputs by
programming the MATCH and MATCHRELOAD registers of the SCTs to control the base
frequency and the duty cycle of each SCT output. More complex waveforms that span
multiple counter cycles or change behavior across or within counter cycles can be
generated using the state capability built into the SCT timers.
Combining the PWM functions with the analog functions, the PWM output can react to
control signals like comparator outputs or the ADC interrupts. The SCT IPU adds
emergency shut-down functions and pre-processing of controlling events. For an overview
of the PWM subsystem, see Figure 2 “PWM-Analog subsystem”.
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Chapter 1: LPC15xx Introductory information
digital signal from/to pins
analog peripheral
analog signal from/to pins
digital peripheral
digital signal internal
analog signal internal
ANALOG IN
TRIGGER
SWITCH MATRIX
THRESHOLD CROSSING
INTERRUPTS
ADC0/ADC1
4
VDDA DIVIDER
TEMP SENSOR
VOLTAGE
REFERENCE
SCT1
MATCH/
MATCHRELOAD OUTPUTS
8 x PWM OUT
TIMER1
TIMER2
SCT2
MATCH/
MATCHRELOAD OUTPUTS
TIMER3
SCT3
MATCH/
MATCHRELOAD OUTPUTS
ACMP0
ACMP1
ACMP2
ACMP3
6 x PWM OUT
6 x PWM OUT
OUTPUTS
SCT IPU
ANALOG IN
Fig 2.
SCT0
MATCH/
MATCHRELOAD OUTPUTS
8 x PWM OUT
TIMER0
SWITCH MATRIX
INPUT MUX
SCT0/1/2/3
aaa-010873
PWM-Analog subsystem
1.4.3.2 Timer controlled subsystem
The timers, the analog components, and the DMA can be configured to form a subsystem
that can run independently of the main processor under the control of the SCTs and any
events that are generated by the A/D converters, the comparators, the SCT output
themselves, or the external pins. A/D conversions can be triggered by the timer outputs,
the comparator outputs or by events from external pins. Data can be transferred from the
ADCs to memory using the DMA controller, and the DMA transfers can be triggered by the
ADCs, the comparator outputs, or by the timer outputs.
For an overview of the subsystem, see Figure 3 “Subsystem with timers, switch matrix,
DMA, and analog components”.
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Chapter 1: LPC15xx Introductory information
analog peripheral
analog signal from/to pins
digital peripheral
INPUT MUX
DMA
digital signal from/to pins
digital signal internal
analog signal internal
4
VOLTAGE
REFERENCE
SCT IPU
INPUT MUX
TEMP SENSOR
TIMER1 (SCT1)
TIMER2 (SCT2)
NVIC
OUTPUTS
TIMER0 (SCT0)
VDDA DIVIDER
THRESHOLD CROSSING
INTERRUPTS
TRIGGER
SWITCH MATRIX
ANALOG IN
ADC0/ADC1
ACMP1
ACMP2
ACMP3
SWITCH MATRIX
ACMP0
OUTPUTS
ANALOG IN
TIMER3 (SCT3)
DAC_SHUTOFF
DAC
aaa-010874
Fig 3.
Subsystem with timers, switch matrix, DMA, and analog components
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Chapter 1: LPC15xx Memory mapping
Rev. 1.1 — 3 March 2014
User manual
1.1 How to read this chapter
USB is not available on parts LPC1519/18/17.
1.2 General description
The LPC15xx incorporates several distinct memory regions. Figure 1 shows the overall
map of the entire address space from the user program viewpoint following reset.
The APB peripheral area is 2 x 512 kB in size and is divided to allow for two blocks of up
to 32 peripherals. Each peripheral is allocated 16 kB of space simplifying the address
decoding.
The registers incorporated into the ARM Cortex-M3 core, such as NVIC, SysTick, and
sleep mode control, are located on the private peripheral bus.
1.2.1 SRAM
The parts contain a total 36 kB, 20 kB or 12 kB of contiguous, on-chip static RAM memory.
For each SRAM configuration, the SRAM is divided into three blocks: 2 x 16 kB + 4 kB for
36 kB SRAM, 2 x 8 kB + 4 kB for 20 kB SRAM, and 2 x 4 kB + 4 kB for 12 kB SRAM. The
bottom 16 kB, 8 kB, or 4 kB are enabled by the boot loader and cannot be disabled. The
next two SRAM blocks in each configuration can be disabled or enabled individually in the
SYSCON block to save power. See Section 3.6.22 “System clock control register 0”.
Table 1.
LPC15xx SRAM configurations
SRAM0
SRAM1
SRAM2
LPC1549/19 (total SRAM = 36 kB)
Address range
0x0200 0000 to
0x0200 3FFF
0x0200 4000 to
0x0200 7FFF
0x0200 8000 to
0x0200 8FFF
Size
16 kB
16 kB
4 kB
Control
cannot be disabled
disable/enable
disable/enable
Default
enabled
enabled
enabled
0x0200 2000 to
0x0200 3FFF
0x0200 4000 to
0x0200 4FFF
LPC1548/18 (total SRAM = 20 kB)
Address range
0x0200 0000 to
0x0200 1FFF
Size
8 kB
8 kB
4 kB
Control
cannot be disabled
disable/enable
disable/enable
Default
enabled
enabled
enabled
LPC1547/17 (total SRAM = 12 kB)
UM10736
User manual
Address range
0x0200 0000 to
0x0200 0FFF
0x0200 1000 to
0x0200 1FFF
0x0200 2000 to
0x0200 2FFF
Size
4 kB
4 kB
4 kB
Control
cannot be disabled
disable/enable
disable/enable
Default
enabled
enabled
enabled
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Chapter 1: LPC15xx Memory mapping
1.2.2 Memory mapping
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The private peripheral bus includes the ARM Cortex-M3 peripherals such as the NVIC, SysTick, and the core control registers.
Fig 1.
Memory mapping
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Chapter 1: LPC15xx Memory mapping
1.2.3 AHB multilayer matrix
TEST/DEBUG
INTERFACE
ARM
CORTEX-M3
System
bus
I-code
bus
USB
DMA
masters
D-code
bus
slaves
FLASH
SRAM0
SRAM1
SRAM2
ROM
EEPROM
HS GPIO
SCTIMER0/PWM
SCTIMER1/PWM
SCTIMER2/PWM
SCTIMER3/PWM
CRC
AHB-TO-APB
BRIDGE0
WWDT
ACMP
DAC
ADC0
SWM
PMU
SPI1
INPUT MUX
USART1
I2C0
QEI
USART2
RTC
SPI0
SYSCON
AHB-TO-APB
BRIDGE1
AHB MULTILAYER MATRIX
RIT
PINT
MRT
ADC1
SCTIPU
IOCON
FLASH CTRL
GINT0
GINT1
USART2
C_CAN
EEPROM CTRL
= master-slave connection
aaa-010870
Fig 2.
AHB multilayer matrix connections
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Chapter 1: LPC15xx Memory mapping
1.2.4 Memory Protection Unit (MPU)
The Cortex-M3 processor has a memory protection unit (MPU) that provides fine grain
memory control, enabling applications to implement security privilege levels, separating
code, data and stack on a task-by-task basis. Such requirements are critical in many
embedded applications.
The MPU register interface is located on the private peripheral bus and is described in
detail in Ref. 1.
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller
(NVIC)
Rev. 1.1 — 3 March 2014
User manual
2.1 How to read this chapter
USB is available on parts LPC1549/48/47.
2.2 Features
•
•
•
•
•
•
•
•
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3.
Tightly coupled interrupt controller provides low interrupt latency.
Controls system exceptions and peripheral interrupts.
The NVIC supports 47 vectored interrupts.
Eight programmable interrupt priority levels with hardware priority level masking.
Software interrupt generation using the ARM exceptions SVCall and PendSV.
Support for NMI.
ARM Cortex-M3 Vector table offset register VTOR implemented.
2.3 General description
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
2.3.1 Interrupt sources
Table 2 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. The interrupt number does not imply any
interrupt priority.
See Ref. 1 for a detailed description of the NVIC and the NVIC register description.
Table 2.
Connection of interrupt sources to the NVIC
Interrupt
number
Name
Description
Flags
0
WDT
Windowed watchdog timer
interrupt
WARNINT - watchdog warning interrupt
1
BOD
BOD interrupt
BODINTVAL - BOD interrupt level
2
FLASH
Flash controller
-
3
EE
EEPROM controller interrupt -
4
DMA
DMA
Interrupt A and interrupt B, error interrupt
5
GINT0
GPIO group0 interrupt
Enabled pin interrupts
6
GINT1
GPIO group1 interrupt
Enabled pin interrupts
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
Table 2.
Connection of interrupt sources to the NVIC
Interrupt
number
Name
Description
Flags
7
PIN_INT0
Pin interrupt 0 or pattern
match engine slice 0
interrupt
PSTAT - pin interrupt status
8
PIN_INT1
Pin interrupt 1 or pattern
match engine slice 1
interrupt
PSTAT - pin interrupt status
9
PIN_INT2
Pin interrupt 2 or pattern
match engine slice 2
interrupt
PSTAT - pin interrupt status
10
PIN_INT3
Pin interrupt 3 or pattern
match engine slice 3
interrupt
PSTAT - pin interrupt status
11
PIN_INT4
Pin interrupt 4 or pattern
match engine slice 4
interrupt
PSTAT - pin interrupt status
12
PIN_INT5
Pin interrupt 5 or pattern
match engine slice 5
interrupt
PSTAT - pin interrupt status
13
PIN_INT6
Pin interrupt 6 or pattern
match engine slice 6
interrupt
PSTAT - pin interrupt status
14
PIN_INT7
Pin interrupt 7 or pattern
match engine slice 7
interrupt
PSTAT - pin interrupt status
15
RIT
RIT interrupt
RITINT; masked compare interrupt
16
SCT0
State configurable timer
interrupt
EVFLAG SCT event
17
SCT1
State configurable timer
interrupt
EVFLAG SCT event
18
SCT2
State configurable timer
interrupt
EVFLAG SCT event
19
SCT3
State configurable timer
interrupt
EVFLAG SCT event
20
MRT
Multi-rate timer interrupt
Global MRT interrupt.
GFLAG0
GFLAG1
GFLAG2
GFLAG3
21
UART0
USART0 interrupt
See Table 350 “USART Interrupt Enable read and set
register (INTENSET, address 0x4004 000C(USART0),
0x4004 400C (USART1), 0x400C 000C (USART2)) bit
description”.
22
UART1
USART1 interrupt
Same as UART0
23
UART2
USART2 interrupt
Same as UART0
24
I2C0
I2C0 interrupt
See Table 379 “Interrupt Enable Set and read register
(INTENSET, address 0x4005 0008) bit description”.
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
Table 2.
Connection of interrupt sources to the NVIC
Interrupt
number
Name
Description
Flags
25
SPI0
SPI0 interrupt
See Table 364 “SPI Interrupt Enable read and Set
register (INTENSET, addresses 0x4004 800C (SPI0),
0x4004 C00C (SPI1)) bit description”.
26
SPI1
SPI1 interrupt
Same as SPI0
27
C_CAN0
C_CAN0 interrupt
INTID. See Table 398.
28
USB
USB interrupt
USB_Int_Req. See Table 342.
29
USB_FIQ
USB interrupt
USB_Int_Req_FIQ. See Table 342.
30
USB_WAKEUP
USB wake-up interrupt
USB need_clock signal
31
ADC0_SEQA
ADC0 sequence A
completion.
See Table 445.
32
ADC0_SEQB
ADC0 sequence B
completion.
See Table 445.
33
ADC0_THCMP
ADC0 threshold compare.
See Table 445.
34
ADC0_OVR
ADC0 overrun.
See Table 445.
35
ADC1_SEQA
ADC1 sequence A
completion.
See Table 445.
36
ADC1_SEQB
ADC1 sequence B
completion.
See Table 445.
37
ADC1_THCMP
ADC1 threshold compare.
See Table 445.
38
ADC1_OVR
ADC1 overrun.
See Table 445.
39
DAC
DAC interrupt
Internal DMA timer overflow.
40
CMP0
Analog comparator 0
interrupt (ACMP0)
COMPEDGE - rising, falling, or both edges can set the
bit.
41
CMP1
Analog comparator 1
interrupt (ACMP1)
COMPEDGE - rising, falling, or both edges can set the
bit.
42
CMP2
Analog comparator 2
interrupt (ACMP2)
COMPEDGE - rising, falling, or both edges can set the
bit.
43
CMP3
Analog comparator 3
interrupt (ACMP3)
COMPEDGE - rising, falling, or both edges can set the
bit.
44
QEI
QEI interrupt
See Table 321.
45
RTC_ALARM
RTC alarm interrupt
ALARM1HZ. See Table 272.
46
RTC_WAKE
RTC wake-up interrupt
WAKEHIRES. See Table 272.
2.4 Register description
The NVIC registers are located on the ARM private peripheral bus.
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
Table 3.
Register overview: NVIC (base address 0xE000 E000)
Name
Access Address Description
offset
Reset
value
Reference
ISER0
R/W
0x100
Interrupt Set Enable Register 0. This register allows enabling
interrupts and reading back the interrupt enables for specific
peripheral functions.
0
Table 4
ISER1
R/W
0x104
Interrupt Set Enable Register 1.
0
Table 5
ICER0
R/W
0x180
Interrupt Clear Enable Register 0. This register allows disabling
interrupts and reading back the interrupt enables for specific
peripheral functions.
0
Table 6
ICER1
R/W
0x184
Interrupt Clear Enable Register 1.
0
Table 7
ISPR0
R/W
0x200
Interrupt Set Pending Register 0. This register allows changing the
interrupt state to pending and reading back the interrupt pending
state for specific peripheral functions.
0
Table 8
ISPR1
R/W
0x204
Interrupt Set Pending Register 1.
0
Table 9
ICPR0
R/W
0x280
Interrupt Clear Pending Register 0. This register allows changing the 0
interrupt state to not pending and reading back the interrupt pending
state for specific peripheral functions.
ICPR1
R/W
0x284
Interrupt Clear Pending Register 1.
0
Table 11
IABR0
R
0x300
Interrupt Active Bit Register 0. This register allows reading the
current interrupt active state for specific peripheral functions.
0
Table 12
IABR1
R
0x304
Interrupt Active Bit Register 1.
0
Table 13
IPR0
R/W
0x400
Interrupt Priority Registers 0. This register allows assigning a priority 0
to each interrupt. This register contains the 3-bit priority fields for
interrupts 0 to 3.
Table 14
IPR1
R/W
0x404
Interrupt Priority Registers 1 This register allows assigning a priority
to each interrupt. This register contains the 3-bit priority fields for
interrupts 4 to 7.
0
Table 15
IPR2
R/W
0x408
Interrupt Priority Registers 2. This register allows assigning a priority 0
to each interrupt. This register contains the 3-bit priority fields for
interrupts 8 to 11.
Table 16
IPR3
R/W
0x40C
Interrupt Priority Registers 3. This register allows assigning a priority 0
to each interrupt. This register contains the 3-bit priority fields for
interrupts 12 to 15.
Table 17
IPR4
R/W
0x410
Interrupt Priority Registers 4. This register allows assigning a priority 0
to each interrupt. This register contains the 3-bit priority fields for
interrupts 16 to 19.
Table 18
IPR5
R/W
0x414
Interrupt Priority Registers 5. This register allows assigning a priority 0
to each interrupt. This register contains the 3-bit priority fields for
interrupts 20 to 23.
Table 19
IPR6
R/W
0x418
Interrupt Priority Registers 6. This register allows assigning a priority 0
to each interrupt. This register contains the 3-bit priority fields for
interrupts 24 to 27.
Table 20
IPR7
R/W
0x41C
Interrupt Priority Registers 7. This register allows assigning a priority 0
to each interrupt. This register contains the 3-bit priority fields for
interrupts 28 to 31.
Table 21
IPR8
R/W
0x420
Interrupt Priority Registers 8. This register allows assigning a priority 0
to each interrupt. This register contains the 3-bit priority fields for
interrupts 32 to 35.
Table 22
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
Table 3.
Register overview: NVIC (base address 0xE000 E000) …continued
Name
Access Address Description
offset
Reset
value
IPR9
R/W
0x424
Interrupt Priority Registers 9. This register allows assigning a priority 0
to each interrupt. This register contains the 3-bit priority fields for
interrupts 36 to 39.
Table 23
IPR10
R/W
0x428
Interrupt Priority Registers 10. This register allows assigning a priority 0
to each interrupt. This register contains the 3-bit priority fields for
interrupts 40 to 43.
Table 24
IPR11
R/W
0x42C
Interrupt Priority Registers 11. This register allows assigning a priority 0
to each interrupt. This register contains the 3-bit priority fields for
interrupts 44 to 46.
Table 25
STIR
W
0xF00
Software Trigger Interrupt Register. This register allows software to
generate an interrupt.
Table 26
0
Reference
2.4.1 Interrupt Set Enable Register 0 register
The ISER0 register allows to enable peripheral interrupts or to read the enabled state of
those interrupts. Disable interrupts through the ICER0.
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 enables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Table 4.
UM10736
User manual
Interrupt Set Enable Register 0 register (ISER0, address 0xE000 E100) bit
description
Bit
Symbol
Description
Reset value
0
ISE_WDT
Interrupt enable.
0
1
ISE_BOD
Interrupt enable.
0
2
ISE_FLASH
Interrupt enable.
0
3
ISE_EE
Interrupt enable.
0
4
ISE_DMA
Interrupt enable.
0
5
ISE_GINT0
Interrupt enable.
0
6
ISE_GINT1
Interrupt enable.
0
7
ISE_PIN_INT0
Interrupt enable.
0
8
ISE_PIN_INT1
Interrupt enable.
0
9
ISE_PIN_INT2
Interrupt enable.
0
10
ISE_PIN_INT3
Interrupt enable.
0
11
ISE_PIN_INT4
Interrupt enable.
0
12
ISE_PIN_INT5
Interrupt enable.
0
13
ISE_PIN_INT6
Interrupt enable.
0
14
ISE_PIN_INT7
Interrupt enable.
0
15
ISE_RIT
Interrupt enable.
0
16
ISE_SCT0
Interrupt enable.
0
17
ISE_SCT1
Interrupt enable.
0
18
ISE_SCT2
Interrupt enable.
0
19
ISE_SCT3
Interrupt enable.
0
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
Table 4.
Interrupt Set Enable Register 0 register (ISER0, address 0xE000 E100) bit
description …continued
Bit
Symbol
Description
Reset value
20
ISE_MRT
Interrupt enable.
0
21
ISE_UART0
Interrupt enable.
0
22
ISE_UART1
Interrupt enable.
0
23
ISE_UART2
Interrupt enable.
0
24
ISE_I2C0
Interrupt enable.
0
25
ISE_SPI0
Interrupt enable.
0
26
ISE_SPI1
Interrupt enable.
0
27
ISE_CCAN0
Interrupt enable.
0
28
ISE_USB
Interrupt enable.
0
29
ISE_USB_FIQ
Interrupt enable.
0
30
ISE_USB_WAKEKUP
Interrupt enable.
0
31
ISE_ADC0_SEQA
Interrupt enable.
0
2.4.2 Interrupt Set Enable Register 1 register
The ISER1 register allows to enable peripheral interrupts or to read the enabled state of
those interrupts. Disable interrupts through the ICER1.
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 enables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Table 5.
UM10736
User manual
Interrupt Set Enable Register 1 register (ISER1, address 0xE000 E104) bit
description
Bit
Symbol
Description
Reset value
0
ISE_ADC0_SEQB
Interrupt enable.
0
1
ISE_ADC0_THCMP
Interrupt enable.
0
2
ISE_ADC0_OVR
Interrupt enable.
0
3
ISE_ADC1_SEQA
Interrupt enable.
0
4
ISE_ADC1_SEQB
Interrupt enable.
0
5
ISE_ADC1_THCMP
Interrupt enable.
0
6
ISE_ADC1_OVR
Interrupt enable.
0
7
ISE_DAC
Interrupt enable.
0
8
ISE_ACMP0
Interrupt enable.
0
9
ISE_ACMP1
Interrupt enable.
0
10
ISE_ACMP2
Interrupt enable.
0
11
ISE_ACMP3
Interrupt enable.
0
12
ISE_QEI
Interrupt enable.
0
13
ISE_RTC_ALARM
Interrupt enable.
0
14
ISE_RTC_WAKE
Interrupt enable.
0
31:15
-
Reserved
0
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
2.4.3 Interrupt clear enable register 0
The ICER0 register allows disabling the peripheral interrupts, or for reading the enabled
state of those interrupts. Enable interrupts through the ISER0 register.
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 disables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Table 6.
UM10736
User manual
Interrupt clear enable register 0 (ICER0, address 0xE000 E180)
Bit
Symbol
Description
Reset value
0
ICE_WDT
Interrupt disable.
0
1
ICE_BOD
Interrupt disable.
0
2
ICE_FLASH
Interrupt disable.
0
3
ICE_EE
Interrupt disable.
0
4
ICE_DMA
Interrupt disable.
0
5
ICE_GINT0
Interrupt disable.
0
6
ICE_GINT1
Interrupt disable.
0
7
ICE_PIN_INT0
Interrupt disable.
0
8
ICE_PIN_INT1
Interrupt disable.
0
9
ICE_PIN_INT2
Interrupt disable.
0
10
ICE_PIN_INT3
Interrupt disable.
0
11
ICE_PIN_INT4
Interrupt disable.
0
12
ICE_PIN_INT5
Interrupt disable.
0
13
ICE_PIN_INT6
Interrupt disable.
0
14
ICE_PIN_INT7
Interrupt disable.
0
15
ICE_RIT
Interrupt disable.
0
16
ICE_SCT0
Interrupt disable.
0
17
ICE_SCT1
Interrupt disable.
0
18
ICE_SCT2
Interrupt disable.
0
19
ICE_SCT3
Interrupt disable.
0
20
ICE_MRT
Interrupt disable.
0
21
ICE_UART0
Interrupt disable.
0
22
ICE_UART1
Interrupt disable.
0
23
ICE_UART2
Interrupt disable.
0
24
ICE_I2C0
Interrupt disable.
0
25
ICE_SPI0
Interrupt disable.
0
26
ICE_SPI1
Interrupt disable.
0
27
ICE_CCAN0
Interrupt disable.
0
28
ICE_USB
Interrupt disable.
0
29
ICE_USB_FIQ
Interrupt disable.
0
30
ICE_USB_WAKEKUP
Interrupt disable.
0
31
ICE_ADC0_SEQA
Interrupt disable.
0
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
2.4.4 Interrupt clear enable register 1
The ICER1 register allows disabling the peripheral interrupts, or for reading the enabled
state of those interrupts. Enable interrupts through the ISER1 register.
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 disables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Table 7.
Interrupt clear enable register1 (ICER1, address 0xE000 E184)
Bit
Symbol
Description
Reset value
0
ICE_ADC0_SEQB
Interrupt disable.
0
1
ICE_ADC0_THCMP
Interrupt disable.
0
2
ICE_ADC0_OVR
Interrupt disable.
0
3
ICE_ADC1_SEQA
Interrupt disable.
0
4
ICE_ADC1_SEQB
Interrupt disable.
0
5
ICE_ADC1_THCMP
Interrupt disable.
0
6
ICE_ADC1_OVR
Interrupt disable.
0
7
ICE_DAC
Interrupt disable.
0
8
ICE_ACMP0
Interrupt disable.
0
9
ICE_ACMP1
Interrupt disable.
0
10
ICE_ACMP2
Interrupt disable.
0
11
ICE_ACMP3
Interrupt disable.
0
12
ICE_QEI
Interrupt disable.
0
13
ICE_RTC_ALARM
Interrupt disable.
0
14
ICE_RTC_WAKE
Interrupt disable.
0
31:15
-
Reserved
0
2.4.5 Interrupt Set Pending Register 0 register
The ISPR0 register allows setting the pending state of the peripheral interrupts, or for
reading the pending state of those interrupts. Clear the pending state of interrupts through
the ICPR0 registers.
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 changes the interrupt state to pending.
Read — 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is
pending.
Table 8.
UM10736
User manual
Interrupt set pending register 0 register (ISPR0, address 0xE000 E200) bit
description
Bit
Symbol
Description
Reset value
0
ISP_WDT
Interrupt pending set.
0
1
ISP_BOD
Interrupt pending set.
0
2
ISP_FLASH
Interrupt pending set.
0
3
ISP_EE
Interrupt pending set.
0
4
ISP_DMA
Interrupt pending set.
0
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
Table 8.
Interrupt set pending register 0 register (ISPR0, address 0xE000 E200) bit
description …continued
Bit
Symbol
Description
Reset value
5
ISP_GINT0
Interrupt pending set.
0
6
ISP_GINT1
Interrupt pending set.
0
7
ISP_PIN_INT0
Interrupt pending set.
0
8
ISP_PIN_INT1
Interrupt pending set.
0
9
ISP_PIN_INT2
Interrupt pending set.
0
10
ISP_PIN_INT3
Interrupt pending set.
0
11
ISP_PIN_INT4
Interrupt pending set.
0
12
ISP_PIN_INT5
Interrupt pending set.
0
13
ISP_PIN_INT6
Interrupt pending set.
0
14
ISP_PIN_INT7
Interrupt pending set.
0
15
ISP_RIT
Interrupt pending set.
0
16
ISP_SCT0
Interrupt pending set.
0
17
ISP_SCT1
Interrupt pending set.
0
18
ISP_SCT2
Interrupt pending set.
0
19
ISP_SCT3
Interrupt pending set.
0
20
ISP_MRT
Interrupt pending set.
0
21
ISP_UART0
Interrupt pending set.
0
22
ISP_UART1
Interrupt pending set.
0
23
ISP_UART2
Interrupt pending set.
0
24
ISP_I2C0
Interrupt pending set.
0
25
ISP_SPI0
Interrupt pending set.
0
26
ISP_SPI1
Interrupt pending set.
0
27
ISP_CCAN0
Interrupt pending set.
0
28
ISP_USB
Interrupt pending set.
0
29
ISP_USB_FIQ
Interrupt pending set.
0
30
ISP_USB_WAKEKUP
Interrupt pending set.
0
31
ISP_ADC0_SEQA
Interrupt pending set.
0
2.4.6 Interrupt Set Pending Register 1 register
The ISPR1 register allows setting the pending state of the peripheral interrupts, or for
reading the pending state of those interrupts. Clear the pending state of interrupts through
the ICPR1 registers.
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 changes the interrupt state to pending.
Read — 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is
pending.
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
Table 9.
Interrupt set pending register 1 register (ISPR1, address 0xE000 E204) bit
description
Bit
Symbol
Description
Reset value
0
ISP_ADC0_SEQB
Interrupt pending set.
0
1
ISP_ADC0_THCMP
Interrupt pending set.
0
2
ISP_ADC0_OVR
Interrupt pending set.
0
3
ISP_ADC1_SEQA
Interrupt pending set.
0
4
ISP_ADC1_SEQB
Interrupt pending set.
0
5
ISP_ADC1_THCMP
Interrupt pending set.
0
6
ISP_ADC1_OVR
Interrupt pending set.
0
7
ISP_DAC
Interrupt pending set.
0
8
ISP_ACMP0
Interrupt pending set.
0
9
ISP_ACMP1
Interrupt pending set.
0
10
ISP_ACMP2
Interrupt pending set.
0
11
ISP_ACMP3
Interrupt pending set.
0
12
ISP_QEI
Interrupt pending set.
0
13
ISP_RTC_ALARM
Interrupt pending set.
0
14
ISP_RTC_WAKE
Interrupt pending set.
0
31:15
-
Reserved
0
2.4.7 Interrupt Clear Pending Register 0 register
The ICPR0 register allows clearing the pending state of the peripheral interrupts, or for
reading the pending state of those interrupts. Set the pending state of interrupts through
the ISPR0 register.
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read — 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is
pending.
Table 10.
UM10736
User manual
Interrupt clear pending register 0 register (ICPR0, address 0xE000 E280) bit
description
Bit
Symbol
Function
Reset value
0
ICP_WDT
Interrupt pending clear.
0
1
ICP_BOD
Interrupt pending clear.
0
2
ICP_FLASH
Interrupt pending clear.
0
3
ICP_EE
Interrupt pending clear.
0
4
ICP_DMA
Interrupt pending clear.
0
5
ICP_GINT0
Interrupt pending clear.
0
6
ICP_GINT1
Interrupt pending clear.
0
7
ICP_PIN_INT0
Interrupt pending clear.
0
8
ICP_PIN_INT1
Interrupt pending clear.
0
9
ICP_PIN_INT2
Interrupt pending clear.
0
10
ICP_PIN_INT3
Interrupt pending clear.
0
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
Table 10.
Interrupt clear pending register 0 register (ICPR0, address 0xE000 E280) bit
description …continued
Bit
Symbol
Function
Reset value
11
ICP_PIN_INT4
Interrupt pending clear.
0
12
ICP_PIN_INT5
Interrupt pending clear.
0
13
ICP_PIN_INT6
Interrupt pending clear.
0
14
ICP_PIN_INT7
Interrupt pending clear.
0
15
ICP_RIT
Interrupt pending clear.
0
16
ICP_SCT0
Interrupt pending clear.
0
17
ICP_SCT1
Interrupt pending clear.
0
18
ICP_SCT2
Interrupt pending clear.
0
19
ICP_SCT3
Interrupt pending clear.
0
20
ICP_MRT
Interrupt pending clear.
0
21
ICP_UART0
Interrupt pending clear.
0
22
ICP_UART1
Interrupt pending clear.
0
23
ICP_UART2
Interrupt pending clear.
0
24
ICP_I2C0
Interrupt pending clear.
0
25
ICP_SPI0
Interrupt pending clear.
0
26
ICP_SPI1
Interrupt pending clear.
0
27
ICP_CCAN0
Interrupt pending clear.
0
28
ICP_USB
Interrupt pending clear.
0
29
ICP_USB_FIQ
Interrupt pending clear.
0
30
ICP_USB_WAKEKUP
Interrupt pending clear.
0
31
ICP_ADC0_SEQA
Interrupt pending clear.
0
2.4.8 Interrupt Clear Pending Register 1 register
The ICPR1 register allows clearing the pending state of the peripheral interrupts, or for
reading the pending state of those interrupts. Set the pending state of interrupts through
the ISPR1 register.
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read — 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is
pending.
Table 11.
Bit
UM10736
User manual
Interrupt clear pending register 1 register (ICPR1, address 0xE000 E284) bit
description
Symbol
Function
0
ICP_ADC0_SEQB
Interrupt pending clear.
0
1
ICP_ADC0_THCMP
Interrupt pending clear.
0
2
ICP_ADC0_OVR
Interrupt pending clear.
0
3
ICP_ADC1_SEQA
Interrupt pending clear.
0
4
ICP_ADC1_SEQB
Interrupt pending clear.
0
5
ICP_ADC1_THCMP
Interrupt pending clear.
0
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
Table 11.
Interrupt clear pending register 1 register (ICPR1, address 0xE000 E284) bit
description …continued
Bit
Symbol
Function
Reset value
6
ICP_ADC1_OVR
Interrupt pending clear.
0
7
ICP_DAC
Interrupt pending clear.
0
8
ICP_ACMP0
Interrupt pending clear.
0
9
ICP_ACMP1
Interrupt pending clear.
0
10
ICP_ACMP2
Interrupt pending clear.
0
11
ICP_ACMP3
Interrupt pending clear.
0
12
ICP_QEI
Interrupt pending clear.
0
13
ICP_RTC_ALARM
Interrupt pending clear.
0
14
ICP_RTC_WAKE
Interrupt pending clear.
0
31:15
-
Reserved
0
2.4.9 Interrupt Active Bit Register 0
The IABR0 register is a read-only register that allows reading the active state of the
peripheral interrupts. Use this register to determine which peripherals are asserting an
interrupt to the NVIC and may also be pending if there are enabled.
The bit description is as follows for all bits in this register:
Write — n/a.
Read — 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
Table 12.
UM10736
User manual
Interrupt Active Bit Register 0 (IABR0, address 0xE000 E300) bit description
Bit
Symbol
Function
Reset value
0
IAB_WDT
Interrupt active state.
0
1
IAB_BOD
Interrupt active state.
0
2
IAB_FLASH
Interrupt active state.
0
3
IAB_EE
Interrupt active state.
0
4
IAB_DMA
Interrupt active state.
0
5
IAB_GINT0
Interrupt active state.
0
6
IAB_GINT1
Interrupt active state.
0
7
IAB_PIN_INT0
Interrupt active state.
0
8
IAB_PIN_INT1
Interrupt active state.
0
9
IAB_PIN_INT2
Interrupt active state.
0
10
IAB_PIN_INT3
Interrupt active state.
0
11
IAB_PIN_INT4
Interrupt active state.
0
12
IAB_PIN_INT5
Interrupt active state.
0
13
IAB_PIN_INT6
Interrupt active state.
0
14
IAB_PIN_INT7
Interrupt active state.
0
15
IAB_RIT
Interrupt active state.
0
16
IAB_SCT0
Interrupt active state.
0
17
IAB_SCT1
Interrupt active state.
0
18
IAB_SCT2
Interrupt active state.
0
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
Table 12.
Interrupt Active Bit Register 0 (IABR0, address 0xE000 E300) bit description
Bit
Symbol
Function
Reset value
19
IAB_SCT3
Interrupt active state.
0
20
IAB_MRT
Interrupt active state.
0
21
IAB_UART0
Interrupt active state.
0
22
IAB_UART1
Interrupt active state.
0
23
IAB_UART2
Interrupt active state.
0
24
IAB_I2C0
Interrupt active state.
0
25
IAB_SPI0
Interrupt active state.
0
26
IAB_SPI1
Interrupt active state.
0
27
IAB_CCAN0
Interrupt active state.
0
28
IAB_USB
Interrupt active state.
0
29
IAB_USB_FIQ
Interrupt active state.
0
30
IAB_USB_WAKEKUP
Interrupt active state.
0
31
IAB_ADC0_SEQA
Interrupt active state.
0
2.4.10 Interrupt Active Bit Register 1
The IABR1 register is a read-only register that allows reading the active state of the
peripheral interrupts. Use this register to determine which peripherals are asserting an
interrupt to the NVIC and may also be pending if there are enabled.
The bit description is as follows for all bits in this register:
Write — n/a.
Read — 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
Table 13.
UM10736
User manual
Interrupt Active Bit Register 1 (IABR1, address 0xE000 E304) bit description
Bit
Symbol
Function
Reset value
0
IAB_ADC0_SEQB
Interrupt active state.
0
1
IAB_ADC0_THCMP
Interrupt active state.
0
2
IAB_ADC0_OVR
Interrupt active state.
0
3
IAB_ADC1_SEQA
Interrupt active state.
0
4
IAB_ADC1_SEQB
Interrupt active state.
0
5
IAB_ADC1_THCMP
Interrupt active state.
0
6
IAB_ADC1_OVR
Interrupt active state.
0
7
IAB_DAC
Interrupt active state.
0
8
IAB_ACMP0
Interrupt active state.
0
9
IAB_ACMP1
Interrupt active state.
0
10
IAB_ACMP2
Interrupt active state.
0
11
IAB_ACMP3
Interrupt active state.
0
12
IAB_QEI
Interrupt active state.
0
13
IAB_RTC_ALARM
Interrupt active state.
0
14
IAB_RTC_WAKE
Interrupt active state.
0
31:15
-
Reserved
0
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
2.4.11 Interrupt Priority Register 0
The IPR0 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 14.
Interrupt Priority Register 0 (IPR0, address 0xE000 E400) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_WDT
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_BOD
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
20:16 -
These bits ignore writes, and read as 0.
0
23:21 IP_FLASH
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
28:24 -
These bits ignore writes, and read as 0.
0
31:29 IP_EE
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
2.4.12 Interrupt Priority Register 1
The IPR0 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 15.
Interrupt Priority Register 1 (IPR1, address 0xE000 E404) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_DMA
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_GINT0
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
20:16 -
These bits ignore writes, and read as 0.
0
23:21 IP_GINT1
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
28:24 -
These bits ignore writes, and read as 0.
0
31:29 IP_PIN_INT0
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
2.4.13 Interrupt Priority Register 2
The IPR0 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 16.
UM10736
User manual
Interrupt Priority Register 2 (IPR2, address 0xE000 E408) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_PIN_INT1
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_PIN_INT2
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
20:16 -
These bits ignore writes, and read as 0.
0
23:21 IP_PIN_INT3
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
28:24 -
These bits ignore writes, and read as 0.
0
31:29 IP_PIN_INT4
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
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2.4.14 Interrupt Priority Register 3
The IPR3 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 17.
Interrupt Priority Register 3 (IPR3, address 0xE000 E40C) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_PIN_INT5
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_PIN_INT6
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
20:16 -
These bits ignore writes, and read as 0.
0
23:21 IP_PIN_INT7
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
28:24 -
These bits ignore writes, and read as 0.
0
31:29 IP_RIT
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
2.4.15 Interrupt Priority Register 4
The IPR4 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 18.
Interrupt Priority Register 4 (IPR4, address 0xE000 E410) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_SCT0
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_SCT1
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
20:16 -
These bits ignore writes, and read as 0.
23:21 IP_SCT2
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
28:24 -
These bits ignore writes, and read as 0.
31:29 IP_SCT3
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
0
0
2.4.16 Interrupt Priority Register 5
The IPR5 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 19.
UM10736
User manual
Interrupt Priority Register 5 (IPR5, address 0xE000 E414) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_MRT
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_UART0
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
20:16 -
These bits ignore writes, and read as 0.
23:21 IP_UART1
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
28:24 -
These bits ignore writes, and read as 0.
31:29 IP_UART2
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
2.4.17 Interrupt Priority Register 6
The IPR6 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 20.
Interrupt Priority Register 6 (IPR6, address 0xE000 E418) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_I2C0
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_SPI0
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
20:16 -
These bits ignore writes, and read as 0.
0
23:21 IP_SPI1
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
28:24 -
These bits ignore writes, and read as 0.
0
31:29 IP_C_CAN0
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
2.4.18 Interrupt Priority Register 7
The IPR7 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 21.
Interrupt Priority Register 7 (IPR7, address 0xE000 E41C) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_USB
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_USB_FIQ
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
20:16 -
These bits ignore writes, and read as 0.
0
23:21 IP_WAKEUP
Interrupt Priority. 0 = highest priority. 7 = lowest priority.
0
28:24 -
These bits ignore writes, and read as 0.
0
31:29 IP_ADC0_SEQA
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
2.4.19 Interrupt Priority Register 8
The IPR8 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 22.
Interrupt Priority Register 8 (IPR8, address 0xE000 E420) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_ADC0_SEQB
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_ADC0_THCMP Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
UM10736
User manual
20:16 -
These bits ignore writes, and read as 0.
23:21 IP_ADC0_OVR
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
28:24 -
These bits ignore writes, and read as 0.
31:29 IP_ADC1_SEQA
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
2.4.20 Interrupt Priority Register 9
The IPR9 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 23.
Interrupt Priority Register 9 (IPR9, address 0xE000 E424) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_ADC1_SEQB
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_ADC1_THCMP Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
20:16 -
These bits ignore writes, and read as 0.
0
23:21 IP_ADC1_OVR
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
28:24 -
These bits ignore writes, and read as 0.
31:29 IP_DAC
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
0
2.4.21 Interrupt Priority Register 10
The IPR10 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 24.
Interrupt Priority Register 10 (IPR10, address 0xE000 E428) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_ACMP0
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_ACMP1
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
20:16 -
These bits ignore writes, and read as 0.
23:21 IP_ACMP2
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
28:24 -
These bits ignore writes, and read as 0.
31:29 IP_ACMP3
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
0
0
2.4.22 Interrupt Priority Register 11
The IPR11 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.
Table 25.
UM10736
User manual
Interrupt Priority Register 11 (IPR11, address 0xE000 E42C) bit description
Bit
Symbol
Description
Reset value
4:0
-
These bits ignore writes, and read as 0.
0
7:5
IP_QEI
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
12:8
-
These bits ignore writes, and read as 0.
0
15:13 IP_RTC_ALARM
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
20:16 -
These bits ignore writes, and read as 0.
23:21 IP_RTC_WAKE
Interrupt Priority. 0 = highest priority. 7 = lowest priority. 0
28:24 -
These bits ignore writes, and read as 0.
0
31:29 -
Reserved
0
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Chapter 2: LPC15xx Nested Vectored Interrupt Controller (NVIC)
2.4.23 Software Trigger Interrupt Register
The STIR register provides an alternate way for software to generate an interrupt, in
addition to using the ISPR registers. This mechanism can only be used to generate
peripheral interrupts, not system exceptions.
By default, only privileged software can write to the STIR register. Unprivileged software
can be given this ability if privileged software sets the USERSETMPEND bit in the ARM
Cortex-M3 CCR register.
The interrupt number to be programmed in this register is listed in Table 2.
Table 26.
UM10736
User manual
Software Trigger Interrupt Register (STIR, address 0xE000 EF00) bit description
Bit
Symbol
Description
8:0
INTID
Writing a value to this field generates an interrupt for the specified the
interrupt number. The range allowed for this part is 0 to 46.
31:9
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
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Chapter 3: LPC15xx System configuration (SYSCON)
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User manual
3.1 How to read this chapter
USB and USB PLL related registers are available only on parts LPC1549/48/47.
3.2 Features
•
•
•
•
•
•
•
•
System and bus configuration.
Clock select and control.
Reset control.
Wake-up control.
BOD configuration.
High-accuracy frequency measurement function for on-chip and off-chip clocks.
Uses a selection of on-chip clocks as reference clock.
Device ID register.
3.3 Basic configuration
Configure the SYSCON block as follows:
• The SYSCON uses the CLKOUT, RESET pins which can be configured through the
switch matrix. See Section 3.4. RESET is enabled by default.
• No clock configuration is needed. The clock to the SYSCON block is always enabled.
By default, the SYSCON block is clocked by the IRC.
• Target and reference clocks for the frequency measurement function are selected in
the input mux block. See Table 134.
3.3.1 Set up the PLL
The PLL creates a stable output clock at a higher frequency than the input clock. If you
need a main clock with a frequency higher than the 12 MHz IRC clock, use the PLL to
boost the input frequency.
1. Power up the system PLL in the PDRUNCFG register.
Section 3.6.47 “Power configuration register”
2. Select the PLL input in the SYSPLLCLKSEL register. You have the following input
options:
– IRC: 12 MHz internal oscillator.
– System oscillator: External crystal oscillator using the XTALIN/XTALOUT pins.
Section 3.6.18 “System PLL clock source select register”
3. Configure the PLL M and N dividers.
Section 3.6.40 “System PLL control register”
4. Wait for the PLL to lock by monitoring the PLL lock status.
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Chapter 3: LPC15xx System configuration (SYSCON)
Section 3.6.41 “System PLL status register”
3.3.2 Configure the main clock and system clock
The clock source for the registers and memories is derived from main clock. The main
clock can be sourced from the IRC at a fixed clock frequency of 12 MHz or from the PLL.
The divided main clock is called the system clock and clocks the core, the memories, and
the peripherals (register interfaces and peripheral clocks).
1. Select the main clock. You have the following options:
– IRC: 12 MHz internal oscillator (default)
– System oscillator
– Watchdog oscillator
– The output of the system PLL
– The RTC 32 kHz oscillator
Section 3.6.12 “Main clock source select register A” and Section 3.6.13 “Main clock
source select register B”.
2. Select the divider value for the system clock. A divider value of 0 disables the system
clock.
Section 3.6.21 “System clock divider register”
3. Select the memories and peripherals that are operating in your application and
therefore must have an active clock. The core is always clocked.
Section 3.6.22 “System clock control register 0” and Section 3.6.23 “System clock
control register 1”.
3.3.3 Set up the system oscillator using XTALIN and XTALOUT
To use the system oscillator, follow these steps:
1. Connect the XTALIN and XTALOUT pins to an external crystal.
2. In the SYSOSCCTRL register, disable the BYPASS bit and select the oscillator
frequency range according to the desired oscillator output clock. See Table 66
“System oscillator control register (SYSOSCCTRL, address 0x4007 4188) bit
description”.
3.3.4 Measure the frequency of a clock signal
The frequency of any on-chip or off-chip clock signal can be measured accurately with a
selectable reference clock. For example, the frequency measurement function can be
used to accurately determine the frequency of the watchdog oscillator which varies over a
wide range depending on process and temperature.
The clock frequency to be measured and the reference clock are selected in the input mux
block. See Table 134 “Frequency measure function frequency clock select register
(FREQMEAS_REF, address 0x4001 4160) bit description” and Table 135 “Frequency
measure function target clock select register (FREQMEAS_TARGET, address
0x4001 4164) bit description”.
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Chapter 3: LPC15xx System configuration (SYSCON)
Details on the accuracy and measurement process are described in Section 3.7.5
“Frequency measure function”.
To start a frequency measurement cycle and read the result, see Table 59 “Frequency
measure function control register (FREQMECTRL, address 0x4007 4120) bit description”.
3.4 Pin description
Table 27.
SYSCON pin description
Function
Direction Pin
Description
SWM register
Reference
CLKOUT
O
any
CLKOUT clock output.
PINASSIGN13
Table 120
XTALIN
I
XTALIN
Input to the system oscillator.
n/a
-
XTALOUT
Output from the system oscillator.
n/a
-
RESET/PIO0_21
External reset input
PINENABLE1
Table 124
XTALOUT O
RESET
I
3.5 General description
3.5.1 Clock generation
The system control block facilitates the clock generation. Except for the peripheral clocks
(SYSTICK clock, fractional baud rate generator clock, glitch filter clock, ARM trace clock),
the clocks to the core and peripherals run at the same frequency. The maximum clock
frequency is 72 MHz. See Figure 3.
The low-power watchdog oscillator provides a fixed 503 kHz clock. The accuracy of this
clock is limited to +/- 40 % over temperature and processing. To determine the actual
watchdog oscillator output, use the frequency measure block. See Section 3.3.4.
The part contains three identical PLLs. The system PLL produces the clock for the core
and peripherals. Two additional PLLs can create independent clocks for the USB and the
SCT. The output of all three PLLs can be monitored through the CLKOUT pin.
You can select the output of any of the three PLLs to derive an asynchronous ADC
sampling clock. See also Section 28.3.
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Chapter 3: LPC15xx System configuration (SYSCON)
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Fig 3.
Clock generation
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Chapter 3: LPC15xx System configuration (SYSCON)
3.6 Register description
All system control block registers reside on word address boundaries. Details of the
registers appear in the description of each function.
All address offsets not shown in Table 28 are reserved and should not be written to. The
reset value after boot shows the reset value seen when the boot loader executes but does
not enter ISP mode, that is the flash contains valid user code.
Table 28.
Register overview: System configuration (base address 0x4007 4000)
Name
Access
Offset
Description
Reset
value
Reset
Reference
value
after boot
SYSMEMREMAP
R/W
0x000
System memory remap
0x0
0x2
Table 29
-
-
0x004
Reserved
-
-
-
-
-
-
-
-
0x008
Reserved
AHBBUFEN0
R/W
0x00C
AHB-to-APB bridge 0 write buffering
control
AHBBUFEN1
R/W
0x010
AHB-to-APB bridge 1 write buffering
control
SYSTCKCAL
R/W
0x014
System tick counter calibration
0x0
0x0
Table 32
-
R/W
0x018
Reserved
-
-
-
NMISRC
R/W
0x01C
NMI Source Control
0x0
0x0
Table 33
-
-
0x020 0x03C
Reserved
-
-
-
SYSRSTSTAT
R/W
0x040
System reset status register
0x0
0x0
Table 34
PRESETCTRL0
R/W
0x044
Peripheral reset control 0
0x0
0x0
Table 35
0x0
Table 36
PRESETCTRL1
R/W
0x048
Peripheral reset control 1
0x0
PIOPORCAP0
R
0x04C
POR captured PIO status 0
user
user
Table 37
dependent dependent
PIOPORCAP1
R
0x050
POR captured PIO status 1
user
user
Table 38
dependent dependent
PIOPORCAP2
R
0x054
POR captured PIO status 2
user
user
Table 39
dependent dependent
-
-
0x058 0x07C
Reserved
-
-
-
MAINCLKSELA
R/W
0x080
Main clock source select A
0x0
0x0
Table 40
MAINCLKSELB
R/W
0x084
Main clock source select B
0x0
0x0
Table 41
USBCLKSEL
R/W
0x088
USB clock source select
0x0
0x0
Table 42
ADCASYNCCLKSEL
R/W
0x08C
ADC asynchronous clock source
select
0x0
0x0
Table 43
-
R/W
0x090
Reserved
-
-
-
CLKOUTSELA
R/W
0x094
CLKOUT clock source select A
0x0
0x0
Table 44
CLKOUTSELB
R/W
0x098
CLKOUT clock source select B
0x0
0x0
Table 45
-
R/W
0x09C
Reserved
-
-
-
SYSPLLCLKSEL
R/W
0x0A0
System PLL clock source select
0x0
0x0
Table 46
USBPLLCLKSEL
R/W
0x0A4
USB PLL clock source select
0x0
0x0
Table 47
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 28.
Register overview: System configuration (base address 0x4007 4000) …continued
Name
Access
Offset
Description
Reset
value
Reset
Reference
value
after boot
SCTPLLCLKSEL
R/W
0x0A8
SCT PLL clock source select
0x0
0x0
Table 48
-
-
0x0AC 0x0BC
Reserved
-
-
-
SYSAHBCLKDIV
R/W
0x0C0
System clock divider
0x1
0x1
Table 49
SYSAHBCLKCTRL0
R/W
0x0C4
System clock control 0
0x1
0x19B
Table 50
SYSAHBCLKCTRL1
R/W
0x0C8
System clock control 1
0x0
0x0
Table 51
SYSTICKCLKDIV
R/W
0x0CC
SYSTICK clock divider
0x0
0x0
Table 52
UARTCLKDIV
R/W
0x0D0
USART clock divider. Clock divider
for the USART fractional baud rate
generator.
0x0
0x0
Table 53
IOCONCLKDIV
R/W
0x0D4
Peripheral clock to the IOCON block
for programmable glitch filter
0x0
0x0
Table 54
TRACECLKDIV
R/W
0x0D8
ARM trace clock divider
0x0
0x0
Table 55
-
-
0x0DC 0x0E8
Reserved
-
-
-
USBCLKDIV
R/W
0x0EC
USB clock divider
0x0
0x0
Table 56
ADCASYNCCLKDIV
R/W
0x0F0
Asynchronous ADC clock divider
0x0
0x0
Table 57
-
-
0x0F4
Reserved
-
-
-
CLKOUTDIV
R/W
0x0F8
CLKOUT clock divider
0x0
0x0
Table 58
-
-
0x0FC 0x11C
Reserved
-
-
-
FREQMECTRL
R/W
0x120
Frequency measure register
0x0
0x0
Table 59
FLASHCFG
R/W
0x124
Flash waitstates configuration
register
-
0x201A
Table 60
FRGCTRL
R/W
0x128
USART fractional baud rate
generator control
0xFF
0xFF
Table 61
USBCLKCTRL
R/W
0x12C
USB clock control
0x0
0x0
Table 62
USBCLKST
R/W
0x130
USB clock status
0x1
0x1
Table 63
-
-
0x134 0x17C
Reserved
BODCTRL
R/W
0x180
Brown-Out Detect
0x0
0x0
Table 64
IRCCTRL
R/W
0x184
IRC trim value
part
part
Table 65
dependent dependent
SYSOSCCTRL
R/W
0x188
System oscillator control
0x0
0x0
Table 66
-
-
0x18C
Reserved
-
-
-
0x190
RTC oscillator 32 kHz output control
0x1
0x1
Table 67
RTCOSCCTRL
-
-
0x194
Reserved
-
-
-
SYSPLLCTRL
R/W
0x198
System PLL control
0x0
0x0
Table 68
SYSPLLSTAT
R
0x19C
System PLL status
0x0
0x0
Table 69
USBPLLCTRL
R/W
0x1A0
USB PLL control
0x0
0x0
Table 70
USBPLLSTAT
R
0x1A4
USB PLL status
0x0
0x0
Table 71
SCTPLLCTRL
R/W
0x1A8
SCT PLL control
0x0
0x0
Table 72
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 28.
Register overview: System configuration (base address 0x4007 4000) …continued
Name
Access
Offset
Description
Reset
value
Reset
Reference
value
after boot
SCTPLLSTAT
R
0x1AC
SCT PLL status
0x0
0x0
Table 73
-
-
0x1B0 0x1FC
Reserved
-
-
-
-
-
0x200
Reserved
-
-
-
PDAWAKECFG
R/W
0x204
Power-down states for wake-up from 0xFFFF
deep-sleep
FF00
0xFFFF
FE00
Table 74
PDRUNCFG
R/W
0x208
Power configuration register
0xFFFF
FF00
0xFFFF
FE00
Table 75
-
-
0x20C 0x214
-
-
-
-
STARTERP0
R/W
0x218
Start logic 0 wake-up enable register 0x0
0x0
Table 76
STARTERP1
R/W
0x21C
Start logic 1 wake-up enable register 0x0
0x0
Table 77
-
-
0x220 0x3F0
Reserved
-
-
-
JTAG_IDCODE
R
0x3F4
JTAG ID code register
0x1906
C02B
0x19D6
C02B
Table 78
DEVICE_ID0
R
0x3F8
Part ID register
part
part
Table 79
dependent dependent
DEVICE_ID1
R
0x3FC
Boot ROM and die revision register
0x0841
9D6C
0x0841
9D6C
Table 80
3.6.1 System memory remap register
The system memory remap register selects whether the exception vectors are read from
boot ROM, flash, or SRAM. By default, the flash memory is mapped to address 0x0000
0000. When the MAP bits in the SYSMEMREMAP register are set to 0x0 or 0x1, the boot
ROM or RAM respectively are mapped to the bottom 512 bytes of the memory map
(addresses 0x0000 0000 to 0x0000 0200).
If the flash contains valid user code, the boot loader sets the MAP bits to 0x2. In ISP
mode, the MAP bits are set to 0x0.
Table 29.
Bit
Symbol
1:0
MAP
31:2
UM10736
User manual
System memory remap register (SYSMEMREMAP, address 0x4007 4000) bit
description
-
Value
Description
Reset
value
System memory remap. Value 0x3 is reserved.
0x2
0x0
Boot Loader Mode. Interrupt vectors are re-mapped to Boot
ROM.
0x1
User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
0x2
User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
-
Reserved
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Chapter 3: LPC15xx System configuration (SYSCON)
3.6.2 AHB-to-APB bridge 0 write buffering control register
This register controls the buffering of write transactions between the AHB and each APB
peripheral individually across the AHB-to-APB bridge 0.
When write buffering is disabled, it takes four cycles on the AHB to finish a write
transaction from the AHB side to the APB peripheral as three waitstates are inserted in
each transaction.
When the write buffering is enabled, the following two situations can occur:
1. If there is no outstanding transaction on the bus bridge, a write transaction from the
AHB master finishes in one cycle (no waitstates are inserted). The write data is
queued in the bridge’s buffer register, and the bridge continues to handle the write
transaction to the APB peripheral while the AHB is ready to take another transaction
(read or write).
2. If there is an outstanding transaction from a previous read or write by any of the AHB
masters, a write from the AHB is held by inserting waitstates until the write buffer is
available for the latest request.
Remark: Buffering is available for write transactions only. Read transactions between the
APB and the AHB always take four cycles regardless of the buffer setting.
Table 30.
AHB-to-APB bridge 0 write buffering control register (AHBBUFEN0, address
0x4007 400C) bit description
Bit
Symbol
0
ADC0_BUF
1
2
Value
Description
Reset
value
ADC AHB-APB write buffering
0
0
Disabled.
1
Enabled.
DAC_BUF
DAC AHB-APB write buffering
0
Disabled.
1
Enabled.
ACMP_BUF
ACMP AHB-APB write buffering
0
1
Disabled.
Enabled.
-
Reserved.
0
5
INPUTMUX_BUF
INPUT MUX AHB-APB write buffering
0
1
Disabled.
Enabled.
9:6
-
Reserved.
0
10
RTC_BUF
RTC AHB-APB write buffering
0
11
13:12
User manual
0
4:3
0
UM10736
0
0
Disabled.
1
Enabled.
WWDT_BUF
-
WWDT AHB-APB write buffering
0
Disabled.
1
Enabled.
Reserved.
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 30.
AHB-to-APB bridge 0 write buffering control register (AHBBUFEN0, address
0x4007 400C) bit description
Bit
Symbol
14
SWM_BUF
15
16
17
18
19
20
Value
Description
Reset
value
SWM AHB-APB write buffering
0
0
Disabled.
1
Enabled.
PMU_BUF
PMU AHB-APB write buffering
0
Disabled.
1
Enabled.
UART0_BUF
0
USART0 AHB-APB write buffering
0
Disabled.
1
Enabled.
UART1_BUF
0
USART1 AHB-APB write buffering
0
Disabled.
1
Enabled.
0
Disabled.
1
Enabled.
SPI0_BUF
0
SPI0 AHB-APB write buffering
SPI1_BUF
0
SPI1 AHB-APB write buffering
0
Disabled.
1
Enabled.
I2C0_BUF
0
I2C0 AHB-APB write buffering
0
Disabled.
1
Enabled.
0
21
-
Reserved.
0
22
QEI_BUF
QEI AHB-APB write buffering
0
0
Disabled.
1
Enabled.
28:23
-
Reserved.
0
29
SYSCON_BUF
SYSCON AHB-APB write buffering
0
31:30
-
0
Disabled.
1
Enabled.
Reserved.
0
3.6.3 AHB-to-APB bridge 1 write buffering control register
This register controls the buffering of write transactions between the AHB and each APB
peripheral individually across the AHB-to-APB bridge 1.
When write buffering is disabled, it takes four cycles on the AHB to finish a write
transaction from the AHB side to the APB peripheral as three waitstates are inserted in
each transaction.
When the write buffering is enabled, the following two situations can occur:
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Chapter 3: LPC15xx System configuration (SYSCON)
1. If there is no outstanding transaction on the bus bridge, a write transaction from the
AHB master finishes in one cycle (no waitstates are inserted). The write data is
queued in the bridge’s buffer register, and the bridge continues to handle the write
transaction to the APB peripheral while the AHB is ready to take another transaction
(read or write).
2. If there is an outstanding transaction from a previous read or write by any of the AHB
masters, a write from the AHB is held by inserting waitstates until the write buffer is
available for the latest request.
Remark: Buffering is available for write transactions only. Read transactions between the
APB and the AHB always take four cycles regardless of the buffer setting.
Table 31.
Bit
Symbol
0
ADC1_BUF
Description
Reset
value
ADC1 AHB-APB write buffering
0
0
Disabled.
1
Enabled.
-
Reserved.
0
8
MRT_BUF
MRT AHB-APB write buffering
0
10
11
0
Disabled.
1
Enabled.
0
Disabled.
1
Enabled.
PINT_BUF
PINT AHB-APB write buffering
GINT0_BUF
GINT0 AHB-APB write buffering
0
Disabled.
1
Enabled.
GINT1_BUF
GINT1 AHB-APB write buffering
0
Disabled.
1
Enabled.
0
0
0
12
-
Reserved.
0
13
RIT_BUF
RIT AHB-APB write buffering
0
14
15
16
27:17
User manual
Value
7:1
9
UM10736
AHB-to-APB bridge 1 write buffering control register (AHBBUFEN1, address
0x4007 4010) bit description
0
Disabled.
1
Enabled.
SCTIPU_BUF
SCTIPU AHB-APB write buffering
0
Disabled.
1
Enabled.
0
Disabled.
1
Enabled.
FMC_BUF
FMC AHB-APB write buffering
UART2_BUF
-
USART2 AHB-APB write buffering
0
Disabled.
1
Enabled.
Reserved.
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 31.
AHB-to-APB bridge 1 write buffering control register (AHBBUFEN1, address
0x4007 4010) bit description
Bit
Symbol
28
CCAN_BUF
29
-
30
IOCON_BUF
31
Value
Description
Reset
value
C_CAN AHB-APB write buffering
0
0
Disabled.
1
Enabled.
Reserved.
0
IOCON AHB-APB write buffering
0
0
Disabled.
1
Enabled.
EEPROM_BUF
EEPROM AHB-APB write buffering
0
Disabled.
1
Enabled.
0
3.6.4 System tick counter calibration register
This register determines the value of the SYST_CALIB register. See Table 295.
Table 32.
System tick timer calibration register (SYSTCKCAL, address 0x4007 4014) bit
description
Bit
Symbol Description
25:0
CAL
31:26 -
Reset
value
System tick timer calibration value
0
Reserved
-
3.6.5 NMI source selection register
The NMI source selection register selects a peripheral interrupts as source for the NMI
interrupt of the ARM Cortex-M3 core. For a list of all peripheral interrupts and their IRQ
numbers see Table 2. For a description of the NMI functionality, see Ref. 1.
Remark: When you want to change the interrupt source for the NMI, you must first disable
the NMI source by setting bit 31 in this register to 0. Then change the source by updating
the IRQN bits and re-enable the NMI source by setting bit 31 to 1.
Table 33.
NMI source selection register (NMISRC, address 0x4007 401C) bit description
Bit
Symbol Description
Reset
value
5:0
IRQN
The IRQ number of the interrupt that acts as the Non-Maskable Interrupt 0
(NMI) if bit 31 is 1.
30:6
-
Reserved
-
31
NMIEN
Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source
selected by bits 5:0.
0
Remark: If the NMISRC register is used to select an interrupt as the source of
Non-Maskable interrupts, and the selected interrupt is enabled, one interrupt request can
result in both a Non-Maskable and a normal interrupt. This can be avoided by disabling
the normal interrupt in the NVIC.
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Chapter 3: LPC15xx System configuration (SYSCON)
3.6.6 System reset status register
If another reset signal - for example the external RESET pin - remains asserted after the
POR signal is negated, then its bit is set to detected. Write a one to clear the reset.
The reset value given in Table 34 applies to the POR reset.
Table 34.
System reset status register (SYSRSTSTAT, address 0x4007 4040) bit description
Bit
Symbol
0
POR
1
2
3
4
31:5
Value
Description
Reset
value
POR reset status
0
0
No POR detected
1
POR detected. Writing a one clears this reset.
EXTRST
External reset status.
0
0
No reset event detected.
1
Reset detected. Writing a one clears this reset.
WDT
Status of the Watchdog reset
0
0
No WDT reset detected
1
WDT reset detected. Writing a one clears this reset.
BOD
Status of the Brown-out detect reset
0
No BOD reset detected
1
BOD reset detected. Writing a one clears this reset.
0
No System reset detected
1
System reset detected. Writing a one clears this reset.
-
Reserved
SYSRST
-
0
Status of the software system reset
0
-
3.6.7 Peripheral reset control register 0
The PRESETCTRL0 register allows software to reset specific peripherals. Writing a zero
to any assigned bit in this register clears the reset and allows the specified peripheral to
operate. Writing a one asserts the reset.
Table 35.
Bit
Symbol
6:0
7
User manual
Value
Description
Reset
value
-
Reserved. Only write 0 to these bits.
0
FLASH_RST
Flash controller reset control
0
0
Clear flash reset.
1
Assert flash reset.
8
-
Reserved. Only write 0 to this bit.
-
9
EEPROM_RST
EEPROM controller reset control
0
10
UM10736
Peripheral reset control register 0 (PRESETCTRL0, address 0x4007 4044) bit
description
-
0
Clear EEPROM reset.
1
Assert EEPROM reset.
Reserved. Only write 0 to this bit.
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 35.
Peripheral reset control register 0 (PRESETCTRL0, address 0x4007 4044) bit
description
Bit
Symbol
11
MUX_RST
12
-
13
IOCON_RST
17:14
-
18
PINT_RST
19
20
Value
Description
Reset
value
Input mux reset control
0
0
Clear pin mux reset.
1
Assert pin mux reset.
0
IOCON reset control
0
0
Clear IOCON reset.
1
Assert IOCON reset.
Reserved. Only write 0 to this bit.
0
Pin interrupt (PINT) reset control
0
0
Clear PINT reset.
1
Assert PINT reset.
GINT_RST
Grouped interrupt (GINT) reset control
0
Clear GINT reset.
1
Assert GINT reset.
DMA_RST
DMA reset control
0
1
21
Reserved. Only write 0 to this bit.
CRC_RST
0
0
Clear DMA reset.
Assert DMA reset.
CRC generator reset control
0
Clear CRC reset.
1
Assert CRC reset.
0
26:22
-
Reserved. Only write 0 to these bits.
0
27
ADC0_RST
ADC0 reset control
0
28
0
Clear ADC0 reset.
1
Assert ADC0 reset.
0
Clear ADC1 reset.
1
Assert ADC1 reset.
ADC1_RST
ADC1 reset control
0
29
-
Reserved.Only write 0 to this bit.
30
ACMP_RST
Analog Comparator (ACMP) reset control for all 0
four 4 comparators in the analog comparator
block.
31
-
0
Clear ACMP reset.
1
Assert ACMP reset.
-
Reserved
0
-
3.6.8 Peripheral reset control register 1
The PRESETCTRL1 register allows software to reset specific peripherals. Writing a zero
to any assigned bit in this register clears the reset and allows the specified peripheral to
operate. Writing a one asserts the reset.
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 36.
Peripheral reset control register 1 (PRESETCTRL1, address 0x4007 4048) bit
description
Bit
Symbol
0
MRT_RST
Value
0
1
1
2
3
4
5
6
7
Assert MRT reset.
Assert RIT reset.
0
Clear SCT0 reset.
1
Assert SCT0 reset.
State configurable timer 0 (SCT0) reset control
State configurable timer 1 (SCT1) reset control
0
Clear SCT1 reset.
1
Assert SCT1 reset.
State configurable timer 2 (SCT2) reset control
0
Clear SCT2 reset.
1
Assert SCT2 reset.
State configurable timer 3 (SCT3) reset control
0
Clear SCT3 reset.
1
Assert SCT3 reset.
SCTIPU_RST
State configurable timer IPU (SCTIPU) reset
control
0
Clear SCTIPU reset.
1
Assert SCTIPU reset.
CCAN_RST
CCAN reset control
0
Clear CCAN reset.
1
Assert CCAN reset.
0
0
0
0
0
0
Reserved.Only write 0 to this bit.
0
SPI0 reset control
0
0
Clear SPI0 reset.
1
Assert SPI0 reset.
SPI1_RST
0
SPI1 reset control
0
Clear SPI1 reset.
1
Assert SPI1 reset.
0
12:11
-
Reserved.Only write 0 to these bits.
0
13
I2C0_RST
I2C0 reset control
0
16:14
User manual
Clear MRT reset.
1
SCT3_RST
SPI0_RST
0
Clear RIT reset.
SCT2_RST
9
Multi-rate timer (MRT) reset control
0
SCT1_RST
-
Reset
value
Repetitive interrupt timer (RIT) reset control
SCT0_RST
8
10
UM10736
RIT_RST
Description
-
0
Clear I2C0 reset.
1
Assert I2C0 reset.
Reserved. Only write 0 to these bits.
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Table 36.
Peripheral reset control register 1 (PRESETCTRL1, address 0x4007 4048) bit
description
Bit
Symbol
17
UART0_RST
18
Value
Reset
value
USART0 reset control
0
0
Clear USART0 reset.
1
Assert USART0 reset.
UART1_RST
19
Description
USART1 reset control
0
Clear USART1 reset.
1
Assert USART1 reset.
UART2_RST
USART2 reset control
0
Clear USART2 reset.
1
Assert USART2 reset.
0
0
20
-
Reserved. Only write 0 to these bits.
0
21
QEI_RST
QEI reset control
0
0
Clear QEI reset.
1
Assert QEI reset.
22
-
Reserved. Only write 0 to this bit.
0
23
USB_RST
USB reset control
0
27:24
0
Clear USB reset.
1
Assert USB reset.
-
28
31:29
-
Reserved. Only write 0 to these bits.
0
Reserved
0
0
Clear PVT reset.
1
Assert PVT reset.
-
Reserved. Only write 0 to these bits.
-
3.6.9 POR captured PIO status register 0
The PIOPORCAP0 register captures the state of GPIO port 0 at power-on-reset. Each bit
represents the reset state of one GPIO pin. This register is a read-only status register.
Table 37.
POR captured PIO status register 0 (PIOPORCAP0, address 0x4007 404C) bit
description
Bit
Symbol
Description
Reset value
31:0
PIOSTAT
State of PIO0_31 through PIO0_0 at power-on reset
Implementation
dependent
3.6.10 POR captured PIO status register 1
The PIOPORCAP1 register captures the state of GPIO port 1 at power-on-reset. Each bit
represents the reset state of one GPIO pin. This register is a read-only status register.
Table 38.
UM10736
User manual
POR captured PIO status register 1 (PIOPORCAP1, address 0x4007 4050) bit
description
Bit
Symbol
Description
Reset value
31:0
PIOSTAT
State of PIO1_31 through PIO1_0 at power-on reset
Implementation
dependent
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3.6.11 POR captured PIO status register 2
The PIOPORCAP2 register captures the state of GPIO port 2 at power-on-reset. Each bit
represents the reset state of one GPIO pin. This register is a read-only status register.
Table 39.
POR captured PIO status register 2 (PIOPORCAP2, address 0x4007 4054) bit
description
Bit
Symbol
Description
Reset value
11:0
PIOSTAT
State of PIO2_11 through PIO2_0 at power-on reset
Implementation
dependent
31:12
-
Reserved.
-
3.6.12 Main clock source select register A
This register selects one of the internal oscillators, IRC, system oscillator, or watchdog
oscillator. The oscillator selected is then one of the inputs to the main clock source select
register B (see Table 41), which selects the clock source for the main clock. All clocks to
the core, memories, and peripherals are derived from the main clock.
Table 40.
Main clock source select register A (MAINCLKSELA, address 0x4007 4080) bit
description
Bit
Symbol
1:0
SEL
31:2
-
Value
Description
Reset value
Clock source for main clock source selector A
0
0x0
IRC Oscillator
0x1
System oscillator
0x2
Watchdog oscillator
0x3
Reserved
-
Reserved
-
3.6.13 Main clock source select register B
This register selects the clock source for the main clock. All clocks to the core, memories,
and peripherals are derived from the main clock.
One input to this register is the main clock source select register A (see Table 40), which
selects one of the three internal oscillators, IRC, system oscillator, or watchdog oscillator.
Table 41.
Bit
Symbol
1:0
SEL
31:2
UM10736
User manual
Main clock source select register B (MAINCLKSELB, address 0x4007 4084) bit
description
-
Value
Description
Reset value
Clock source for main clock source selector B.
Selects the clock source for the main clock.
0
0x0
MAINCLKSELA. Clock source selected in
MAINCLKSELA register.
0x1
System PLL input.
0x2
System PLL output.
0x3
RTC oscillator 32 kHz output.
-
Reserved
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3.6.14 USB clock source select register
This register selects the clock source for the USB usb_clk. The clock source can be either
the USB PLL output or the main clock, and the clock can be further divided by the
USBCLKDIV register (see Table 56) to obtain a 48 MHz clock.
Table 42.
USB clock source select (USBCLKSEL, address 0x4007 4088) bit description
Bit
Symbol
1:0
SEL
31:2
Value
Description
Reset
value
USB clock source.
0x0
0x0
IRC Oscillator
0x1
System oscillator
0x2
USB PLL out
0x3
Main clock
-
Reserved
0x00
3.6.15 ADC asynchronous clock source select register
This register selects an clock source from the IRC or any of the PLL outputs for the 12-bit
ADCs that is asynchronous to the system clock. To use this clock, select the
asynchronous clock mode in the ADC control register.
Table 43.
ADC asynchronous clock source select (ADCASYNCCLKSEL, address
0x4007 408C) bit description
Bit
Symbol
1:0
SEL
31:2
Value
Description
Reset
value
ADC clock source.
0x0
0x0
IRC Oscillator
0x1
System PLL output
0x2
USB PLL output
0x3
SCT PLL output
-
Reserved
0x00
3.6.16 CLKOUT clock source select register A
This register pre-selects one of the internal oscillators for the clock sources visible on the
CLKOUT pin. The selection for the CLKOUT clock source is done in the CLKOUT clock
source B register.
Table 44.
Bit
Symbol
1:0
SEL
31:2
UM10736
User manual
CLKOUT clock source select register (CLKOUTSELA, address 0x4007 4094) bit
description
-
Value
Description
Reset
value
CLKOUT clock source
0
0x0
IRC oscillator
0x1
Crystal oscillator (SYSOSC)
0x2
Watchdog oscillator
0x3
Main clock
-
Reserved
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3.6.17 CLKOUT clock source select register B
This register selects the clock source visible on the CLKOUT pin. The internal oscillators
are pre-selected in the CLKOUTSELA register (see Table 44).
Table 45.
CLKOUT clock source select register (CLKOUTSELB, address 0x4007 4098) bit
description
Bit
Symbol
1:0
SEL
31:2
-
Value
Description
Reset
value
CLKOUT clock source
0
0x0
CLKOUTSELA. Clock source selected in the CLKOUTSELA
register.
0x1
USB PLL output.
0x2
SCT PLL output.
0x3
RTC 32 kHz output.
-
Reserved
0
3.6.18 System PLL clock source select register
This register selects the clock source for the system PLL.
Table 46.
System PLL clock source select register (SYSPLLCLKSEL, address 0x4007 40A0)
bit description
Bit
Symbol
1:0
SEL
31:2
-
Value
Description
Reset
value
System PLL clock source
0
0x0
IRC
0x1
Crystal Oscillator (SYSOSC)
0x2
Reserved.
0x3
Reserved.
-
Reserved
-
3.6.19 USB PLL clock source select register
This register selects the clock source for the dedicated USB PLL.
Table 47.
Bit
Symbol
1:0
SEL
31:2
UM10736
User manual
USB PLL clock source select (USBPLLCLKSEL, address 0x4007 40A4) bit
description
-
Value
Description
Reset
value
USB PLL clock source
0x00
0x0
IRC. The USB PLL clock source must be switched to
system oscillator for correct USB operation.
0x1
System oscillator
0x2
Reserved
0x3
Reserved
Reserved
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3.6.20 SCT PLL clock source select register
This register selects the clock source for the dedicated SCT PLL.
Table 48.
SCT PLL clock source select (SCTPLLCLKSEL, address 0x4007 40A8) bit
description
Bit
Symbol
1:0
SEL
31:2
Value
Description
Reset
value
SCT PLL clock source
0x00
0x0
IRC
0x1
System oscillator
0x2
Reserved
0x3
Reserved
-
Reserved
0x00
3.6.21 System clock divider register
This register controls how the main clock is divided to provide the system clock to the
core, memories, and the peripherals. The system clock can be shut down completely by
setting the DIV field to zero.
Table 49.
System clock divider register (SYSAHBCLKDIV, address 0x4007 40C0) bit
description
Bit
Symbol
Description
Reset
value
7:0
DIV
System AHB clock divider values
0: System clock disabled.
1: Divide by 1.
to
255: Divide by 255.
0x01
31:8
-
Reserved
-
3.6.22 System clock control register 0
The SYSAHBCLKCTRL0 register enables the clocks to individual system and peripheral
blocks. The system clock (bit 0) provides the clock for the AHB, the APB bridge, the ARM
Cortex-M3, the SYSCON block, and the PMU. This clock cannot be disabled.
See Section 1.2.1 for details on the SRAM configuration.
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 50.
System clock control register 0 (SYSAHBCLKCTRL0, address 0x4007 40C4) bit
description
Bit
Symbol
Value
0
SYS
This bit is read-only and always reads as 1. It
1
configures the always-on clock for the AHB, the APB
bridges, the Cortex-M3 core clocks, SYSCON, reset
control, SRAM0, and the PMU. Writes to this bit are
ignored.
1
ROM
Enables clock for ROM.
0
Disable
1
Enable
1
-
Reserved
0
3
SRAM1
Enables clock for SRAM1.
1
0
Disable
1
Enable
SRAM2
Enables clock for SRAM2.
0
1
1
Disable
Enable
6:5
-
Reserved
0
7
FLASH
Enables clock for flash controller.
1
0
1
Disable
Enable
8
-
Reserved
1
9
EEPROM
Enables clock for EEPROM controller.
0
0
Disable
1
Enable
10
-
Reserved
0
11
MUX
Enables clock for input mux.
0
12
13
14
15
User manual
Reset
value
2
4
UM10736
Description
0
Disable
1
Enable
SWM
Enables clock for switch matrix.
0
Disable
1
Enable
IOCON
Enables clock for IOCON block.
0
Disable
1
Enable
GPIO0
Enables clock for GPIO0 port registers.
0
Disable
1
Enable
GPIO1
Enables clock for GPIO1 port registers.
0
Disable
1
Enable
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0
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 50.
System clock control register 0 (SYSAHBCLKCTRL0, address 0x4007 40C4) bit
description …continued
Bit
Symbol
16
GPIO2
17
-
18
PINT
19
20
21
22
23
Value
Description
Reset
value
Enables clock for GPIO2 port registers.
0
0
Disable
1
Enable
Reserved
0
Enables clock for pin interrupt block.
0
0
Disable
1
Enable
GINT
Enables clock for grouped pin interrupt block.
0
Disable
1
Enable
DMA
Enables clock for DMA.
0
Disable
1
Enable
CRC
Enables clock for CRC.
0
Disable
1
Enable
0
Disable
1
Enable
WWDT
Enables clock for WWDT.
RTC
Enables clock for RTC.
0
Disable
1
Enable
0
0
0
0
0
26:24
-
Reserved
0
27
ADC0
Enables clock for ADC0 register interface.
0
28
0
Disable
1
Enable
ADC1
Enables clock for ADC1 register interface.
0
1
29
30
31
DAC
-
Disable
Enable
Enables clock for DAC.
0
Disable
1
Enable
ACMP
0
0
Enables clock to analog comparator block. This is the 0
clock to the register interface for all 4 comparators.
0
Disable
1
Enable
Reserved
0
3.6.23 System clock control register 1
The SYSAHBCLKCTRL register enables the clocks to individual peripheral blocks.
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 51.
System clock control register 1 (SYSAHBCLKCTRL1, address 0x4007 40C8) bit
description
Bit
Symbol
0
MRT
Value
0
1
1
2
3
4
5
6
7
User manual
Reset
value
Enables clock for multi-rate timer.
0
Disable
Enable
Enables clock for repetitive interrupt timer.
0
Disable
1
Enable
0
Disable
1
Enable
SCT0
Enables clock for SCT0.
SCT1
Enables clock for SCT1.
0
Disable
1
Enable
SCT2
Enables clock for SCT2.
0
Disable
1
Enable
SCT3
Enables clock for SCT3.
0
Disable
1
Enable
SCTIPU
Enables clock for SCTIPU.
0
Disable
1
Enable
CCAN
Enables clock for CCAN.
0
Disable
1
Enable
0
0
0
0
0
0
0
8
-
Reserved
0
9
SPI0
Enables clock for SPI0.
0
10
UM10736
RIT
Description
0
Disable
1
Enable
SPI1
Enables clock for SPI1.
0
Disable
1
Enable
12:11
-
Reserved
0
13
I2C0
Enables clock for I2C0.
0
0
Disable
1
Enable
16:14
-
Reserved
0
17
UART0
Enables clock for USART0.
0
0
Disable
1
Enable
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 51.
System clock control register 1 (SYSAHBCLKCTRL1, address 0x4007 40C8) bit
description …continued
Bit
Symbol
18
UART1
19
Value
Description
Reset
value
Enables clock for USART1.
0
0
Disable
1
Enable
UART2
Enables clock for USART2.
0
Disable
1
Enable
0
20
-
Reserved
0
21
QEI
Enables clock for QEI.
0
0
Disable
1
Enable
22
-
Reserved
0
23
USB
Enables clock for USB register interface.
0
27:24
-
0
Disable
1
Enable
-
Reserved
-
Reserved
0
Reserved
-
28
31:29
-
-
3.6.24 SYSTICK clock divider register
This register configures the SYSTICK peripheral clock. The SYSTICK timer clock can be
shut down by setting the DIV field to zero.
Table 52.
SYSTICK clock divider (SYSTICKCLKDIV, address 0x4007 40CC) bit description
Bit
Symbol
Description
Reset
value
7:0
DIV
SYSTICK clock divider values.
0: Disable SYSTICK timer clock.
1: Divide by 1.
to 255: Divide by 255.
0x00
31:8
-
Reserved
0x00
3.6.25 USART clock divider register
This register configures the clock for the fractional baud rate generator and all USARTs.
The UART clock can be disabled by setting the DIV field to zero (this is the default
setting).
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 53.
USART clock divider register (UARTCLKDIV, address 0x4007 40D0) bit
description
Bit
Symbol
Description
Reset
value
7:0
DIV
USART fractional baud rate generator clock divider values.
0: Clock disabled.
1: Divide by 1.
to
255: Divide by 255.
0
31:8
-
Reserved
-
3.6.26 IOCON glitch filter clock divider register
This register configures the peripheral input clock (IOCONFILTR_PCLK) to the IOCON
programmable glitch filter. The clock can be shut down by setting the DIV bits to 0x0.
Table 54.
IOCON glitch filter clock divider register (IOCONCLKDIV, address 0x4007 40D4)
bit description
Bit
Symbol
Description
Reset value
7:0
DIV
IOCON glitch filter clock divider values
0: Disable IOCONFILTR_PCLK.
1: Divide by 1.
to
255: Divide by 255.
0
31:8
-
Reserved
0x00
3.6.27 ARM trace clock divider register
This register configures the ARM trace clock. The ARM trace clock can be shut down by
setting the DIV field to zero.
Table 55.
ARM trace clock divider (TRACECLKDIV, address 0x4007 40D8) bit description
Bit
Symbol
Description
Reset
value
7:0
DIV
ARM trace clock divider values.
0: Disable TRACE_CLK.
1: Divide by 1.
to 255: Divide by 255.
0x00
31:8
-
Reserved
0x00
3.6.28 USB clock source divider register
This register allows the USB clock usb_clk to be divided to 48 MHz. The usb_clk can be
shut down by setting the DIV bits to 0x0.
Table 56.
UM10736
User manual
USB clock source divider (USBCLKDIV, address 0x4007 40EC) bit description
Bit
Symbol
Description
Reset
value
7:0
DIV
USB clock divider values
0: Disable USB clock.
1: Divide by 1.
to 255: Divide by 255.
0x00
31:8
-
Reserved
0x00
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3.6.29 ADCASYNCCLKDIV clock source divider register
This register divides the asynchronous clock to the ADCs. The clock can be shut down by
setting the DIV bits to 0x0.
Table 57.
ADC asynchronous clock source divider (ADCASYNCCLKDIV, address
0x4007 40F0) bit description
Bit
Symbol
Description
Reset
value
7:0
DIV
USB clock divider values
0: Disable USB clock.
1: Divide by 1.
to 255: Divide by 255.
0x00
31:8
-
Reserved
0x00
3.6.30 CLKOUT clock divider register
This register determines the divider value for the clock signal on the CLKOUT pin.
Table 58.
CLKOUT clock divider register (CLKOUTDIV, address 0x4007 40F8) bit
description
Bit
Symbol
Description
Reset
value
7:0
DIV
CLKOUT clock divider values
0: Disable CLKOUT clock divider.
1: Divide by 1.
to
255: Divide by 255.
0
31:8
-
Reserved
-
3.6.31 Frequency measure function control register
This register starts the frequency measurement function and stores the result in the
CAPVAL field. The target frequency can be calculated as follows with the frequencies
given in MHz:
Ftarget = (CAPVAL - 2) x Freference/214
Select the target and reference frequencies using the
Table 59.
UM10736
User manual
Frequency measure function control register (FREQMECTRL, address 0x4007
4120) bit description
Bit
Symbol
Description
Reset
value
13:0
CAPVAL
Stores the capture result which is used to calculate the frequency of
the target clock. This field is read-only.
0
30:14
-
Reserved.
-
31
PROG
Set this bit to one to initiate a frequency measurement cycle.
0
Hardware clears this bit when the measurement cycle has completed
and there is valid capture data in the CAPVAL field (bits 13:0).
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3.6.32 Flash configuration register
Depending on the system clock frequency, access to the flash memory can be configured
with various access times by writing to the FLASHCFG register.
Changing the FLASHCFG register value causes the flash accelerator to invalidate all of
the holding latches, resulting in new reads of flash information as required. This
guarantees synchronization of the flash accelerator to CPU operation.
Remark: Improper setting of this register may result in incorrect operation of the flash
memory. Do not change the flash access time when using the power API in efficiency,
low-current, or performance modes.
Table 60.
Flash configuration register (FLASHCFG, address 0x4007 4124) bit description
Bit
Symbol
11:0
-
Reserved. Do not change the value of these bits. Bits 0x1A
11:0 must be written back exactly as read.
13:12
FLASHTIM
Flash memory access time. FLASHTIM +1 is equal to
the number of system clocks used for flash access.
31:14
-
Value
Description
Reset
value
0x2
0x0
1 clock cycle. 1 system clock flash access time (for
system clock frequencies of up to 25 MHz).
0x1
2 clock cycles. 2 system clocks flash access time (for
system clock frequencies of up to 55 MHz).
0x2
3 clock cycles. 3 system clocks flash access time (for
system clock frequencies of up to 72 MHz).
0x3
Reserved.
-
Reserved. Do not change the value of these bits. Bits 31:14 must be written back exactly as read.
3.6.33 USART fractional baud rate generator register
All USART peripherals share a common clock U_PCLK, which can be adjusted by a
fractional divider:
U_PCLK = UARTCLKDIV/(1 + MULT/DIV).
This register sets the MULT and DIV values. UARTCLKDIV is the USART clock
configured in the UARTCLKDIV register.
Remark: To use of the fractional baud rate generator, you must write 0xFF to the DIV
value to yield a denominator value of 256. All other values are not supported.
See also:
Section 24.3.1 “Configure the USART clock and baud rate”
Section 24.7.1 “Clocking and baud rates”
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 61.
USART fractional baud rate generator register (FRGCTRL, address 0x4007 4128)
bit description
Bit
Symbol
Description
Reset
value
7:0
DIV
Denominator of the fractional divider. DIV is equal to the programmed 0xFF
value +1. Always set to 0xFF to use with the fractional baud rate
generator.
15:8
MULT
Numerator of the fractional divider. MULT is equal to the programmed 0
value.
31:16
-
Reserved
-
3.6.34 USB clock control register
This register controls the use of the USB need_clock signal and the polarity of the
need_clock signal for triggering the USB wake-up interrupt. For details of how to use the
USB need_clock signal for waking up the part from Deep-sleep or Power-down modes,
see Section 23.7.6.
Table 62.
USB clock control (USBCLKCTRL, address 0x4007 412C) bit description
Bit
Symbol
0
AP_CLK
1
31:2
Value
Description
Reset
value
USB need_clock signal control
0x0
0
Under hardware control.
1
Forced HIGH.
POL_CLK
USB need_clock polarity for triggering the USB
wake-up interrupt
0
Falling edge of the USB need_clock triggers the USB
wake-up (default).
1
Rising edge of the USB need_clock triggers the USB
wake-up.
-
Reserved. Do not write one to reserved bits.
0x0
0x00
3.6.35 USB clock status register
This register is read-only and returns the status of the USB need_clock signal. For details
of how to use the USB need_clock signal for waking up the part from Deep-sleep or
Power-down modes, see Section 23.7.6.
Table 63.
Symbol
0
NEED_CLKST
31:1
UM10736
User manual
USB clock status (USBCLKST, address 0x4007 4130) bit description
Bit
-
Value
Description
Reset
value
USB need_clock signal status
0x1
0
LOW
1
HIGH
Reserved
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Chapter 3: LPC15xx System configuration (SYSCON)
3.6.36 BOD control register
The BOD control register selects two separate threshold values for sending a BOD
interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed in
Table 64 are typical values.
Both the BOD interrupt and the BOD reset, depending on the value of bit BODRSTENA in
this register, can wake-up the chip from Sleep, Deep-sleep, and Power-down modes. See
Table 517 “power_mode_configure routine”.
The BOD levels are defined in the LPC15xx data sheet.
Table 64.
BOD control register (BODCTRL, address 0x4007 4180) bit description
Bit
Symbol
1:0
BODRSTLEV
3:2
4
Value Description
BOD reset level
0x0
Reserved.
0x1
Reserved.
0x2
Level 2
0x3
Level 3
BODINTVAL
0
BOD interrupt level
0x0
Reserved.
0x1
Reserved.
0x2
Level 2:
0x3
Level 3
BODRSTENA
31:5 -
Reset
value
0
BOD reset enable
0
Disable reset function.
1
Enable reset function.
-
Reserved
0
0x00
3.6.37 IRC control register
This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset
and written by the boot code on start-up.
Table 65.
IRC control register (IRCCTRL, address 0x4007 4184) bit description
Bit
Symbol
Description
Reset value
7:0
TRIM
Trim value
0x80, then flash will reprogram
31:8
-
Reserved
0x00
3.6.38 System oscillator control register
This register configures the frequency range for the system oscillator. The system
oscillator itself is powered on or off in the PDRUNCFG register. See Table 75.
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 66.
System oscillator control register (SYSOSCCTRL, address 0x4007 4188) bit
description
Bit
Symbol
0
BYPASS
1
31:2
Value
Description
Reset
value
Bypass system oscillator
0x0
0
Disabled. Oscillator is not bypassed.
1
Enabled. PLL input (sys_osc_clk) is fed directly
from the XTALIN pin bypassing the oscillator. Use
this mode when using an external clock source
instead of the crystal oscillator.
FREQRANGE
Determines frequency range for system oscillator.
-
0
Low frequency. 1 MHz - 20 MHz frequency range.
1
High frequency. 15 MHz - 25 MHz frequency range
-
Reserved
0x0
0x00
3.6.39 RTC oscillator control register
This register enables the 32 kHz output of the RTC oscillator. This clock can be used to
create the main clock when the PLL input is selected as the clock source to the main
clock. Do not use the system PLL with 32 kHz clock.
Table 67.
RTC oscillator control register (RTCOSCCTRL, address 0x4007 4190) bit
description
Bit
Symbol
0
EN
31:1
-
Value
Description
Reset
value
RTC 32 kHz clock enable.
1
0
Disabled. RTC clock off.
1
Enabled. RTC clock on.
-
Reserved
0x00
3.6.40 System PLL control register
This register connects and enables the system PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied to a higher frequency and then divided
down to provide the actual clock used by the CPU, peripherals, and memories. The PLL
can produce a clock up to the maximum allowed for the CPU.
Remark: The divider values for P and M must be selected so that the PLL output clock
frequency FCLKOUT is lower than 100 MHz.
Remark: This PLL supports a 6-bit feedback divider MSEL.
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 68.
System PLL control register (SYSPLLCTRL, address 0x4007 4198) bit description
Bit
Symbol
5:0
7:6
31:8
Description
Reset
value
MSEL
Feedback divider value. The division value M is the
programmed MSEL value + 1.
00000: Division ratio M = 1
to
111111: Division ratio M = 64
0
PSEL
Post divider ratio P. The division ratio is 2  P.
0
-
Value
0x0
P=1
0x1
P=2
0x2
P=4
0x3
P=8
-
Reserved. Do not write ones to reserved bits.
-
3.6.41 System PLL status register
This register is a Read-only register and supplies the PLL lock status.
Table 69.
System PLL status register (SYSPLLSTAT, address 0x4007 419C) bit description
Bit
Symbol
0
LOCK
31:1
-
Value
Description
Reset
value
PLL lock status
0
0
PLL not locked
1
PLL locked
-
Reserved
-
3.6.42 USB PLL control register
The USB PLL is identical to the system PLL and is used to provide a dedicated clock to
the USB block.
This register connects and enables the USB PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock 48 MHz clock used by the USB subsystem.
Remark: This PLL supports a 6-bit feedback divider MSEL.
Table 70.
UM10736
User manual
USB PLL control (USBPLLCTRL, address 0x4007 41A0) bit description
Bit
Symbol
5:0
MSEL
Value
Description
Reset
value
Feedback divider value. The division value M is the
0x000
programmed MSEL value + 1.
00000: Division ratio M = 1 to 111111: Division ratio M =
64.
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 70.
USB PLL control (USBPLLCTRL, address 0x4007 41A0) bit description
Bit
Symbol
7:6
PSEL
31:8
Value
Description
Reset
value
Post divider ratio P. The division ratio is 2 x P.
0x00
0x0
P=1
0x1
P=2
0x2
P=4
0x3
P=8
-
Reserved. Do not write ones to reserved bits.
0x00
3.6.43 USB PLL status register
This register is a Read-only register and supplies the PLL lock status.
Table 71.
USB PLL status (USBPLLSTAT, address 0x4007 41A4) bit description
Bit
Symbol
0
LOCK
31:1
Value
Description
Reset
value
PLL lock status
0x0
0
PLL not locked
1
PLL locked
-
Reserved
0x00
3.6.44 SCT PLL control register
The SCT PLL is identical to the system PLL and is used to provide a dedicated clock to
the SCTs.
Remark: This PLL supports a 6-bit feedback divider MSEL.
Table 72.
SCT PLL control (SCTPLLCTRL, address 0x4007 41A8) bit description
Bit
Symbol
5:0
MSEL
Feedback divider value. The division value M is the
0x000
programmed MSEL value + 1.
00000: Division ratio M = 1 to 111111: Division ratio M =
64.
7:6
PSEL
Post divider ratio P. The division ratio is 2 x P.
31:8
-
Value
Description
0x0
P=1
0x1
P=2
0x2
P=4
0x3
P=8
Reserved. Do not write ones to reserved bits.
Reset
value
0x00
0x00
3.6.45 SCT PLL status register
This register is a Read-only register and supplies the PLL lock status.
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 73.
SCT PLL status (SCTPLLSTAT, address 0x4007 41AC) bit description
Bit
Symbol
0
LOCK
31:1
Value
Description
Reset
value
PLL lock status
0x0
0
PLL not locked
1
PLL locked
-
Reserved
0x00
3.6.46 Wake-up configuration register
This register controls the power configuration of the device when waking up from
Deep-sleep or Power-down mode.
Table 74.
Wake-up configuration register (PDAWAKECFG, address 0x4007 4204) bit
description
Bit
Symbol
2:0
-
Reserved. Always write these bits as 0s.
0
3
IRCOUT_PD
IRC oscillator output wake-up configuration
0
4
Value Description
0
Powered
1
Powered down
IRC
IRC oscillator wake-up configuration
0
1
5
6
-
8
BOD_PD
10
11
12
User manual
Powered down
0
Powered
1
Powered down
0
Powered
1
Powered down
EEPROM
EEPROM wake-up configuration
BOD wake-up configuration
0
1
Powered down
USB PHY wake-up configuration
0
Powered
1
Powered down
ADC0 wake-up configuration
0
Powered
1
Powered down
ADC1_PD
ADC1 wake-up configuration
0
Powered
1
Powered down
0
Powered
1
Powered down
DAC_PD
0
0
Powered
ADC0_PD
0
Reserved
0
USBPHY_PD
0
Powered
Flash memory wake-up configuration
7
9
UM10736
FLASH
Reset value
DAC wake-up configuration
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 74.
Bit
Symbol
13
ACMP0_PD
14
15
16
17
18
19
20
21
22
23
24
User manual
Value Description
Reset value
Analog comparator 0 wake-up configuration
0
Powered
1
Powered down
ACMP1_PD
1
Analog comparator 1 wake-up configuration
0
Powered
1
Powered down
ACMP2_PD
1
Analog comparator 2 wake-up configuration
0
Powered
1
Powered down
0
Powered
1
Powered down
ACMP3_PD
1
Analog comparator 3 wake-up configuration
IREF_PD
1
Internal voltage reference wake-up configuration
0
Powered
1
Powered down
TS_PD
Temperature sensor wake-up configuration
0
Powered
1
Powered down
VDDADIV_PD
0
Powered
1
Powered down
Watchdog oscillator wake-up configuration.
0
Powered
1
Powered down
SYSOSC_PD
System oscillator wake-up configuration
0
Powered
1
Powered down
SYSPLL_PD
System PLL wake-up configuration
0
Powered
1
Powered down
USBPLL_PD
USB PLL wake-up configuration
0
Powered
1
Powered down
SCTPLL_PD
USB PLL wake-up configuration
0
Powered
1
Powered down
-
Reserved
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1
VDDA divider wake-up configuration. This is the
divider for the VDDA/2 input to the ADCs.
WDTOSC_PD
31:25 -
UM10736
Wake-up configuration register (PDAWAKECFG, address 0x4007 4204) bit
description …continued
1
1
1
1
1
1
0
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Chapter 3: LPC15xx System configuration (SYSCON)
3.6.47 Power configuration register
The PDRUNCFG register controls the power to the various analog blocks. This register
can be written to at any time while the chip is running, and a write will take effect
immediately with the exception of the power-down signal to the IRC.
To avoid glitches when powering down the IRC, the IRC clock is automatically switched off
at a clean point. Therefore, for the IRC a delay is possible before the power-down state
takes effect.
The system oscillator requires typically 500 μs to start up after the SYSOSC_PD bit has
been changed from 1 to 0. There is no hardware flag to monitor the state of the system
oscillator. Therefore, add a software delay of about 500 μs before using the system
oscillator after power-up.
Table 75.
Power configuration register (PDRUNCFG, address 0x4007 4208) bit description
Bit
Symbol
2:0
-
3
IRCOUT_PD
4
5
6
Value Description
IRC oscillator output
0
Powered
1
Powered down
IRC oscillator
0
Powered
1
Powered down
FLASH
Flash memory
0
Powered
1
Powered down
EEPROM
EEPROM
0
Powered
1
Powered down
0
0
0
-
Reserved
0
8
BOD_PD
BOD power-down
0
10
11
0
Powered
1
Powered down
USBPHY_PD
USB PHY power-down
0
Powered
1
Powered down
ADC0_PD
ADC0 power-down
0
Powered
1
Powered down
ADC1_PD
ADC1 power-down
0
1
12
User manual
0
7
9
UM10736
Reserved. Always write these bits as 0s.
0
IRC
Reset value
DAC_PD
1
1
1
Powered
Powered down
DAC power-down
0
Powered
1
Powered down
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 75.
Symbol
13
ACMP0_PD
14
15
16
17
18
19
20
21
22
23
24
User manual
Value Description
Reset value
Analog comparator 0 power-down
0
Powered
1
Powered down
ACMP1_PD
1
Analog comparator 1 power-down
0
Powered
1
Powered down
0
Powered
1
Powered down
ACMP2_PD
1
Analog comparator 2 power-down
ACMP3_PD
1
Analog comparator 3 power-down
0
Powered
1
Powered down
IREF_PD
1
Internal voltage reference power-down
0
Powered
1
Powered down
TS_PD
1
Temperature sensor power-down
0
Powered
1
Powered down
VDDADIV_PD
1
VDDA divider power-down. This is the divider for 1
the VDDA/2 input to the ADCs.
0
Powered
1
Powered down
0
Powered
1
Powered down
WDTOSC_PD
Watchdog oscillator power-down.
SYSOSC_PD
1
System oscillator power-down.After power-up,
add a software delay of approximately 500 μs
before using.
0
Powered
1
Powered down
0
Powered
1
Powered down
SYSPLL_PD
System PLL power-down
USBPLL_PD
USB PLL power-down
0
Powered
1
Powered down
SCTPLL_PD
31:25 -
UM10736
Power configuration register (PDRUNCFG, address 0x4007 4208) bit description
Bit
USB PLL power-down
0
Powered
1
Powered down
-
Reserved
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1
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Chapter 3: LPC15xx System configuration (SYSCON)
3.6.48 Start logic 0 wake-up enable register
The STARTERP0 register enables an interrupt for wake-up from deep-sleep mode and
power-down modes. For details see Section 4.7.4 and Section 4.7.5.
Remark: Also enable the corresponding interrupts in the NVIC. See Table 2 “Connection
of interrupt sources to the NVIC”.
Table 76.
Bit
Symbol
0
WWDT
1
-
5
GINT0
7
8
9
10
11
12
13
User manual
Value
Description
Reset
value
WWDT interrupt wake-up.
0
0
Disabled
1
Enabled
BOD
4:2
6
UM10736
Start logic 0 wake-up enable register 0 (STARTERP0, address 0x4007 4218) bit
description
BOD interrupt wake-up.
0
Disabled
1
Enabled
Reserved.
0
Group interrupt 0 wake-up.
0
0
Disabled
1
Enabled
GINT1
Group interrupt 1 wake-up.
0
Disabled
1
Enabled
PINT0
GPIO pin interrupt 0 wake-up
0
Disabled
1
Enabled
PINT1
GPIO pin interrupt 1 wake-up
0
Disabled
1
Enabled
0
Disabled
1
Enabled
PINT2
GPIO pin interrupt 2 wake-up
PINT3
GPIO pin interrupt 3 wake-up
0
Disabled
1
Enabled
PINT4
GPIO pin interrupt 4 wake-up
0
Disabled
1
Enabled
PINT5
GPIO pin interrupt 5 wake-up
0
Disabled
1
Enabled
0
Disabled
1
Enabled
PINT6
0
GPIO pin interrupt 6 wake-up
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0
0
0
0
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 76.
Start logic 0 wake-up enable register 0 (STARTERP0, address 0x4007 4218) bit
description …continued
Bit
Symbol
14
PINT7
Value
Description
Reset
value
GPIO pin interrupt 7 wake-up
0
0
Disabled
1
Enabled
20:15
-
Reserved.
21
USART0
USART0 interrupt wake-up. Configure USART 0
in synchronous slave mode or in 32 kHz
mode..
0
1
22
23
24
25
26
USART1
0
Disabled
Enabled
USART1 interrupt wake-up. Configure USART 0
in synchronous slave mode or in 32 kHz
mode...
0
Disabled
1
Enabled
USART2
USART2 interrupt wake-up. Configure USART 0
in synchronous slave mode or in 32 kHz
mode...
0
Disabled
1
Enabled
I2C
I2C interrupt wake-up.
0
Disabled
1
Enabled
SPI0
SPI0 interrupt wake-up
0
Disabled
1
Enabled
SPI1
SPI1 interrupt wake-up
0
Disabled
1
Enabled
0
0
0
29:27
-
Reserved
0
30
USB_WAKEUP
USB need_clock signal wake-up
0
31
-
0
Disabled
1
Enabled
Reserved
-
3.6.49 Start logic 1 wake-up enable register
This register selects which interrupts wake up the part from deep-sleep and power-down
modes. For details see Section 4.7.4 and Section 4.7.5.
Remark: Also enable the corresponding interrupts in the NVIC. See Table 2 “Connection
of interrupt sources to the NVIC”.
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Chapter 3: LPC15xx System configuration (SYSCON)
Table 77.
Start logic 1 wake-up enable register (STARTERP1, address 0x4007 421C) bit
description
Bit
Symbol
7:0
8
9
Value
Description
Reset
value
-
Reserved
-
ACMP0
Analog comparator 0 interrupt wake-up
0
0
Disabled
1
Enabled
ACMP1
Analog comparator 1 interrupt wake-up
0
1
10
ACMP2
11
-
13
RTCALARM
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
-
RTC alarm interrupt wake-up
0
Disabled
1
Enabled
RTC wake-up interrupt wake-up
0
Disabled
1
Enabled
-
0
Reserved
0
RTCWAKE
31:15
Enabled
Analog comparator 3 interrupt wake-up
12
14
Disabled
Analog comparator 2 interrupt wake-up
ACMP3
0
0
Reserved.
-
3.6.50 JTAG ID code register
This register contains the JTAG ID code.
Table 78.
JTAG ID code register (JTAGIDCODE, address 0x4007 43F4) bit description
Bit
Symbol
Description
Reset value
31:0
JTAGID
JTAG ID code.
0x19D6 C02B
3.6.51 Device ID0 register
This register contains the part ID. The part ID can also be obtained using the ISP or IAP
ReadPartID commands. See Table 490 and Table 505.
LPC1549 = 0x00001549
LPC1548 = 0x00001548
LPC1547 = 0x00001547
LPC1519 = 0x00001519
LPC1518 = 0x00001518
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Chapter 3: LPC15xx System configuration (SYSCON)
LPC1517 = 0x00001517
Table 79.
Device ID0 register (DEVICE_ID0, address 0x4007 43F8) bit description
Bit
Symbol
Description
Reset value
31:0
PARTID
Part ID
part dependent
3.6.52 Device ID1 register
This register contains the boot ROM and die revisions.
Table 80.
Device ID1 register (DEVICE_ID1, address 0x4007 43FC) bit description
Bit
Symbol
Description
Reset value
31:0
REVID
Revision.
0x0841 9D6C
3.7 Functional description
3.7.1 Reset
Reset has the following sources:
•
•
•
•
•
The RESET pin. The RESET pin is a Schmitt trigger input pin.
Watchdog reset.
Power-On Reset (POR).
Brown Out Detect (BOD).
ARM software reset.
Assertion of the POR or the BOD reset, once the operating voltage attains a usable level,
starts the IRC. After the IRC-start-up time (maximum of 6 s on power-up), the IRC
provides a stable clock output. The reset remains asserted until the external Reset is
released, the oscillator is running, and the flash controller has completed its initialization.
On the assertion of any reset source (ARM software reset, POR, BOD reset, External
reset, and Watchdog reset), the following processes are initiated:
1. The IRC is enabled or starts up if not running.
2. The flash wake-up timer starts. This takes approximately 100 s. Then the flash
initialization sequence is started, which takes about 250 cycles.
3. The boot code in the ROM starts. The boot code performs the boot tasks and may
jump to the flash.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Remark: The switch matrix is only reset after a POR or BOD reset.
3.7.2 Start-up behavior
See Figure 4 for the start-up timing after reset. The IRC is the default clock at Reset and
provides a clean system clock shortly after the supply voltage reaches the threshold value
of 1.8 V.
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Chapter 3: LPC15xx System configuration (SYSCON)
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Fig 4.
Start-up timing
3.7.3 Brown-out detection
The part includes up to four levels for monitoring the voltage on the VDD pin. If this voltage
falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC or
issues a reset, depending on the value of the BODRSTENA bit in the BOD control register
(Table 64).
The interrupt signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC (see Table 3) in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register.
If the BOD interrupt is enabled in the STARTERP register and in the NVIC, the BOD
interrupt can wake up the chip from Deep-sleep and power-down mode.
If the BOD reset is enabled, the forced BOD reset can wake up the chip from Deep-sleep
or Power-down mode.
3.7.4 PLL functional description
The LPC15xx uses the PLL to create the clocks for the core and peripherals.
All three PLLs (system, USB, and SCT) are identical.
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Chapter 3: LPC15xx System configuration (SYSCON)
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(1) Do not use the IRC as a clock source for the USB full-speed operation.
Fig 5.
PLL block diagram
The block diagram of this PLL is shown in Figure 5. The input frequency range is 10 MHz
to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This
block compares the phase and frequency of its inputs, and generates a control signal
when phase and/ or frequency do not match. The loop filter filters these control signals
and drives the current controlled oscillator (CCO), which generates the main clock and
optionally two additional phases. The CCO frequency range is 156 MHz to 320 MHz.
These clocks are either divided by 2P by the programmable post divider to create the
output clocks, or are sent directly to the outputs. The main output clock is then divided by
M by the programmable feedback divider to generate the feedback clock. The output
signal of the phase-frequency detector is also monitored by the lock detector, to signal
when the PLL has locked on to the input clock.
Remark: The divider values for P and M must be selected so that the PLL output clock
frequency FCLKOUT is lower than 100 MHz because the main clock is limited to a
maximum frequency of 100 MHz
3.7.4.1 Lock detector
The lock detector measures the phase difference between the rising edges of the input
and feedback clocks. Only when this difference is smaller than the so called “lock
criterion” for more than eight consecutive input clock periods, the lock output switches
from low to high. A single too large phase difference immediately resets the counter and
causes the lock signal to drop (if it was high). Requiring eight phase measurements in a
row to be below a certain figure ensures that the lock detector will not indicate lock until
both the phase and frequency of the input and feedback clocks are very well aligned. This
effectively prevents false lock indications, and thus ensures a glitch free lock signal.
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Chapter 3: LPC15xx System configuration (SYSCON)
3.7.4.2 Power-down control
To reduce the power consumption when the PLL clock is not needed, a PLL Power-down
mode has been incorporated. This mode is enabled by setting the SYSPLL_PD bit to one
in the Power configuration register (Table 75). In this mode, the internal current reference
will be turned off, the oscillator and the phase-frequency detector will be stopped and the
dividers will enter a reset state. While in PLL Power-down mode, the lock output will be
low to indicate that the PLL is not in lock. When the PLL Power-down mode is terminated
by setting the SYSPLL_PD bit to zero, the PLL will resume its normal operation and will
make the lock signal high once it has regained lock on the input clock.
3.7.4.3 Divider ratio programming
3.7.4.3.1
Post divider
The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two
times the value of P selected by PSEL bits as shown in Table 68. This guarantees an
output clock with a 50% duty cycle.
3.7.4.3.2
Feedback divider
The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio
between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus
one, as specified in Table 68.
3.7.4.3.3
Changing the divider values
Changing the divider ratio while the PLL is running is not recommended. As there is no
way to synchronize the change of the MSEL and PSEL values with the dividers, the risk
exists that the counter will read in an undefined value, which could lead to unwanted
spikes or drops in the frequency of the output clock. The recommended way of changing
between divider settings is to power down the PLL, adjust the divider settings and then let
the PLL start up again.
3.7.4.4 Frequency selection
The PLL frequency equations use the following parameters (also see Figure 5):
Table 81.
3.7.4.4.1
PLL frequency parameters
Parameter
System PLL
FCLKIN
Frequency of sys_pllclkin (input clock to the system PLL) from the
SYSPLLCLKSEL multiplexer (see Section 3.6.18).
FCCO
Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz.
FCLKOUT
Frequency of sys_pllclkout. This is the PLL output frequency and must be
< 100 MHz.
P
System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see
Section 3.6.40).
M
System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see
Section 3.6.40).
Normal mode
In this mode the post divider is enabled, giving a 50% duty cycle clock with the following
frequency relations:
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(1)
Fclkout = M  Fclkin =  FCCO    2  P 
To select the appropriate values for M and P, it is recommended to follow these steps:
1. Specify the input clock frequency Fclkin.
2. Calculate M to obtain the desired output frequency Fclkout with M = Fclkout / Fclkin.
3. Find a value so that FCCO = 2  P  Fclkout.
4. Verify that all frequencies and divider values conform to the limits specified in
Table 68.
Remark: The divider values for P and M must be selected so that the PLL output clock
frequency FCLKOUT is lower than 100 MHz.
Table 82 shows how to configure the PLL for a 12 MHz crystal oscillator using the
SYSPLLCTRL register (Table 68). The main clock is equivalent to the system clock if the
system clock divider SYSAHBCLKDIV is set to one (see Table 49).
Table 82.
PLL configuration examples
PLL input
clock
sys_pllclkin
(Fclkin)
Main clock
(Fclkout)
MSEL bits
Table 68
M
PSEL bits
divider Table 68
value
P
divider
value
FCCO
SYSAHBCLKDIV
frequency
System
clock
12 MHz
72 MHz
5
6
1
2
288 MHz
1
72 MHz
12 MHz
60 MHz
4
5
1
2
240 MHz
2
30 MHz
12 MHz
24 MHz
1
2
2
4
192 MHz
1
24 MHz
3.7.4.4.2
PLL Power-down mode
In this mode, the internal current reference will be turned off, the oscillator and the
phase-frequency detector will be stopped and the dividers will enter a reset state. While in
PLL Power-down mode, the lock output will be low, to indicate that the PLL is not in lock.
When the PLL Power-down mode is terminated by SYSPLL_PD bit to zero in the
Power-down configuration register (Table 75), the PLL will resume its normal operation
and will make the lock signal high once it has regained lock on the input clock.
3.7.5 Frequency measure function
The Frequency Measure circuit is based on two 14-bit counters, one clocked by the
reference clock and one by the target clock. Synchronization between the clocks is
performed at the start and end of each count sequence.
A measurement cycle is initiated by software setting a control/status bit in the
FREQMECTRL register (Table 59). The software can then poll this same
measure-in-progress bit which will be cleared by hardware when the measurement
operation is completed.
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The measurement cycle terminates when the reference counter rolls-over. At that point
the state of the target counter is loaded into a capture field in the FREQMEAS register,
and the measure-in-progress bit is cleared. Software can read this capture value and
apply to it a specific calculation which will return the precise frequency of the target clock
in MHz.
3.7.5.1 Accuracy
The frequency measurement function can measure the frequency of any on-chip (or
off-chip) clock (referred to as the target clock) to a high degree of accuracy using another
on-chip clock of known frequency as a reference.
The following constraints apply:
• The frequency of the reference clock must be (somewhat) greater that the frequency
of the target clock.
• The system clock used to access the frequency measure function register must also
be greater than the frequency of the target clock.
The frequency measurement function circuit is able to measure the target frequency with
an error of less than 0.1%, provided the reference frequency is precisely known.
Uncertainty in the reference clock (for example the +/- 1% accuracy of the IRC) will add to
the measurement error of the target clock. In general, though, this additional error is less
than the uncertainty of the reference clock.
There can also be a modest loss of accuracy if the reference frequency exceeds the
target frequency by a very large margin (25x or more). Accuracy is not a simple function of
the magnitude of the frequency difference, however. Nearly identical frequency
combinations, still with a spread of about 43x, result in errors of less than 0.05 %.
If the target and reference clocks are different by more than a factor of approximately
500, then the accuracy decreases to +/- 4 %.
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Chapter 4: LPC15xx Power Management Unit (PMU)
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4.1 How to read this chapter
The LPC15xx provides an on-chip API in the boot ROM to optimize power consumption in
active and sleep modes and configure the part for deep-sleep and power-down modes.
See Chapter 35
The PMU is identical for all parts.
4.2 Features
• Control of the reduced power modes
• Four general purpose backup registers to retain data in Deep power-down mode
4.3 Basic configuration
The PMU is always on as long as the VDD or VBAT supply voltages are present.
To turn analog components on or off in active and sleep modes, use the PDRUNCFG
register (see Table 75). In deep-sleep and power-down modes, the power profile API
controls which analog peripherals remain powered up (see Table 517). There is no
register implemented to turn analog peripherals on or off for deep-sleep mode or
power-down mode.
4.4 Pin description
In Deep power-down only the WAKEUP pin (PIO0_17) is functional if VDD is present. To
conserve additional power, the WAKEUP pin function can be disabled in the GPREG4
register.
Remark: When entering Deep power-down mode, an external pull-up resistor is required
on the WAKEUP pin to hold it HIGH until LOW going pulse wakes up the part. In addition,
pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode.
4.5 General description
Power to the part is supplied via two power domains. The main power domain is powered
by VDD and supplies power to the core, peripheral, memories, inputs and outputs via an
on-chip regulator.
A second, always-on power domain can either be powered be VDD if present or by VBAT
and supplies power to the RTC and five general-purpose back-up registers which can be
used to save data in deep power-down mode or when VDD is shut down.
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Chapter 4: LPC15xx Power Management Unit (PMU)
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Fig 6.
Power domains
The power use is controlled by the PMU, by the SYSCON block, and the ARM Cortex-M3
core. The ROM based power configuration API configures the part for each reduced
power mode. The following modes are supported in order from highest to lowest power
consumption:
1. Active mode: The part is in active mode after a POR and when it is fully powered and
operational after booting.
2. Sleep mode:
The sleep mode affects the ARM Cortex-M3 core only. The clock to the core is shut
off. Peripherals and memories are active and operational.
3. Deep-sleep and power-down modes:
The Deep-sleep and power-down modes affect the core and the entire system with
memories and peripherals. In both modes, the clock to the core is shut down and the
peripherals receive no internal clocks. All SRAM and registers maintain their internal
states.
Through the power profiles API, you can opt to keep several peripherals running for
safe operation of the part (WWDT and BOD) or for monitoring analog inputs
(comparators and internal voltage reference and temperature sensor via one of the
comparators).
The differences between Deep-sleep mode and Power-down modes are the
following:
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Chapter 4: LPC15xx Power Management Unit (PMU)
a. In Deep-sleep mode, the flash is in stand-by mode and the IRC is running with its
output disabled to minimize wake-up time.
b. In Power-down mode, the flash and the IRC are powered down to conserve power
at the expense of longer wake-up times.
4. Deep power-down mode:
For maximal power savings, the entire system (the core and all peripherals) is shut
down except for the PMU with the general purpose registers (GPREG) and the RTC.
On wake-up, the part reboots.
Table 83.
Peripheral configuration in reduced power modes
Peripheral
Sleep mode
Deep-sleep mode
Power-down mode
Deep
power-down
mode
IRC
software
configurable
on
off
off
IRC output
software
configurable
off
off
off
Flash
software
configurable
on
off
off
BOD
software
configurable
software configurable
software configurable
off
PLL
software
configurable
off
off
off
SysOsc
software
configurable
off
off
off
WDosc/WWDT
software
configurable
software configurable
software configurable
off
USART
software
configurable
off; but can create wake-up
interrupt in synchronous slave
mode or 32 kHz clock mode
off; but can create wake-up interrupt off
in synchronous slave mode or 32 kHz
clock mode
SPI
software
configurable
off; but can create wake-up
interrupt in slave mode
off; but can create wake-up interrupt
in slave mode
off
I2C
software
configurable
off; but can create wake-up
interrupt in slave mode
off; but can create wake-up interrupt
in slave mode
off
Other digital
peripherals
software
configurable
off
off
off
Analog
peripherals
software
configurable
software configurable
software configurable
off
RTC oscillator
software
configurable
software configurable
software configurable
software
configurable
4.5.1 Wake-up process
The part always wakes up to the active mode. To wake up from the reduced power
modes, you must configure the wake-up source. Each reduced power mode supports its
own wake-up sources and needs to be configured accordingly as shown in Table 84.
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Chapter 4: LPC15xx Power Management Unit (PMU)
Table 84.
Wake-up sources for reduced power modes
Power mode
Wake-up source
Sleep
Any interrupt
Enable interrupt in NVIC.
Deep-sleep and
Power-down
Pin interrupts
Enable pin interrupts in NVIC and STARTERP0 registers.
BOD interrupt
BOD reset
WWDT interrupt
WWDT reset
ACMP
output/temperature
sensor/internal
voltage reference
RTC 1 Hz alarm timer
RTC 1 kHz timer
time-out and alarm
Enable interrupt in NVIC and STARTERP0 registers.
Enable interrupt in BODCTRL register.
Configure the BOD to keep running in this mode with the power API.
Enable reset in BODCTRL register.
•
•
•
•
•
•
•
•
Enable interrupt in NVIC and STARTERP0 registers.
•
•
Enable the RTC 1 Hz oscillator in the RTC CTRL register.
•
•
Enable the RTCALARM interrupt in the STARTERP1 register.
•
Start RTC 1 kHz timer by writing a time-out value to the RTC WAKE
register.
•
Enable the RTCWAKE interrupt in the STARTERP1 register.
WWDT running. Enable WWDT in WWDT MOD register and feed.
Enable interrupt in WWDT MOD register.
Configure the WDOSC to keep running in this mode with the power API.
WWDT running.
Enable reset in WWDT MOD register.
Enable analog comparator interrupt in the NVIC and STARTERP1 register.
Configure the analog comparators or the temperature sensor or the
internal voltage reference to keep running with the power API.
Start RTC alarm timer by writing a time-out value to the RTC COUNT
register.
Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTC
CTRL register.
Interrupt from I2C in slave mode. See Section 26.4.3.2.
SPI interrupt
Interrupt from SPI in slave mode. See Section 25.3.1.2.
USART interrupt
Interrupt from USART in slave or 32 kHz mode. See Section 24.3.2.2.
USB interrupt
USB wake signal. See Section 23.7.6.1.
RTC 1 Hz alarm timer
RTC 1 kHz timer
time-out and alarm
User manual
•
•
•
I2C interrupt
Deep power-down WAKEUP pin
PIO0_17
UM10736
Conditions
Enable the WAKEUP function in the GPREG4 register in the PMU. This is the
default.
•
•
Enable the RTC 1 Hz oscillator in the RTC CTRL register.
•
Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTC
CTRL register.
•
Start RTC 1 kHz timer by writing a time-out value to the RTC WAKE
register.
Start RTC alarm timer by writing a time-out value to the RTC COUNT
register.
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Chapter 4: LPC15xx Power Management Unit (PMU)
4.6 Register description
Table 85.
Register overview: PMU (base address 0x4003 C000)
Name
Access
Address
offset
Description
Reset
value
Reference
PCON
R/W
0x000
Power control register
0x0
Table 86
GPREG0
R/W
0x004
General purpose register 0
0x0
Table 87
GPREG1
R/W
0x008
General purpose register 1
0x0
Table 87
GPREG2
R/W
0x00C
General purpose register 2
0x0
Table 87
GPREG3
R/W
0x010
General purpose register 3
0x0
Table 87
GPREG4
R/W
0x014
General purpose register 4.
WAKEUP pad control.
0x0
Table 88
4.6.1 Power control register
The power control register provides a lock mechanism to prevent the part from entering
Deep power-down mode. Together with the BOD and WWDT, the lock bit allows safe
operation of the part at all times.
In addition, this register sets the flags that indicate what reduced power mode the part has
exited on wake-up.
Table 86.
Power control register (PCON, address 0x4003 C000) bit description
Bit
Symbol
2:0
3
Value
Description
Reset
value
-
Reserved.
000
NODPD
A 1 in this bit prevents entry to Deep power-down mode.
This bit is cleared by power-on reset (POR).
0
7:4
-
8
SLEEPFLAG
-
10:9
-
11
DPDFLAG
31:12
-
Reserved. Do not write ones to this bit.
0
Sleep mode flag
0
0
Read: No power-down mode entered. The part is in Active
mode.
Write: No effect.
1
Read: Sleep, Deep-sleep, or Power-down mode entered.
Write: Writing a 1 clears the SLEEPFLAG bit to 0.
-
Reserved. Do not write ones to this bit.
0
Deep power-down flag
0
0
Read: Deep power-down mode not entered.
Write: No effect.
0
1
Read: Deep power-down mode entered.
Write: Clear the Deep power-down flag.
-
Reserved. Do not write ones to this bit.
0
4.6.2 General purpose registers 0 to 3
The general purpose registers retain data through the Deep power-down mode when
power is still applied to the VDD pin but the chip has entered Deep power-down mode.
Only a cold boot - when all power has been completely removed from the chip - will reset
the general purpose registers.
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Table 87.
General purpose registers 0 to 3 (GPREG[0:3], address 0x4003 C004 (GPREG0) to
0x4003 C010 (GPREG3)) bit description
Bit
Symbol
Description
Reset
value
31:0
GPDATA
Data retained during Deep power-down mode.
0x0
4.6.3 General purpose register 4
This register provides extra bits for data to be retained during Deep power-down mode. In
addition, this register configures the functionality and the hysteresis of the WAKEUP pin
(PIO0_17).
The bits in the register not used for the WAKEUP pin control (bits 31:10) can be used for
storing additional data which are retained in Deep power-down mode in the same way as
registers GPREG0 to GPREG3.
Remark: If there is a possibility that the external voltage applied on pin VDD drops below
2.2 V during Deep power-down, the hysteresis of the WAKEUP input pin has to be
disabled in this register before entering Deep power-down mode in order for the chip to
wake up.
Table 88.
General purpose register 4 (GPREG4, address 0x4003 C014) bit description
Bit
Symbol
0
WAKEUPHYS
1
Value
Description
Reset
value
WAKEUP pin hysteresis enable
0
0
Disabled. Hysteresis for WAKEUP pin disabled.
1
Enabled. Hysteresis for WAKEUP pin enabled.
WAKEPAD_
DISABLE
WAKEUP pin disable. Setting this bit disables the
wake-up pin, so it can be used for other purposes.
0
Remark: Never set this bit if you intend to use a pin to
wake up the part from Deep power-down mode. You
can only disable the wake-up pin if the RTC wake-up
is enabled and configured.
Remark: Setting this bit is not necessary if Deep
power-down mode is not used.
UM10736
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0
Enabled. The wake-up function is enabled on pin
PIO0_17.
1
Disabled. Setting this bit disables the wake-up
function on pin PIO0_17.
9:2
-
Reserved. Do not write 1s to reserved bits.
0x0
31:10
-
Data retained during Deep power-down mode.
0x0
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Chapter 4: LPC15xx Power Management Unit (PMU)
4.7 Functional description
4.7.1 Power management
The LPC15xx support a variety of power control features. In Active mode, when the chip is
running, power and clocks to selected peripherals can be optimized for power
consumption. In addition, there are four special modes of processor power reduction with
different peripherals running: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode.
Remark: The Debug mode is not supported in Sleep, Deep-sleep, Power-down, or Deep
power-down modes.
4.7.2 Active mode
In Active mode, the ARM Cortex-M3 core, memories, and peripherals are clocked by the
system clock or main clock.
The chip is in Active mode after reset and the default power configuration is determined
by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power
configuration can be changed during run time.
4.7.2.1 Power configuration in Active mode
Power consumption in Active mode is determined by the following configuration choices:
• The SYSAHBCLKCTRL registers controls which memories and peripherals are
running (Table 50 and Table 51).
• The power to various analog blocks (PLL, oscillators, the BOD circuit, and the flash
block) can be controlled at any time individually through the PDRUNCFG register
(Table 75 “Power configuration register (PDRUNCFG, address 0x4007 4208) bit
description”).
• The clock source for the system clock can be selected from the IRC (default), the
system oscillator, the 32 kHz oscillator, or the watchdog oscillator (see Figure 3 and
related registers).
• The system clock frequency can be selected by the SYSPLLCTRL (Table 68) and the
SYSAHBCLKDIV register (Table 49). You can find optimal settings for setting the
system PLL by using the set_pll routine in the power API (Table 515).
• Several peripherals use individual peripheral clocks with their own clock dividers. The
peripheral clocks can be shut down through the corresponding clock divider registers.
• The power API provides an easy way to optimize power consumption depending on
CPU load and performance requirements. See Section 35.3.
4.7.3 Sleep mode
In Sleep mode, the system clock to the ARM Cortex-M3 core is stopped and execution of
instructions is suspended until either a reset or an interrupt occurs.
Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL registers,
continue operation during Sleep mode and may generate interrupts to cause the
processor to resume execution. Sleep mode eliminates dynamic power used by the
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Chapter 4: LPC15xx Power Management Unit (PMU)
processor itself, memory systems and related controllers, and internal buses. The
processor state and registers, peripheral registers, and internal SRAM values are
maintained, and the logic levels of the pins remain static.
As in active mode, the power API provides an easy way to optimize power consumption
depending on CPU load and performance requirements in sleep mode. See Section 35.3.
4.7.3.1 Power configuration in Sleep mode
Power consumption in Sleep mode is configured by the same settings as in Active mode:
• The clock remains running.
• The system clock frequency remains the same as in Active mode, but the processor is
not clocked.
• Analog and digital peripherals are selected as in Active mode.
4.7.3.2 Programming Sleep mode
The following steps must be performed to enter Sleep mode:
1. In the NVIC, enable all interrupts that are needed to wake up the part.
2. Call power API: pPWRD->power_mode_configure(SLEEP, peripheral);
Remark: The peripheral parameter is don’t care.
3. Issue the ARM Cortex-M3 Wait-For-Interrupt (WFI) instruction.
4.7.3.3 Wake-up from Sleep mode
Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the
processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns
to its original power configuration defined by the contents of the PDRUNCFG and the
SYSAHBCLKCTRL registers. If a reset occurs, the microcontroller enters the default
configuration in Active mode.
4.7.4 Deep-sleep mode
In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All
analog blocks are powered down by default but can be selected to keep running through
the power API if needed as wake-up sources. The main clock, and therefore all peripheral
clocks, are disabled. The IRC is running, but its output is disabled. The flash is in stand-by
mode.
Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power
used by the processor itself, memory systems and related controllers, and internal buses.
The processor state and registers, peripheral registers, and internal SRAM values are
maintained, and the logic levels of the pins remain static.
4.7.4.1 Power configuration in Deep-sleep mode
Power consumption in Deep-sleep mode is determined by which analog wake-up sources
are enabled. Serial peripherals and pin interrupts configured to wake up the part do not
contribute to the power consumption. All wake-up events (from analog and serial
peripherals) must be enabled in the STARTERP registers and in the NVIC. In addition,
each analog block must be explicitly enabled through the power API function
power_mode_configure() for wake-up. See Table 84.
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Chapter 4: LPC15xx Power Management Unit (PMU)
4.7.4.2 Programming Deep-sleep mode
The following steps must be performed to enter Deep-sleep mode:
1. Select wake-up sources and enable all selected wake-up events in the STARTERP
registers (Table 76 and Table 77) and in the NVIC.
2. Select the power configuration after wake-up in the PDAWAKECFG (Table 74)
register.
3. Select the IRC as the main clock. See Table 40.
4. Call the power API with the parameter peripheral set to enable the analog peripherals
the serve as wake-up sources (see Table 518 “Bit values for the
power_mode_configure peripheral parameter”):
pPWRD->power_mode_configure(DEEP_SLEEP, peripheral);
5. Use the ARM WFI instruction.
4.7.4.3 Wake-up from Deep-sleep mode
The part can wake up from Deep-sleep mode in the following ways:
• Using a signal on one of the eight pin interrupts selected in Table 131. Each pin
interrupt must also be enabled in the STARTERP0 register (Table 76) and in the
NVIC.
• Using an interrupt from any analog block configured in the power API. Also enable the
wake-up sources in the STARTERP registers (Table 76 and Table 77) and the NVIC.
• Using a reset from the RESET pin, or the BOD or WWDT (if enabled in the power
API).
• Using a wake-up signal from any of the serial peripherals. Also enable the wake-up
sources in the STARTERP registers (Table 76 and Table 77) and the NVIC.
• GPIO group interrupt signal. Interrupt must also be enabled in the STARTERP1
register (Table 76) and in the NVIC.
• RTC alarm signal or wake-up signal. See Section 18.1. Interrupts must also be
enabled in the STARTERP1 register (Table 76) and in the NVIC.
4.7.5 Power-down mode
In Power-down mode, the system clock to the processor is disabled as in Sleep mode. All
analog blocks are powered down by default but can be selected to keep running if needed
for waking up the part. The main clock and therefore all peripheral clocks are disabled
except for the clock to the watchdog timer if the watchdog oscillator is selected. The IRC
itself and the flash are powered down, decreasing power consumption compared to
Deep-sleep mode.
Power-down mode eliminates all power used by analog peripherals and all dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses. The processor state and registers, peripheral registers, and internal SRAM values
are maintained, and the logic levels of the pins remain static. Wake-up times are longer
compared to the Deep-sleep mode.
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Chapter 4: LPC15xx Power Management Unit (PMU)
4.7.5.1 Power configuration in Power-down mode
Power consumption in power-down mode is determined by which analog wake-up
sources are enabled. Serial peripherals and pin interrupts configured to wake up the part
do not contribute to the power consumption. All wake-up events (from analog and serial
peripherals) must be enabled in the STARTERP registers and in the NVIC. In addition,
each analog block must be explicitly enabled through the power API function
power_mode_configure() for wake-up. See Table 84.
4.7.5.2 Programming Power-down mode
The following steps must be performed to enter Power-down mode:
1. Select wake-up sources and enable all related wake-up events in the STARTERP
registers (Table 76 and Table 77) and in the NVIC.
2. Select the power configuration after wake-up in the PDAWAKECFG (Table 74)
register.
3. Select the IRC as the main clock. See Table 40.
4. Call the power API with the peripheral parameter set to enable the analog wake-up
sources: pPWRD->power_mode_configure(POWER_DOWN, peripheral);
5. Use the ARM WFI instruction.
4.7.5.3 Wake-up from Power-down mode
The part can wake up from Power-down mode in the following ways:
• Using a signal on one of the eight pin interrupts selected in Table 131. Each pin
interrupt must also be enabled in the STARTERP0 register (Table 76) and in the
NVIC.
• Using an interrupt from any analog block configured in the power API. Also enable the
wake-up sources in the STARTERP registers (Table 76 and Table 77) and the NVIC.
• Using a reset from the RESET pin, or the BOD or WWDT (if enabled in the power
API).
• Using a wake-up signal from any of the serial peripherals. Also enable the wake-up
sources in the STARTERP registers (Table 76 and Table 77) and the NVIC.
• GPIO group interrupt signal. Interrupt must also be enabled in the STARTERP1
register (Table 76) and in the NVIC.
• RTC alarm signal or wake-up signal. See Section 18.1. Interrupts must also be
enabled in the STARTERP1 register (Table 76) and in the NVIC.
4.7.6 Deep power-down mode
In Deep power-down mode, power and clocks are shut off to the entire chip with the
exception of the WAKEUP pin and the RTC.
During Deep power-down mode, the contents of the SRAM and registers are not retained
except for a small amount of data which can be stored in the general purpose registers of
the PMU block.
All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin. In
this mode, you must pull the RESET pin HIGH externally.
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Chapter 4: LPC15xx Power Management Unit (PMU)
Remark: Setting bit 3 in the PCON register (Table 86) prevents the part from entering
Deep-power down mode.
4.7.6.1 Power configuration in Deep power-down mode
Deep power-down mode has no configuration options. All clocks, the core, and all
peripherals are powered down. Only the WAKEUP pin and the RTC are powered.
4.7.6.2 Programming Deep power-down mode using the WAKEUP pin:
The following steps must be performed to enter Deep power-down mode when using the
WAKEUP pin for waking up:
1. Pull the WAKEUP pin externally HIGH.
2. Ensure that bit 3 in the PCON register (Table 86) is cleared.
3. Store data to be retained in the general purpose registers (Section 4.6.2).
4. Call the power API: pPWRD->power_mode_configure(DEEP_POWER_DOWN, peripheral);
Remark: The peripheral parameter is don’t care.
5. Use the ARM WFI instruction.
4.7.6.3 Wake-up from Deep power-down mode using the WAKEUP pin:
Pulling the WAKEUP pin LOW wakes up the part from Deep power-down, and the chip
goes through the entire reset process.
1. On the WAKEUP pin, transition from HIGH to LOW.
– The PMU will turn on the on-chip voltage regulator. When the core voltage reaches
the power-on-reset (POR) trip point, a system reset will be triggered and the chip
re-boots.
– All registers except the DPDCTRL and GPREG0 to GPREG3registers will be in
their reset state.
2. Once the chip has booted, read the deep power-down flag in the PCON register
(Table 86) to verify that the reset was caused by a wake-up event from Deep
power-down and was not a cold reset.
3. Clear the deep power-down flag in the PCON register (Table 86).
4. (Optional) Read the stored data in the general purpose registers (Section 4.6.2).
5. Set up the PMU for the next Deep power-down cycle.
Remark: The RESET pin has no functionality in Deep power-down mode.
4.7.6.4 Programming Deep power-down mode using the RTC for wake-up:
The following steps must be performed to enter Deep power-down mode when using the
RTC for waking up:
1. Set up the RTC high resolution timer. Write to the RTC VAL register. This starts the
high res timer if enabled. Another option is to use the 1 Hz alarm timer.
2. Ensure that bit 3 in the PCON register (Table 86) is cleared.
3. Store data to be retained in the general purpose registers (Section 4.6.2).
4. Call the power API: pPWRD->power_mode_configure(DEEP_POWER_DOWN, peripheral);
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Chapter 4: LPC15xx Power Management Unit (PMU)
Remark: The peripheral parameter is don’t care.
5. Use the ARM WFI instruction.
4.7.6.5 Wake-up from Deep power-down mode using the RTC:
The part goes through the entire reset process when the RTC times out:
1. When the high resolution timer count reaches 0, the following happens:
– The PMU will turn on the on-chip voltage regulator. When the core voltage reaches
the power-on-reset (POR) trip point, a system reset will be triggered and the chip
boots.
– All registers except the DPDCTRL and GPREG0 to GPREG3 registers will be in
their reset state.
2. Once the chip has booted, read the deep power-down flag in the PCON register
(Table 86) to verify that the reset was caused by a wake-up event from Deep
power-down and was not a cold reset.
3. Clear the deep power-down flag in the PCON register (Table 86).
4. (Optional) Read the stored data in the general purpose registers (Section 4.6.2).
5. Set up the PMU for the next Deep power-down cycle.
Remark: The RESET pin has no functionality in Deep power-down mode.
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Chapter 5: LPC15xx Boot process
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5.1 How to read this chapter
USB drivers and the USB boot option are available on parts LPC1549/48/47 only.
5.2 Features
• 32 kB on-chip boot ROM
• Contains the boot loader with In-System Programming (ISP) facility and the following
APIs:
– In-Application Programming (IAP) of flash memory
– Power profiles for optimizing power consumption and system performance and for
controlling low power modes
– USART drivers
– C_CAN drivers
– I2C drivers
– DMA drivers
– SPI drivers
5.3 Pin description
The parts support ISP via the USART0, C_CAN, or USB interfaces. The ISP mode is
determined by the state of two pins at boot time:
Table 89.
ISP modes
ISP mode
ISP_0
ISP_1
Description
No ISP
HIGH
HIGH
ISP bypassed. Part attempts to boot from flash.
If the part is not programmed or contains invalid user
code, this mode will enter ISP via USB.
Remark: If IAP function Reinvoke ISP is called, and
both ISP pins are HIGH, the part enters one of the ISP
mode depending on the parameter passed with the
IAP function. See Table 508.
C_CAN
HIGH
LOW
Part enters ISP via C_CAN.
USB
LOW
HIGH
Part enters ISP via USB.
USART0
LOW
LOW
Part enters ISP via USART0.
The ISP pin assignment is different for each package, so that the fewest functions
possible are blocked. No more than four pins must be set aside for entering ISP in any
ISP mode. The boot code assigns two ISP pins for each package which are probed when
the part boots to determine whether or not to enter ISP mode. Once the ISP mode has
been determined, the boot loader configures the necessary serial pins for each package.
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Chapter 5: LPC15xx Boot process
Pins which are not configured by the boot loader for the selected boot mode (for example
CAN0_RD and CAN0_TD in USART mode) can be assigned to any function through the
switch matrix.
Table 90.
ISP pin assignments
ISP pin
LQFP48
LQFP64
LQFP100
ISP_0
PIO0_4
PIO1_9
PIO2_5
ISP_1
PIO0_16
PIO1_11
PIO2_4
U0_TXD
PIO0_15
PIO0_18
PIO2_6
U0_RXD
PIO0_14
PIO0_13
PIO2_7
CAN0_TD
PIO0_18
PIO0_31
PIO2_8
CAN0_RD
PIO0_13
PIO0_11
PIO2_9
PIO0_16
PIO1_11
PIO2_4
USART mode
C_CAN mode
USB mode
USB_VBUS (same as ISP_1)
Table 91.
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Default pin assignments for different ISP modes
Symbol
LQFP48
LQFP64
LQFP100
PIO0_4/ADC0_4
ISP_0
-
-
PIO0_11/ADC1_3
-
CAN0_RD (C_CAN
mode only)
-
PIO0_13/ADC1_6
CAN0_RD (C_CAN
mode only)
U0_RXD (USART
mode only)
-
PIO0_14/ADC1_7/
SCT1_OUT5
U0_RXD (USART
mode only)
-
-
PIO0_15/ADC1_8
U0_TXD (USART
mode only)
-
-
PIO0_16/ADC1_9
ISP_1. In USB mode
also USB_VBUS.
-
-
PIO0_18/SCT0_OUT5
CAN0_TD (C_CAN
mode only)
U0_TXD (USART
mode only)
-
PIO0_31/ADC0_9
-
CAN0_TD (C_CAN
mode only)
-
PIO1_9/ACMP2_I4
-
ISP_0
-
PIO1_11
-
ISP_1. In USB mode
also USB_VBUS.
-
PIO2_4
-
-
ISP_1. In USB mode
also USB_VBUS.
PIO2_5
-
-
ISP_0
PIO2_6
-
-
U0_TXD (USART
mode only)
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Chapter 5: LPC15xx Boot process
Table 91.
Default pin assignments for different ISP modes …continued
Symbol
LQFP48
LQFP64
LQFP100
PIO2_7
-
-
U0_RXD (USART
mode only)
PIO2_8
-
-
CAN0_TD (C_CAN
mode only)
PIO2_9
-
-
CAN0_RD (C_CAN
mode only)
5.4 General description
The boot loader controls initial operation after reset and also provides the means to
program the flash memory. This could be initial programming of a blank device, erasure
and re-programming of a previously programmed device, or programming of the flash
memory by the application program in a running system.
The boot loader code is executed every time the part is powered on or reset (see
Figure 7). The loader can execute the ISP command handler or the user application code.
See Table 89 “ISP modes” for different boot modes.
The boot loader version can be read by ISP/IAP calls (see Table 492 or Table 506).
Assuming that power supply pins are at their nominal levels when the rising edge on
RESET pin is generated, it may take up to 3 ms before the boot pins are sampled and the
decision whether to continue with user code or ISP handler is made. If the boot pins are
sampled LOW and the watchdog overflow flag is set, the external hardware request to
start the ISP command handler is ignored. If there is no request for the ISP command
handler execution, a search is made for a valid user program. If a valid user program is
found then the execution control is transferred to it. If a valid user program is not found,
the auto-baud routine is invoked.
Remark: In USB ISP mode, an external 12 MHz crystal is required to communicate with
the external storage device.
See Chapter 34 “LPC15xx Flash/EEPROM API” for the ISP and IAP commands.
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Chapter 5: LPC15xx Boot process
5.4.1 Boot process flowchart
RESET
INITIALIZE
CRP1/2/3
ENABLED?
no
ENABLE DEBUG
yes
WATCHDOG
FLAG SET?
A
yes
no
USER CODE
VALID?
CRP3/NO_ISP
ENABLED?
yes
no
no
yes
EXECUTE INTERNAL
USER CODE
no
ENTER ISP
MODE?
yes
ISP_0 = HIGH
ISP_1 = HIGH
user code
not valid
yes
ISP_0 = LOW
ISP_1 = HIGH
ISP_0 = LOW
ISP_1 = LOW
yes
yes
ENUMERATE AS MSC
DEVICE TO PC
USER CODE
VALID?
ISP_0 = HIGH
ISP_1 = LOW
yes
RUN AUTO-BAUD
INIT C_CAN
no
no
yes
AUTO-BAUD
SUCCESSFUL?
yes
RECEIVE CRYSTAL FREQUENCY
A
RUN ISP COMMAND HANDLER
Fig 7.
Boot process flowchart
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Chapter 5: LPC15xx Boot process
5.4.2 Criterion for valid user code
The reserved ARM Cortex-M3 exception vector location 7 (offset 0x0000 001C in the
vector table) should contain the 2’s complement of the check-sum of table entries 0
through 6. This causes the checksum of the first 8 table entries to be 0. The boot loader
code checksums the first 8 locations in sector 0 of the flash. If the result is 0, then
execution control is transferred to the user code.
If the signature is not valid, the part enumerates as a USB MSC device. See Figure 7
“Boot process flowchart” and Section 34.5 “USB communication protocol”.
5.4.3 ROM-based APIs
Once the part has booted, the user code can access several APIs located in the boot
ROM to access the flash memory, optimize power consumption, and operate the
peripherals.
The location of the APIs in boot ROM is shown in Figure 8.
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Chapter 5: LPC15xx Boot process
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Table 92.
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API reference
API
Description
Reference
Flash IAP
Flash In-Application programming
Table 500
USB API
USB driver
Section 42.3.1
C_CAN API
C_CAN driver
Table 583
Power profiles API
Configure system clock and power consumption.
Control low power modes and wake-up.
Table 514
I2C driver
I2C ROM driver
Table 542
DMA driver
DMA ROM driver
Table 531
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Chapter 5: LPC15xx Boot process
Table 92.
API reference
API
Description
Reference
SPI driver
SPI ROM driver
Table 575
ADC driver
ADC ROM driver
Table 563
USART driver
USART ROM driver for USART0/1/2
Table 521
typedef struct {
const USBD_API_T *pUSBD; /*!< USBD API function table base address */
const uint32_t reserved0; /*!< Reserved */
const CAND_API_T *pCAND; /*!< C_CAN API function table base address */
const PWRD_API_T *pPWRD; /*!< Power API function table base address */
const reserved1;
/*!< reserved */
const I2CD_API_T *pI2CD; /*!< I2C driver API function table base address */
const DMAD_API_T *pDMAD; /*!< DMA driver API function table base address */
const SPID_API_T *pSPID; /*!< SPI driver API function table base address */
const ADCD_API_T *pADCD; /*!< ADC driver API function table base address */
const UARTD_API_T *pUARTD; /*!< USART driver API function table base address */
} LPC_ROM_API_T;
#define ROM_DRIVER_BASE (0x03000200UL)
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Chapter 6: LPC15xx Pin description
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6.1 Pin description
PIO0_0/ADC0_10/
SCT0_OUT3
LQFP100
Symbol
LQFP64
Pin description
LQFP48
Table 93.
1
2
2
PIO0_1/ADC0_7/
SCT0_OUT4
2
PIO0_2/ADC0_6/
SCT1_OUT3
3
PIO0_3/ADC0_5/
SCT1_OUT4
PIO0_4/ADC0_4
PIO0_5/ADC0_3
PIO0_6/ADC0_2/
SCT2_OUT3
5
6
6
8
[2]
[2]
[2]
Reset Type
state[1]
Description
I; PU
IO
PIO0_0 — General purpose port 0 input/output 0.
A
ADC0_10 — ADC0 input 10.
O
SCT0_OUT3 — SCTimer0/PWM output 3.
IO
PIO0_1 — General purpose port 0 input/output 1.
A
ADC0_7 — ADC0 input 7.
O
SCT0_OUT4 — SCTimer0/PWM output 4.
IO
PIO0_2 — General purpose port 0 input/output 2.
I; PU
I; PU
ADC0_6 — ADC0 input 6.
4
5
6
7
7
8
9
10
10
[2]
13
[2]
14
[2]
16
[2]
PIO0_7/ADC0_1
8
11
17
[2]
PIO0_8/ADC0_0/TDO
9
12
19
[2]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
O
SCT1_OUT3 — SCTimer1/PWM output 3.
IO
PIO0_3 — General purpose port 0 input/output 3.
A
ADC0_5 — ADC0 input 5.
O
SCT1_OUT4 — SCTimer1/PWM output 4.
IO
PIO0_4 — General purpose port 0 input/output 4. This is
the ISP_0 boot pin for the LQFP48 package.
A
ADC0_4 — ADC0 input 4.
IO
PIO0_5 — General purpose port 0 input/output 5.
A
ADC0_3 — ADC0 input 3.
IO
PIO0_6 — General purpose port 0 input/output 6.
A
ADC0_2 — ADC0 input 2.
O
SCT2_OUT3 — SCTimer2/PWM output 3.
IO
PIO0_7 — General purpose port 0 input/output 7.
A
ADC0_1 — ADC0 input 1.
IO
PIO0_8 — General purpose port 0 input/output 8.
In boundary scan mode: TDO (Test Data Out).
PIO0_9/ADC1_1/TDI
12
16
24
[2]
I; PU
A
ADC0_0 — ADC0 input 0.
IO
PIO0_9 — General purpose port 0 input/output 9.
In boundary scan mode: TDI (Test Data In).
PIO0_10/ADC1_2
PIO0_11/ADC1_3
15
18
19
23
28
[2]
33
[2]
I; PU
I; PU
A
ADC1_1 — ADC1 input 1.
IO
PIO0_10 — General purpose port 0 input/output 10.
A
ADC1_2 — ADC1 input 2.
IO
PIO0_11 — General purpose port 0 input/output 11.
On the LQFP64 package, this pin is assigned to
CAN0_RD in ISP C_CAN mode.
A
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ADC1_3 — ADC1 input 3.
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PIO0_13/ADC1_6
LQFP100
PIO0_12/DAC_OUT
LQFP64
Pin description
Symbol
LQFP48
Table 93.
19
24
35
21
29
[3]
43
[2]
Reset Type
state[1]
Description
I; PU
IO
PIO0_12 — General purpose port 0 input/output 12. If this
pin is configured as a digital input, the input voltage level
must not be higher than VDDA.
A
DAC_OUT — DAC analog output.
IO
PIO0_13 — General purpose port 0 input/output 13.
I; PU
On the LQFP64 package, this pin is assigned to U0_RXD
in ISP USART mode.
On the LQFP48 package, this pin is assigned to
CAN0_RD in ISP C_CAN mode.
PIO0_14/ADC1_7/
SCT1_OUT5
PIO0_15/ADC1_8
22
30
45
[2]
I; PU
A
ADC1_6 — ADC1 input 6.
IO
PIO0_14 — General purpose port 0 input/output 14.
On the LQFP48 package, this pin is assigned to U0_RXD
in ISP USART mode.
23
31
47
[2]
I; PU
A
ADC1_7 — ADC1 input 7.
O
SCT1_OUT5 — SCTimer1/PWM output 5.
IO
PIO0_15 — General purpose port 0 input/output 15.
On the LQFP48 package, this pin is assigned to U0_TXD
in ISP USART mode.
PIO0_16/ADC1_9
24
32
49
[2]
I; PU
A
ADC1_8 — ADC1 input 8.
IO
PIO0_16 — General purpose port 0 input/output 16.
On the LQFP48 package, this is the ISP_1 boot pin.
PIO0_17/WAKEUP/
TRST
28
39
61
[4]
I; PU
A
ADC1_9 — ADC1 input 9.
IO
PIO0_17 — General purpose port 0 input/output 17. In
boundary scan mode: TRST (Test Reset).
This pin triggers a wake-up from Deep power-down mode.
If you need to wake up from Deep power-down mode via
an external pin, do not assign any movable function to this
pin. Pull this pin HIGH externally while in Deep
power-down mode. Pull this pin LOW to exit Deep
power-down mode. A LOW-going pulse as short as 50 ns
wakes up the part.
PIO0_18/
SCT0_OUT5
13
17
26
[5]
I; PU
IO
PIO0_18 — General purpose port 0 input/output 18.
On the LQFP64 package, this pin is assigned to U0_TXD
in ISP USART mode.
On the LQFP48 package, this pin is assigned to
CAN0_TD in ISP C_CAN mode.
SWCLK/
PIO0_19/TCK
29
40
63
[5]
I; PU
O
SCT0_OUT5 — SCTimer0/PWM output 5.
I
SWCLK — Serial Wire Clock. SWCLK is enabled by
default on this pin.
In boundary scan mode: TCK (Test Clock).
IO
UM10736
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PIO0_19 — General purpose port 0 input/output 19.
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RESET/PIO0_21
LQFP100
SWDIO/
PIO0_20/SCT1_OUT6/
TMS
LQFP64
Pin description
Symbol
LQFP48
Table 93.
33
44
69
[5]
Reset Type
state[1]
Description
I; PU
SWDIO — Serial Wire Debug I/O. SWDIO is enabled by
default on this pin.
I/O
In boundary scan mode: TMS (Test Mode Select).
34
45
71
[6]
I; PU
I/O
PIO0_20 — General purpose port 0 input/output 20.
O
SCT1_OUT6 — SCTimer1/PWM output 6.
I
RESET — External reset input: A LOW-going pulse as
short as 50 ns on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and
processor execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH
externally. The RESET pin can be left unconnected or be
used as a GPIO or for any movable function if an external
RESET function is not needed.
PIO0_22/I2C0_SCL
PIO0_23/I2C0_SDA
37
38
49
50
78
79
[7]
[7]
IA
IA
PIO0_24/SCT0_OUT6
43
58
90
[8]
I; PU
PIO0_25/ACMP0_I4
44
60
93
[2]
I; PU
95
[2]
PIO0_26/ACMP0_I3/
SCT3_OUT3
PIO0_27/ACMP_I1
PIO0_28/ACMP1_I3
45
46
47
PIO0_29/ACMP2_I3/
SCT2_OUT4
48
PIO0_30/ADC0_11
-
UM10736
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61
62
63
64
1
97
[2]
98
[2]
100
1
[2]
[2]
I; PU
I; PU
I; PU
I; PU
I; PU
I/O
PIO0_21 — General purpose port 0 input/output 21.
IO
PIO0_22 — General purpose port 0 input/output 22.
I/O
I2C0_SCL — I2C-bus clock input/output. High-current sink
if I2C Fast-mode Plus is selected in the I/O configuration
register.
IO
PIO0_23 — General purpose port 0 input/output 23.
I/O
I2C0_SDA — I2C-bus data input/output. High-current sink
if I2C Fast-mode Plus is selected in the I/O configuration
register.
IO
PIO0_24 — General purpose port 0 input/output 24.
High-current output driver.
O
SCT0_OUT6 — SCTimer0/PWM output 6.
IO
PIO0_25 — General purpose port 0 input/output 25.
A
ACMP0_I4 — Analog comparator 0 input 4.
IO
PIO0_26 — General purpose port 0 input/output 26.
A
ACMP0_I3 — Analog comparator 0 input 3.
O
SCT3_OUT3 — SCTimer3/PWM output 3.
IO
PIO0_27 — General purpose port 0 input/output 27.
A
ACMP_I1 — Analog comparator common input 1.
IO
PIO0_28 — General purpose port 0 input/output 28.
A
ACMP1_I3 — Analog comparator 1 input 3.
IO
PIO0_29 — General purpose port 0 input/output 29.
A
ACMP2_I3 — Analog comparator 2 input 3.
O
SCT2_OUT4 — SCTimer2/PWM output 4.
IO
PIO0_30 — General purpose port 0 input/output 30.
A
ADC0_11 — ADC0 input 11.
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Chapter 6: LPC15xx Pin description
LQFP100
PIO0_31/ADC0_9
LQFP64
Pin description
Symbol
LQFP48
Table 93.
-
3
3
[2]
Reset Type
state[1]
Description
I; PU
PIO0_31 — General purpose port 0 input/output 31.
IO
On the LQFP64 package, this pin is assigned to
CAN0_TD in ISP C_CAN mode.
PIO1_0/ADC0_8
-
4
5
[2]
I; PU
I; PU
I; PU
PIO1_1/ADC1_0
-
15
23
[2]
PIO1_2/ADC1_4
-
25
36
[2]
I; PU
I; PU
PIO1_3/ADC1_5
-
28
41
[2]
PIO1_4/ADC1_10
-
33
51
[2]
I; PU
I; PU
PIO1_5/ADC1_11
-
34
52
[2]
PIO1_6/ACMP_I2
-
46
73
[2]
I; PU
I; PU
PIO1_7/ACMP3_I4
-
51
81
[2]
PIO1_8/ACMP3_I3/
SCT3_OUT4
-
53
84
[2]
PIO1_9/ACMP2_I4
-
54
85
[2]
I; PU
A
ADC0_9 — ADC0 input 9.
IO
PIO1_0 — General purpose port 1 input/output 0.
A
ADC0_8 — ADC0 input 8.
IO
PIO1_1 — General purpose port 1 input/output 1.
A
ADC1_0 — ADC1 input 0.
IO
PIO1_2 — General purpose port 1 input/output 2.
A
ADC1_4 — ADC1 input 4.
IO
PIO1_3 — General purpose port 1 input/output 3.
A
ADC1_5 — ADC1 input 5.
IO
PIO1_4 — General purpose port 1 input/output 4.
A
ADC1_10 — ADC1 input 10.
IO
PIO1_5 — General purpose port 1 input/output 5.
A
ADC1_11 — ADC1 input 11.
IO
PIO1_6 — General purpose port 1 input/output 6.
A
ACMP_I2 — Analog comparator common input 2.
IO
PIO1_7 — General purpose port 1 input/output 7.
A
ACMP3_I4 — Analog comparator 3 input 4.
IO
PIO1_8 — General purpose port 1 input/output 8.
A
ACMP3_I3 — Analog comparator 3 input 3.
O
SCT3_OUT4 — SCTimer3/PWM output 4.
IO
PIO1_9 — General purpose port 1 input/output 9.
On the LQFP64 package, this is the ISP_0 boot pin.
A
PIO1_10/ACMP1_I4
-
59
91
[2]
I; PU
ACMP2_I4 — Analog comparator 2 input 4.
IO
PIO1_10 — General purpose port 1 input/output 10.
A
ACMP1_I4 — Analog comparator 1 input 4.
PIO1_11 — General purpose port 1 input/output 11.
PIO1_11
-
38
58
[5]
I; PU
IO
PIO1_12
-
-
9
[5]
I; PU
IO
PIO1_12 — General purpose port 1 input/output 12.
11
[5]
I; PU
IO
PIO1_13 — General purpose port 1 input/output 13.
I; PU
IO
PIO1_14 — General purpose port 1 input/output 14.
On the LQFP64 package, this is the ISP_1 boot pin.
PIO1_13
-
-
PIO1_14/SCT0_OUT7
-
-
12
[5]
O
SCT0_OUT7 — SCTimer0/PWM output 7.
PIO1_15
-
-
15
[5]
I; PU
IO
PIO1_15 — General purpose port 1 input/output 15.
18
[5]
I; PU
IO
PIO1_16 — General purpose port 1 input/output 16.
I; PU
IO
PIO1_17 — General purpose port 1 input/output 17.
O
SCT1_OUT7 — SCTimer1/PWM output 7.
I; PU
IO
PIO1_18 — General purpose port 1 input/output 18.
PIO1_16
-
-
PIO1_17/SCT1_OUT7
-
-
20
[5]
PIO1_18
-
-
25
[5]
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Chapter 6: LPC15xx Pin description
Table 93.
Pin description
LQFP100
Description
LQFP64
Reset Type
state[1]
LQFP48
Symbol
PIO1_19
-
-
29
[5]
I; PU
IO
PIO1_19 — General purpose port 1 input/output 19.
PIO1_20/SCT2_OUT5
-
-
34
[5]
I; PU
IO
PIO1_20 — General purpose port 1 input/output 20.
O
SCT2_OUT5 — SCTimer2/PWM output 5.
37
[5]
I; PU
IO
PIO1_21 — General purpose port 1 input/output 21.
PIO1_21
-
-
PIO1_22
-
-
38
[5]
I; PU
IO
PIO1_22 — General purpose port 1 input/output 22.
PIO1_23
-
-
42
[5]
I; PU
IO
PIO1_23 — General purpose port 1 input/output 23.
44
[5]
I; PU
IO
PIO1_24 — General purpose port 1 input/output 24.
O
SCT3_OUT5 — SCTimer3/PWM output 5.
PIO1_24/SCT3_OUT5
-
-
PIO1_25
-
-
46
[5]
I; PU
IO
PIO1_25 — General purpose port 1 input/output 25.
PIO1_26
-
-
48
[5]
I; PU
IO
PIO1_26 — General purpose port 1 input/output 26.
50
[5]
I; PU
IO
PIO1_27 — General purpose port 1 input/output 27.
55
[5]
I; PU
IO
PIO1_28 — General purpose port 1 input/output 28.
PIO1_27
PIO1_28
-
-
PIO1_29
-
-
56
[5]
I; PU
IO
PIO1_29 — General purpose port 1 input/output 29.
PIO1_30
-
-
59
[5]
I; PU
IO
PIO1_30 — General purpose port 1 input/output 30.
60
[5]
I; PU
IO
PIO1_31 — General purpose port 1 input/output 31.
62
[5]
I; PU
IO
PIO2_0 — General purpose port 2 input/output 0.
PIO1_31
PIO2_0
-
-
PIO2_1
-
-
64
[5]
I; PU
IO
PIO2_1 — General purpose port 2 input/output 1.
PIO2_2
-
-
72
[5]
I; PU
IO
PIO2_2 — General purpose port 2 input/output 2.
76
[5]
I; PU
IO
PIO2_3 — General purpose port 2 input/output 3.
77
[5]
I; PU
IO
PIO2_4 — General purpose port 2 input/output 4.
I; PU
IO
I; PU
IO
PIO2_3
PIO2_4
-
-
On the LQFP100 package, this is the ISP_1 boot pin.
PIO2_5
-
-
80
[5]
PIO2_6
-
-
82
[5]
PIO2_5 — General purpose port 2 input/output 5.
On the LQFP100 package, this is the ISP_0 boot pin.
PIO2_6 — General purpose port 2 input/output 6.
On the LQFP100 package, this pin is assigned to U0_TXD
in ISP USART mode.
PIO2_7
-
-
86
[5]
I; PU
IO
PIO2_7 — General purpose port 2 input/output 7.
On the LQFP100 package, this pin is assigned to
U0_RXD in ISP USART mode.
PIO2_8
-
-
92
[5]
I; PU
IO
PIO2_8 — General purpose port 2 input/output 8.
On the LQFP100 package, this pin is assigned to
CAN0_TD in ISP C_CAN mode.
PIO2_9
-
-
94
[5]
I; PU
IO
PIO2_9 — General purpose port 2 input/output 9.
On the LQFP100 package, this pin is assigned to
CAN0_RD in ISP C_CAN mode.
PIO2_10
PIO2_11
-
-
96
[5]
I; PU
IO
PIO2_10 — General purpose port 2 input/output 10.
99
[5]
I; PU
IO
PIO2_11 — General purpose port 2 input/output 11.
I; PU
IO
PIO2_12 — General purpose port 2 input/output 12. On
parts LPC1519/17/18 only.
I; PU
IO
PIO2_13 — General purpose port 2 input/output 13. On
parts LPC1519/17/18 only.
PIO2_12
35
47
74
[5]
PIO2_13
36
48
75
[5]
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Chapter 6: LPC15xx Pin description
Table 93.
Pin description
LQFP100
Description
LQFP64
Reset Type
state[1]
LQFP48
Symbol
USB_DP
35
47
74
[10]
-
IO
USB bidirectional D+ line. Pad includes internal 33 Ω
series termination resistor. On parts LPC1549/48/47 only.
USB_DM
36
48
75
[10]
-
IO
USB bidirectional D line. Pad includes internal 33 Ω
series termination resistor. On parts LPC1549/48/47 only.
RTCXIN
31
42
66
[9]
-
RTC oscillator input. This input should be grounded if the
RTC is not used.
RTCXOUT
32
43
67
[9]
-
RTC oscillator output.
-
Input to the oscillator circuit and internal clock generator
circuits. Input voltage must not exceed 1.8 V.
-
Output from the oscillator amplifier.
XTALIN
26
36
54
[9]
XTALOUT
25
35
53
[9]
VBAT
30
41
65
-
Battery supply voltage. If no battery is used, tie VBAT to
VDD or to ground.
VDDA
16
20
30
-
Analog supply voltage. VDD and the analog reference
voltages VREFP_ADC and VREFP_DAC_VDDCMP must
not exceed the voltage level on VDDA. VDDAshould typically
be the same voltages as VDD but should be isolated to
minimize noise and error. VDDA should be tied to VDD if the
ADC is not used.
VDD
39,
27,
42
22,
52,
37,
57
4,
32,
70,
83,
57,
89
-
3.3 V supply voltage (2.4 V to 3.6 V). The voltage level on
VDD must be equal or lower than the analog supply
voltage VDDA.
VREFP_DAC_VDDCMP 14
18
27
-
DAC positive reference voltage and analog comparator
reference voltage. The voltage level on
VREFP_DAC_VDDCMP must be equal to or lower than
the voltage applied to VDDA.
VREFN
11
14
22
-
ADC and DAC negative voltage reference. If the ADC is
not used, tie VREFN to VSS.
VREFP_ADC
10
13
21
-
ADC positive reference voltage. The voltage level on
VREFP_ADC must be equal to or lower than the voltage
applied to VDDA. If the ADC is not used, tie VREFP_ADC
to VDD.
VSSA
17
21
31
-
Analog ground. VSSAshould typically be the same voltage
as VSS but should be isolated to minimize noise and error.
VSSA should be tied to VSS if the ADC is not used.
VSS
41,
20,
40
56,
26,
27,
55
88,
7,
39,
40,
68,
87
-
Ground.
[1]
[9]
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.
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[2]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as analog input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin includes a 10 ns on/off
glitch filter. By default, the glitch filter is turned on.
[3]
This pin is not 5 V tolerant due to special analog functionality. When configured for a digital function, this pin is 3 V tolerant and provides
standard digital I/O functions with configurable internal pull-up and pull-down resistors and hysteresis. When configured for DAC_OUT,
the digital section of the pin is disabled and this pin is a 3 V tolerant analog output. This pin includes a 10 ns on/off glitch filter. By default,
the glitch filter is turned on.
[4]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, and configurable hysteresis. This pin
includes a 10 ns on/off glitch filter. By default, the glitch filter is turned on. This pin is powered in deep power-down mode and can wake
up the part.
[5]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[6]
5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.
[7]
I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus.
[8]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes
high-current output driver.
[9]
Special analog pin.
[10] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only). This pad is not 5 V tolerant.
Table 94.
UM10736
User manual
Movable functions
Function name
Type
Description
U0_TXD
O
Transmitter output for USART0.
U0_RXD
I
Receiver input for USART0.
U0_RTS
O
Request To Send output for USART0.
U0_CTS
I
Clear To Send input for USART0.
U0_SCLK
I/O
Serial clock input/output for USART0 in synchronous mode.
U1_TXD
O
Transmitter output for USART1.
U1_RXD
I
Receiver input for USART1.
U1_RTS
O
Request To Send output for USART1.
U1_CTS
I
Clear To Send input for USART1.
U1_SCLK
I/O
Serial clock input/output for USART1 in synchronous mode.
U2_TXD
O
Transmitter output for USART2.
U2_RXD
I
Receiver input for USART2.
U2_SCLK
I/O
Serial clock input/output for USART1 in synchronous mode.
SPI0_SCK
I/O
Serial clock for SPI0.
SPI0_MOSI
I/O
Master Out Slave In for SPI0.
SPI0_MISO
I/O
Master In Slave Out for SPI0.
SPI0_SSEL0
I/O
Slave select 0 for SPI0.
SPI0_SSEL1
I/O
Slave select 1 for SPI0.
SPI0_SSEL2
I/O
Slave select 2 for SPI0.
SPI0_SSEL3
I/O
Slave select 3 for SPI0.
SPI1_SCK
I/O
Serial clock for SPI1.
SPI1_MOSI
I/O
Master Out Slave In for SPI1.
SPI1_MISO
I/O
Master In Slave Out for SPI1.
SPI1_SSEL0
I/O
Slave select 0 for SPI1.
SPI1_SSEL1
I/O
Slave select 1 for SPI1.
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Chapter 6: LPC15xx Pin description
Table 94.
UM10736
User manual
Movable functions …continued
Function name
Type
Description
CAN0_TD
O
CAN0 transmit.
CAN0_RD
I
CAN0 receive.
USB_VBUS
I
USB VBUS.
SCT0_OUT0
O
SCTimer0/PWM output 0.
SCT0_OUT1
O
SCTimer0/PWM output 1.
SCT0_OUT2
O
SCTimer0/PWM output 2.
SCT1_OUT0
O
SCTimer1/PWM output 0.
SCT1_OUT1
O
SCTimer1/PWM output 1.
SCT1_OUT2
O
SCTimer1/PWM output 2.
SCT2_OUT0
O
SCTimer2/PWM output 0.
SCT2_OUT1
O
SCTimer2/PWM output 1.
SCT2_OUT2
O
SCTimer2/PWM output 2.
SCT3_OUT0
O
SCTimer3/PWM output 0.
SCT3_OUT1
O
SCTimer3/PWM output 1.
SCT3_OUT2
O
SCTimer3/PWM output 2.
SCT_ABORT0
I
SCT abort 0.
SCT_ABORT1
I
SCT abort 1.
ADC0_PINTRIG0
I
ADC0 external pin trigger input 0.
ADC0_PINTRIG1
I
ADC0 external pin trigger input 1.
ADC1_PINTRIG0
I
ADC1 external pin trigger input 0.
ADC1_PINTRIG1
I
ADC1 external pin trigger input 1.
DAC_PINTRIG
I
DAC external pin trigger input.
DAC_SHUTOFF
I
DAC shut-off external input.
ACMP0_O
O
Analog comparator 0 output.
ACMP1_O
O
Analog comparator 1 output.
ACMP2_O
O
Analog comparator 2 output.
ACMP3_O
O
Analog comparator 3 output.
CLKOUT
O
Clock output.
ROSC
O
Analog comparator ring oscillator output.
ROSC_RESET
I
Analog comparator ring oscillator reset.
USB_FTOGGLE
O
USB frame toggle. Do not assign this function to a pin until a USB
device is connected and the first SOF interrupt has been received
by the device.
QEI_PHA
I
QEI phase A input.
QEI_PHB
I
QEI phase B input.
QEI_IDX
I
QEI index input.
GPIO_INT_BMAT
O
Output of the pattern match engine.
SWO
O
Serial wire output.
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Chapter 6: LPC15xx Pin description
LQFP64
LQFP100
Pins connected to the INPUT MUX and SCT IPU
LQFP48
Table 95.
Symbol
Description
PIO0_2/ADC0_6/SCT1_OUT3
3
6
8
SCT0 input mux
PIO0_3/ADC0_5/SCT1_OUT4
4
7
10
SCT0 input mux
PIO0_4/ADC0_4
5
8
13
SCT2 input mux
PIO0_5/ADC0_3
6
9
14
FREQMEAS
PIO0_7/ADC0_1
8
11
17
SCT3 input mux
PIO0_14/ADC1_7/SCT1_OUT5
22
30
45
SCTIPU input SAMPLE_IN_A0
PIO0_15/ADC1_8
23
31
47
SCT1 input mux
PIO0_16/ADC1_9
24
32
49
SCT1 input mux
PIO0_17/WAKEUP/TRST
28
39
61
SCT0 input mux
SWCLK/PIO0_19/TCK
29
40
63
FREQMEAS
RESET/PIO0_21
34
45
71
SCT1 input mux
PIO0_25/ACMP0_I4
44
60
93
SCTIPU input SAMPLE_IN_A1
PIO0_27/ACMP_I1
46
62
97
SCT2 input mux
PIO0_30/ADC0_11
-
1
1
FREQMEAS
PIO0_31/ADC0_9
-
3
3
SCT1 input mux
PIO1_4/ADC1_10
-
33
51
SCT1 input mux
PIO1_5/ADC1_11
-
34
52
SCT1 input mux
SCT0 input mux
PIO1_6/ACMP_I2
-
46
73
SCT0 input mux
PIO1_7/ACMP3_I4
-
51
81
SCT0 input mux
PIO1_11
-
38
58
SCT3 input mux
SCTIPU input SAMPLE_IN_A2
UM10736
User manual
PIO1_12
-
-
9
SCT0 input mux
PIO1_13
-
-
11
SCT0 input mux
PIO1_15
-
-
12
SCT1 input mux
PIO1_16
-
-
18
SCT1 input mux
PIO1_18
-
-
25
SCT2 input mux
PIO1_19
-
-
29
SCT2 input mux
PIO1_21
-
-
37
SCT3 input mux
PIO1_22
-
-
38
SCT3 input mux
PIO1_26
-
-
48
SCTIPU input SAMPLE_IN_A3
PIO1_27
-
-
50
FREQMEAS
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
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User manual
7.1 How to read this chapter
The IOCON block is identical for all LPC15xx parts. Registers for pins that are not
available on a specific package are reserved.
Table 96.
Available pin configuration registers
Package
GPIO Port 0
GPIO Port 1
GPIO Port 2
Pins/configuration registers available
LQFP48
PIO0_0 to PIO0_29
-
-
LQFP64
PIO0_0 to PIO0_31
PIO1_0 to PIO1_11
-
LQFP100
PIO0_0 to PIO0_31
PIO1_0 to PIO1_31
PIO2_0 to PIO2_11
7.2 Features
The following electrical properties are configurable for each pin:
•
•
•
•
•
Pull-up/pull-down resistor
Open-drain mode
Hysteresis
Digital filter with programmable time constant
10 ns, digital glitch filter on selected pins
The true open-drain pins PIO0_22 and PIO0_23 can be configured for different I2C-bus
speeds.
The switch matrix configures a pin for its analog function automatically, when the analog
function is enabled in the PINENABLEn registers.
7.3 Basic configuration
Enable the clock to the IOCON in the SYSAHBCLKCTRL0 register (Table 50, bit 13).
Once the pins are configured, you can disable the IOCON clock to conserve power.
Each pin has a programmable digital input filter. The base clock for the filter is the output
of the IOCONCLKDIV clock divider in the SYSCON block (see Table 54). The base clock
can be divided individually for each pin to create the glitch filter constant in each digital pin
configuration register.
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
,2&21
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Fig 9.
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IOCON clocking
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
7.4 General description
7.4.1 Pin configuration
9''
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Fig 10. Pin configuration
7.4.2 Pin function
The pin function is determined entirely through the switch matrix. By default one GPIO
function is assigned to each pin. The switch matrix can assign all functions from the
movable function table to any pin in the IOCON block or enable a special function like an
analog input on a specific pin.
Related links:
Section 8.4.2 “Movable functions”
7.4.3 Pin mode
The MODE bit in the IOCON register allows enabling or disabling an on-chip pull-up
resistor for each pin. By default all pull-up resistors are enabled except for the I2C-bus
pins PIO0_22 and PIO0_23, which do not have a programmable pull-up resistor.
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
The repeater mode enables the pull-up resistor if the pin is high and enables the
pull-down resistor if the pin is low. This causes the pin to retain its last known state if it is
configured as an input and is not driven externally. Repeater mode may typically be used
to prevent a pin from floating (and potentially using significant power if it floats to an
indeterminate state) if it is temporarily not driven.
7.4.4 Open-drain mode
An open-drain mode can be enabled for all digital I/O pins that are not the I2C-bus pins.
This mode is not a true open-drain mode. The input cannot be pulled up above VDD.
Remark: As opposed to the true open-drain I2C-bus pins, digital pins with configurable
open-drain mode are not 5 V tolerant when VDD = 0.
7.4.5 Analog mode
The switch matrix automatically configures the pin in analog mode whenever an analog
input or output is selected as the pin’s function through the switch matrix PINENABLE
registers.
When using a pin in analog mode, disable the pull-up and pull-down resistors.
7.4.6 I2C-bus mode
The I2C-bus pins PIO0_22 and PIO0_23 can be programmed to support a true open-drain
mode independently of whether the I2C function is selected or another digital function. If
the I2C function is selected, all three I2C modes, Standard mode, Fast-mode, and
Fast-mode plus, are supported. A digital glitch filter can be configured for all functions.
Pins PIO0_22 and PIO0_23 operate as high-current sink drivers (20 mA) independently of
the programmed function.
7.4.7 Input glitch filter
Selected pins (see Section 7.5.1 “Digital pin control registers with glitch filter on port 0”)
provide the option of turning on or off a 10 ns input glitch filter. The glitch filter is turned on
by default. The RESET pin has a 20 ns glitch filter (not configurable).
7.4.8 Programmable digital filter
All GPIO pins are equipped with a programmable digital filter. The filter rejects input
pulses with a selectable duration of shorter than one, two, or three cycles of a filter clock
(S_MODE = 1, 2, or 3). For each individual pin, the filter clock is derived from the main
clock using the IOCONCLKDIV register divided by the CLKDIV value (PCLKn). The filter
can also be bypassed entirely.
Any input pulses of duration Tpulse of either polarity will be rejected if:
Tpulse TPCLKn  S_MODE
Input pulses of one filter clock cycle longer may also be rejected:
Tpulse TPCLKn (S_MODE + 1)
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
Remark: The filtering effect is accomplished by requiring that the input signal be stable for
(S_MODE +1) successive edges of the filter clock before being passed on to the chip.
Enabling the filter results in delaying the signal to the internal logic and should be done
only if specifically required by an application. For high-speed or time critical functions
ensure that the filter is bypassed.
If the delay of the input signal must be minimized, select a faster PCLK and a higher
sample mode (S_MODE) to minimize the effect of the potential extra clock cycle.
If the sensitivity to noise spikes must be minimized, select a slower PCLK and lower
sample mode.
Related registers and links:
Table 54 “IOCON glitch filter clock divider register (IOCONCLKDIV, address 0x4007
40D4) bit description”
7.5 Register description
Each port pin PIOm_n has one IOCON register assigned to control the pin’s electrical
characteristics.
Table 97.
Register overview: I/O configuration (base address 0x400F 8000)
Name
Access Address Description
offset
Reset
value
Reference
PIO0_0 to PIO0_17
R/W
0x000 to Digital I/O control for port 0 pins PIO0_0 to PIO0_17.
0x044
With analog function and glitch filter.
0x90
Table 99
PIO0_18 to PIO0_21 R/W
0x048 to Digital I/O control for port 0 pins PIO0_18 to PIO0_21.
0x054
Without glitch filter.
0x90
Table 100
PIO0_22
R/W
0x058
I/O control for open-drain pin PIO0_22. This pin is used
for the I2C-bus SCL function.
0x90
Table 101
PIO0_23
R/W
0x05C
I/O control for open-drain pin PIO0_23. This pin is used
for the I2C-bus SDA function.
0x90
Table 101
PIO0_24
R/W
0x060
Digital I/O control for port 0 pins PIO0_24. Without glitch
filter.
0x90
Table 100
PIO0_25 to PIO0_31 R/W
0x064 to Digital I/O control for port 0 pins PIO0_25 to
0x07C
PIO0_31.With analog function and glitch filter.
0x90
Table 99
PIO1_0 to PIO1_10
R/W
0x080 to Digital I/O control for port 1 pins PIO1_0 to PIO1_10.
0x0A8
With analog function and glitch filter.
0x90
Table 102
PIO1_11 to PIO1_31
R/W
0x0AC to Digital I/O control for port 1 pins PIO1_11to
0x0FC
PIO1_31.Without glitch filter.
0x90
Table 103
PIO2_0 to PIO2_13
R/W
0x100 to Digital I/O control for port 2 pins PIO2_0 to PIO2_13.
0x134
Without glitch filter.
0x90
Table 104
Table 98.
Digital I/O configuration register types
Name
Address
offset
True
open-drain
Analog
Glitch filter
on/off
Digital
filter
High-drive
output
Reference
PIO0_0
0x000
no
yes
yes
yes
no
Table 99
PIO0_1
0x004
no
yes
yes
yes
no
Table 99
PIO0_2
0x008
no
yes
yes
yes
no
Table 99
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
Table 98.
Digital I/O configuration register types
Name
Address
offset
True
open-drain
Analog
Glitch filter
on/off
Digital
filter
High-drive
output
Reference
PIO0_3
0x00C
no
yes
yes
yes
no
Table 99
PIO0_4
0x010
no
yes
yes
yes
no
Table 99
PIO0_5
0x014
no
yes
yes
yes
no
Table 99
PIO0_6
0x018
no
yes
yes
yes
no
Table 99
PIO0_7
0x01C
no
yes
yes
yes
no
Table 99
PIO0_8
0x020
no
yes
yes
yes
no
Table 99
PIO0_9
0x024
no
yes
yes
yes
no
Table 99
PIO0_10
0x028
no
yes
yes
yes
no
Table 99
PIO0_11
0x02C
no
yes
yes
yes
no
Table 99
PIO0_12
0x030
no
yes
yes
yes
no
Table 99
PIO0_13
0x034
no
yes
yes
yes
no
Table 99
PIO0_14
0x038
no
yes
yes
yes
no
Table 99
PIO0_15
0x03C
no
yes
yes
yes
no
Table 99
PIO0_16
0x040
no
yes
yes
yes
no
Table 99
PIO0_17
0x044
no
yes
yes
yes
no
Table 99
PIO0_18
0x048
no
no
no
yes
no
Table 100
PIO0_19
0x04C
no
no
no
yes
no
Table 100
PIO0_20
0x050
no
no
no
yes
no
Table 100
PIO0_21
0x054
no
no
no
yes
no
Table 100
PIO0_22
0x058
yes
no
no
yes
no
Table 101
PIO0_23
0x05C
yes
no
no
yes
no
Table 101
PIO0_24
0x060
no
no
no
yes
yes
Table 100
PIO0_25
0x064
no
yes
yes
yes
no
Table 99
PIO0_26
0x068
no
yes
yes
yes
no
Table 102
PIO0_27
0x06C
no
yes
yes
yes
no
Table 102
PIO0_28
0x070
no
yes
yes
yes
no
Table 102
PIO0_29
0x074
no
yes
yes
yes
no
Table 102
PIO0_30
0x078
no
yes
yes
yes
no
Table 102
PIO0_31
0x07C
no
yes
yes
yes
no
Table 102
PIO1_0
0x080
no
yes
yes
yes
no
Table 102
PIO1_1
0x084
no
yes
yes
yes
no
Table 102
PIO1_2
0x088
no
yes
yes
yes
no
Table 102
PIO1_3
0x08C
no
yes
yes
yes
no
Table 102
PIO1_4
0x090
no
yes
yes
yes
no
Table 102
PIO1_5
0x094
no
yes
yes
yes
no
Table 102
PIO1_6
0x098
no
yes
yes
yes
no
Table 102
PIO1_7
0x09C
no
yes
yes
yes
no
Table 102
PIO1_8
0x0A0
no
yes
yes
yes
no
Table 102
PIO1_9
0x0A4
no
yes
yes
yes
no
Table 102
PIO1_10
0x0A8
no
yes
yes
yes
no
Table 102
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
Table 98.
Digital I/O configuration register types
Name
Address
offset
True
open-drain
Analog
Glitch filter
on/off
Digital
filter
High-drive
output
Reference
PIO1_11
0x0AC
no
no
no
yes
no
Table 103
PIO1_12
0x0B0
no
no
no
yes
no
Table 103
PIO1_13
0x0B4
no
no
no
yes
no
Table 103
PIO1_14
0x0B8
no
no
no
yes
no
Table 103
PIO1_15
0x0BC
no
no
no
yes
no
Table 103
PIO1_16
0x0C0
no
no
no
yes
no
Table 103
PIO1_17
0x0C4
no
no
no
yes
no
Table 103
PIO1_18
0x0C8
no
no
no
yes
no
Table 103
PIO1_19
0x0CC
no
no
no
yes
no
Table 103
PIO1_20
0x0D0
no
no
no
yes
no
Table 103
PIO1_21
0x0D4
no
no
no
yes
no
Table 103
PIO1_22
0x0D8
no
no
no
yes
no
Table 103
PIO1_23
0x0DC
no
no
no
yes
no
Table 103
PIO1_24
0x0E0
no
no
no
yes
no
Table 103
PIO1_25
0x0E4
no
no
no
yes
no
Table 103
PIO1_26
0x0E8
no
no
no
yes
no
Table 103
PIO1_27
0x0EC
no
no
no
yes
no
Table 103
PIO1_28
0x0F0
no
no
no
yes
no
Table 103
PIO1_29
0x0F4
no
no
no
yes
no
Table 103
PIO1_30
0x0F8
no
no
no
yes
no
Table 103
PIO1_31
0x0FC
no
no
no
yes
no
Table 103
PIO2_0
0x100
no
yes
yes
yes
no
Table 104
PIO2_1
0x104
no
yes
yes
yes
no
Table 104
PIO2_2
0x108
no
yes
yes
yes
no
Table 104
PIO2_3
0x10C
no
no
no
yes
no
Table 104
PIO2_4
0x110
no
no
no
yes
no
Table 104
PIO2_5
0x114
no
no
no
yes
no
Table 104
PIO2_6
0x118
no
no
no
yes
no
Table 104
PIO2_7
0x11C
no
no
no
yes
no
Table 104
PIO2_8
0x120
no
no
no
yes
no
Table 104
PIO2_9
0x124
no
no
no
yes
no
Table 104
PIO2_10
0x128
no
no
no
yes
no
Table 104
PIO2_11
0x12C
no
no
no
yes
no
Table 104
PIO2_12
0x130
no
no
no
yes
no
Table 104
PIO2_13
0x134
no
no
no
yes
no
Table 104
7.5.1 Digital pin control registers with glitch filter on port 0
The digital pin control registers control the digital properties of all pins except the pins with
true open-drain I2C-bus functions. The pin’s function is determined by the switch matrix.
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If any of the pins is connected to an analog function through the switch matrix
PINENABLE registers, the digital portion of the pin is disconnected.
For each pin controlled by these registers, the digital glitch filter is enabled.
Table 99.
Digital pin control registers PIO0_0 to PIO0_17 register (PIO0_[0:17], address
0x400F 8000 (PIO0_0) to 0x400F 8044 (PIO0_17) and 0x400F 8064 (PIO0_25) to
0x400F 807C (PIO0_31)) bit description
Bit
Symbol
2:0
4:3
5
6
Value
Description
Reset
value
-
Reserved. Only write 0 to these bits.
0
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x2
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
0
Disable.
1
Enable.
HYS
Hysteresis.
INV
7
-
8
FILTR
9
-
10
OD
0
Invert input
0
0
Input not inverted (HIGH on pin reads as 1; LOW on pin reads
as 0).
1
Input inverted (HIGH on pin reads as 0, LOW on pin reads as
1).
-
Reserved.
1
Selects 10 ns input glitch filter.
0
0
Filter enabled.
1
Filter disabled.
-
Reserved.
0
Open-drain mode.
0
0
Disable.
1
Open-drain mode enabled.
Remark: This is not a true open-drain mode.
12:11
UM10736
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S_MODE
Digital filter sample mode.
0
0x0
Bypass input filter.
0x1
1 clock cycle. Input pulses shorter than one filter clock are
rejected.
0x2
2 clock cycles. Input pulses shorter than two filter clocks are
rejected.
0x3
3 clock cycles. Input pulses shorter than three filter clocks are
rejected.
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
Table 99.
Digital pin control registers PIO0_0 to PIO0_17 register (PIO0_[0:17], address
0x400F 8000 (PIO0_0) to 0x400F 8044 (PIO0_17) and 0x400F 8064 (PIO0_25) to
0x400F 807C (PIO0_31)) bit description
Bit
Symbol
15:13
CLKDIV
31:16
-
Value
Description
Reset
value
Select peripheral clock divider for input filter sampling clock
IOCONCLKDIV. Value 0x7 is reserved.
0
0x0
PCLK.
0x1
PCLK/2.
0x2
PCLK/4.
0x3
PCLK/8.
0x4
PCLK/16.
0x5
PCLK/32.
0x6
PCLK/64.
-
Reserved.
0
7.5.2 Digital pin control registers without glitch filter on port 0
The digital pin control registers control the digital properties of all pins except the pins with
true open-drain I2C-bus functions. The pin’s function is determined by the switch matrix.
If any of the pins is connected to an analog function through the switch matrix
PINENABLE registers, the digital portion of the pin is disconnected.
Pins controlled by these registers do not have a glitch filter.
Table 100. Digital pin control registers PIO0_18 to PIO0_21 register (PIO0_[18:21], address
0x400F 8048 (PIO0_18) to 0x400F 8054 (PIO0_21), and 0x400F 8060 (PIO0_24)) bit
description
Bit
Symbol
2:0
4:3
5
6
9:7
UM10736
User manual
Value
Description
Reset
value
-
Reserved. Only write 0 to these bits.
0
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x2
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
HYS
Hysteresis.
0
Disable.
1
Enable.
INV
-
0
Invert input
0
0
Input not inverted (HIGH on pin reads as 1; LOW on pin reads
as 0).
1
Input inverted (HIGH on pin reads as 0, LOW on pin reads as
1).
-
Reserved.
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
Table 100. Digital pin control registers PIO0_18 to PIO0_21 register (PIO0_[18:21], address
0x400F 8048 (PIO0_18) to 0x400F 8054 (PIO0_21), and 0x400F 8060 (PIO0_24)) bit
description
Bit
Symbol
10
OD
Value
Description
Reset
value
Open-drain mode.
0
0
Disable.
1
Open-drain mode enabled.
Remark: This is not a true open-drain mode.
12:11
15:13
31:16
S_MODE
Digital filter sample mode.
0x0
Bypass input filter.
0x1
1 clock cycle. Input pulses shorter than one filter clock are
rejected.
0x2
2 clock cycles. Input pulses shorter than two filter clocks are
rejected.
0x3
3 clock cycles. Input pulses shorter than three filter clocks are
rejected.
CLKDIV
-
0
Select peripheral clock divider for input filter sampling clock
IOCONCLKDIV. Value 0x7 is reserved.
0x0
PCLK.
0x1
PCLK/2.
0x2
PCLK/4.
0x3
PCLK/8.
0x4
PCLK/16.
0x5
PCLK/32.
0x6
PCLK/64.
-
Reserved.
0
0
7.5.3 Digital pin control registers for open-drain pins PIO0_22/23 on port 0
Table 101. Digital open-drain pin control registers (PIO0_[22:23], address 0x400F 805C
(PIO0_22) to 0x400F 8060 (PIO0_23)) bit description
Bit
Symbol
5:0
-
Reserved. Only write 0 to these bits.
0x10
6
INV
Invert input
0
7
UM10736
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-
Value
Description
Reset
value
0
Input not inverted (HIGH on pin reads as 1; LOW on pin
reads as 0).
1
Input inverted (HIGH on pin reads as 0, LOW on pin reads
as 1).
Reserved.
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
Table 101. Digital open-drain pin control registers (PIO0_[22:23], address 0x400F 805C
(PIO0_22) to 0x400F 8060 (PIO0_23)) bit description
Bit
Symbol
Value
9:8
I2CMODE
Description
Reset
value
Selects I2C mode.
0
Select Standard mode (I2CMODE = 00, default) or
Standard I/O functionality (I2CMODE = 01) if the pin
function is GPIO (FUNC = 000).
10
-
12:11
S_MODE
15:13
31:16
0x0
Standard mode/ Fast-mode I2C.
0x1
Standard digital I/O functionality
0x2
Fast-mode Plus I2C
0x3
Reserved.
-
Reserved.
-
Digital filter sample mode.
0
0x0
Bypass input filter.
0x1
1 clock cycle. Input pulses shorter than one filter clock are
rejected.
0x2
2 clock cycles. Input pulses shorter than two filter clocks
are rejected.
0x3
3 clock cycles. Input pulses shorter than three filter clocks
are rejected.
CLKDIV
-
Select peripheral clock divider for input filter sampling clock 0
IOCONCLKDIV. Value 0x7 is reserved.
0x0
PCLK.
0x1
PCLK/2.
0x2
PCLK/4.
0x3
PCLK/8.
0x4
PCLK/16.
0x5
PCLK/32.
0x6
PCLK/64.
-
Reserved.
-
7.5.4 Digital pin control registers with glitch filter on port 1
The digital pin control registers control the digital properties of all pins except the pins with
true open-drain I2C-bus functions. The pin’s function is determined by the switch matrix.
If any of the pins is connected to an analog function through the switch matrix
PINENABLE registers, the digital portion of the pin is disconnected.
For each pin controlled by these registers, the digital glitch filter is enabled.
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
Table 102. Digital pin control registers PIO1_0 to PIO1_10 register (PIO1_[0:10], address
0x400F 8080 (PIO1_0) to 0x400F 80A8 (PIO1_10)) bit description
Bit
Symbol
2:0
4:3
5
6
Value
Description
Reset
value
-
Reserved. Only write 0 to these bits.
0
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x2
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
HYS
Hysteresis.
0
Disable.
1
Enable.
INV
7
-
8
FILTR
Invert input
-
10
OD
0
0
Input not inverted (HIGH on pin reads as 1; LOW on pin reads
as 0).
1
Input inverted (HIGH on pin reads as 0, LOW on pin reads as
1).
-
Reserved.
1
Selects 10 ns input glitch filter.
0
0
9
0
Filter enabled.
1
Filter disabled.
-
Reserved.
0
Open-drain mode.
0
0
Disable.
1
Open-drain mode enabled.
Remark: This is not a true open-drain mode.
12:11
UM10736
User manual
S_MODE
Digital filter sample mode.
0
0x0
Bypass input filter.
0x1
1 clock cycle. Input pulses shorter than one filter clock are
rejected.
0x2
2 clock cycles. Input pulses shorter than two filter clocks are
rejected.
0x3
3 clock cycles. Input pulses shorter than three filter clocks are
rejected.
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
Table 102. Digital pin control registers PIO1_0 to PIO1_10 register (PIO1_[0:10], address
0x400F 8080 (PIO1_0) to 0x400F 80A8 (PIO1_10)) bit description
Bit
Symbol
15:13
CLKDIV
31:16
-
Value
Description
Reset
value
Select peripheral clock divider for input filter sampling clock
IOCONCLKDIV. Value 0x7 is reserved.
0
0x0
PCLK.
0x1
PCLK/2.
0x2
PCLK/4.
0x3
PCLK/8.
0x4
PCLK/16.
0x5
PCLK/32.
0x6
PCLK/64.
-
Reserved.
0
7.5.5 Digital pin control registers without glitch filter on port 1
The digital pin control registers control the digital properties of all pins except the pins with
true open-drain I2C-bus functions. The pin’s function is determined by the switch matrix.
If any of the pins is connected to an analog function through the switch matrix
PINENABLE registers, the digital portion of the pin is disconnected.
Pins controlled by these registers do not have a glitch filter.
Table 103. Digital pin control registers PIO1_11 to PIO1_31 register (PIO1_[11:31], address
0x400F 80AC (PIO1_11) to 0x400F 80FC (PIO1_31)) bit description
Bit
Symbol
2:0
4:3
Value
Description
Reset
value
-
Reserved. Only write 0 to these bits.
0
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x2
0x0
5
6
UM10736
User manual
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
HYS
Hysteresis.
0
Disable.
1
Enable.
INV
0
Invert input
0
0
Input not inverted (HIGH on pin reads as 1; LOW on pin reads
as 0).
1
Input inverted (HIGH on pin reads as 0, LOW on pin reads as
1).
7
-
-
Reserved.
1
9:8
-
-
Reserved.
0
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
Table 103. Digital pin control registers PIO1_11 to PIO1_31 register (PIO1_[11:31], address
0x400F 80AC (PIO1_11) to 0x400F 80FC (PIO1_31)) bit description
Bit
Symbol
10
OD
Value
Description
Reset
value
Open-drain mode.
0
0
Disable.
1
Open-drain mode enabled.
Remark: This is not a true open-drain mode.
12:11
15:13
31:16
S_MODE
Digital filter sample mode.
0x0
Bypass input filter.
0x1
1 clock cycle. Input pulses shorter than one filter clock are
rejected.
0x2
2 clock cycles. Input pulses shorter than two filter clocks are
rejected.
0x3
3 clock cycles. Input pulses shorter than three filter clocks are
rejected.
CLKDIV
-
0
Select peripheral clock divider for input filter sampling clock
IOCONCLKDIV. Value 0x7 is reserved.
0x0
PCLK.
0x1
PCLK/2.
0x2
PCLK/4.
0x3
PCLK/8.
0x4
PCLK/16.
0x5
PCLK/32.
0x6
PCLK/64.
-
Reserved.
0
0
7.5.6 Digital pin control registers without glitch filter on port 2
The digital pin control registers control the digital properties of all pins except the pins with
true open-drain I2C-bus functions. The pin’s function is determined by the switch matrix.
If any of the pins is connected to an analog function through the switch matrix
PINENABLE registers, the digital portion of the pin is disconnected.
Pins controlled by these registers do not have a glitch filter.
Table 104. Digital pin control registers PIO2_0 to PIO2_13 register (PIO2_[0:13], address
0x400F 8100 (PIO2_0) to 0x400F 8124 (PIO2_13)) bit description
UM10736
User manual
Bit
Symbol
2:0
4:3
Value
Description
Reset
value
-
Reserved. Only write 0 to these bits.
0
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x2
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
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Chapter 7: LPC15xx I/O pin configuration (IOCON)
Table 104. Digital pin control registers PIO2_0 to PIO2_13 register (PIO2_[0:13], address
0x400F 8100 (PIO2_0) to 0x400F 8124 (PIO2_13)) bit description
Bit
Symbol
5
HYS
6
Value
Description
Reset
value
Hysteresis.
0
0
Disable.
1
Enable.
INV
Invert input
0
0
Input not inverted (HIGH on pin reads as 1; LOW on pin reads
as 0).
1
Input inverted (HIGH on pin reads as 0, LOW on pin reads as
1).
7
-
-
Reserved.
1
9:8
-
-
Reserved.
0
10
OD
Open-drain mode.
0
0
Disable.
1
Open-drain mode enabled.
Remark: This is not a true open-drain mode.
12:11
15:13
31:16
UM10736
User manual
S_MODE
Digital filter sample mode.
0x0
Bypass input filter.
0x1
1 clock cycle. Input pulses shorter than one filter clock are
rejected.
0x2
2 clock cycles. Input pulses shorter than two filter clocks are
rejected.
0x3
3 clock cycles. Input pulses shorter than three filter clocks are
rejected.
CLKDIV
-
0
Select peripheral clock divider for input filter sampling clock
IOCONCLKDIV. Value 0x7 is reserved.
0x0
PCLK.
0x1
PCLK/2.
0x2
PCLK/4.
0x3
PCLK/8.
0x4
PCLK/16.
0x5
PCLK/32.
0x6
PCLK/64.
-
Reserved.
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Chapter 8: LPC15xx Switch Matrix (SWM)
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8.1 How to read this chapter
The switch matrix is available on all parts.
8.2 Features
• Flexible assignment of digital peripheral functions to pins
• Enable/disable of analog functions
8.3 Basic configuration
Once configured, no clocks are needed for the switch matrix to function. The system clock
is needed only to write to or read from the pin assignment registers. After the switch matrix
is configured, disable the clock to the switch matrix block in the SYSAHBCLKCTRL
register.
Before activating a peripheral or enabling its interrupt, use the switch matrix to connect the
peripheral to external pins.
The serial wire debug pins SWCLK and SWDIO are assigned by default to pins PIO0_19
and PIO0_20. If the user code disables the SWD functions through the switch matrix to
use the pins for other functions, the SWD port is disabled.
Remark: For the purpose of programming the pin functions through the switch matrix,
every programmable pin (all pins except some special function pins, the power, and the
ground pins) is identified in a package-independent way by its GPIO port pin number.
Remark: The switch matrix is only reset by a POR or BOD reset. A hardware reset via the
RESET pin or a watchdog timer reset do not reset the switch matrix. Therefore, peripheral
functions remain connected to pins through the hardware or watchdog reset and the pins
remain input or output as defined by the switch matrix and assume the default state as
defined by the peripheral connected to them. See also Section 3.7.1.
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Chapter 8: LPC15xx Switch Matrix (SWM)
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A pin is identified for the purpose of programming the switch matrix by its default GPIO port pin.
Fig 11. Example: Connect function U0_RXD and U0_TXD to pins
The switch matrix connects all internal signals listed in the table of movable functions
through the pin assignment registers to external pins on the package. External pins are
identified by their default GPIO pin number PIO0_n. Follow these steps to connect an
internal signal FUNC to an external pin. An example of a movable function is the UART
transmit signal TXD:
1. Find the function FUNC in the list of movable function in Table 105 or in the data
sheet.
2. Use the LPC15xx data sheet to decide which pin x on the LPC15xx package to
connect FUNC to.
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Chapter 8: LPC15xx Switch Matrix (SWM)
3. Use the pin description table to find the default GPIO function PIO0_n assigned to
package pin x. m is the pin number (0 to 31 for port 0, 32 to 63 for port 1, 64 to 75 for
port 2).
4. Locate the pin assignment register for the function FUNC in the switch matrix register
description.
5. Disable any special functions on pin PIO0_n in the PINENABLE0 register.
6. Program the pin number m into the bits assigned to FUNC.
FUNC is now connected to pin x on the package.
8.3.2 Enable an analog input or other special function
The switch matrix enables functions that can only be assigned to one pin. Examples are
analog inputs, all GPIO pins, and the debug SWD pins.
• If you want to assign a GPIO pin, disable any special function available on this pin in
the PINENABLE0 register and do not assign any movable function to it.
By default, all pins except pins hosting the RESET and serial wire functions are
assigned to GPIO.
• For all other functions that are not in the table of movable functions, do the following:
a. Locate the function in the pin description table in the data sheet. This shows the
package pin for this function.
b. Enable the function in the PINENABLE0/1 registers. All other possible functions on
this pins are now disabled.
8.4 General description
The switch matrix connects internal signals (functions) to external pins. Functions are
signals coming from or going to a single pin on the package and coming from or going to
an on-chip peripheral block. Examples of functions are the GPIOs, the UART transmit
output (TXD), or the clock output CLKOUT. Many peripherals have several functions that
must be connected to external pins.
Most functions can be assigned through the switch matrix to any external pin that is not a
power or ground pin. These functions are called movable functions.
Analog inputs and outputs as well as open-drain I2C functions and a few digital functions
such as the SCT outputs are assigned to one particular external pin with the appropriate
electrical characteristics and have to be enabled on that pin. These functions are called
fixed-pin functions. If a fixed-pin function is not enabled on the assigned pin, it can be
replaced by any other movable function.
GPIOs are fixed-pin functions. Each GPIO is assigned to one and only one external pin.
By default, all external pins have the GPIO function assigned. External pins are therefore
identified by their fixed-pin GPIO function.
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Chapter 8: LPC15xx Switch Matrix (SWM)
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Fig 12. Switch matrix block diagram
8.4.1 Switch matrix register interface
The switch matrix consists of two blocks of pin-assignment registers PINASSIGN and
PINENABLE. Every function has an assigned field (1-bit or 8-bit wide) within this bank of
registers where you can program the external pin - identified by its GPIO function - you
want the function to connect to.
GPIOs range from PIO0_0 to PIO2_11 and, for assignment through the pin-assignment
registers, are consecutively numbered 0 to 75 (32 pins for port 0 and 1, 12 pins for port 2).
There are two types of functions which must be assigned to port pins in different ways:
1. Movable functions (PINASSIGN0 to 8):
All movable functions are digital functions. Assign movable functions to pin numbers
through the 8 bits of the PINASSIGN register associated with this function. Once the
function is assigned a pin PIO0_n, it is connected through this pin to a physical pin on
the package.
Remark: You are allowed to assign only one digital output function to an external pin
at any given time.
Remark: You can assign more than one digital input function to one external pin.
2. Fixed-pin functions (PINENABLE0/1):
Some functions require pins with special characteristics and cannot be moved to
other physical pins. Hence these functions are mapped to a fixed port pin. Examples
of fixed-pin functions are the oscillator pins or comparator inputs.
Each fixed-pin function is associated with one bit in the PINENABLE0 register which
selects or deselects the function.
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Chapter 8: LPC15xx Switch Matrix (SWM)
– If a fixed-pin function is deselected, any movable function can be assigned to its
port and pin.
– If a fixed-pin function is deselected and no movable function is assigned to this pin,
the pin is GPIO.
– On reset, all fixed-pin functions are deselected.
– If a fixed-pin function is selected, its assigned pin can not be used for any other
function.
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Chapter 8: LPC15xx Switch Matrix (SWM)
8.4.2 Movable functions
Table 105. Movable functions
Function name
Type
Description
SWM Pin assign
register
Reference
U0_TXD
O
Transmitter output for USART0.
PINASSIGN0
Table 107
U0_RXD
I
Receiver input for USART0.
PINASSIGN0
Table 107
U0_RTS
O
Request To Send output for USART0.
PINASSIGN0
Table 107
U0_CTS
I
Clear To Send input for USART0.
PINASSIGN0
Table 107
U0_SCLK
I/O
Serial clock input/output for USART0 in synchronous
mode.
PINASSIGN1
Table 108
U1_TXD
O
Transmitter output for USART1.
PINASSIGN1
Table 108
U1_RXD
I
Receiver input for USART1.
PINASSIGN1
Table 108
U1_RTS
O
Request To Send output for USART1.
PINASSIGN1
Table 108
U1_CTS
I
Clear To Send input for USART1.
PINASSIGN2
Table 109
U1_SCLK
I/O
Serial clock input/output for USART1 in synchronous
mode.
PINASSIGN2
Table 109
U2_TXD
O
Transmitter output for USART2.
PINASSIGN2
Table 109
U2_RXD
I
Receiver input for USART2.
PINASSIGN2
Table 109
U2_SCLK
I/O
Serial clock input/output for USART1 in synchronous
mode.
PINASSIGN3
Table 110
SPI0_SCK
I/O
Serial clock for SPI0.
PINASSIGN3
Table 110
SPI0_MOSI
I/O
Master Out Slave In for SPI0.
PINASSIGN3
Table 110
SPI0_MISO
I/O
Master In Slave Out for SPI0.
PINASSIGN3
Table 110
SPI0_SSEL0
I/O
Slave select 0 for SPI0.
PINASSIGN4
Table 111
SPI0_SSEL1
I/O
Slave select 1 for SPI0.
PINASSIGN4
Table 111
SPI0_SSEL2
I/O
Slave select 2 for SPI0.
PINASSIGN4
Table 111
SPI0_SSEL3
I/O
Slave select 3 for SPI0.
PINASSIGN4
Table 111
SPI1_SCK
I/O
Serial clock for SPI1.
PINASSIGN5
Table 112
SPI1_MOSI
I/O
Master Out Slave In for SPI1.
PINASSIGN5
Table 112
SPI1_MISO
I/O
Master In Slave Out for SPI1.
PINASSIGN5
Table 112
SPI1_SSEL0
I/O
Slave select 0 for SPI1.
PINASSIGN5
Table 112
SPI1_SSEL1
I/O
Slave select 1 for SPI1.
PINASSIGN6
Table 113
CAN0_TD
O
CAN0 transmit.
PINASSIGN6
Table 113
CAN0_RD
I
CAN0 receive.
PINASSIGN6
Table 113
USB_VBUS
I
USB VBUS.
PINASSIGN7
Table 114
SCT0_OUT0
O
SCT0 output 0.
PINASSIGN7
Table 114
SCT0_OUT1
O
SCT0 output 1.
PINASSIGN7
Table 114
SCT0_OUT2
O
SCT0 output 2.
PINASSIGN7
Table 114
SCT1_OUT0
O
SCT1 output 0.
PINASSIGN8
Table 115
SCT1_OUT1
O
SCT1 output 1.
PINASSIGN8
Table 115
SCT1_OUT2
O
SCT1 output 2.
PINASSIGN8
Table 115
SCT2_OUT0
O
SCT2 output 0.
PINASSIGN8
Table 115
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Table 105. Movable functions …continued
Function name
Type
Description
SWM Pin assign
register
Reference
SCT2_OUT1
O
SCT2 output 1.
PINASSIGN9
Table 116
SCT2_OUT2
O
SCT2 output 2.
PINASSIGN9
Table 116
SCT3_OUT0
O
SCT3 output 0.
PINASSIGN9
Table 116
SCT3_OUT1
O
SCT3 output 1.
PINASSIGN9
Table 116
SCT3_OUT2
O
SCT3 output 2.
PINASSIGN10
Table 117
SCT_ABORT0
I
SCT abort 0.
PINASSIGN10
Table 117
SCT_ABORT1
I
SCT abort 1.
PINASSIGN10
Table 117
ADC0_PINTRIG0 I
ADC0 external pin trigger input 0.
PINASSIGN10
Table 117
ADC0_PINTRIG1 I
ADC0 external pin trigger input 1.
PINASSIGN11
Table 118
ADC1_PINTRIG0 I
ADC1 external pin trigger input 0.
PINASSIGN11
Table 118
ADC1_PINTRIG1 I
ADC1 external pin trigger input 1.
PINASSIGN11
Table 118
DAC_PINTRIG
I
DAC external pin trigger input.
PINASSIGN11
Table 118
DAC_SHUTOFF
I
DAC shut-off external input.
PINASSIGN12
Table 119
ACMP0_O
O
Analog comparator 0 output.
PINASSIGN12
Table 119
ACMP1_O
O
Analog comparator 1 output.
PINASSIGN12
Table 119
ACMP2_O
O
Analog comparator 2 output.
PINASSIGN12
Table 119
ACMP3_O
O
Analog comparator 3 output.
PINASSIGN13
Table 120
CLKOUT
O
Clock output.
PINASSIGN13
Table 120
ROSC
O
Analog comparator ring oscillator output.
PINASSIGN13
Table 120
ROSC_RESET
I
Analog comparator ring oscillator reset.
PINASSIGN13
Table 120
USB_FTOGGLE
O
USB frame toggle. Do not assign this function to a pin until PINASSIGN14
a USB device is connected and the first SOF interrupt has
been received by the device.
Table 121
QEI_PHA
I
QEI phase A input.
PINASSIGN14
Table 121
QEI_PHB
I
QEI phase B input.
PINASSIGN14
Table 121
QEI_IDX
I
QEI index input.
PINASSIGN14
Table 121
GPIO_INT_BMAT O
Output of the pattern match engine.
PINASSIGN15
Table 122
SWO
Serial wire output.
PINASSIGN15
Table 122
O
8.5 Register description
Table 106. Register overview: Switch matrix (base address 0x4003 8000)
Name
Access
Offset
Description
Reset value
Reference
PINASSIGN0
R/W
0x000
Pin assign register 0. Assign movable
functions U0_TXD, U0_RXD, U0_RTS,
U0_CTS.
0xFFFF FFFF
Table 107
PINASSIGN1
R/W
0x004
Pin assign register 1. Assign movable
functions U0_SCLK, U1_TXD, U1_RXD,
U1_RTS.
0xFFFF FFFF
Table 108
PINASSIGN2
R/W
0x008
Pin assign register 2. Assign movable
functions U1_CTS, U1_SCLK, U2_TXD,
U2_RXD.
0xFFFF FFFF
Table 109
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Chapter 8: LPC15xx Switch Matrix (SWM)
Table 106. Register overview: Switch matrix (base address 0x4003 8000) …continued
Name
Access
Offset
Description
PINASSIGN3
R/W
0x00C
Pin assign register 3. Assign movable
0xFFFF FFFF
function U2_SCLK, SPI0_SCK, SPI0_MOSI,
SPI0_MISO.
Table 110
PINASSIGN4
R/W
0x010
Pin assign register 4. Assign movable
functions SPI0_SSEL0, SPI0_SSEL1,
SPI0_SSEL2, SPI0_SSEL3.
0xFFFF FFFF
Table 111
PINASSIGN5
R/W
0x014
Pin assign register 5. Assign movable
functions SPI1_SCK, SPI1_MOSI,
SPI1_MISO, SPI1_SSEL0
0xFFFF FFFF
Table 112
PINASSIGN6
R/W
0x018
Pin assign register 6. Assign movable
functions SPI1_SSEL1, CAN0_TD,
CAN0_RD.
0xFFFF FFFF
Table 113
PINASSIGN7
R/W
0x01C
Pin assign register 7. Assign movable
functions USB_VBUS, SCT0_OUT0,
SCT0_OUT1, SCT0_OUT2
0xFFFF FFFF
Table 114
PINASSIGN8
R/W
0x020
Pin assign register 8. Assign movable
functions SCT1_OUT0, SCT1_OUT1,
SCT1_OUT2, SCT2_OUT0
0xFFFF FFFF
Table 115
PINASSIGN9
R/W
0x024
Pin assign register 9. Assign movable
functions SCT2_OUT1, SCT2_OUT2,
SCT3_OUT0, SCT3_OUT1
0xFFFF FFFF
Table 116
PINASSIGN10
R/W
0x028
Pin assign register 10. Assign movable
functions SCT3_OUT2, SCT_ABORT0,
SCT_ABORT1, ADC0_PINTRIG0
0xFFFF FFFF
Table 117
PINASSIGN11
R/W
0x02C
Pin assign register 11. Assign movable
functions ADC0_PINTRIG1,
ADC1_PINTRIG0, ADC1_PINTRIG1,
DAC_PINTRIG
0xFFFF FFFF
Table 118
PINASSIGN12
R/W
0x030
Pin assign register 12. Assign movable
functions DAC_SHUTOFF, ACMP0_O,
ACMP1_O, ACMP2_O
0xFFFF FFFF
Table 119
PINASSIGN13
R/W
0x034
Pin assign register 13. Assign movable
functions ACMP3_O, CLKOUT, ROSC,
ROSC_RESET
0xFFFF FFFF
Table 120
PINASSIGN14
R/W
0x038
Pin assign register 14. Assign movable
functions USB_FTOGGLE, QEI_PHA,
QEI_PHB, QEI_IDX
0xFFFF FFFF
Table 121
PINASSIGN15
R/W
0x03C
Pin assign register 15. Assign movable
functions GPIO_INT_BMAT, SWO
0xFFFF FFFF
Table 122
-
-
-
Reserved
-
PINENABLE0
R/W
0x1C0
Pin enable register 0. Enables fixed-pin
functions for ADC0, ADC1, and analog
comparator.
0xFFFF FFFF
Table 123
PINENABLE1
R/W
0x1C4
Pin enable register 0. Enables fixed-pin
functions for analog comparator, I2C, SCT
outputs, RESET, serial wire debug.
0xFF1F FFFF
Table 124
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Reference
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8.5.1 PINASSIGN0
Table 107. Pin assign register 0 (PINASSIGN0, address 0x4003 8000) bit description
Bit
Symbol
Description
Reset
value
7:0
UART0_TXD_O
UART0_TXD function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
15:8
UART0_RXD_I
UART0_RXD function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
UART0_RTS_O
UART0_RTS function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
UART0_CTS_I
UART0_CTS function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
8.5.2 PINASSIGN1
Table 108. Pin assign register 1 (PINASSIGN1, address 0x4003 8004) bit description
Bit
Symbol
Description
Reset
value
7:0
UART0_SCLK_IO UART0_SCLK function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
15:8
UART1_TXD_O
UART1_TXD function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
UART1_RXD_I
UART1_RXD function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
UART1_RTS_O
UART1_RTS function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
8.5.3 PINASSIGN2
Table 109. Pin assign register 2 (PINASSIGN2, address 0x4003 8008) bit description
UM10736
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Bit
Symbol
Description
Reset
value
7:0
UART1_CTS_I
UART1_CTS function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
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Table 109. Pin assign register 2 (PINASSIGN2, address 0x4003 8008) bit description
Bit
Symbol
Description
Reset
value
15:8
UART1_SCLK_IO UART1_SCLK function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
UART2_TXD_O
UART2_TXD function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
UART2_RXD_I
UART2_RXD function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
8.5.4 PINASSIGN3
Table 110. Pin assign register 3 (PINASSIGN3, address 0x4003 800C) bit description
Bit
Symbol
Description
Reset
value
7:0
UART2_SCLK_IO UART2_SCLK function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
15:8
SPI0_SCK_IO
SPI0_SCK function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0,...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
SPI0_MOSI_IO
SPI0_MOSI function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
SPI0_MISO_IO
SPI0_MISO function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
8.5.5 PINASSIGN4
Table 111. Pin assign register 4 (PINASSIGN4, address 0x4003 8010) bit description
UM10736
User manual
Bit
Symbol
Description
Reset
value
7:0
SPI0_SSELSN_0
_IO
SPI0_SSELSN_0 function assignment. The value is the
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
15:8
SPI0_SSELSN_1
_IO
SPI0_SSELSN_1 function assignment. The value is the
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
SPI0_SSELSN_2
_IO
SPI0_SSELSN_2 function assignment. The value is the
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
SPI0_SSELSN_3
_IO
SPI0_SSELSN_3 function assignment. The value is the
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
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8.5.6 PINASSIGN5
Table 112. Pin assign register 5 (PINASSIGN5, address 0x4003 8014) bit description
Bit
Symbol
Description
Reset
value
7:0
SPI1_SCK_IO
SPI1_SCK function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
15:8
SPI1_MOSI_IO
SPI1_MOSI function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
SPI1_MISO_IO
SPI1_MISO function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
SPI1_SSELSN_0
_IO
SPI1_SSELSN_0 function assignment. The value is the
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
8.5.7 PINASSIGN6
Table 113. Pin assign register 6 (PINASSIGN6, address 0x4003 8018) bit description
Bit
Symbol
Description
Reset
value
7:0
SPI1_SSELSN_1
_IO
SPI1_SSELSN_1 function assignment. The value is the
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
15:8
CAN_TD1_O
CAN_TD1 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
CAN_RD1_I
CAN_RD1 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
-
Reserved,
0xFF
8.5.8 PINASSIGN7
Table 114. Pin assign register 7 (PINASSIGN7, address 0x4003 801C) bit description
UM10736
User manual
Bit
Symbol
Description
Reset
value
7:0
USB_VBUS_I
USB_VBUS function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
15:8
SCT0_OUT0_O
SCT0_OUT0 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
SCT0_OUT1_O
SCT0_OUT1 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
SCT0_OUT2_O
SCT0_OUT2 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
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8.5.9 PINASSIGN8
Table 115. Pin assign register 8 (PINASSIGN8, address 0x4003 8020) bit description
Bit
Symbol
Description
Reset
value
7:0
SCT1_OUT0_O
SCT1_OUT0 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
15:8
SCT1_OUT1_O
SCT1_OUT1 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
SCT1_OUT2_O
SCT1_OUT2 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
SCT2_OUT0_O
SCT2_OUT0 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
8.5.10 PINASSIGN9
Table 116. Pin assign register 9 (PINASSIGN9, address 0x4003 8024) bit description
Bit
Symbol
Description
Reset
value
7:0
SCT2_OUT1_O
SCT2_OUT1 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
15:8
SCT2_OUT2_O
SCT2_OUT2 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
SCT3_OUT0_O
SCT3_OUT0 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
SCT3_OUT1_O
SCT3_OUT1 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
8.5.11 PINASSIGN10
Table 117. Pin assign register 10 (PINASSIGN10, address 0x4003 8028) bit description
UM10736
User manual
Bit
Symbol
Description
Reset
value
7:0
SCT3_OUT2_O
SCT3_OUT2 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
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Table 117. Pin assign register 10 (PINASSIGN10, address 0x4003 8028) bit description
Bit
Symbol
Description
Reset
value
15:8
SCT_ABORT0_I
SCT_ABORT0 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
SCT_ABORT1_I
SCT_ABORT1 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
ADC0_PIN_TRIG
0_I
ADC0_PIN_TRIG0 function assignment. The value is the 0xFF
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
8.5.12 PINASSIGN11
Table 118. Pin assign register 11 (PINASSIGN11, address 0x4003 802C) bit description
Bit
Symbol
Description
Reset
value
7:0
ADC0_PIN_TRIG
1_I
ADC0_PIN_TRIG1 function assignment. The value is the 0xFF
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
15:8
ADC1_PIN_TRIG
0_I
ADC1_PIN_TRIG0 function assignment. The value is the 0xFF
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
23:16
ADC1_PIN_TRIG
1_I
ADC1_PIN_TRIG1 function assignment. The value is the 0xFF
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
31:24
DAC_PIN_TRIG_I DAC_PIN_TRIG function assignment. The value is the
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
8.5.13 PINASSIGN12
Table 119. Pin assign register 12 (PINASSIGN12, address 0x4003 8030) bit description
UM10736
User manual
Bit
Symbol
Description
7:0
DAC_SHUTOFF_I DAC_SHUTOFF function assignment. The value is the
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
15:8
ACMP0_OUT_O
ACMP0_OUT function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
ACMP1_OUT_O
ACMP1_OUT function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
ACMP2_OUT_O
ACMP2_OUT function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
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Chapter 8: LPC15xx Switch Matrix (SWM)
8.5.14 PINASSIGN13
Table 120. Pin assign register 13 (PINASSIGN13, address 0x4003 8034) bit description
Bit
Symbol
Description
Reset
value
7:0
ACMP3_OUT_O
ACMP3_OUT function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
15:8
CLK_OUT_O
CLK_OUT function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
ROSC0_O
ROSC0 function assignment. The value is the pin number 0xFF
to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 =
32, ..., PIO2_11 = 75.
31:24
ROSC_RST0_I
ROSC_RST0 function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
8.5.15 PINASSIGN14
Table 121. Pin assign register 14 (PINASSIGN14, address 0x4003 8038) bit description
Bit
Symbol
Description
Reset
value
7:0
USB_FRAME_TO USB_FRAME_TOG function assignment. The value is the 0xFF
G_O
pin number to be assigned to this function. PIO0_0 = 0,
..., PIO1_0 = 32, ..., PIO2_11 = 75.
15:8
QEI0_PHA_I
QEI0_PHA function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
23:16
QEI0_PHB_I
QEI0_PHB function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
31:24
QEI0_IDX_I
QEI0_IDX function assignment. The value is the pin
number to be assigned to this function. PIO0_0 = 0, ...,
PIO1_0 = 32, ..., PIO2_11 = 75.
0xFF
8.5.16 PINASSIGN15
Table 122. Pin assign register 15 (PINASSIGN15, address 0x4003 803C) bit description
UM10736
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Bit
Symbol
Description
7:0
GPIO_INT_BMAT GPIO_INT_BMATCH function assignment. The value is
CH_O
the pin number to be assigned to this function. PIO0_0 =
0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.
15:8
SWO_O
SWO function assignment. The value is the pin number to 0xFF
be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32,
..., PIO2_11 = 75.
23:16
-
Reserved.
0xFF
31:24
-
Reserved.
0xFF
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Reset
value
0xFF
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Chapter 8: LPC15xx Switch Matrix (SWM)
8.5.17 PINENABLE0
This register enables analog or digital fixed-pin functions that can only be assigned to one
pin.
If the fixed-pin function is disabled, this pin is connected to GPIO or any digital pin function
that is assigned to it through the PINASSIGN registers. By default the fixed-pin function is
deselected and GPIO is assigned to this pin.
Table 123. Pin enable register 0 (PINENABLE0, address 0x4003 81C0) bit description
Bit
Symbol
0
ADC0_0
1
2
3
4
5
6
7
8
9
Value
User manual
ADC0_0 function enable.
1
Enabled on pin PIO0_8.
1
Disabled.
ADC0_1
ADC0_1 function enable.
0
Enabled on pin PIO0_7.
1
Disabled.
ADC0_2
ADC0_2 function enable.
0
Enabled on pin PIO0_6.
1
Disabled.
0
Enabled on pin PIO0_5.
1
Disabled.
ADC0_3
ADC0_3 function enable.
ADC0_4
ADC0_4 function enable.
0
Enabled on pin PIO0_4.
1
Disabled.
ADC0_5
ADC0_5 function enable.
0
Enabled on pin PIO0_3.
1
Disabled.
ADC0_6
ADC0_6 function enable.
0
Enabled on pin PIO0_2.
1
Disabled.
0
Enabled on pin PIO0_1.
1
Disabled.
ADC0_7
ADC0_7 function enable.
ADC0_8
ADC0_8 function enable.
0
Enabled on pin PIO1_0.
1
Disabled.
ADC0_9
ADC0_9 function enable.
1
UM10736
Reset
value
0
0
10
Description
ADC0_10
1
1
1
1
1
1
1
1
1
Enabled on pin PIO0_31.
Disabled.
ADC0_10 function enable.
0
Enabled on pin PIO0_0.
1
Disabled.
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Table 123. Pin enable register 0 (PINENABLE0, address 0x4003 81C0) bit description
Bit
Symbol
11
ADC0_11
12
13
14
15
16
17
18
19
20
21
22
23
24
UM10736
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Value
Reset
value
ADC0_11 function enable.
1
0
Enabled on pin PIO0_30.
1
Disabled.
ADC1_0
ADC1_0 function enable.
0
Enabled on pin PIO1_1.
1
Disabled.
ADC1_1
ADC1_1 function enable.
0
Enabled on pin PIO0_9.
1
Disabled.
0
Enabled on pin PIO0_10.
1
Disabled.
ADC1_2
ADC1_2 function enable.
ADC1_3
ADC1_3 function enable.
0
Enabled on pin PIO0_11.
1
Disabled.
ADC1_4
ADC1_4 function enable.
0
Enabled on pin PIO1_2.
1
Disabled.
ADC1_5
ADC1_5 function enable.
0
Enabled on pin PIO1_3.
1
Disabled.
0
Enabled on pin PIO0_13.
1
Disabled.
ADC1_6
ADC1_6 function enable.
ADC1_7
ADC1_7 function enable.
0
Enabled on pin PIO0_14.
1
Disabled.
ADC1_8
ADC1_8 function enable.
0
Enabled on pin PIO0_15.
1
Disabled.
ADC1_9
ADC1_9 function enable.
0
Enabled on pin PIO0_16.
1
Disabled.
ADC1_10
ADC1_10 function enable.
0
Enabled on pin PIO1_4.
1
Disabled.
ADC1_11
DAC_OUT
Description
ADC1_11 function enable.
0
Enabled on pin PIO1_5.
1
Disabled.
DAC_OUT function enable.
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1
1
1
1
1
1
1
1
1
1
1
1
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Chapter 8: LPC15xx Switch Matrix (SWM)
Table 123. Pin enable register 0 (PINENABLE0, address 0x4003 81C0) bit description
Bit
Symbol
Value
Description
0
Enabled on pin PIO0_12.
1
25
26
27
28
Disabled.
ACMP_I1
ACMP input 1 (common input) function enable.
0
Enabled on pin PIO0_27.
1
Disabled.
ACMP_I2
ACMP input 2 (common input) function enable.
0
Enabled on pin PIO1_6.
1
Disabled.
ACMP0_I3
Analog comparator 0 input 3 function enable.
0
Enabled on pin PIO0_26.
1
Disabled.
ACMP0_I4
Analog comparator 0 input 4 function enable.
0
30
31
1
1
1
1
Enabled on pin PIO0_25.
1
29
Reset
value
Disabled.
ACMP1_I3
Analog comparator 1 input 3 function enable.
0
Enabled on pin PIO0_28.
1
Disabled.
ACMP1_I4
Analog comparator 1 input 4 function enable.
0
Enabled on pin PIO1_10.
1
Disabled.
ACMP2_I3
Analog comparator 2 input 3 function enable.
0
Enabled on pin PIO0_29.
1
Disabled.
1
1
1
8.5.18 PINENABLE 1
This register enables analog or digital fixed-pin functions that can only be assigned to one
pin.
If the fixed-pin function is disabled, this pin is connected to GPIO or any digital pin function that is
assigned to it through the PINASSIGN registers. By default the fixed-pin function is deselected and
GPIO is assigned to this pin.
Table 124. Pin enable register 1 (PINENABLE1, address 0x4003 81C4) bit description
Bit
Symbol
0
ACMP2_I4
1
2
UM10736
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Value
Reset
value
Analog comparator 2 input 4 function enable.
1
0
Enabled on pin PIO1_9.
1
Disabled.
ACMP3_I3
ACMP3_I4
Description
Analog comparator 3 input 3 function enable.
0
Enabled on pin PIO1_8.
1
Disabled.
Analog comparator 3 input 4 function enable.
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Chapter 8: LPC15xx Switch Matrix (SWM)
Table 124. Pin enable register 1 (PINENABLE1, address 0x4003 81C4) bit description
Bit
Symbol
Value
Description
0
Enabled on pin PIO1_7.
1
3
4
5
6
7
8
9
10
11
12
13
14
15
I2C0_SDA
0
Enabled on pin PIO0_23.
1
Disabled.
I2C0_SCL function enable.
0
Enabled on pin PIO0_22.
1
Disabled.
SCT0_OUT3
SCT0_OUT3 function enable.
0
Enabled on pin PIO0_0.
1
Disabled.
SCT0_OUT4
SCT0_OUT4 function enable.
0
Enabled on pin PIO0_1.
1
Disabled.
SCT0_OUT5
SCT0_OUT5 function enable.
0
Enabled on function PIO0_18.
1
Disabled.
0
Enabled on pin PIO0_24.
1
Disabled.
SCT0_OUT6
SCT0_OUT6 function enable.
SCT0_OUT7
SCT0_OUT7 function enable.
0
Enabled on pin PIO1_14.
1
Disabled.
SCT1_OUT3
SCT1_OUT3 function enable.
0
Enabled on pin PIO0_2.
1
Disabled.
SCT1_OUT4
SCT1_OUT4 function enable.
0
Enabled on pin PIO0_3.
1
Disabled.
0
Enabled on pin PIO0_14.
1
Disabled.
SCT1_OUT5
SCT1_OUT5 function enable.
SCT1_OUT6
SCT1_OUT6 function enable.
0
Enabled on pin PIO0_20.
1
Disabled.
SCT1_OUT7
SCT1_OUT7 function enable.
0
Enabled on pin PIO1_17.
1
Disabled.
SCT2_OUT3
SCT2_OUT3 function enable.
0
UM10736
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Disabled.
I2C0_SDA function enable.
I2C0_SCL
Reset
value
1
1
1
1
1
1
1
1
1
1
1
1
1
Enabled on pin PIO0_6.
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Chapter 8: LPC15xx Switch Matrix (SWM)
Table 124. Pin enable register 1 (PINENABLE1, address 0x4003 81C4) bit description
Bit
16
17
18
19
20
21
22
23
31:24
UM10736
User manual
Symbol
Value
Description
1
Disabled.
0
Enabled on pin PIO0_29.
1
Disabled.
SCT2_OUT4
SCT2_OUT4 function enable.
SCT2_OUT5
SCT2_OUT5 function enable.
0
Enabled on pin PIO1_20.
1
Disabled.
SCT3_OUT3
SCT3_OUT3 function enable.
0
Enabled on pin PIO0_26.
1
Disabled.
SCT3_OUT4
SCT3_OUT4 function enable.
0
Enabled on pin PIO1_8.
1
Disabled.
0
Enabled on pin PIO1_24.
1
Disabled.
SCT3_OUT5
SCT3_OUT5 function enable.
RESET function enable.
RESETN
0
Enabled on pin PIO0_21.
1
Disabled.
SWCLK
SWCLK function enable.
0
Enabled on pin PIO0_19.
1
Disabled.
SWDIO
-
SWDIO function enable.
0
Enabled on pin PIO0_20.
1
Disabled.
-
Reserved.
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Reset
value
1
1
1
1
1
0
0
0
1
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Chapter 9: LPC15xx Input multiplexing (INPUT MUX)
Rev. 1.1 — 3 March 2014
User manual
9.1 How to read this chapter
Input multiplexing is available for all parts. Depending on the package, not all inputs from
external pins may be available. See Table 96 “Available pin configuration registers”.
9.2 Features
•
•
•
•
Configures the inputs to the SCTs.
Configures the inputs to the pin interrupt block and pattern match engine.
Configures the inputs to the DMA triggers.
Configures the inputs to the frequency measure function. This function is controlled by
the FREQMECTRL register in the SYSCON block.
9.3 Basic configuration
Once set up, no clocks are needed for the input multiplexer to function. The system clock
is needed only to write to or read from the INPUT MUX registers. Once the input
multiplexer is configured, disable the clock to the INPUT MUX block in the
SYSAHBCLKCTRL register.
9.4 Pin description
The input multiplexer has no dedicated pins. However, several external pins can be
selected as inputs to the SCT input multiplexer and all digital pins of ports 0 and 1 can be
selected as inputs to the pin interrupts. Multiplexer inputs from external pins work
independently of any function assigned to the pin through the switch matrix as long as no
analog function is enabled.
Table 125. INPUT MUX pin description
UM10736
User manual
Pins
Peripheral
Input mux
Reference
PIO0_2, PIO0_3, PIO0_17, PIO0_30, PIO1_6,
PIO1_7, PIO1_12, PIO1_13
SCT0
Table 127
PIO0_15, PIO0_16, PIO0_21, PIO0_31, PIO1_4, SCT1
PIO1_5, PIO1_15, PIO1_16
Table 128
P0_4, P0_27, P1_18, P1_19
SCT2
Table 129
PIO0_7, PIO1_11, PIO1_21, PIO1_22
SCT3
Table 130
PIO0_n, PIO1_n (n = 0 to 31)
Pin interrupts 0 to 7
Table 131
PIO0_5, PIO0_19, PIO0_30, PIO1_27
Frequency measure block
Table 134
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Chapter 9: LPC15xx Input multiplexing (INPUT MUX)
9.5 General description
The inputs to the four SCTs, to the DMA trigger, to the eight pin interrupts, and to the
frequency measure block are multiplexed to multiple input sources. The sources can be
external pins, interrupts, or output signals of other peripherals.
The input multiplexing makes it possible to design complex event-driven processes
without CPU intervention by connecting peripherals like the SCTs and the ADCs, the
SCTs and the analog comparators, or two SCTs internally with each other.
The DMA can use trigger input multiplexing to sequence DMA transactions without the
use of interrupt service routines.
SLQV
6&7RXWSXWV
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6&7,38RXWSXWV
'(%8*
SLQV
6&7RXWSXWV
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86%B)72**/(
'(%8*
SLQV
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6&7,38RXWSXWV
'(%8*
6&7B,108;
6&7B,108;
SLQV
6&7B,108;
9.5.1 SCT input multiplexing
6&7
LQSXWV
6&7RXWSXWV
6&7
6&7
6&7
LQSXWV
6&7RXWSXWV
6&7
6&7
Fig 13. SCT input multiplexing
9.5.2 Pin interrupt input multiplexing
The input mux for the pin interrupts and pattern match engine multiplexes all pins from
ports 0 and 1.
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Chapter 9: LPC15xx Input multiplexing (INPUT MUX)
,138708;
DOOSLQV3,2>@BP
('*(/(9(/
'(7(&7/2*,&
L
3,176(/
DOOSLQV3,2>@BP
19,&SLQLQWHUUXSW
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('*(/(9(/
'(7(&7/2*,&
L
3,176(/
19,&SLQLQWHUUXSW
3DWWHUQPDWFKHQJLQHVOLFHVWR
Fig 14. Pin interrupt multiplexing
9.5.3 DMA trigger input multiplexing
'0$WULJJHU
LQSXWV
$'&VHTXHQFH
LQWHUUXSWV
6&7'0$UHTXHVWV
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,138708;
WULJJHULQSXW
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IURP'0$FKDQQHO
WULJJHURXWSXW
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,13B1
IURP'0$FKDQQHO
,13B1
'0$B,108;B,108;
IURP'0$FKDQQHO
IURP'0$FKDQQHO
,13B1
Fig 15. DMA trigger multiplexing
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Chapter 9: LPC15xx Input multiplexing (INPUT MUX)
9.6 Register description
All input mux registers reside on word address boundaries. Details of the registers appear
in the description of each function.
All address offsets not shown in Table 126 are reserved and should not be written to.
Table 126. Register overview: Input multiplexing (base address 0x4001 4000)
Name
Access
Offset
Description
Reset
value
Reference
SCT0_INMUX0
R/W
0x000
Input mux register for SCT0 input 0
0x1F
Table 127
SCT0_INMUX1
R/W
0x004
Input mux register for SCT0 input 1
0x1F
Table 127
SCT0_INMUX2
R/W
0x008
Input mux register for SCT0 input 2
0x1F
Table 127
SCT0_INMUX3
R/W
0x00C
Input mux register for SCT0 input 3
0x1F
Table 127
SCT0_INMUX4
R/W
0x010
Input mux register for SCT0 input 4
0x1F
Table 127
SCT0_INMUX5
R/W
0x014
Input mux register for SCT0 input 5
0x1F
Table 127
SCT0_INMUX6
R/W
0x018
Input mux register for SCT0 input 6
0x1F
Table 127
-
-
0x01C
Reserved.
-
-
0x020
Input mux register for SCT1 input 0
0x1F
Table 128
SCT1_INMUX0
SCT1_INMUX1
R/W
0x024
Input mux register for SCT1 input 1
0x1F
Table 128
SCT1_INMUX2
R/W
0x028
Input mux register for SCT1 input 2
0x1F
Table 128
SCT1_INMUX3
R/W
0x02C
Input mux register for SCT1 input 3
0x1F
Table 128
SCT1_INMUX4
R/W
0x030
Input mux register for SCT1 input 4
0x1F
Table 128
SCT1_INMUX5
R/W
0x034
Input mux register for SCT1 input 5
0x1F
Table 128
SCT1_INMUX6
R/W
0x038
Input mux register for SCT1 input 6
0x1F
Table 128
-
-
0x03C
Reserved.
-
-
SCT2_INMUX0
R/W
0x040
Input mux register for SCT2 input 0
0x1F
Table 129
SCT2_INMUX1
R/W
0x044
Input mux register for SCT2 input 1
0x1F
Table 129
SCT2_INMUX2
R/W
0x048
Input mux register for SCT2 input 2
0x1F
Table 129
-
-
0x04C
0x05C
Reserved.
-
-
SCT3_INMUX0
R/W
0x060
Input mux register for SCT3 input 0
0x1F
Table 130
SCT3_INMUX1
R/W
0x064
Input mux register for SCT3 input 1
0x1F
Table 130
SCT3_INMUX2
R/W
0x068
Input mux register for SCT3 input 2
0x1F
Table 130
-
-
0x06C
0x0BC
Reserved.
-
-
PINTSEL0
R/W
0x0C0
Pin interrupt select register 0
0x7F
Table 131
PINTSEL1
R/W
0x0C4
Pin interrupt select register 1
0x7F
Table 131
PINTSEL2
R/W
0x0C8
Pin interrupt select register 2
0x7F
Table 131
PINTSEL3
R/W
0x0CC
Pin interrupt select register 3
0x7F
Table 131
PINTSEL4
R/W
0x0D0
Pin interrupt select register 4
0x7F
Table 131
PINTSEL5
R/W
0x0D4
Pin interrupt select register 5
0x7F
Table 131
PINTSEL6
R/W
0x0D8
Pin interrupt select register 6
0x7F
Table 131
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Chapter 9: LPC15xx Input multiplexing (INPUT MUX)
Table 126. Register overview: Input multiplexing (base address 0x4001 4000) …continued
Name
Access
Offset
Description
Reset
value
Reference
PINTSEL7
R/W
0x0DC
Pin interrupt select register 7
0x7F
Table 131
DMA_ITRIG_INMUX0
R/W
0x0E0
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX1
R/W
0x0E4
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX2
R/W
0x0E8
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX3
R/W
0x0EC
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX4
R/W
0x0F0
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX5
R/W
0x0F4
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX6
R/W
0x0F8
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX7
R/W
0x0FC
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX8
R/W
0x100
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX9
R/W
0x104
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX10 R/W
0x108
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX11 R/W
0x10C
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX12 R/W
0x110
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX13 R/W
0x114
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX14 R/W
0x118
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX15 R/W
0x11C
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
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Chapter 9: LPC15xx Input multiplexing (INPUT MUX)
Table 126. Register overview: Input multiplexing (base address 0x4001 4000) …continued
Name
Access
Offset
Description
Reset
value
Reference
DMA_ITRIG_INMUX16 R/W
0x120
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_ITRIG_INMUX17 R/W
0x124
Input mux register for trigger inputs 0 to 23 connected to 0x1F
DMA channel 0. Selects from ADC, SCT, ACMP DMA
interrupts and DMA requests.
Table 132
DMA_INMUX_INMUX0 R/W
0x140
Input mux register for DMA trigger input 20. Selects from 0x1F
18 DMA trigger outputs.
Table 133
DMA_INMUX_INMUX1 R/W
0x144
Input mux register for DMA trigger input 21. Selects from 0x1F
18 DMA trigger outputs.
Table 133
DMA_INMUX_INMUX2 R/W
0x148
Input mux register for DMA trigger input 22. Selects from 0x1F
18 DMA trigger outputs.
Table 133
DMA_INMUX_INMUX3 R/W
0x14C
Input mux register for DMA trigger input 23. Selects from 0x1F
18 DMA trigger outputs.
Table 133
FREQMEAS_REF
R/W
0x160
Clock selection for frequency measurement function
reference clock
0xF
Table 134
FREQMEAS_TARGET R/W
0x164
Clock selection for frequency measurement function
target clock
0xF
Table 135
9.6.1 SCT0 Input mux registers 0 to 6
With the SCT0 Input mux registers you can select one input source for each SCT0 input
from 23 external and internal sources. (An exception is SCT0 input SCT0_IN7 which is
connected to the SCT PLL clock and not multiplexed with any other signals.)
The output of SCT0 Input mux register 0 selects the source for SCT0 input 0, the output
of SCT0 Input mux register 1 selects the source for SCT0 input 1, and so forth up to SCT0
Input mux register 6, which selects the input for SCT0 input 6.
The value to be programmed in this register is the Input mux input number ranging from 0
for pin PIO0_2 to 22 for the DEBUG_HALTED signal from the ARM CoreSight debug
signal.
Inputs 0 to 7 are directly connected to specific external pins as indicated in the register
description table. The same pins can also be connected through the switch matrix as
inputs to another peripheral.
See Section 15.3.1 “SCT inputs and outputs” for details.
Table 127. SCT0 Input mux registers 0 to 6 (SCT0_INMUX[0:6], address 0x4001 4000
(SCT0_INMUX0) to 0x4001 4018 (SCT0_INMUX6)) bit description
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Bit
Symbol
4:0
INP_N
Value
Description
Reset
value
Input number (decimal value) to SCT0 inputs 0 to 6.
0x1F
0x0
PIO0_2. (external pin)
0x1
PIO0_3. (external pin)
0x2
PIO0_17. (external pin)
0x3
PIO0_30. (external pin)
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Table 127. SCT0 Input mux registers 0 to 6 (SCT0_INMUX[0:6], address 0x4001 4000
(SCT0_INMUX0) to 0x4001 4018 (SCT0_INMUX6)) bit description
Bit
31:5
Symbol
-
Value
Description
0x4
PIO1_6. (external pin)
0x5
PIO1_7. (external pin)
0x6
PIO1_12. (external pin)
0x7
PIO1_13. (external pin)
Reset
value
0x8
SCT1_OUT4. (large SCT1 output 4)
0x9
SCT2_OUT4. (small SCT2 output 4)
0xA
SCT2_OUT5. (small SCT2 output 5)
0xB
ADC0_THCMP_IRQ. (ADC0 threshold compare
interrupt)
0xC
ADC1_THCMP_IRQ
0xD
ACMP0_OUT. (One output from each analog comparator)
0xE
ACMP1_OUT
0xF
ACMP2_OUT
0x10
ACMP3_OUT
0x11
SCTIPU_ABORT
0x12
SCTIPU_SAMPLE0
0x13
SCTIPU_SAMPLE1
0x14
SCTIPU_SAMPLE2
0x15
SCTIPU_SAMPLE3
0x16
DEBUG_HALTED. (from ARM Cortex CoreSight
Debugger)
Reserved.
-
9.6.2 SCT1 Input mux registers 0 to 6
With the SCT1 Input mux registers you can select one input source for each SCT1 input
from 23 external and internal sources. (An exception is SCT1 input SCT1_IN7 which is
connected to the SCT PLL clock and not multiplexed with any other signals.)
The output of SCT1 Input mux register 0 selects the source for SCT1 input 0, the output
of SCT1 Input mux register 1 selects the source for SCT1 input 1, and so forth up to SCT1
Input mux register 6, which selects the input for SCT1 input 6.
The value to be programmed in this register is the Input mux input number ranging from 0
for pin PIO0_15 to 22 for the DEBUG_HALTED signal from the ARM CoreSight debug
signal.
Inputs 0 to 7 are directly connected to specific external pins as indicated in the register
description table. The same pins can also be connected through the switch matrix as
inputs to another peripheral.
See Section 15.3.1 “SCT inputs and outputs” for details.
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Table 128. SCT1 Input mux registers 0 to 6 (SCT1_INMUX[0:6], address 0x4007 4020
(SCT1_INMUX0) to 0x4001 4038 (SCT1_INMUX6)) bit description
Bit
Symbol
4:0
INP_N
31:5
-
Value Description
Reset
value
Input number (decimal value) to SCT1 inputs 0 to 6.
0x0
PIO0_15. (external pin)
0x1
PIO0_16. (external pin)
0x2
PIO0_21. (external pin)
0x3
PIO0_31. (external pin)
0x4
PIO1_4 (external pin)
0x5
PIO1_5. (external pin)
0x6
PIO1_15. (external pin)
0x7
PIO1_16. (external pin)
0x8
SCT0_OUT4 (large SCT0 output 4)
0x9
SCT3_OUT4 (small SCT3 output 4)
0xA
SCT3_OUT5 (small SCT3 output 5)
0xB
ADC0_THCMP_IRQ. (ADC0 threshold compare
interrupt)
0xC
ADC1_THCMP_IRQ
0xD
ACMP0_OUT. (One output from each analog comparator)
0xE
ACMP1_OUT
0xF
ACMP2_OUT
0x10
ACMP3_OUT
0x11
SCTIPU_ABORT
0x12
SCTIPU_SAMPLE0
0x13
SCTIPU_SAMPLE1
0x14
SCTIPU_SAMPLE2
0x15
SCTIPU_SAMPLE3
0x16
DEBUG_HALTED. (from ARM Cortex CoreSight
Debugger)
Reserved.
0x1F
-
9.6.3 SCT2 Input mux registers 0 to 2
With the SCT2 Input mux registers you can select one input source for each SCT2 input
from 21 external and internal sources.
The output of SCT2 Input mux register 0 selects the source for SCT2 input 0, the output
of SCT2 Input mux register 1 selects the source for SCT2 input 1, and SCT2 Input mux
register 2, selects the input for SCT2 input 2.
The value to be programmed in this register is the Input mux input number ranging from 0
for pin PIO0_4 to 20 for the DEBUG_HALTED signal from the ARM CoreSight debug
signal.
Inputs 0 to 3 are directly connected to specific external pins as indicated in the register
description table. The same pins can also be connected through the switch matrix as
inputs to another peripheral.
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See Section 16.3.1 “SCT inputs and outputs” for details.
Table 129. SCT2 Input mux registers 0 to 2 (SCT2_INMUX[0:2], address 0x4001 4040
(SCT2_INMUX0) to 0x4001 4048 (SCT2_INMUX2)) bit description
Bit
Symbol
4:0
INP_N
Value
-
Reset
value
Input number (decimal value) to SCT2 inputs 0 to 2.
0x1F
0x0
PIO0_4. (external pin)
0x1
PIO0_27. (external pin)
0x2
PIO1_18. (external pin)
0x3
PIO1_19. (external pin)
0x4
SCT0_OUT4
0x5
SCT0_OUT5
0x6
SCT0_OUT7
0x7
SCT0_OUT8
0x8
ADC0_THCMP_IRQ
0x9
ADC1_THCMP_IRQ
0xA
ACMP0_OUT (One output from each analog
comparator)
0xB
ACMP1_OUT
0xC
ACMP2_OUT
0xD
ACMP3_OUT
0xE
SCTIPU_ABORT
0xF
SCTIPU_SAMPLE0
0x10
SCTIPU_SAMPLE1
0x11
SCTIPU_SAMPLE2
0x12
SCTIPU_SAMPLE3
0x13
USB_FRAME_TOGGLE
0x14
31:5
Description
DEBUG_HALTED
Reserved.
-
9.6.4 SCT3 Input mux registers 0 to 2
With the SCT3 Input mux registers you can select one input source for each SCT3 input
from 21 external and internal sources.
The output of SCT3 Input mux register 0 selects the source for SCT3 input 0, the output
of SCT3 Input mux register 1 selects the source for SCT3 input 1, and SCT3 Input mux
register 2, selects the input for SCT3 input 2.
The value to be programmed in this register is the Input mux input number ranging from 0
for pin PIO0_7 to 20 for the DEBUG_HALTED signal from the ARM CoreSight debug
signal.
Inputs 0 to 3 are directly connected to specific external pins as indicated in the register
description table. The same pins can also be connected through the switch matrix as
inputs to another peripheral.
See Section 16.3.1 “SCT inputs and outputs” for details.
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Table 130. SCT3 Input mux registers 0 to 2 (SCT3_INMUX[0:2], address 0x4001 4060
(SCT3_INMUX0) to 0x4001 4068 (SCT3_INMUX2)) bit description
Bit
Symbol
4:0
INP_N
Value
-
Reset
value
Input number (decimal value) to SCT3 inputs 0 to 2. 0x1F
0x0
31:5
Description
PIO0_7. (external pin)
0x1
PIO1_11. (external pin)
0x2
PIO1_21. (external pin)
0x3
PIO1_22. (external pin)
0x4
SCT1_OUT4
0x5
SCT1_OUT5
0x6
SCT1_OUT7
0x7
SCT1_OUT8
0x8
ADC0_THCMP_IRQ
0x9
ADC1_THCMP_IRQ
0xA
ACMP0_OUT
0xB
ACMP1_OUT
0xC
ACMP2_OUT
0xD
ACMP3_OUT
0xE
SCTIPU_ABORT3
0xF
SCTIPU_SAMPLE0
0x10
SCTIPU_SAMPLE1
0x11
SCTIPU_SAMPLE2
0x12
SCTIPU_SAMPLE3
0x13
USB_FRAME_TOGGLE
0x14
DEBUG_HALTED
Reserved.
-
9.6.5 Pin interrupt select registers
Each of these 8 registers selects one pin from all digital pins on GPIO ports 0 and 1 as the
source of a pin interrupt or as the input to the pattern match engine. To select a pin for any
of the eight pin interrupts or pattern match engine inputs, write the GPIO port pin number
as 0 to 31 for pins PIO0_0 to PIO0_31 to the INTPIN bits. Port 1 pins correspond to pin
numbers 32 to 63. For example, setting INTPIN to 0x5 in PINTSEL0 selects pin PIO0_5
for pin interrupt 0.
Remark: The GPIO port pin number serves to identify the pin to the PINTSEL register.
Any digital function, including GPIO, can be assigned to this pin through the switch matrix.
Each of the 8 pin interrupts must be enabled in the NVIC using interrupt slots # 7 to 14
(see Table 2).
To use the selected pins for pin interrupts or the pattern match engine, see Section 12.5.2
“Pattern match engine”.
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Table 131. Pin interrupt select registers (PINTSEL[0:7], address 0x4001 40C0 (PINTSEL0) to
0x4001 40DC (PINTSEL7)) bit description
Bit
Symbol
Description
Reset
value
7:0
INTPIN
Pin number select for pin interrupt or pattern match engine input.
(PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
0x7F
31:8
-
Reserved
-
9.6.6 DMA input trigger input mux registers 0 to 17
With the DMA input trigger input mux registers you can select one trigger input for each of
the 18 DMA channels from 20 internal sources.
By default, none of the triggers are selected.
Table 132. DMA input trigger Input mux registers 0 to 17 (DMA_ITRIG_INMUX[0:17], address
0x4001 40E0 (DMA_ITRIG_INMUX0) to 0x4001 4124 (DMA_ITRIG_INMUX17)) bit
description
Bit
Symbol
4:0
INP
31:5
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Value
Description
Reset
value
Trigger input number (decimal value) for DMA channel
n (n = 0 to 17).
0x1F
0x0
ADC0_SEQA_IRQ
0x1
ADC0_SEQB_IRQ
0x2
ADC1_SEQA_IRQ
0x3
ADC1_SEQB_IRQ
0x4
SCT0_DMA0
0x5
SCT0_DMA1
0x6
SCT1_DMA0
0x7
SCT1_DMA1
0x8
SCT2_DMA0
0x9
SCT2_DMA1
0xA
SCT3_DMA0
0xB
SCT3_DMA1
0xC
ACMP0_OUT. (One output from each analog
comparator)
0xD
ACMP1_OUT
0xE
ACMP2_OUT
0xF
ACMP3_OUT
0x10
DMA trigger mux 0. (DMA_INMUX_INMUX0).
0x11
DMA trigger mux 1. (DMA_INMUX_INMUX1)
0x12
DMA trigger mux 2. (DMA_INMUX_INMUX2).
0x13
DMA trigger mux 3. (DMA_INMUX_INMUX3).
Reserved.
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9.6.7 DMA trigger input mux input mux registers 0 to 3
This register provides a multiplexer for inputs 16 to 19 of each DMA trigger input mux
register DMA_ITRIG_INMUX. These inputs can be selected from the 18 trigger outputs
generated by the DMA (one trigger output per channel).
By default, none of the triggers are selected.
Table 133. DMA input trigger input mux input mux registers 0 to 3 (DMA_INMUX_INMUX[0:3],
address 0x4001 4140 (DMA_INMUX_INMUX0) to 0x4001 414C
(DMA_INMUX_INMUX3)) bit description
Bit
Symbol
Description
Reset value
4:0
INP
DMA trigger output number (decimal value) for DMA
channel n (n = 0 to 17).
0x1F
31:5
-
Reserved.
-
9.6.8 Frequency measure function reference clock select register
This register selects a clock for the reference clock of the frequency measure function.
By default, no clock is selected.
Table 134. Frequency measure function frequency clock select register (FREQMEAS_REF,
address 0x4001 4160) bit description
Bit
Symbol
3:0
CLKIN
Value
-
Reset
value
Clock source number (decimal value) for frequency
measure function target clock.
0xF
0x0
System oscillator (MAIN_OSC)
0x1
IRC
0x2
WDOSC
0x3
32KHZOSC
0x4
USB_FTOGGLE
0x5
PIO0_5. (external pin)
0x6
PIO0_19. (external pin)
0x7
PIO0_30. (external pin)
0x8
31:4
Description
PIO1_27. (external pin)
Reserved.
-
9.6.9 Frequency measure function target clock select register
This register selects a clock for the target clock of the frequency measure function.
By default, no clock is selected.
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Chapter 9: LPC15xx Input multiplexing (INPUT MUX)
Table 135. Frequency measure function target clock select register (FREQMEAS_TARGET,
address 0x4001 4164) bit description
Bit
Symbol
3:0
CLKIN
31:4
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Value
Description
Reset
value
Clock source number (decimal value) for frequency
measure function target clock.
0xF
0x0
System oscillator (MAIN_OSC)
0x1
IRC
0x2
WDOSC
0x3
32KHZOSC
0x4
USB_FTOGGLE
0x5
PIO0_5. (external pin)
0x6
PIO0_19. (external pin)
0x7
PIO0_30. (external pin)
0x8
PIO1_27. (external pin)
Reserved.
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10.1 How to read this chapter
All GPIO registers refer to 32 pins on each port. Depending on the package type, not all
pins are available, and the corresponding bits in the GPIO registers are reserved (see
Table 136).
Table 136. GPIO pins available
Package
GPIO Port 0
GPIO Port 1
GPIO Port 2
LQFP48
PIO0_0 to PIO0_29
-
-
LQFP64
PIO0_0 to PIO0_31
PIO1_0 to PIO1_11
-
LQFP100
PIO0_0 to PIO0_31
PIO1_0 to PIO1_31
PIO2_0 to PIO2_11
10.2 Basic configuration
For the GPIO port registers, enable the clock to each GPIO port in the
SYSAHBCLKCTRL0 register (Table 50, bit 14 to 16).
10.3 Features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.
10.4 General description
The GPIO pins can be used in several ways to set pins as inputs or outputs and use the
inputs as combinations of level and edge sensitive interrupts.
The GPIOs can be used as external interrupts together with the pin interrupt and group
interrupt blocks, see Section 12.2 and Section 11.2.
The GPIO port registers configure each GPIO pin as input or output and read the state of
each pin if the pin is configured as input or set the state of each pin if the pin is configured
as output.
10.5 Register description
Note: In all GPIO registers, bits that are not shown are reserved.
GPIO port addresses can be read and written as bytes, halfwords, or words.
Remark: ext in this table and subsequent tables indicates that the data read after reset
depends on the state of the pin, which in turn may depend on an external source.
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Chapter 10: LPC15xx General Purpose I/O (GPIO)
Table 137. Register overview: GPIO port (base address 0x1C00 0000)
Name
Access
Address
offset
Description
Reset
value
Width
Reference
B0 to B31
R/W
0x0000 to 0x001F
Byte pin registers port 0; pins
PIO0_0 to PIO0_31
ext
byte (8 bit)
Table 138
B32 to B63
R/W
0x0020 to 0x003F
Byte pin registers port 1
ext
byte (8 bit)
Table 138
B64 to B75
R/W
0x0040 to 0x004B
Byte pin registers port 2
ext
byte (8 bit)
Table 138
W0 to W31
R/W
0x1000 to 0x107C
Word pin registers port 0
ext
word (32 bit)
Table 139
W32 to W63
R/W
0x1080 to 0x10FC
Word pin registers port 1
ext
word (32 bit)
Table 139
W64 to W75
R/W
0x1100 to 0x112C
Word pin registers port 2
ext
word (32 bit)
Table 139
DIR0
R/W
0x2000
Direction registers port 0
0
word (32 bit)
Table 140
DIR1
R/W
0x2004
Direction registers port 1
0
word (32 bit)
Table 140
DIR2
R/W
0x2008
Direction registers port 2
0
word (32 bit)
Table 140
MASK0
R/W
0x2080
Mask register port 0
0
word (32 bit)
Table 141
MASK1
R/W
0x2084
Mask register port 1
0
word (32 bit)
Table 141
MASK2
R/W
0x2088
Mask register port 2
0
word (32 bit)
Table 141
PIN0
R/W
0x2100
Port pin register port 0
ext
word (32 bit)
Table 142
PIN1
R/W
0x2104
Port pin register port 1
ext
word (32 bit)
Table 142
PIN2
R/W
0x2108
Port pin register port 2
ext
word (32 bit)
Table 142
MPIN0
R/W
0x2180
Masked port register port 0
ext
word (32 bit)
Table 143
MPIN1
R/W
0x2184
Masked port register port 1
ext
word (32 bit)
Table 143
MPIN2
R/W
0x2188
Masked port register port 2
ext
word (32 bit)
Table 143
SET0
R/W
0x2200
Write: Set register for port 0
Read: output bits for port 0
0
word (32 bit)
Table 144
SET1
R/W
0x2204
Write: Set register for port 1
Read: output bits for port 1
0
word (32 bit)
Table 144
SET2
R/W
0x2208
Write: Set register for port 2
Read: output bits for port 2
0
word (32 bit)
Table 144
CLR0
WO
0x2280
Clear port 0
NA
word (32 bit)
Table 145
CLR1
WO
0x2284
Clear port 1
NA
word (32 bit)
Table 145
CLR2
WO
0x2288
Clear port 2
NA
word (32 bit)
Table 145
NOT0
WO
0x2300
Toggle port 0
NA
word (32 bit)
Table 146
NOT1
WO
0x2304
Toggle port 1
NA
word (32 bit)
Table 146
NOT2
WO
0x2308
Toggle port 2
NA
word (32 bit)
Table 146
10.5.1 GPIO port byte pin registers
Each GPIO pin has a byte register in this address range. Software typically reads and
writes bytes to access individual pins, but can read or write halfwords to sense or set the
state of two pins, and read or write words to sense or set the state of four pins.
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Table 138. GPIO port byte pin registers (B[0:B75], addresses 0x1C00 0000 (B0) to 0x1C00
004B (B75)) bit description
Bit
Symbol Description
0
PBYTE
7:1
Reset Access
value
Read: state of the pin PIOm_n, regardless of direction,
ext
masking, or alternate function, except that pins configured as
analog I/O always read as 0. One register for each port pin:
m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11
for port 2.
Write: loads the pin’s output bit.
R/W
Reserved (0 on read, ignored on write)
-
0
10.5.2 GPIO port word pin registers
Each GPIO pin has a word register in this address range. Any byte, halfword, or word read
in this range will be all zeros if the pin is low or all ones if the pin is high, regardless of
direction, masking, or alternate function, except that pins configured as analog I/O always
read as zeros. Any write will clear the pin’s output bit if the value written is all zeros, else it
will set the pin’s output bit.
Table 139. GPIO port word pin registers (W[0:75], addresses 0x1C00 1000 (W0) to 0x1C00
112C (W75)) bit description
Bit
Symbol
Description
Reset Access
value
31:0
PWORD
Read 0: pin PIOm_n is LOW.
Write 0: clear output bit.
Read 0xFFFF FFFF: pin PIOm_n is HIGH.
Write any value 0x0000 0001 to 0xFFFF FFFF: set output
bit.
ext
R/W
Remark: Only 0 or 0xFFFF FFFF can be read. Writing any
value other than 0 will set the output bit.
One register for each port pin: m = port 0 to 2; n = pin 0 to 31
for port 0 and 1 and pin 0 to 11 for port2.
10.5.3 GPIO port direction registers
Each GPIO port has one direction register for configuring the port pins as inputs or
outputs.
Table 140. GPIO direction port register (DIR[0:2], address 0x1C00 2000 (DIR0) to 0x1C00
2008 (DIR2)) bit description
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Bit
Symbol
Description
31:0
DIRP
Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = 0
PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to
31 for port 0 and 1 and pin 0 to 11 for port2.
0 = input.
1 = output.
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Reset Access
value
R/W
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10.5.4 GPIO port mask registers
These registers affect writing and reading the MPORT registers. Zeroes in these registers
enable reading and writing; ones disable writing and result in zeros in corresponding
positions when reading.
Table 141. GPIO mask port register (MASK[0:2], address 0x1C00 2080 (MASK0) to 0x1C00
2088 (MASK2)) bit description
Bit
Symbol
Description
Reset Access
value
31:0
MASKP
Controls which bits corresponding to PIOm_n are active in the 0
MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 =
PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and
pin 0 to 11 for port2.
0 = Read MPORT: pin state; write MPORT: load output bit.
1 = Read MPORT: 0; write MPORT: output bit not affected.
R/W
10.5.5 GPIO port pin registers
Reading these registers returns the current state of the pins read, regardless of direction,
masking, or alternate functions, except that pins configured as analog I/O always read as
0s. Writing these registers loads the output bits of the pins written to, regardless of the
Mask register.
Table 142. GPIO port pin register (PIN[0:2], address 0x1C00 2100 (PIN0) to 0x1C00 2108
(PIN2) ) bit description
Bit
Symbol Description
Reset Access
value
31:0
PORT
ext
Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 =
PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to
31 for port 0 and 1 and pin 0 to 11 for port2.
0 = Read: pin is low; write: clear output bit.
1 = Read: pin is high; write: set output bit.
R/W
10.5.6 GPIO masked port pin registers
These registers are similar to the PORT registers, except that the value read is masked by
ANDing with the inverted contents of the corresponding MASK register, and writing to one
of these registers only affects output register bits that are enabled by zeros in the
corresponding MASK register
Table 143. GPIO masked port pin register (MPIN[0:2], address 0x1C00 2180 (MPIN0) to
0x1C00 2188 (MPIN2) ) bit description
Bit
Symbol
Description
Reset Access
value
31:0
MPORTP
Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., ext
bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port
0 and 1 and pin 0 to 11 for port2.
R/W
0 = Read: pin is LOW and/or the corresponding bit in the
MASK register is 1; write: clear output bit if the
corresponding bit in the MASK register is 0.
1 = Read: pin is HIGH and the corresponding bit in the
MASK register is 0; write: set output bit if the
corresponding bit in the MASK register is 0.
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10.5.7 GPIO port set registers
Output bits can be set by writing ones to these registers, regardless of MASK registers.
Reading from these register returns the port’s output bits, regardless of pin directions.
Table 144. GPIO set port register (SET[0:2], address 0x1C00 2200 (SET0) to 0x1C00 2208
(SET2) ) bit description
Bit
Symbol
Description
Reset
value
Access
31:0
SETP
Read or set output bits.
0 = Read: output bit: write: no operation.
1 = Read: output bit; write: set output bit.
0
R/W
10.5.8 GPIO port clear registers
Output bits can be cleared by writing ones to these write-only registers, regardless of
MASK registers.
Table 145. GPIO clear port register (CLR[0:2], 0x1C00 2280 (CLR0) to 0x1C00 2288 (CLR2))
bit description
Bit
Symbol
Description
Reset Access
value
31:0
CLRP
Clear output bits:
0 = No operation.
1 = Clear output bit.
NA
WO
10.5.9 GPIO port toggle registers
Output bits can be toggled/inverted/complemented by writing ones to these write-only
registers, regardless of MASK registers.
Table 146. GPIO toggle port register (NOT[0:2], address 0x1C00 2300 (NOT0) to 0x1C00 2308
(NOT2)) bit description
Bit
Symbol Description
Reset
value
Access
31:0
NOTP
NA
WO
Toggle output bits:
0 = no operation.
1 = Toggle output bit.
10.6 Functional description
10.6.1 Reading pin state
Software can read the state of all GPIO pins except those selected for analog input or
output in the “I/O Configuration” logic. A pin does not have to be selected for GPIO in “I/O
Configuration” in order to read its state. There are four ways to read pin state:
• The state of a single pin can be read with 7 high-order zeros from a Byte Pin register.
• The state of a single pin can be read in all bits of a byte, halfword, or word from a
Word Pin register.
• The state of multiple pins in a port can be read as a byte, halfword, or word from a
PORT register.
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• The state of a selected subset of the pins in a port can be read from a Masked Port
(MPORT) register. Pins having a 1 in the port’s Mask register will read as 0 from its
MPORT register.
10.6.2 GPIO output
Each GPIO pin has an output bit in the GPIO block. These output bits are the targets of
write operations to the pins. Two conditions must be met in order for a pin’s output bit to
be driven onto the pin:
1. The pin must be selected for GPIO operation in the switch matrix (this is the default),
and
2. the pin must be selected for output by a 1 in its port’s DIR register.
If either or both of these conditions is (are) not met, writing to the pin has no effect.
There are seven ways to change GPIO output bits:
• Writing to a Byte Pin register loads the output bit from the least significant bit.
• Writing to a Word Pin register loads the output bit with the OR of all of the bits written.
(This feature follows the definition of truth of a multi-bit value in programming
languages.)
• Writing to a port’s PORT register loads the output bits of all the pins written to.
• Writing to a port’s MPORT register loads the output bits of pins identified by zeros in
corresponding positions of the port’s MASK register.
• Writing ones to a port’s SET register sets output bits.
• Writing ones to a port’s CLR register clears output bits.
• Writing ones to a port’s NOT register toggles/complements/inverts output bits.
The state of a port’s output bits can be read from its SET register. Reading any of the
registers described in 10.6.1 returns the state of pins, regardless of their direction or
alternate functions.
10.6.3 Masked I/O
A port’s MASK register defines which of its pins should be accessible in its MPORT
register. Zeroes in MASK enable the corresponding pins to be read from and written to
MPORT. Ones in MASK force a pin to read as 0 and its output bit to be unaffected by
writes to MPORT. When a port’s MASK register contains all zeros, its PORT and MPORT
registers operate identically for reading and writing.
Applications in which interrupts can result in Masked GPIO operation, or in task switching
among tasks that do Masked GPIO operation, must treat code that uses the Mask register
as a protected/restricted region. This can be done by interrupt disabling or by using a
semaphore.
The simpler way to protect a block of code that uses a MASK register is to disable
interrupts before setting the MASK register, and re-enable them after the last operation
that uses the MPORT or MASK register.
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More efficiently, software can dedicate a semaphore to the MASK registers, and
set/capture the semaphore controlling exclusive use of the MASK registers before setting
the MASK registers, and release the semaphore after the last operation that uses the
MPORT or MASK registers.
10.6.4 Recommended practices
The following lists some recommended uses for using the GPIO port registers:
•
•
•
•
For initial setup after Reset or re-initialization, write the PORT registers.
To change the state of one pin, write a Byte Pin or Word Pin register.
To change the state of multiple pins at a time, write the SET and/or CLR registers.
To change the state of multiple pins in a tightly controlled environment like a software
state machine, consider using the NOT register. This can require less write operations
than SET and CLR.
• To read the state of one pin, read a Byte Pin or Word Pin register.
• To make a decision based on multiple pins, read and mask a PORT register.
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Chapter 11: LPC15xx Group GPIO input interrupt (GINT0/1)
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11.1 How to read this chapter
11.2 Features
• The inputs from any number of digital pins can be enabled to contribute to a combined
group interrupt.
• The polarity of each input enabled for the group interrupt can be configured HIGH or
LOW.
• Enabled interrupts can be logically combined through an OR or AND operation.
• Two group interrupts are supported to reflect two distinct interrupt patterns.
• The grouped interrupts can wake up the part from sleep, deep-sleep or power-down
modes.
11.3 Basic configuration
For the group interrupt feature, enable the clock to both the GROUP0 and GROUP1
register interfaces in the SYSAHBCLKCTRL0 register ((Table 50, bit 19). The group
interrupt wake-up feature is enabled in the STARTERP0 register (Table 76).
The GINT block reads the input from the pin directly bypassing the switch matrix.
Make sure that no analog function is selected on pins that are input to the group
interrupts. Selecting an analog function in the switch matrix PINENABLE registers
disables the digital pad and the digital signal is tied to 0.
11.4 General description
The GPIO pins can be used in several ways to set pins as inputs or outputs and use the
inputs as combinations of level and edge sensitive interrupts.
For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks
(GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are
enabled to generate interrupts and what the active polarities of each of those inputs are.
The GPIO grouped interrupt registers also select whether the interrupt output will be level
or edge triggered and whether it will be based on the OR or the AND of all of the enabled
inputs.
When the designated pattern is detected on the selected input pins, the GPIO grouped
interrupt block generates an interrupt. If the part is in a power-savings mode, it l first
asynchronously wakes the part up prior to asserting the interrupt request. The interrupt
request line can be cleared by writing a one to the interrupt status bit in the control
register.
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Chapter 11: LPC15xx Group GPIO input interrupt (GINT0/1)
11.5 Register description
Note: In all registers, bits that are not shown are reserved.
Table 147. Register overview: GROUP0 interrupt (base address 0x400A 8000 (GINT0) and
0x400A C000 (GINT1))
Name
Access Address Description
offset
Reset
value
Reference
CTRL
R/W
0x000
GPIO grouped interrupt control
register
0
Table 148
PORT_POL0 R/W
0x020
GPIO grouped interrupt port 0 polarity 0xFFFF
register
FFFF
Table 149
PORT_POL1 R/W
0x024
GPIO grouped interrupt port 1 polarity 0xFFFF
register
FFFF
Table 149
PORT_POL2 R/W
0x028
GPIO grouped interrupt port 2 polarity 0xFFFF
register
FFFF
Table 149
PORT_ENA0 R/W
0x040
GPIO grouped interrupt port 0 enable
register
0
Table 150
PORT_ENA1 R/W
0x044
GPIO grouped interrupt port 1 enable
register
0
Table 150
PORT_ENA2 R/W
0x048
GPIO grouped interrupt port 2 enable
register
0
Table 150
11.5.1 Grouped interrupt control register
Table 148. GPIO grouped interrupt control register (CTRL, addresses 0x400A 8000 (GINT0)
and 0x400A C000 (GINT1)) bit description
Bit
Symbol
0
INT
1
2
31:3
Value
Reset value
Group interrupt status. This bit is cleared by writing a 0
one to it. Writing zero has no effect.
0
No interrupt request is pending.
1
Interrupt request is active.
COMB
Combine enabled inputs for group interrupt
0
0
OR functionality: A grouped interrupt is generated
when any one of the enabled inputs is active (based
on its programmed polarity).
1
AND functionality: An interrupt is generated when all
enabled bits are active (based on their programmed
polarity).
TRIG
-
Description
Group interrupt trigger
0
Edge-triggered
1
Level-triggered
-
Reserved
0
0
11.5.2 GPIO grouped interrupt port polarity registers
The grouped interrupt port polarity registers determine how the polarity of each enabled
pin contributes to the grouped interrupt. Each port is associated with its own port polarity
register, and the values of both registers together determine the grouped interrupt.
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Chapter 11: LPC15xx Group GPIO input interrupt (GINT0/1)
Each register PORT_POLm controls the polarity of pins in port m.
Table 149. GPIO grouped interrupt port polarity registers (PORT_POL[0:2], addresses
0x400A 8020 (PORT_POL0) to 0x400A 8028 (PORT_POL2) (GINT0) and 0x400A
C020 (PORT_POL0) to 0x400A C028 (PORT_POL2) (GINT1)) bit description
Bit
Symbol Description
31:0
POL
Reset Access
value
Configure pin polarity of port m pins for group interrupt. Bit n 1
corresponds to pin PIOm_n of port m.
0 = the pin is active LOW. If the level on this pin is LOW, the
pin contributes to the group interrupt.
1 = the pin is active HIGH. If the level on this pin is HIGH, the
pin contributes to the group interrupt.
-
11.5.3 GPIO grouped interrupt port enable registers
The grouped interrupt port enable registers enable the pins which contribute to the
grouped interrupt. Each port is associated with its own port enable register, and the values
of both registers together determine which pins contribute to the grouped interrupt.
Each register PORT_ENm enables pins in port m.
Table 150. GPIO grouped interrupt port enable registers (PORT_ENA[0:2], addresses 0x400A
8040 (PORT_ENA0) to 0x400A 8048 (PORT_ENA2) (GINT0) and 0x400A C040
(PORT_ENA0) to 0x400A C048 (PORT_ENA2) (GINT1)) bit description
Bit
Symbol Description
31:0
ENA
Reset Access
value
Enable port 0 pin for group interrupt. Bit n corresponds to pin 0
Pm_n of port m.
0 = the port 0 pin is disabled and does not contribute to the
grouped interrupt.
1 = the port 0 pin is enabled and contributes to the grouped
interrupt.
-
11.6 Functional description
Any subset of the pins in each port can be selected to contribute to a common group
interrupt (GINT) and can be enabled to wake the part up from Deep-sleep mode or
Power-down mode.
An interrupt can be requested for each port, based on any selected subset of pins within
each port. The pins that contribute to each port interrupt are selected by 1s in the port’s
Enable register, and an interrupt polarity can be selected for each pin in the port’s Polarity
register. The level on each pin is exclusive-ORed with its polarity bit, and the result is
ANDed with its enable bit. These results are then inclusive-ORed among all the pins in the
port to create the port’s raw interrupt request.
The raw interrupt request from each of the two group interrupts is sent to the NVIC, which
can be programmed to treat it as level- or edge-sensitive, or it can be edge-detected by
the wake-up interrupt logic (see Table 76).
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
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12.1 How to read this chapter
The pin interrupt generator and the pattern match engine are available on all LPC15xx
parts.
12.2 Features
• Pin interrupts
– Up to eight pins can be selected from all GPIO pins on ports 0 and 1 as edge- or
level-sensitive interrupt requests. Each request creates a separate interrupt in the
NVIC.
– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
– Level-sensitive interrupt pins can be HIGH- or LOW-active.
• Pattern match engine
– Up to 8 pins can be selected from all digital pins on ports 0 and 1 to contribute to a
boolean expression. The boolean expression consists of specified levels and/or
transitions on various combinations of these pins.
– Each bit slice minterm (product term) comprising the specified boolean expression
can generate its own, dedicated interrupt request.
– Any occurrence of a pattern match can be programmed to also generate an RXEV
notification to the ARM CPU. The RXEV signal can be connected to a pin.
– Pattern match can be used, in conjunction with software, to create complex state
machines based on pin inputs.
12.3 Basic configuration
• Pin interrupts:
– Select up to eight external interrupt pins from all digital port pins on ports 0 and 1 in
the INMUX block (Table 131). The pin selection process is the same for pin
interrupts and the pattern match engine. The two features are mutually exclusive.
– Enable the clock to the pin interrupt register block in the SYSAHBCLKCTRL0
register (Table 50, bit 18).
– If you want to use the pin interrupts to wake up the part from deep-sleep mode or
power-down mode, enable the pin interrupt wake-up feature in the STARTERP0
register (Table 76).
– Each selected pin interrupt is assigned to one interrupt in the NVIC (interrupts #7 to
#14 for pin interrupts 0 to 7).
• Pattern match engine:
– Select up to eight external pins from all digital port pins on ports 0 and 1 in the
Input mux block (Table 131). The pin selection process is the same for pin
interrupts and the pattern match engine. The two features are mutually exclusive.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
– Enable the clock to the pin interrupt register block in the SYSAHBCLKCTRL
register (Table 50, bit 18).
– Each bit slice of the pattern match engine is assigned to one interrupt in the NVIC
(interrupts #7 to #14 for pin interrupts 0 to 7).
– The combined interrupt from all slices or slice combinations can be connected to
the ARM RXEV request and to pin function GPIO_INT_BMAT through the switch matrix
movable function register (PINASSIGN15, Table 122).
12.3.1 Configure pins as pin interrupts or as inputs to the pattern match
engine
Follow these steps to configure pins as pin interrupts:
1. Determine the pins that serve as pin interrupts on the LPC15xx package. See the data
sheet for determining the GPIO port pin number associated with the package pin.
2. For each pin interrupt, program the GPIO port pin number from ports 0 and 1 into one
of the eight PINTSEL registers in the Input mux block.
Remark: The port pin number serves to identify the pin to the PINTSEL register. Any
function, including GPIO, can be assigned to this pin through the switch matrix.
3. Enable each pin interrupt in the NVIC.
Once the pin interrupts or pattern match inputs are configured, you can set up the pin
interrupt detection levels or the pattern match boolean expression.
See Section 9.6.5 “Pin interrupt select registers” in the Input mux block for the PINTSEL
registers.
Remark: The inputs to the Pin interrupt select registers bypass the switch matrix. They do
not have to be selected as GPIO in the switch matrix. Make sure that no analog function is
selected on pins that are input to the PINSELECT registers.
12.4 Pin description
The inputs to the pin interrupt and pattern match engine are determined by the pin
interrupt select registers in the Input mux. See Section 9.6.5 “Pin interrupt select
registers”.
The pattern match engine output is assigned to an external pin through the switch matrix.
See Section 8.3.1 “Connect an internal signal to a package pin” for the steps that you
need to follow to assign the GPIO pattern match function to a pin on the LPC15xx
package.
Table 151. GPIO pin interrupt/pattern match pin description
Function
Direction Type
GPIO_INT_BMAT
O
external any pin
to pin
PINASSIGN15
Table 122
GPIO pattern match output
8 pin interrupts
I
external any pin
to pin
PINSEL[0:7]
Table 131
External pin interrupts
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
12.5 General description
Pins with configurable functions can serve as external interrupts or inputs to the pattern
match engine. You can configure up to eight pins total using the PINTSEL registers in the
Input mux block for these features.
12.5.1 Pin interrupts
From all available GPIO pins, up to eight pins can be selected in the system control block
to serve as external interrupt pins (see Table 131). The external interrupt pins are
connected to eight individual interrupts in the NVIC and are created based on rising or
falling edges or on the input level on the pin.
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12.5.2 Pattern match engine
The pattern match feature allows complex boolean expressions to be constructed from
the same set of eight GPIO pins that were selected for the GPIO pin interrupts. Each term
in the boolean expression is implemented as one slice of the pattern match engine. A slice
consists of an input selector and a detect logic that monitors the selected input
continuously and creates a HIGH output if the input qualifies as detected, that is as true.
Several terms can be combined to a minterm and a pin interrupt is asserted when the
minterm evaluates as true.
The detect logic of each slice can detect the following events on the selected input:
• Edge with memory (sticky): A rising edge, a falling edge, or a rising or falling edge that
is detected at any time after the edge-detection mechanism has been cleared. The
input qualifies as detected (the detect logic output remains HIGH) until the pattern
match engine detect logic is cleared again.
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• Event (non-sticky): Every time an edge (rising or falling) is detected, the detect logic
output for this pin goes HIGH. This bit is cleared after one clock cycle, and the detect
logic can detect another edge,
• Level: A HIGH or LOW level on the selected input.
Figure 18 shows the details of the edge detection logic for each slice.
You can combine a sticky event with non-sticky events to create a pin interrupt whenever
a rising or falling edge occurs after a qualifying edge event.
You can create a time window during which rising or falling edges can create a pin
interrupt by combining a level detect with an event detect. See Section 12.7.3 for details.
The connections between the pins and the pattern match engine are shown in Figure 17.
All pins that are inputs to the pattern match engine are selected in the SYSCON block and
can be GPIO port pins or other pin function depending on the switch matrix configuration.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
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Fig 17. Pattern match engine connections
The pattern match logic continuously monitors the eight inputs and generates interrupts
when any one or more minterms (product terms) of the specified boolean expression is
matched. A separate interrupt request is generated for each individual minterm.
In addition, the pattern match module can be enabled to generate a Receive Event
(RXEV) output to the ARM core when the entire boolean expression is true (i.e. when any
minterm is matched).
The RXEV output is also be routed to GPIO_INT_BMAT pin. This allows the GPIO module
to provide a rudimentary programmable logic capability employing up to eight inputs and
one output.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
The pattern match function utilizes the same eight interrupt request lines as the pin
interrupts so these two features are mutually exclusive as far as interrupt generation is
concerned. A control bit is provided to select whether interrupt requests are generated in
response to the standard pin interrupts or to pattern matches. Note that, if the pin
interrupts are selected, the RXEV request to the CPU can still be enabled for pattern
matches.
Remark: Pattern matching cannot be used to wake the part up from power-down modes.
Pin interrupts must be selected in order to use the GPIO for wake-up.
The pattern match module is constructed of eight bit-slice elements. Each bit slice is
programmed to represent one component of one minterm (product term) within the
boolean expression. The interrupt request associated with the last bit slice for a particular
minterm will be asserted whenever that minterm is matched.
(See bit slice drawing Figure 18).
The pattern match capability can be used to create complex software state machines.
Each minterm (and its corresponding individual interrupt) represents a different transition
event to a new state. Software can then establish the new set of conditions (that is a new
boolean expression) that will cause a transition out of the current state.
,1
,1
,1
,1
,1
,1
,1
,1
08;
5LVH 'HWHFW
)URP 3UHYLRXV
6OLFH
VWLFN\ ZLWK V\QFK
FOHDU
)DOO 'HWHFW
30&)*
3URGB(QGSWVL
VWLFN\ ZLWK V\QFK
FOHDU
3065&
65&L
3DWWHUQB0DWFKL
,QWUB5HTL
08;
5LVH 'HWHFW
QRQVWLFN\
)DOO 'HWHFW
QRQVWLFN\
7R 1H[W 6OLFH
30&)*
&)*L
Fig 18. Pattern match bit slice with detect logic
12.5.2.1 Example
Assume the expression: (IN0)~(IN1)(IN3)^ + (IN1)(IN2) + (IN0)~(IN3)~(IN4) is specified
through the registers PMSRC (Table 164) and PMCFG (Table 165). Each term in the
boolean expression, (IN0), ~(IN1), (IN3)^, etc., represents one bit slice of the pattern
match engine.
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• In the first minterm (IN0)~(IN1)(IN3)^, bit slice 0 monitors for a high-level on input
(IN0), bit slice 1 monitors for a low level on input (IN1) and bit slice 2 monitors for a
rising-edge on input (IN3). If this combination is detected, that is if all three terms are
true, the interrupt associated with bit slice 2 will be asserted.
• In the second minterm (IN1)(IN2), bit slice 3 monitors input (IN1) for a high level, bit
slice 4 monitors input (IN2) for a high level. If this combination is detected, the
interrupt associated with bit slice 4 will be asserted.
• In the third minterm (IN0)~(IN3)~(IN4), bit slice 5 monitors input (IN0) for a high level,
bit slice 6 monitors input (IN3) for a low level, and bit slice 7 monitors input (IN4) for a
low level. If this combination is detected, the interrupt associated with bit slice 7 will be
asserted.
• The ORed result of all three minterms asserts the RXEV request to the CPU and the
GPIO_INT_BMAT output. That is, if any of the three terms are true, the output is
asserted.
Related links:
Section 12.7.2
12.6 Register description
Table 152. Register overview: Pin interrupts/pattern match engine (base address: 0x400A
4000)
UM10736
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Name
Access Address Description
offset
Reset Reference
value
ISEL
R/W
0x000
Pin Interrupt Mode register
0
Table 153
IENR
R/W
0x004
Pin interrupt level or rising edge interrupt
enable register
0
Table 154
SIENR
WO
0x008
Pin interrupt level or rising edge interrupt
set register
NA
Table 155
CIENR
WO
0x00C
Pin interrupt level (rising edge interrupt)
clear register
NA
Table 156
IENF
R/W
0x010
Pin interrupt active level or falling edge
interrupt enable register
0
Table 157
SIENF
WO
0x014
Pin interrupt active level or falling edge
interrupt set register
NA
Table 158
CIENF
WO
0x018
Pin interrupt active level or falling edge
interrupt clear register
NA
Table 159
RISE
R/W
0x01C
Pin interrupt rising edge register
0
Table 160
FALL
R/W
0x020
Pin interrupt falling edge register
0
Table 161
IST
R/W
0x024
Pin interrupt status register
0
Table 162
PMCTRL
R/W
0x028
Pattern match interrupt control register
0
Table 163
PMSRC
R/W
0x02C
Pattern match interrupt bit-slice source
register
0
Table 164
PMCFG
R/W
0x030
Pattern match interrupt bit slice
configuration register
0
Table 165
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
12.6.1 Pin interrupt mode register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 131), one
bit in the ISEL register determines whether the interrupt is edge or level sensitive.
Table 153. Pin interrupt mode register (ISEL, address 0x400A 4000) bit description
Bit
Symbol Description
Reset Access
value
7:0
PMODE Selects the interrupt mode for each pin interrupt. Bit n
configures the pin interrupt selected in PINTSELn.
0 = Edge sensitive
1 = Level sensitive
0
R/W
31:8
-
-
-
Reserved.
12.6.2 Pin interrupt level or rising edge interrupt enable register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 131), one
bit in the IENR register enables the interrupt depending on the pin interrupt mode
configured in the ISEL register:
• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
enabled.
• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled.
The IENF register configures the active level (HIGH or LOW) for this interrupt.
Table 154. Pin interrupt level or rising edge interrupt enable register (IENR, address 0x400A
4004) bit description
Bit
Symbol
Description
Reset Access
value
7:0
ENRL
Enables the rising edge or level interrupt for each pin
interrupt. Bit n configures the pin interrupt selected in
PINTSELn.
0 = Disable rising edge or level interrupt.
1 = Enable rising edge or level interrupt.
0
R/W
31:8
-
Reserved.
-
-
12.6.3 Pin interrupt level or rising edge interrupt set register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 131), one
bit in the SIENR register sets the corresponding bit in the IENR register depending on the
pin interrupt mode configured in the ISEL register:
• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
set.
• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is set.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
Table 155. Pin interrupt level or rising edge interrupt set register (SIENR, address 0x400A
4008) bit description
Bit
Symbol
Description
Reset Access
value
7:0
SETENRL
Ones written to this address set bits in the IENR, thus
enabling interrupts. Bit n sets bit n in the IENR register.
0 = No operation.
1 = Enable rising edge or level interrupt.
NA
WO
31:8
-
Reserved.
-
-
12.6.4 Pin interrupt level or rising edge interrupt clear register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 131), one
bit in the CIENR register clears the corresponding bit in the IENR register depending on
the pin interrupt mode configured in the ISEL register:
• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
cleared.
• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is cleared.
Table 156. Pin interrupt level or rising edge interrupt clear register (CIENR, address 0x400A
400C) bit description
Bit
Symbol
Description
Reset Access
value
7:0
CENRL
Ones written to this address clear bits in the IENR, thus
disabling the interrupts. Bit n clears bit n in the IENR
register.
0 = No operation.
1 = Disable rising edge or level interrupt.
NA
WO
31:8
-
Reserved.
-
-
12.6.5 Pin interrupt active level or falling edge interrupt enable register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 131), one
bit in the IENF register enables the falling edge interrupt or the configures the level
sensitivity depending on the pin interrupt mode configured in the ISEL register:
• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is
enabled.
• If the pin interrupt mode is level sensitive (PMODE = 1), the active level of the level
interrupt (HIGH or LOW) is configured.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
Table 157. Pin interrupt active level or falling edge interrupt enable register (IENF, address
0x400A 4010) bit description
Bit
Symbol Description
Reset Access
value
7:0
ENAF
Enables the falling edge or configures the active level interrupt
for each pin interrupt. Bit n configures the pin interrupt selected
in PINTSELn.
0 = Disable falling edge interrupt or set active interrupt level
LOW.
1 = Enable falling edge interrupt enabled or set active interrupt
level HIGH.
0
R/W
Reserved.
-
-
31:8 -
12.6.6 Pin interrupt active level or falling edge interrupt set register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 131), one
bit in the SIENF register sets the corresponding bit in the IENF register depending on the
pin interrupt mode configured in the ISEL register:
• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is
set.
• If the pin interrupt mode is level sensitive (PMODE = 1), the HIGH-active interrupt is
selected.
Table 158. Pin interrupt active level or falling edge interrupt set register (SIENF, address
0x400A 4014) bit description
Bit
Symbol
Description
7:0
SETENAF Ones written to this address set bits in the IENF, thus
enabling interrupts. Bit n sets bit n in the IENF register.
0 = No operation.
1 = Select HIGH-active interrupt or enable falling edge
interrupt.
NA
WO
31:8
-
-
-
Reserved.
Reset Access
value
12.6.7 Pin interrupt active level or falling edge interrupt clear register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 131), one
bit in the CIENF register sets the corresponding bit in the IENF register depending on the
pin interrupt mode configured in the ISEL register:
• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is
cleared.
• If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is
selected.
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Table 159. Pin interrupt active level or falling edge interrupt clear register (CIENF, address
0x400A 4018) bit description
Bit
Symbol Description
Reset Access
value
7:0
CENAF
Ones written to this address clears bits in the IENF, thus
disabling interrupts. Bit n clears bit n in the IENF register.
0 = No operation.
1 = LOW-active interrupt selected or falling edge interrupt
disabled.
NA
WO
31:8
-
Reserved.
-
-
12.6.8 Pin interrupt rising edge register
This register contains ones for pin interrupts selected in the PINTSELn registers (see
Table 131) on which a rising edge has been detected. Writing ones to this register clears
rising edge detection. Ones in this register assert an interrupt request for pins that are
enabled for rising-edge interrupts. All edges are detected for all pins selected by the
PINTSELn registers, regardless of whether they are interrupt-enabled.
Table 160. Pin interrupt rising edge register (RISE, address 0x400A 401C) bit description
Bit
Symbol
Description
Reset Access
value
7:0
RDET
Rising edge detect. Bit n detects the rising edge of the pin
selected in PINTSELn.
Read 0: No rising edge has been detected on this pin since
Reset or the last time a one was written to this bit.
Write 0: no operation.
Read 1: a rising edge has been detected since Reset or the
last time a one was written to this bit.
Write 1: clear rising edge detection for this pin.
0
R/W
Reserved.
-
-
31:8 -
12.6.9 Pin interrupt falling edge register
This register contains ones for pin interrupts selected in the PINTSELn registers (see
Table 131) on which a falling edge has been detected. Writing ones to this register clears
falling edge detection. Ones in this register assert an interrupt request for pins that are
enabled for falling-edge interrupts. All edges are detected for all pins selected by the
PINTSELn registers, regardless of whether they are interrupt-enabled.
Table 161. Pin interrupt falling edge register (FALL, address 0x400A 4020) bit description
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Bit
Symbol Description
7:0
FDET
Falling edge detect. Bit n detects the falling edge of the pin
0
selected in PINTSELn.
Read 0: No falling edge has been detected on this pin since
Reset or the last time a one was written to this bit.
Write 0: no operation.
Read 1: a falling edge has been detected since Reset or the
last time a one was written to this bit.
Write 1: clear falling edge detection for this pin.
R/W
31:8
-
Reserved.
-
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value
-
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
12.6.10 Pin interrupt status register
Reading this register returns ones for pin interrupts that are currently requesting an
interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones
to this register clears both rising- and falling-edge detection for the pin. For level-sensitive
pins, writing ones inverts the corresponding bit in the Active level register, thus switching
the active level on the pin.
Table 162. Pin interrupt status register (IST, address 0x400A 4024) bit description
Bit
Symbol Description
Reset Access
value
7:0
PSTAT
Pin interrupt status. Bit n returns the status, clears the edge 0
interrupt, or inverts the active level of the pin selected in
PINTSELn.
Read 0: interrupt is not being requested for this interrupt pin.
Write 0: no operation.
Read 1: interrupt is being requested for this interrupt pin.
Write 1 (edge-sensitive): clear rising- and falling-edge
detection for this pin.
Write 1 (level-sensitive): switch the active level for this pin (in
the IENF register).
R/W
31:8
-
Reserved.
-
-
12.6.11 Pattern Match Interrupt Control Register
The pattern match control register contains one bit to select pattern-match interrupt
generation (as opposed to pin interrupts which share the same interrupt request lines),
and another to enable the RXEV output to the cpu. This register also allows the current
state of any pattern matches to be read.
If the pattern match feature is not used (either for interrupt generation or for RXEV
assertion) bits SEL_PMATCH and ENA_RXEV of this register should be left at 0 to
conserve power.
Remark: Set up the pattern-match configuration in the PMSRC and PMCFG registers
before writing to this register to enable (or re-enable) the pattern-match functionality. This
eliminates the possibility of spurious interrupts as the feature is being enabled.
Table 163. Pattern match interrupt control register (PMCTRL, address 0x400A 4028)
bit description
UM10736
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Bit
Symbol
Value
0
SEL_PMATCH
Description
Reset
value
Specifies whether the 8 pin interrupts are controlled by 0
the pin interrupt function or by the pattern match
function.
0
Pin interrupt. Interrupts are driven in response to the
standard pin interrupt function
1
Pattern match. Interrupts are driven in response to
pattern matches.
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Table 163. Pattern match interrupt control register (PMCTRL, address 0x400A 4028)
bit description
Bit
Symbol
1
ENA_RXEV
23:2
-
31:24
PMAT
Value
Description
Reset
value
Enables the RXEV output to the ARM cpu and/or to a
GPIO output when the specified boolean expression
evaluates to true.
0
0
Disabled. RXEV output to the cpu is disabled.
1
Enabled. RXEV output to the cpu is enabled.
Reserved. Do not write 1s to unused bits.
-
0
This field displays the current state of pattern matches. 0x0
A 1 in any bit of this field indicates that the
corresponding product term is matched by the current
state of the appropriate inputs.
12.6.12 Pattern Match Interrupt Bit-Slice Source register
The bit-slice source register specifies the input source for each of the eight pattern match
bit slices.
Each of the possible eight inputs is selected in the pin interrupt select registers, see
Table 131. Input 0 corresponds to the pin selected in the PINTSEL0 register, input 1
corresponds to the pin selected in the PINTSEL1 register, and so forth.
Remark: Writing any value to either the PMCFG register or the PMSRC register, or
disabling the pattern-match feature (by clearing both the SEL_PMATCH and ENA_RXEV
bits in the PMCTRL register to zeros) will erase all edge-detect history.
Table 164. Pattern match bit-slice source register (PMSRC, address 0x4008 402C) bit description
Bit
Symbol
Description
Reset value
7:0
Reserved
Software should not write 1s to unused bits.
0
10:8
SRC0
Selects the input source for bit slice 0
0
UM10736
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Value
0x0
Input 0. Selects the pin selected in the PINTSEL0 register as the source
to bit slice 0.
0x1
Input 1. Selects the pin selected in the PINTSEL1 register as the source
to bit slice 0.
0x2
Input 2. Selects the pin selected in the PINTSEL2 register as the source
to bit slice 0.
0x3
Input 3. Selects the pin selected in the PINTSEL3 register as the source
to bit slice 0.
0x4
Input 4. Selects the pin selected in the PINTSEL4 register as the source
to bit slice 0.
0x5
Input 5. Selects the pin selected in the PINTSEL5 register as the source
to bit slice 0.
0x6
Input 6. Selects the pin selected in the PINTSEL6 register as the source
to bit slice 0.
0x7
Input 7. Selects the pin selected in the PINTSEL7 register as the source
to bit slice 0.
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Table 164. Pattern match bit-slice source register (PMSRC, address 0x4008 402C) bit description
Bit
Symbol
13:11
SRC1
16:14
Value
User manual
Reset value
Selects the input source for bit slice 1
0
0x0
Input 0. Selects pin interrupt input 0 as the source to bit slice 1.
0x1
Input 0. Selects the pin selected in the PINTSEL0 register as the source
to bit slice 0.
0x2
Input 1. Selects the pin selected in the PINTSEL1 register as the source
to bit slice 0.
0x3
Input 2. Selects the pin selected in the PINTSEL2 register as the source
to bit slice 0.
0x4
Input 3. Selects the pin selected in the PINTSEL3 register as the source
to bit slice 0.
0x5
Input 4. Selects the pin selected in the PINTSEL4 register as the source
to bit slice 0.
0x6
Input 5. Selects the pin selected in the PINTSEL5 register as the source
to bit slice 0.
0x7
Input 6. Selects the pin selected in the PINTSEL6 register as the source
to bit slice 0.
SRC2
UM10736
Description
Selects the input source for bit slice 2
0
0x0
Input 0. Selects the pin selected in the PINTSEL0 register as the source
to bit slice 0.
0x1
Input 1. Selects the pin selected in the PINTSEL1 register as the source
to bit slice 0.
0x2
Input 2. Selects the pin selected in the PINTSEL2 register as the source
to bit slice 0.
0x3
Input 3. Selects the pin selected in the PINTSEL3 register as the source
to bit slice 0.
0x4
Input 4. Selects the pin selected in the PINTSEL4 register as the source
to bit slice 0.
0x5
Input 5. Selects the pin selected in the PINTSEL5 register as the source
to bit slice 0.
0x6
Input 6. Selects the pin selected in the PINTSEL6 register as the source
to bit slice 0.
0x7
Input 7. Selects the pin selected in the PINTSEL7 register as the source
to bit slice 0.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
Table 164. Pattern match bit-slice source register (PMSRC, address 0x4008 402C) bit description
Bit
Symbol
19:17
SRC3
22:20
Value
User manual
Reset value
Selects the input source for bit slice 3
0
0x0
Input 0. Selects the pin selected in the PINTSEL0 register as the source
to bit slice 0.
0x1
Input 1. Selects the pin selected in the PINTSEL1 register as the source
to bit slice 0.
0x2
Input 2. Selects the pin selected in the PINTSEL2 register as the source
to bit slice 0.
0x3
Input 3. Selects the pin selected in the PINTSEL3 register as the source
to bit slice 0.
0x4
Input 4. Selects the pin selected in the PINTSEL4 register as the source
to bit slice 0.
0x5
Input 5. Selects the pin selected in the PINTSEL5 register as the source
to bit slice 0.
0x6
Input 6. Selects the pin selected in the PINTSEL6 register as the source
to bit slice 0.
0x7
Input 7. Selects the pin selected in the PINTSEL7 register as the source
to bit slice 0.
SRC4
UM10736
Description
Selects the input source for bit slice 4
0
0x0
Input 0. Selects the pin selected in the PINTSEL0 register as the source
to bit slice 0.
0x1
Input 1. Selects the pin selected in the PINTSEL1 register as the source
to bit slice 0.
0x2
Input 2. Selects the pin selected in the PINTSEL2 register as the source
to bit slice 0.
0x3
Input 3. Selects the pin selected in the PINTSEL3 register as the source
to bit slice 0.
0x4
Input 4. Selects the pin selected in the PINTSEL4 register as the source
to bit slice 0.
0x5
Input 5. Selects the pin selected in the PINTSEL5 register as the source
to bit slice 0.
0x6
Input 6. Selects the pin selected in the PINTSEL6 register as the source
to bit slice 0.
0x7
Input 7. Selects the pin selected in the PINTSEL7 register as the source
to bit slice 0.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
Table 164. Pattern match bit-slice source register (PMSRC, address 0x4008 402C) bit description
Bit
Symbol
25:23
SRC5
28:26
Value
User manual
Reset value
Selects the input source for bit slice 5
0
0x0
Input 0. Selects the pin selected in the PINTSEL0 register as the source
to bit slice 0.
0x1
Input 1. Selects the pin selected in the PINTSEL1 register as the source
to bit slice 0.
0x2
Input 2. Selects the pin selected in the PINTSEL2 register as the source
to bit slice 0.
0x3
Input 3. Selects the pin selected in the PINTSEL3 register as the source
to bit slice 0.
0x4
Input 4. Selects the pin selected in the PINTSEL4 register as the source
to bit slice 0.
0x5
Input 5. Selects the pin selected in the PINTSEL5 register as the source
to bit slice 0.
0x6
Input 6. Selects the pin selected in the PINTSEL6 register as the source
to bit slice 0.
0x7
Input 7. Selects the pin selected in the PINTSEL7 register as the source
to bit slice 0.
SRC6
UM10736
Description
Selects the input source for bit slice 6
0
0x0
Input 0. Selects the pin selected in the PINTSEL0 register as the source
to bit slice 0.
0x1
Input 1. Selects the pin selected in the PINTSEL1 register as the source
to bit slice 0.
0x2
Input 2. Selects the pin selected in the PINTSEL2 register as the source
to bit slice 0.
0x3
Input 3. Selects the pin selected in the PINTSEL3 register as the source
to bit slice 0.
0x4
Input 4. Selects the pin selected in the PINTSEL4 register as the source
to bit slice 0.
0x5
Input 5. Selects the pin selected in the PINTSEL5 register as the source
to bit slice 0.
0x6
Input 6. Selects the pin selected in the PINTSEL6 register as the source
to bit slice 0.
0x7
Input 7. Selects the pin selected in the PINTSEL7 register as the source
to bit slice 0.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
Table 164. Pattern match bit-slice source register (PMSRC, address 0x4008 402C) bit description
Bit
Symbol
31:29
SRC7
Value
Description
Reset value
Selects the input source for bit slice 7
0
0x0
Input 0. Selects the pin selected in the PINTSEL0 register as the source
to bit slice 0.
0x1
Input 1. Selects the pin selected in the PINTSEL1 register as the source
to bit slice 0.
0x2
Input 2. Selects the pin selected in the PINTSEL2 register as the source
to bit slice 0.
0x3
Input 3. Selects the pin selected in the PINTSEL3 register as the source
to bit slice 0.
0x4
Input 4. Selects the pin selected in the PINTSEL4 register as the source
to bit slice 0.
0x5
Input 5. Selects the pin selected in the PINTSEL5 register as the source
to bit slice 0.
0x6
Input 6. Selects the pin selected in the PINTSEL6 register as the source
to bit slice 0.
0x7
Input 7. Selects the pin selected in the PINTSEL7 register as the source
to bit slice 0.
12.6.13 Pattern Match Interrupt Bit Slice Configuration register
The bit-slice configuration register configures the detect logic and contains bits to select
from among eight alternative conditions for each bit slice that cause that bit slice to
contribute to a pattern match. The seven LSBs of this register specify which bit-slices are
the end-points of product terms in the boolean expression (i.e. where OR terms are to be
inserted in the expression).
Two types of edge detection on each input are possible:
• Sticky: A rising edge, a falling edge, or a rising or falling edge that is detected at any
time after the edge-detection mechanism has been cleared. The input qualifies as
detected (the detect logic output remains HIGH) until the pattern match engine detect
logic is cleared again.
• Non-sticky: Every time an edge (rising or falling) is detected, the detect logic output
for this pin goes HIGH. This bit is cleared after one clock cycle, and the edge detect
logic can detect another edge,
Remark: To clear the pattern match engine detect logic, write any value to either the
PMCFG register or the PMSRC register, or disable the pattern-match feature (by clearing
both the SEL_PMATCH and ENA_RXEV bits in the PMCTRL register to zeros). This will
erase all edge-detect history.
To select whether a slice marks the final component in a minterm of the boolean
expression, write a 1 in the corresponding PROD_ENPTSn bit. Setting a term as the final
component has two effects:
1. The interrupt request associated with this bit slice will be asserted whenever a match to that
product term is detected.
2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an
OR will be inserted in the boolean expression following the element controlled by this bit slice).
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
Table 165. Pattern match bit slice configuration register (PMCFG, address 0x400A 4030) bit description
Bit
Symbol
Value
0
PROD_EN
DPTS0
0
1
1
PROD_EN
DPTS1
0
1
2
PROD_EN
DPTS2
0
1
3
PROD_EN
DPTS3
0
1
4
PROD_EN
DPTS4
0
1
5
PROD_EN
DPTS5
0
1
6
PROD_EN
DPTS6
0
1
7
-
UM10736
User manual
Description
Reset
value
Determines whether slice 0 is an endpoint.
0
No effect. Slice 0 is not an endpoint.
endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the
NVIC is raised if the minterm evaluates as true.
Determines whether slice 1 is an endpoint.
0
No effect. Slice 1 is not an endpoint.
endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the
NVIC is raised if the minterm evaluates as true.
Determines whether slice 2 is an endpoint.
0
No effect. Slice 2 is not an endpoint.
endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the
NVIC is raised if the minterm evaluates as true.
Determines whether slice 3 is an endpoint.
0
No effect. Slice 3 is not an endpoint.
endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the
NVIC is raised if the minterm evaluates as true.
Determines whether slice 4 is an endpoint.
0
No effect. Slice 4 is not an endpoint.
endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the
NVIC is raised if the minterm evaluates as true.
Determines whether slice 5 is an endpoint.
0
No effect. Slice 5 is not an endpoint.
endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the
NVIC is raised if the minterm evaluates as true.
Determines whether slice 6 is an endpoint.
0
No effect. Slice 6 is not an endpoint.
endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the
NVIC is raised if the minterm evaluates as true.
Reserved. Bit slice 7 is automatically considered a product end point.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
Table 165. Pattern match bit slice configuration register (PMCFG, address 0x400A 4030) bit description …continued
Bit
Symbol
10:8
CFG0
13:11
Value
User manual
Reset
value
Specifies the match contribution condition for bit slice 0.
0b000
0x0
Constant HIGH. This bit slice always contributes to a product term match.
0x1
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x2
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x3
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the
specified input has occurred since the last time the edge detection for this bit slice
was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are
written to.
0x4
High level. Match (for this bit slice) occurs when there is a high level on the input
specified for this bit slice in the PMSRC register.
0x5
Low level. Match occurs when there is a low level on the specified input.
0x6
Constant 0. This bit slice never contributes to a match (should be used to disable any
unused bit slices).
0x7
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a
rising or falling edge is first detected on the specified input (this is a non-sticky
version of value 0x3). This bit is cleared after one clock cycle.
CFG1
UM10736
Description
Specifies the match contribution condition for bit slice 1.
0b000
0x0
Constant HIGH. This bit slice always contributes to a product term match.
0x1
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x2
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x3
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the
specified input has occurred since the last time the edge detection for this bit slice
was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are
written to.
0x4
High level. Match (for this bit slice) occurs when there is a high level on the input
specified for this bit slice in the PMSRC register.
0x5
Low level. Match occurs when there is a low level on the specified input.
0x6
Constant 0. This bit slice never contributes to a match (should be used to disable any
unused bit slices).
0x7
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a
rising or falling edge is first detected on the specified input (this is a non-sticky
version of value 0x3). This bit is cleared after one clock cycle.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
Table 165. Pattern match bit slice configuration register (PMCFG, address 0x400A 4030) bit description …continued
Bit
Symbol
16:14
CFG2
19:17
Value
User manual
Reset
value
Specifies the match contribution condition for bit slice 2.
0b000
0x0
Constant HIGH. This bit slice always contributes to a product term match.
0x1
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x2
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x3
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the
specified input has occurred since the last time the edge detection for this bit slice
was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are
written to.
0x4
High level. Match (for this bit slice) occurs when there is a high level on the input
specified for this bit slice in the PMSRC register.
0x5
Low level. Match occurs when there is a low level on the specified input.
0x6
Constant 0. This bit slice never contributes to a match (should be used to disable any
unused bit slices).
0x7
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a
rising or falling edge is first detected on the specified input (this is a non-sticky
version of value 0x3). This bit is cleared after one clock cycle.
CFG3
UM10736
Description
Specifies the match contribution condition for bit slice 3.
0b000
0x0
Constant HIGH. This bit slice always contributes to a product term match.
0x1
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x2
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x3
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the
specified input has occurred since the last time the edge detection for this bit slice
was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are
written to.
0x4
High level. Match (for this bit slice) occurs when there is a high level on the input
specified for this bit slice in the PMSRC register.
0x5
Low level. Match occurs when there is a low level on the specified input.
0x6
Constant 0. This bit slice never contributes to a match (should be used to disable any
unused bit slices).
0x7
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a
rising or falling edge is first detected on the specified input (this is a non-sticky
version of value 0x3). This bit is cleared after one clock cycle.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
Table 165. Pattern match bit slice configuration register (PMCFG, address 0x400A 4030) bit description …continued
Bit
Symbol
22:20
CFG4
25:23
Value
User manual
Reset
value
Specifies the match contribution condition for bit slice 4.
0b000
0x0
Constant HIGH. This bit slice always contributes to a product term match.
0x1
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x2
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x3
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the
specified input has occurred since the last time the edge detection for this bit slice
was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are
written to.
0x4
High level. Match (for this bit slice) occurs when there is a high level on the input
specified for this bit slice in the PMSRC register.
0x5
Low level. Match occurs when there is a low level on the specified input.
0x6
Constant 0. This bit slice never contributes to a match (should be used to disable any
unused bit slices).
0x7
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a
rising or falling edge is first detected on the specified input (this is a non-sticky
version of value 0x3). This bit is cleared after one clock cycle.
CFG5
UM10736
Description
Specifies the match contribution condition for bit slice 5.
0b000
0x0
Constant HIGH. This bit slice always contributes to a product term match.
0x1
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x2
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x3
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the
specified input has occurred since the last time the edge detection for this bit slice
was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are
written to.
0x4
High level. Match (for this bit slice) occurs when there is a high level on the input
specified for this bit slice in the PMSRC register.
0x5
Low level. Match occurs when there is a low level on the specified input.
0x6
Constant 0. This bit slice never contributes to a match (should be used to disable any
unused bit slices).
0x7
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a
rising or falling edge is first detected on the specified input (this is a non-sticky
version of value 0x3). This bit is cleared after one clock cycle.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
Table 165. Pattern match bit slice configuration register (PMCFG, address 0x400A 4030) bit description …continued
Bit
Symbol
28:26
CFG6
31:29
Value
User manual
Reset
value
Specifies the match contribution condition for bit slice 6.
0b000
0x0
Constant HIGH. This bit slice always contributes to a product term match.
0x1
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x2
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x3
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the
specified input has occurred since the last time the edge detection for this bit slice
was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are
written to.
0x4
High level. Match (for this bit slice) occurs when there is a high level on the input
specified for this bit slice in the PMSRC register.
0x5
Low level. Match occurs when there is a low level on the specified input.
0x6
Constant 0. This bit slice never contributes to a match (should be used to disable any
unused bit slices).
0x7
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a
rising or falling edge is first detected on the specified input (this is a non-sticky
version of value 0x3). This bit is cleared after one clock cycle.
CFG7
UM10736
Description
Specifies the match contribution condition for bit slice 7.
0b000
0x0
Constant HIGH. This bit slice always contributes to a product term match.
0x1
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x2
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x3
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the
specified input has occurred since the last time the edge detection for this bit slice
was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are
written to.
0x4
High level. Match (for this bit slice) occurs when there is a high level on the input
specified for this bit slice in the PMSRC register.
0x5
Low level. Match occurs when there is a low level on the specified input.
0x6
Constant 0. This bit slice never contributes to a match (should be used to disable any
unused bit slices).
0x7
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a
rising or falling edge is first detected on the specified input (this is a non-sticky
version of value 0x3). This bit is cleared after one clock cycle.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
12.7 Functional description
12.7.1 Pin interrupts
In this interrupt facility, up to 8 pins are identified as interrupt sources by the Pin Interrupt
Select registers (PINTSEL0-7). All registers in the pin interrupt block contain 8 bits,
corresponding to the pins called out by the PINTSEL0-7 registers. The ISEL register
defines whether each interrupt pin is edge- or level-sensitive. The RISE and FALL
registers detect edges on each interrupt pin, and can be written to clear (and set) edge
detection. The IST register indicates whether each interrupt pin is currently requesting an
interrupt, and this register can also be written to clear interrupts.
The other pin interrupt registers play different roles for edge-sensitive and level-sensitive
pins, as described in Table 166.
Table 166. Pin interrupt registers for edge- and level-sensitive pins
Name
Edge-sensitive function
Level-sensitive function
IENR
Enables rising-edge interrupts.
Enables level interrupts.
SIENR
Write to enable rising-edge interrupts.
Write to enable level interrupts.
CIENR
Write to disable rising-edge interrupts.
Write to disable level interrupts.
IENF
Enables falling-edge interrupts.
Selects active level.
SIENF
Write to enable falling-edge interrupts.
Write to select high-active.
CIENF
Write to disable falling-edge interrupts.
Write to select low-active.
12.7.2 Pattern Match engine example
Suppose the desired boolean pattern to be matched is:
(IN1) + (IN1 * IN2) + (~IN2 * ~IN3 * IN6fe) + (IN5 * IN7ev)
with:
IN6fe = (sticky) falling-edge on input 6
IN7ev = (non-sticky) event (rising or falling edge) on input 7
Each individual term in the expression shown above is controlled by one bit-slice. To
specify this expression, program the pattern match bit slice source and configuration
register fields as follows:
• PMSRC register (Table 164):
– Since bit slice 5 will be used to detect a sticky event on input 6, you can write a 1 to
the SRC5 bits to clear any pre-existing edge detects on bit slice 5.
– SRC0: 001 - select input 1 for bit slice 0
– SRC1: 001 - select input 1 for bit slice 1
– SRC2: 010 - select input 2 for bit slice 2
– SRC3: 010 - select input 2 for bit slice 3
– SRC4: 011 - select input 3 for bit slice 4
– SRC5: 110 - select input 6 for bit slice 5
– SRC6: 101 - select input 5 for bit slice 6
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
– SRC7: 111 - select input 7 for bit slice 7
• PMCFG register (Table 165):
– PROD_ENDPTS0 = 1
– PROD_ENDPTS02 = 1
– PROD_ENDPTS5 = 1
– All other slices are not product term endpoints and their PROD_ENDPTS bits are
0. Slice 7 is always a product term endpoint and does not have a register bit
associated with it.
– = 0100101 - bit slices 0, 2, 5, and 7 are product-term endpoints. (Bit
slice 7 is an endpoint by default - no associated register bit).
– CFG0: 000 - high level on the selected input (input 1) for bit slice 0
– CFG1: 000 - high level on the selected input (input 1) for bit slice 1
– CFG2: 000 - high level on the selected input (input 2) for bit slice 2
– CFG3: 101 - low level on the selected input (input 2) for bit slice 3
– CFG4: 101 - low level on the selected input (input 3) for bit slice 4
– CFG5: 010 - (sticky) falling edge on the selected input (input 6) for bit slice 5
– CFG6: 000 - high level on the selected input (input 5) for bit slice 6
– CFG7: 111 - event (any edge, non-sticky) on the selected input (input 7) for bit
slice 7
• PMCTRL register (Table 163):
– Bit0: Setting this bit will select pattern matches to generate the pin interrupts in
place of the normal pin interrupt mechanism.
For this example, pin interrupt 0 will be asserted when a match is detected on the
first product term (which, in this case, is just a high level on input 1).
Pin interrupt 2 will be asserted in response to a match on the second product term.
Pin interrupt 5 will be asserted when there is a match on the third product term.
Pin interrupt 7 will be asserted on a match on the last term.
– Bit1: Setting this bit will cause the RxEv signal to the ARM CPU to be asserted
whenever a match occurs on ANY of the product terms in the expression.
Otherwise, the RXEV line will not be used.
– Bit31:24: At any given time, bits 0, 2, 5 and/or 7 may be high if the corresponding
product terms are currently matching.
– The remaining bits will always be low.
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
12.7.3 Pattern match engine edge detect examples
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Figure shows pattern match functionality only and accurate timing is not implied. Inputs (INn) are shown synchronized to the
system clock for simplicity.
Fig 19. Pattern match engine examples: sticky edge detect
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Figure shows pattern match functionality only and accurate timing is not implied. Inputs (INn) are shown synchronized to the
system clock for simplicity.
Fig 20. Pattern match engine examples: Windowed non-sticky edge detect evaluates as true
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Chapter 12: LPC15xx Pin interrupt and pattern match (PINT)
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Figure shows pattern match functionality only and accurate timing is not implied. Inputs (INn) are shown synchronized to the
system clock for simplicity.
Fig 21. Pattern match engine examples: Windowed non-sticky edge detect evaluates as false
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Chapter 13: LPC15xx DMA controller
Rev. 1.1 — 3 March 2014
User manual
13.1 How to read this chapter
The DMA controller is available on all parts. For API support see Chapter 37 “LPC15xx
DMA API ROM driver routines”.
13.2 Features
• 18 channels supported with 14 channels connected to peripheral requests of the
USART, SPI, I2C, and DAC peripherals. Four channels have no DMA request
connected.
• DMA operations can be triggered by on- or off-chip events. Each DMA channel can
select one trigger input from 20 sources. Trigger sources are the ADC interrupt, the
analog comparator outputs, and the SCT DMA request lines.
•
•
•
•
•
•
Priority is user selectable for each channel (up to eight priority levels).
Continuous priority arbitration.
Address cache with four entries (each entry is a pair of addresses).
Efficient use of data bus.
Supports single transfers up to 1,024 words.
Address increment options allow packing and/or unpacking data.
13.3 Basic configuration
Configure the DMA as follows:
• Use the SYSAHBCLKCTRL0 register (Table 50) to enable the clock to the DMA
registers interface.
• Clear the DMA peripheral reset using the PRESETCTRL0 register (Table 35).
• The DMA interrupt is connected to slot #4 in the NVIC.
• Each DMA channel has one DMA request line associated and can also select one of
20 input triggers through the input mux registers DMA_ITRIG_INMUX[0:17].
• Trigger outputs are connected to DMA_INMUX_INMUX[0:3] as inputs to DMA
triggers.
For details on the trigger input and output multiplexing, see Section 9.5.3 “DMA trigger
input multiplexing”.
13.3.1 Hardware triggers
Each DMA channel can use one trigger that is independent of the request input for this
channel. The trigger input is selected in the DMA_ITRIG_INMUX registers. There are 20
possible internal trigger sources for each channel with each trigger signal issued by the
output of a peripheral. In addition, the DMA trigger output can be routed to the trigger
input of another channel through the trigger input multiplexing. See Section 9.5.3 “DMA
trigger input multiplexing”.
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Chapter 13: LPC15xx DMA controller
See Table 167 for the connection of input muxes to DMA channels.
See Table 132 for a list of possible trigger input sources.
13.3.2 Trigger outputs
Each channel of the DMA controller provides a trigger output. This allows the possibility of
using the trigger outputs as a trigger source to a different channel in order to support
complex transfers on selected peripherals. This kind of transfer can, for example, use
more than one peripheral DMA request. An example use would be to input data to a
holding buffer from one peripheral, and then output the data to another peripheral, with
both transfers being paced by the appropriate peripheral DMA request. This kind of
operation is called “chained operation” or “channel chaining”.
13.3.3 DMA requests
DMA requests are directly connected to the peripherals. Each channel supports one DMA
request line and one trigger input which is multiplexed to many possible input sources.
For each trigger mux DMA_ITRIG_INMUXn, the following sources are supported:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ADC0 sequence A interrupt ADC0_SEQA_IRQ
ADC0 sequence B interrupt ADC0_SEQB_IRQ
ADC1 sequence A interrupt ADC1_SEQA_IRQ
ADC1 sequence B interrupt ADC1_SEQB_IRQ
SCT0 DMA request 0 SCT0_DMA0
SCT0 DMA request 1 SCT0_DMA1
SCT1 DMA request 0 SCT1_DMA0
SCT1 DMA request 1 SCT1_DMA1
SCT2 DMA request 0 SCT2_DMA0
SCT2 DMA request 1 SCT2_DMA1
SCT3 DMA request 0 SCT3_DMA0
SCT3 DMA request 1 SCT3_DMA1
Output from analog comparator 0 ACMP0_OUT
Output from analog comparator 1 ACMP1_OUT
Output from analog comparator 2 ACMP2_OUT
Output from analog comparator 3 ACMP3_OUT
Four choices of one of the DMA output triggers
Table 167. DMA requests
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DMA channel #
Request input
DMA trigger mux
0
USART0_RX_DMA
DMA_ITRIG_INMUX0
1
USART0_TX_DMA
DMA_ITRIG_INMUX1
2
USART1_RX_DMA
DMA_ITRIG_INMUX2
3
USART1_TX_DMA
DMA_ITRIG_INMUX3
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Table 167. DMA requests
DMA channel #
Request input
DMA trigger mux
4
USART2_RX_DMA
DMA_ITRIG_INMUX4
5
USART2_TX_DMA
DMA_ITRIG_INMUX5
6
SPI0_RX_DMA
DMA_ITRIG_INMUX6
7
SPI0_TX_DMA
DMA_ITRIG_INMUX7
8
SPI1_RX_DMA
DMA_ITRIG_INMUX8
9
SPI1_TX_DMA
DMA_ITRIG_INMUX9
10
I2C0_SLV_DMA
DMA_ITRIG_INMUX10
11
I2C0_MST_DMA
DMA_ITRIG_INMUX11
12
I2C0_MONITOR_DMA
DMA_ITRIG_INMUX12
13
DAC_IRQ
DMA_ITRIG_INMUX13
14
-
DMA_ITRIG_INMUX14
15
-
DMA_ITRIG_INMUX15
16
-
DMA_ITRIG_INMUX16
17
-
DMA_ITRIG_INMUX17
13.3.4 DMA in sleep mode
The DMA can operate and access all SRAM blocks in sleep mode.
13.4 Pin description
The DMA controller has no configurable pins.
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13.5 General description
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Fig 22. DMA block diagram
13.5.1 DMA requests and triggers
An operation on a DMA channel can be initiated by either a DMA request or a trigger
event. DMA requests come from peripherals and specifically indicate when a peripheral
either needs input data to be read from it, or that output data may be sent to it. DMA
requests are created by the UART, SPI, and I2C peripherals.
A trigger initiates a DMA operation and can be a signal from an unrelated peripheral.
Peripherals that generate triggers are the SCTs, the ADCs, and the analog comparators.
In addition, the DMA triggers also create an trigger output that can trigger DMA
transactions on another channel. Triggers can be used to send a character or a string to a
UART or other serial output at a fixed time interval or when an event occurs.
A DMA channel using a trigger can respond by moving data from any memory address to
any other memory address. This can include fixed peripheral data registers, or
incrementing through RAM buffers. The amount of data moved by a single trigger event
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can range from a single transfer to many transfers. A transfer that is started by a trigger
can still be paced using the channel’s DMA request. This allows sending a string to a
serial peripheral, for instance, without overrunning the peripheral’s transmit buffer.
Each trigger input to the DMA has a corresponding output that can be used as a trigger
input to another channel. The trigger outputs appear in the trigger source list for each
channel and can be selected through the DMA_INMUX registers as inputs to other
channels.
13.5.2 DMA Modes
The DMA controller doesn’t really have separate operating modes, but there are ways of
using the DMA controller that have commonly used terminology in the industry.
Once the DMA controller is set up for operation, using any specific DMA channel requires
initializing the registers associated with that channel (see Table 167), and supplying at
least the channel descriptor, which is located somewhere in memory, typically in on-chip
SRAM (see Section 13.6.3). The channel descriptor is shown in Table 168.
Table 168: Channel descriptor
Offset
Description
+ 0x0
Reserved
+ 0x4
Source data end address
+ 0x8
Destination end address
+ 0xC
Link to next descriptor
The source and destination end addresses, as well as the link to the next descriptor are
just memory addresses that can point to any valid address on the device. The starting
address for both source and destination data is the specified end address minus the transfer
length (XFERCOUNT * the address increment as defined by SRCINC and DSTINC). The link to
the next descriptor is used only if it is a linked transfer.
After the channel has had a sufficient number of DMA requests and/or triggers, depending
on its configuration, the initial descriptor will be exhausted. At that point, if the transfer
configuration directs it, the channel descriptor will be reloaded with data from memory
pointed to by the “Link to next descriptor” entry of the initial channel descriptor.
Descriptors loaded in this manner look slightly different the channel descriptor, as shown
in Table 169. The difference is that a new transfer configuration is specified in the reload
descriptor instead of being written to the XFERCFG register for that channel.
This process repeats as each descriptor is exhausted as long as reload is selected in the
transfer configuration for each new descriptor.
Table 169: Reload descriptors
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Offset
Description
+ 0x0
Transfer configuration.
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Table 169: Reload descriptors
Offset
Description
+ 0x4
Source end address. This points to the address of the last entry of the source address
range if the address is incremented. The address to be used in the transfer is calculated
from the end address, data width, and transfer size.
+ 0x8
Destination end address. This points to the address of the last entry of the destination
address range if the address is incremented. The address to be used in the transfer is
calculated from the end address, data width, and transfer size.
+ 0xC
Link to next descriptor. If used, this address must be aligned to a multiple of 16 bytes
(i.e., the size of a descriptor).
13.5.3 Single buffer
This generally applies to memory to memory moves, and peripheral DMA that occurs only
occasionally and is set up for each transfer. For this kind of operation, only the initial
channel descriptor shown in Table 170 is needed.
Table 170: Channel descriptor for a single transfer
Offset
Description
+ 0x0
Reserved
+ 0x4
Source data end address
+ 0x8
Destination data end address
+ 0xC
(not used)
This case is identified by the Reload bit in the XFERCFG register = 0. When the DMA
channel receives a DMA request or trigger (depending on how it is configured), it performs
one or more transfers as configured, then stops. Once the channel descriptor is
exhausted, additional DMA requests or triggers will have no effect until the channel
configuration is updated by software.
13.5.4 Ping-Pong
Ping-pong is a special case of a linked transfer. It is described separately because it is
typically used more frequently than more complicated versions of linked transfers.
A ping-pong transfer uses two buffers alternately. At any one time, one buffer is being
loaded or unloaded by DMA operations. The other buffer has the opposite operation being
handled by software, readying the buffer for use when the buffer currently being used by
the DMA controller is full or empty. Table 171 shows an example of descriptors for
ping-pong from a peripheral to two buffers in memory.
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Table 171: Example descriptors for ping-pong operation: peripheral to buffer
Channel Descriptor
Descriptor B
Descriptor A
+ 0x0 (not used)
+ 0x0 Buffer B transfer configuration
+ 0x0 Buffer A transfer configuration
+ 0x4 Peripheral data end address
+ 0x4 Peripheral data end address
+ 0x4 Peripheral data end address
+ 0x8 Buffer A memory end address
+ 0x8 Buffer B memory end address
+ 0x8 Buffer A memory end address
+ 0xC Address of descriptor B
+ 0xC Address of descriptor A
+ 0xC Address of descriptor B
In this example, the channel descriptor is used first, with a first buffer in memory called
buffer A. The configuration of the DMA channel must have been set to indicate a reload.
Similarly, both descriptor A and descriptor B must also specify reload. When the channel
descriptor is exhausted, descriptor B is loaded using the link to descriptor B, and a
transfer interrupt informs the CPU that buffer A is available.
Descriptor B is then used until it is also exhausted, when descriptor A is loaded using the
link to descriptor A contained in descriptor B. Then a transfer interrupt informs the CPU
that buffer B is available for processing. The process repeats when descriptor A is
exhausted, alternately using each of the 2 memory buffers.
13.5.5 Linked transfers (linked list)
A linked transfer can use any number of descriptors to define a complicated transfer. This
can be configured such that a single transfer, a portion of a transfer, one whole descriptor,
or an entire structure of links can be initiated by a single DMA request or trigger.
An example of a linked transfer could start out like the example for a ping-pong transfer
(Table 171). The difference would be that descriptor B would not link back to descriptor A,
but would continue on to another different descriptor. This could continue as long as
desired, and can be ended anywhere, or linked back to any point to repeat a sequence of
descriptors. Of course, any descriptor not currently in use can be altered by software as
well.
13.5.6 Address alignment for data transfers
Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. Transfers
of 32 bit width require an address alignment to a multiple of 4 bytes. Transfers of 8 bit
width can be at any address.
13.6 Register description
The DMA registers are grouped into DMA control, interrupt and status registers and DMA
channel registers. DMA transfers are controlled by a set of three registers per channel, the
CFG[0:20], CTRLSTAT[0:20], and XFERCFG[0:20] registers.
The reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
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Table 172. Register overview: DMA controller (base address 0x1C00 4000)
Name
Access
Address
offset
Description
Reset
Value
Reference
Global control and status registers
CTRL
R/W
0x000
DMA control.
0
Table 173
INTSTAT
RO
0x004
Interrupt status.
0
Table 174
SRAMBASE
R/W
0x008
SRAM address of the channel configuration table.
0
Table 175
Shared registers
ENABLESET0
RO/W1
0x020
Channel Enable read and Set for all DMA channels.
0
Table 177
ENABLECLR0
W1
0x028
Channel Enable Clear for all DMA channels.
NA
Table 178
ACTIVE0
RO
0x030
Channel Active status for all DMA channels.
0
Table 179
BUSY0
RO
0x038
Channel Busy status for all DMA channels.
0
Table 180
ERRINT0
RO/W1
0x040
Error Interrupt status for all DMA channels.
0
Table 181
INTENSET0
RO/W1
0x048
Interrupt Enable read and Set for all DMA channels.
0
Table 182
INTENCLR0
W1
0x050
Interrupt Enable Clear for all DMA channels.
NA
Table 183
INTA0
RO/W1
0x058
Interrupt A status for all DMA channels.
0
Table 184
INTB0
RO/W1
0x060
Interrupt B status for all DMA channels.
0
Table 185
SETVALID0
W1
0x068
Set ValidPending control bits for all DMA channels.
NA
Table 186
SETTRIG0
W1
0x070
Set Trigger control bits for all DMA channels.
NA
Table 187
ABORT0
W1
0x078
Channel Abort control for all DMA channels.
NA
Table 188
Channel0 registers
CFG0
R/W
0x400
Configuration register for DMA channel 0.
Table 189
CTLSTAT0
RO
0x404
Control and status register for DMA channel 0.
Table 191
XFERCFG0
R/W
0x408
Transfer configuration register for DMA channel 0.
Table 192
Channel1 registers
CFG1
R/W
0x410
Configuration register for DMA channel 1.
Table 189
CTLSTAT1
RO
0x414
Control and status register for DMA channel 1.
Table 191
XFERCFG1
R/W
0x418
Transfer configuration register for DMA channel 1.
Table 192
Channel2 registers
CFG2
R/W
0x420
Configuration register for DMA channel 2.
Table 189
CTLSTAT2
RO
0x424
Control and status register for DMA channel 2.
Table 191
XFERCFG2
R/W
0x428
Transfer configuration register for DMA channel 2.
Table 192
Channel3 registers
CFG3
R/W
0x430
Configuration register for DMA channel 3.
Table 189
CTLSTAT3
RO
0x434
Control and status register for DMA channel 3.
Table 191
XFERCFG3
R/W
0x438
Transfer configuration register for DMA channel 3.
Table 192
Channel4 registers
CFG4
R/W
0x440
Configuration register for DMA channel 4.
Table 189
CTLSTAT4
RO
0x444
Control and status register for DMA channel 4.
Table 191
XFERCFG4
R/W
0x448
Transfer configuration register for DMA channel 4.
Table 192
Channel5 registers
CFG5
R/W
0x450
Configuration register for DMA channel 5.
Table 189
CTLSTAT5
RO
0x454
Control and status register for DMA channel 5.
Table 191
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Chapter 13: LPC15xx DMA controller
Table 172. Register overview: DMA controller (base address 0x1C00 4000)
Name
Access
Address
offset
Description
Reset
Value
Reference
XFERCFG5
R/W
0x458
Transfer configuration register for DMA channel 5.
Table 192
Channel6 registers
CFG6
R/W
0x460
Configuration register for DMA channel 6.
Table 189
CTLSTAT6
RO
0x464
Control and status register for DMA channel 6.
Table 191
XFERCFG6
R/W
0x468
Transfer configuration register for DMA channel 6.
Table 192
Channel7 registers
CFG7
R/W
0x470
Configuration register for DMA channel 7.
Table 189
CTLSTAT7
RO
0x474
Control and status register for DMA channel 7.
Table 191
XFERCFG7
R/W
0x478
Transfer configuration register for DMA channel 7.
Table 192
Channel8 registers
CFG8
R/W
0x480
Configuration register for DMA channel 8.
Table 189
CTLSTAT8
RO
0x484
Control and status register for DMA channel 8.
Table 191
XFERCFG8
R/W
0x488
Transfer configuration register for DMA channel 8.
Table 192
Channel9 registers
CFG9
R/W
0x490
Configuration register for DMA channel 9.
Table 189
CTLSTAT9
RO
0x494
Control and status register for DMA channel 9.
Table 191
XFERCFG9
R/W
0x498
Transfer configuration register for DMA channel 9.
Table 192
Channel10 registers
CFG10
R/W
0x4A0
Configuration register for DMA channel 10.
Table 189
CTLSTAT10
RO
0x4A4
Control and status register for DMA channel 10.
Table 191
XFERCFG10
R/W
0x4A8
Transfer configuration register for DMA channel 10.
Table 192
Channel11 registers
CFG11
R/W
0x4B0
Configuration register for DMA channel 11.
Table 189
CTLSTAT11
RO
0x4B4
Control and status register for DMA channel 11.
Table 191
XFERCFG11
R/W
0x4B8
Transfer configuration register for DMA channel 11.
Table 192
Channel12 registers
CFG12
R/W
0x4C0
Configuration register for DMA channel 12.
Table 189
CTLSTAT12
RO
0x4C4
Control and status register for DMA channel 12.
Table 191
XFERCFG12
R/W
0x4C8
Transfer configuration register for DMA channel 12.
Table 192
Channel13 registers
CFG13
R/W
0x4D0
Configuration register for DMA channel 13.
Table 189
CTLSTAT13
RO
0x4D4
Control and status register for DMA channel 13.
Table 191
XFERCFG13
R/W
0x4D8
Transfer configuration register for DMA channel 13.
Table 192
Channel14 registers
CFG14
R/W
0x4E0
Configuration register for DMA channel 14.
Table 189
CTLSTAT14
RO
0x4E4
Control and status register for DMA channel 14.
Table 191
XFERCFG14
R/W
0x4E8
Transfer configuration register for DMA channel 14.
Table 192
Channel15 registers
CFG15
R/W
0x4F0
Configuration register for DMA channel 15.
Table 189
CTLSTAT15
RO
0x4F4
Control and status register for DMA channel 15.
Table 191
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Table 172. Register overview: DMA controller (base address 0x1C00 4000)
Name
Access
Address
offset
Description
Reset
Value
Reference
XFERCFG15
R/W
0x4F8
Transfer configuration register for DMA channel 15.
Table 192
Channel16 registers
CFG16
R/W
0x500
Configuration register for DMA channel 16.
Table 189
CTLSTAT16
RO
0x504
Control and status register for DMA channel 16.
Table 191
XFERCFG16
R/W
0x508
Transfer configuration register for DMA channel 16.
Table 192
Channel17 registers
CFG17
R/W
0x510
Configuration register for DMA channel 17.
Table 189
CTLSTAT17
RO
0x514
Control and status register for DMA channel 17.
Table 191
XFERCFG17
R/W
0x518
Transfer configuration register for DMA channel 17.
Table 192
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13.6.1 Control register
The CTRL register contains global the control bit for a enabling the DMA controller.
Table 173. Control register (CTRL, address 0x1C00 4000) bit description
Bit
Symbol
0
ENABLE
31:1
Value Description
Reset
value
DMA controller master enable.
0
0
Disabled. The DMA controller is disabled. This clears any
triggers that were asserted at the point when disabled, but
does not prevent re-triggering when the DMA controller is
re-enabled.
1
Enabled. The DMA controller is enabled.
-
Reserved. Read value is undefined, only zero should be
written.
NA
13.6.2 Interrupt Status register
The Read-Only INTSTAT register provides an overview of DMA status. This allows quick
determination of whether any enabled interrupts are pending. Details of which channels
are involved are found in the interrupt type specific registers.
Table 174. Interrupt Status register (INTSTAT, address 0x1C00 4004) bit description
Bit
Symbol
0
-
Reserved. Read value is undefined, only zero should
be written.
NA
1
ACTIVEINT
Summarizes whether any enabled interrupts are
pending.
0
2
31:3
Value Description
Reset
value
0
Not pending. No enabled interrupts are pending.
1
Pending. At least one enabled interrupt is pending.
ACTIVEERRINT
Summarizes whether any error interrupts are pending. 0
0
Not pending. No error interrupts are pending.
1
Pending. At least one error interrupt is pending.
-
Reserved. Read value is undefined, only zero should
be written.
NA
13.6.3 SRAM Base address register
The SRAMBASE register must be configured with an address (preferably in on-chip
SRAM) where DMA descriptors will be stored. Software must set up the descriptors for
those DMA channels that will be used in the application.
Table 175. SRAM Base address register (SRAMBASE, address 0x1C00 4008) bit description
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Bit
Symbol
Description
Reset
value
8:0
-
Reserved. Read value is undefined, only zero should be written.
NA
31:9
OFFSET
Address bits 31:9 of the beginning of the DMA descriptor table. For
18 channels, the table must begin on a 512 byte boundary.
0
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Each DMA channel has an entry for the channel descriptor in the SRAM table. The values
for each channel start at the address offsets found in Table 176. Only the descriptors for
channels defined at extraction are used. The contents of each channel descriptor are
described in Table 168.
Table 176. Channel descriptor map
Descriptor
Table offset
Channel descriptor for DMA channel 0
0x000
Channel descriptor for DMA channel 1
0x010
Channel descriptor for DMA channel 2
0x020
Channel descriptor for DMA channel 3
0x030
Channel descriptor for DMA channel 4
0x040
Channel descriptor for DMA channel 5
0x050
Channel descriptor for DMA channel 6
0x060
Channel descriptor for DMA channel 7
0x070
Channel descriptor for DMA channel 8
0x080
Channel descriptor for DMA channel 9
0x090
Channel descriptor for DMA channel 10
0x0A0
Channel descriptor for DMA channel 11
0x0B0
Channel descriptor for DMA channel 12
0x0C0
Channel descriptor for DMA channel 13
0x0D0
Channel descriptor for DMA channel 14
0x0E0
Channel descriptor for DMA channel 15
0x0F0
Channel descriptor for DMA channel 16
0x100
Channel descriptor for DMA channel 17
0x110
13.6.4 Enable read and Set registers
The ENABLESET0 register determines whether each DMA channel is enabled or
disabled. Disabling a DMA channel does not reset the channel in any way. A channel can
be paused and restarted by clearing, then setting the Enable bit for that channel.
Reading ENABLESET0 provides the current state of all of the DMA channels represented
by that register. Writing a 1 to a bit position in ENABLESET0 that corresponds to an
implemented DMA channel sets the bit, enabling the related DMA channel. Writing a 0 to
any bit has no effect. Enables are cleared by writing to ENABLECLR0.
Table 177. Enable read and Set register 0 (ENABLESET0, address 0x1C00 4020) bit
description
Bit
Symbol
Description
Reset value
17:0
ENA
Enable for DMA channels 17:0. Bit n enables or disables DMA 0
channel n.
0 = disabled.
1 = enabled.
31:18 -
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13.6.5 Enable Clear register
The ENABLECLR0 register is used to clear the channel enable bits in ENABLESET0.
This register is write-only.
Table 178. Enable Clear register 0 (ENABLECLR0, address 0x1C00 4028) bit description
Bit
Symbol
Description
Reset value
17:0
CLR
Writing ones to this register clears the corresponding bits in
ENABLESET0. Bit n clears the channel enable bit n.
NA
Reserved.
-
31:18 -
13.6.6 Active status register
The ACTIVE0 register indicates which DMA channels are active at the point when the
read occurs. The register is read-only.
A DMA channel is considered active when a DMA operation has been started but not yet
fully completed. The Active status will persist from a DMA operation being started, until
the pipeline is empty after end of the last descriptor (when there is no reload). An active
channel may be aborted by software by setting the appropriate bit in one of the Abort
register (see Section 13.6.15).
Table 179. Active status register 0 (ACTIVE0, address 0x1C00 4030) bit description
Bit
Symbol Description
Reset
value
17:0
ACT
0
Active flag for DMA channel n. Bit n corresponds to DMA channel
n.
0 = not active.
1 = active.
31:18 -
Reserved.
-
13.6.7 Busy status register
The BUSY0 register indicates which DMA channels is busy at the point when the read
occurs. This registers is read-only.
A DMA channel is considered busy when there is any operation related to that channel in
the DMA controller’s internal pipeline. This information can be used after a DMA channel
is disabled by software (but still active), allowing confirmation that there are no remaining
operations in progress for that channel.
Table 180. Busy status register 0 (BUSY0, address 0x1C00 4038) bit description
Bit
Symbol
Description
Reset
value
17:0
BSY
Busy flag for DMA channel n. Bit n corresponds to DMA channel n.
0
0 = not busy.
1 = busy.
31:18 -
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13.6.8 Error Interrupt register
The ERRINT0 register contains flags for each DMA channel’s Error Interrupt. Any pending
interrupt flag in the register will be reflected on the DMA interrupt output.
Reading the registers provides the current state of all DMA channel error interrupts.
Writing a 1 to a bit position in ERRINT0 that corresponds to an implemented DMA channel
clears the bit, removing the interrupt for the related DMA channel. Writing a 0 to any bit
has no effect.
Table 181. Error Interrupt register 0 (ERRINT0, address 0x1C00 4040) bit description
Bit
Symbol
Description
Reset
value
17:0
ERR
Error Interrupt flag for DMA channel n. Bit n corresponds to DMA 0
channel n.
0 = error interrupt is not active.
1 = error interrupt is active.
31:18 -
Reserved.
-
13.6.9 Interrupt Enable read and Set register
The INTENSET0 register controls whether the individual Interrupts for DMA channels
contribute to the DMA interrupt output.
Reading the registers provides the current state of all DMA channel interrupt enables.
Writing a 1 to a bit position in INTENSET0 that corresponds to an implemented DMA
channel sets the bit, enabling the interrupt for the related DMA channel. Writing a 0 to any
bit has no effect. Interrupt enables are cleared by writing to INTENCLR0.
Table 182. Interrupt Enable read and Set register 0 (INTENSET0, address 0x1C00 4048) bit
description
Bit
Symbol
17: 0 INTEN
Description
Reset value
Interrupt Enable read and set for DMA channel n. Bit n
corresponds to DMA channel n.
0
0 = interrupt for DMA channel is disabled.
1 = interrupt for DMA channel is enabled.
31:18 -
Reserved.
-
13.6.10 Interrupt Enable Clear register
The INTENCLR0 register is used to clear interrupt enable bits in INTENSET0. The
register is write-only.
Table 183. Interrupt Enable Clear register 0 (INTENCLR0, address 0x1C00 4050) bit
description
Bit
Symbol Description
Reset value
17:0
CLR
Writing ones to this register clears corresponding bits in the
INTENSET0. Bit n corresponds to DMA channel n.
NA
Reserved.
-
31:18 -
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13.6.11 Interrupt A register
The IntA0 register contains the interrupt A status for each DMA channel. The status will be
set when the SETINTA bit is 1 in the transfer configuration for a channel, when the
descriptor becomes exhausted. Writing a 1 to a bit in these registers clears the related
INTA flag. Writing 0 has no effect. Any interrupt pending status in the registers will be
reflected on the DMA interrupt output if it is enabled in the related INTENSET register.
Table 184. Interrupt A register 0 (INTA0, address 0x1C00 4058) bit description
Bit
Symbol
Description
Reset value
17:0
IA
Interrupt A status for DMA channel n. Bit n corresponds to DMA 0
channel n.
0 = the DMA channel interrupt A is not active.
1 = the DMA channel interrupt A is active.
31:18 -
Reserved.
-
13.6.12 Interrupt B register
The INTB0 register contains the interrupt B status for each DMA channel. The status will
be set when the SETINTB bit is 1 in the transfer configuration for a channel, when the
descriptor becomes exhausted. Writing a 1 to a bit in the register clears the related INTB
flag. Writing 0 has no effect. Any interrupt pending status in these registers will be
reflected on the DMA interrupt output if it is enabled in the INTENSET register.
Table 185. Interrupt B register 0 (INTB0, address 0x1C00 4060) bit description
Bit
Symbol
Description
17:0
IB
Interrupt B status for DMA channel n. Bit n corresponds to DMA 0
channel n.
Reset value
0 = the DMA channel interrupt B is not active.
1 = the DMA channel interrupt B is active.
31:18 -
Reserved.
-
13.6.13 Set Valid register
The SETVALID0 register allows setting the Valid bit in the CTRLSTAT register for one or
more DMA channels. See Section 13.6.17 for a description of the VALID bit.
The CFGVALID and SV (set valid) bits allow more direct DMA block timing control by
software. Each Channel Descriptor, in a sequence of descriptors, can be validated by
either the setting of the CFGVALID bit or by setting the channel's SETVALID flag.
Normally, the CFGVALID bit is set. This tells the DMA that the Channel Descriptor is
active and can be executed. The DMA will continue sequencing through descriptor blocks
whose CFGVALID bit are set without further software intervention. Leaving a CFGVALID
bit set to 0 allows the DMA sequence to pause at the Descriptor until software triggers the
continuation. If, during DMA transmission, a Channel Descriptor is found with CFGVALID
set to 0, the DMA checks for a previously buffered SETVALID0 setting for the channel. If
found, the DMA will set the descriptor valid, clear the SV setting, and resume processing
the descriptor. Otherwise, the DMA pauses until the channels SETVALID0 bit is set.
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Table 186. Set Valid 0 register (SETVALID0, address 0x1C00 4068) bit description
Bit
Symbol
Description
Reset value
17:0
SV
SETVALID control for DMA channel n. Bit n corresponds to
DMA channel n.
NA
0 = no effect.
1 = sets the VALIDPENDING control bit for DMA channel n.
31:18 -
Reserved.
-
13.6.14 Set Trigger register
The SETTRIG0 register allows setting the TRIG bit in the CTRLSTAT register for one or
more DMA channel. See Section 13.6.17 for a description of the TRIG bit, and
Section 13.5.1 for a general description of triggering.
Table 187. Set Trigger 0 register (SETTRIG0, address 0x1C00 4070) bit description
Bit
Symbol
Description
Reset value
17:0
TRIG
Set Trigger control bit for DMA channel 0. Bit n corresponds to NA
DMA channel n.
0 = no effect.
1 = sets the TRIG bit for DMA channel n.
31:18 -
Reserved.
-
13.6.15 Abort registers
The Abort0 register allows aborting operation of a DMA channel if needed. To abort a
selected channel, the channel should first be disabled by clearing the corresponding
Enable bit by writing a 1 to the proper bit ENABLECLR. Then wait until the channel is no
longer busy by checking the corresponding bit in BUSY. Finally, write a 1 to the proper bit
of ABORT. This prevents the channel from restarting an incomplete operation when it is
enabled again.
Table 188. Abort 0 register (ABORT0, address 0x1C00 4078) bit description
Bit
Symbol
Description
Reset
value
17:0
ABORTCTRL Abort control for DMA channel 0. Bit n corresponds to DMA
channel n.
NA
0 = no effect.
1 = aborts DMA operations on channel n.
31:18 -
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Chapter 13: LPC15xx DMA controller
13.6.16 Channel configuration registers
The CFGn register contains various configuration options for DMA channel n.
See Table 190 for a summary of trigger options.
Table 189. Configuration registers for channel 0 to 17 (CFG[0:17], addresses 0x1C00 4400 (CFG0) to address 0x1C00
4510 (CFG17)) bit description
Bit
Symbol
0
PERIPHREQEN
1
-
4
TRIGPOL
Reset
value
Peripheral request Enable. If a DMA channel is used to perform a
0
memory-to-memory move, any peripheral DMA request associated with that
channel can be disabled to prevent any interaction between the peripheral
and the DMA controller.
0
Disabled. Peripheral DMA requests are disabled.
1
Enabled. Peripheral DMA requests are enabled.
HWTRIGEN
3:2
5
Value Description
Hardware Triggering Enable for this channel.
0
Disabled. Hardware triggering is not used.
1
Enabled. Use hardware triggering.
0
Reserved. Read value is undefined, only zero should be written.
NA
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
0
0
Active low - falling edge. Hardware trigger is active low or falling edge
triggered, based on TRIGTYPE.
1
Active high - rising edge. Hardware trigger is active high or rising edge
triggered, based on TRIGTYPE.
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
0
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1
Level. Hardware trigger is level triggered. Note that when level triggering
without burst (BURSTPOWER = 0) is selected, only hardware triggers
should be used on that channel.
0
Transfers continue as long as the trigger level is asserted. Once the trigger
is de-asserted, the transfer will be paused until the trigger is, again,
asserted. However, the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are completed.
6
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst
transfer.
0
Single transfer. Hardware trigger causes a single transfer.
1
Burst transfer. When the trigger for this channel is set to edge triggered, a
hardware trigger causes a burst transfer, as defined by BURSTPOWER.
0
When the trigger for this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is asserted, unless the
transfer is complete.
7
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Reserved. Read value is undefined, only zero should be written.
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Table 189. Configuration registers for channel 0 to 17 (CFG[0:17], addresses 0x1C00 4400 (CFG0) to address 0x1C00
4510 (CFG17)) bit description
Bit
Symbol
11:8
BURSTPOWER
Value Description
Reset
value
Burst Power is used in two ways. It always selects the address wrap size
when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected
(see descriptions elsewhere in this register).
0
When the TRIGBURST field elsewhere in this register = 1, Burst Power
selects how many transfers are performed for each DMA trigger. This can be
used, for example, with peripherals that contain a FIFO that can initiate a
DMA operation when the FIFO reaches a certain level.
0000: Burst size = 1 (20).
0001: Burst size = 2 (21).
0010: Burst size = 4 (22).
...
1010: Burst size = 1024 (210). This corresponds to the maximum supported
transfer count.
others: not supported.
The total transfer length as defined in the XFERCOUNT bits in the
XFERCFG register must be an even multiple of the burst size.
13:12 -
Reserved. Read value is undefined, only zero should be written.
14
Source Burst Wrap. When enabled, the source data address for the DMA is 0
“wrapped”, meaning that the source address range for each burst will be the
same. As an example, this could be used to read several sequential
registers from a peripheral for each DMA burst, reading the same registers
again for each burst.
15
SRCBURSTWRAP
0
Disabled. Source burst wrapping is not enabled for this DMA channel.
1
Enabled. Source burst wrapping is enabled for this DMA channel.
Destination Burst Wrap. When enabled, the destination data address for the 0
DMA is “wrapped”, meaning that the destination address range for each
burst will be the same. As an example, this could be used to write several
sequential registers to a peripheral for each DMA burst, writing the same
registers again for each burst.
DSTBURSTWRAP
18:16 CHPRIORITY
NA
0
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1
Enabled. Destination burst wrapping is enabled for this DMA channel.
Priority of this channel when multiple DMA requests are pending.
0
Eight priority levels are supported.
0x0 = highest priority.
0x7 = lowest priority.
31:19 -
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Table 190. Trigger setting summary
TrigBurst TrigType
TrigPol
Description
0
0
0
Hardware DMA trigger is falling edge sensitive. The BURSTPOWER field controls
address wrapping if enabled via SRCBURSTWRAP and/or DSTBURSTWRAP.
0
0
1
Hardware DMA trigger is rising edge sensitive. The BURSTPOWER field controls
address wrapping if enabled via SRCBURSTWRAP and/or DSTBURSTWRAP.
0
1
0
Hardware DMA trigger is low level sensitive. The BURSTPOWER field controls address
wrapping if enabled via SRCBURSTWRAP and/or DSTBURSTWRAP.
0
1
1
Hardware DMA trigger is high level sensitive. The BURSTPOWER field controls
address wrapping if enabled via SRCBURSTWRAP and/or DSTBURSTWRAP.
1
0
0
Hardware DMA trigger is falling edge sensitive. The BURSTPOWER field controls
address wrapping if enabled via SRCBURSTWRAP and/or DSTBURSTWRAP, and
also determines how much data is transferred for each trigger.
1
0
1
Hardware DMA trigger is rising edge sensitive. The BURSTPOWER field controls
address wrapping if enabled via SRCBURSTWRAP and/or DSTBURSTWRAP, and
also determines how much data is transferred for each trigger.
1
1
0
Hardware DMA trigger is low level sensitive. The BURSTPOWER field controls address
wrapping if enabled via SRCBURSTWRAP and/or DSTBURSTWRAP, and also
determines how much data is transferred for each trigger.
1
1
1
Hardware DMA trigger is high level sensitive. The BURSTPOWER field controls
address wrapping if enabled via SRCBURSTWRAP and/or DSTBURSTWRAP, and
also determines how much data is transferred for each trigger.
13.6.17 Channel control and status registers
The CTLSTATn register provides status flags specific to DMA channel n.
Table 191. Control and Status registers for channel 0 to 17 (CTLSTAT[0:17], 0x1C00 4404 (CTLSTAT0) to address
0x1C00 4514 (CTLSTAT17)) bit description
Bit
Symbol
0
VALIDPENDING
Value Description
Reset
value
Valid pending flag for this channel. This bit is set when a 1 is written to the
0
corresponding bit in the related SETVALID register when CFGVALID = 1 for the
same channel.
0
1
No effect on DMA operation.
Valid pending.
1
-
Reserved. Read value is undefined, only zero should be written.
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is 0
cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
31:3
-
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0
Not triggered. The trigger for this DMA channel is not set. DMA operations will
not be carried out.
1
Triggered. The trigger for this DMA channel is set. DMA operations will be
carried out.
Reserved. Read value is undefined, only zero should be written.
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13.6.18 Channel transfer configuration registers
The XFERCFGn register contains transfer related configuration information for DMA
channel n. Using the Reload bit, this register can optionally be automatically reloaded
when the current settings are exhausted (the full transfer count has been completed),
allowing linked transfers with more than one descriptor to be performed.
See “Trigger operation” for details on trigger operation.
Table 192. Transfer Configuration registers for channel 0 to 17 (XFERCFG[0:17], addresses 0x1C00 4408
(XFERCFG0) to 0x1C00 4518 (XFERCFG17)) bit description
Bit
Symbol
0
CFGVALID
1
2
3
4
5
7:6
Value Description
Configuration Valid flag. This bit indicates whether the current channel descriptor is 0
valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
Not valid. The channel descriptor is not considered valid until validated by an
associated SETVALID0 setting.
1
Valid. The current channel descriptor is considered valid.
RELOAD
Indicates whether the channel’s control structure will be reloaded when the current
descriptor is exhausted. Reloading allows ping-pong and linked transfers.
Disabled. Do not reload the channels’ control structure when the current descriptor
is exhausted.
1
Enabled. Reload the channels’ control structure when the current descriptor is
exhausted.
Software Trigger.
When written by software, the trigger for this channel is not set. A new trigger, as
defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
1
When written by software, the trigger for this channel is set immediately. This
feature should not be used with level triggering when TRIGBURST = 0.
Clear Trigger.
0
0
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a
reload, the next descriptor will be started.
1
Cleared. The trigger is cleared when this descriptor is exhausted.
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between
interrupt A and B. They can be used by software to assist with more complex
descriptor usage. By convention, interrupt A may be used when only one interrupt
flag is needed.
0
No effect.
1
Set. The INTA flag for this channel will be set when the current descriptor is
exhausted.
SETINTB
User manual
0
0
CLRTRIG
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0
SWTRIG
-
Reset
Value
Set Interrupt flag B for this channel. There is no hardware distinction between
interrupt A and B. They can be used by software to assist with more complex
descriptor usage. By convention, interrupt A may be used when only one interrupt
flag is needed.
0
No effect.
1
Set. The INTB flag for this channel will be set when the current descriptor is
exhausted.
Reserved. Read value is undefined, only zero should be written.
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Table 192. Transfer Configuration registers for channel 0 to 17 (XFERCFG[0:17], addresses 0x1C00 4408
(XFERCFG0) to 0x1C00 4518 (XFERCFG17)) bit description
Bit
Symbol
9:8
WIDTH
Value Description
Reset
Value
Transfer width used for this DMA channel.
0
0x0
8-bit transfers are performed (8-bit source reads and destination writes).
0x1
16-bit transfers are performed (16-bit source reads and destination writes).
0x2
32-bit transfers are performed (32-bit source reads and destination writes).
0x3
Reserved setting, do not use.
11:10 -
Reserved. Read value is undefined, only zero should be written.
NA
13:12 SRCINC
Determines whether the source address is incremented for each DMA transfer.
0
0x0
No increment. The source address is not incremented for each transfer. This is the
usual case when the source is a peripheral device.
0x1
1 x width. The source address is incremented by the amount specified by Width for
each transfer. This is the usual case when the source is memory.
0x2
2 x width. The source address is incremented by 2 times the amount specified by
Width for each transfer.
0x3
4 x width. The source address is incremented by 4 times the amount specified by
Width for each transfer.
15:14 DSTINC
25:16 XFERCOUNT
Determines whether the destination address is incremented for each DMA transfer. 0
0x0
No increment. The destination address is not incremented for each transfer. This is
the usual case when the destination is a peripheral device.
0x1
1 x width. The destination address is incremented by the amount specified by Width
for each transfer. This is the usual case when the destination is memory.
0x2
2 x width. The destination address is incremented by 2 times the amount specified
by Width for each transfer.
0x3
4 x width. The destination address is incremented by 4 times the amount specified
by Width for each transfer.
Total number of transfers to be performed, minus 1 encoded. The number of bytes
transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field).
0
Remark: The DMA controller uses this bit field during transfer to count down.
Hence, it cannot be used by software to read back the size of the transfer, for
instance, in an interrupt handler.
0x0 = a total of 1 transfer will be performed.
0x1 = a total of 2 transfers will be performed.
...
0x3FF = a total of 1,024 transfers will be performed.
31:26 -
Reserved. Read value is undefined, only zero should be written.
NA
13.7 Functional description
13.7.1 Trigger operation
A trigger of some kind is always needed to start a transfer on a DMA channel. This can be
a hardware or software trigger, and can be used in several ways.
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If a channel is configured with the SWTRIG bit equal to 0, the channel can be later
triggered either by hardware or software. Software triggering is accomplished by writing a
1 to the appropriate bit in the SETTRIG register. Hardware triggering requires setup of the
HWTRIGEN, TRIGPOL, TRIGTYPE, and TRIGBURST fields in the CFG register for the
related channel. When a channel is initially set up, the SWTRIG bit in the XFERCFG
register can be set, causing the transfer to begin immediately.
Once triggered, transfer on a channel will be paced by DMA requests if the
PERIPHREQEN bit in the related CFG register is set. Otherwise, the transfer will proceed
at full speed.
The TRIG bit in the CTLSTAT register can be cleared at the end of a transfer, determined
by the value CLRTRIG (bit 0) in the XFERCFG register. When a 1 is found in CLRTRIG,
the trigger is cleared when the descriptor is exhausted.
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14.1 How to read this chapter
The SCTIPU is available on all parts.
14.2 Features
The SCTIPU pre-processes inputs to the State-Configurable Timers (SCT).
• Four outputs created from a selection of input transitions. Each output can be used as
abort input to the SCTs or for any other application which requires a collection of
multiple SCT inputs to trigger an identical SCT response.
• Four registers to indicate which specific input sources caused the abort input to the
SCTs.
• Four additional outputs which can be sampled at certain times and latched at others
before being routed to SCT inputs.
• Nine abort inputs. Any combination of the abort inputs can trigger the dedicated abort
input of each SCT.
14.3 Basic configuration
Configure the SCTIPU as follows:
• Use the SYSAHBCLKCTRL1 register (Table 51) to enable the clock to the SCTIPU
registers interface.
• Clear the SCTIPU peripheral reset using the PRESETCTRL1 register (Table 36).
• Select the SCTIPU sample inputs from external pins and the comparator outputs. See
Table 193 and Figure 24.
• Select the abort inputs from the SCT_ABORT pins via the switch matrix, the SCT0
output SCT0_OUT9, the ADC threshold compare interrupts, or the comparator
outputs. See Table 197.
• SCTIPU outputs are connected to the SCT inputs and selected through the SCT input
mux registers. See Table 193.
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Chapter 14: LPC15xx SCT Input Processing Unit (SCTIPU)
6&7RXWSXW
SLQV
$&03>@RXWSXWV
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6&7,38
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6&7,138708;
6&7,138708;
Fig 23. SCTIPU connections
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Chapter 14: LPC15xx SCT Input Processing Unit (SCTIPU)
14.3.1 SCTIPU to SCT connections
VDPSOHB
HQDEOHBG
VDPSOHB
HQDEOHBF
VDPSOHB
HQDEOHBE
VDPSOHB
HQDEOHBD
6&7,38
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VFW LQSXWV
6&7 VFW LQSXWV
6&7
VFW LQSXWV
6&7
VFW LQSXWV
6&7
Fig 24. SCTIPU to SCT connections
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Chapter 14: LPC15xx SCT Input Processing Unit (SCTIPU)
14.4 Pin description
Table 193. SCTIPU sample sub-module pin description
Function
I/O
Type
Connect to
Use register
Reference Description
SAMPLE_IN_A0
I
external
to pin
PIO0_14
SAMPLE_CTRL
Table 196
Input source for channel 0
to be routed to output
channel 0.
SAMPLE_IN_B0
I
internal
ACMP0_O out
SAMPLE_CTRL
Table 196
Input source for channel 0
to be routed to output
channel 0.
SAMPLE_IN_A1
I
external
to pin
PIO0_25
SAMPLE_CTRL
Table 196
Input source for channel 1
to be routed to output
channel 1.
SAMPLE_IN_B1
I
internal
ACMP1_O out
SAMPLE_CTRL
Table 196
Input source for channel 1
to be routed to output
channel 1.
SAMPLE_IN_A2
I
external
to pin
PIO1_11
SAMPLE_CTRL
Table 196
Input source for channel 2
to be routed to output
channel 2.
SAMPLE_IN_B2
I
internal
ACMP2_O out
SAMPLE_CTRL
Table 196
Input source for channel 2
to be routed to output
channel 2.
SAMPLE_IN_A3
I
external
to pin
PIO1_26
SAMPLE_CTRL
Table 196
Input source for channel 3
to be routed to output
channel 3.
SAMPLE_IN_B3
I
internal
ACMP3_O out
SAMPLE_CTRL
Table 196
Input source for channel 3
to be routed to output
channel 3.
SAMPLE_ENABLE_A I
internal
SCT0_OUT5
-
-
Latch/sample enable
control input.
SAMPLE_ENABLE_B I
internal
SCT1_OUT5
-
-
Latch/sample enable
control input.
SAMPLE_ENABLE_C I
internal
SCT2_OUT5
-
-
Latch/sample enable
control input.
SAMPLE_ENABLE_D I
internal
SCT3_OUT5
-
-
Latch/sample enable
control input.
SAMPLE_OUT0
internal
SCT0_INMUX[0:6],
SCT1_INMUX[0:6],
SCT2_INMUX[0:2],
SCT3_INMUX[0:2]
SCTn_INMUXm
Table 127,
Table 128,
Table 129,
Table 130
Latched/sampled output
channel 0.
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O
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Chapter 14: LPC15xx SCT Input Processing Unit (SCTIPU)
Table 193. SCTIPU sample sub-module pin description
Function
I/O
Type
Connect to
Use register
Reference Description
SAMPLE_OUT2
O
internal
SCT0_INMUX[0:6],
SCT1_INMUX[0:6],
SCT2_INMUX[0:2],
SCT3_INMUX[0:2]
SCTn_INMUXm
Table 127,
Table 128,
Table 129,
Table 130
Latched/sampled output
channel 1.
SAMPLE_OUT3
O
internal
SCT0_INMUX[0:6],
SCT1_INMUX[0:6],
SCT2_INMUX[0:2],
SCT3_INMUX[0:2]
SCTn_INMUXm
Table 127,
Table 128,
Table 129,
Table 130
Latched/sampled output
channel 2
SAMPLE_OUT4
O
internal
SCT0_INMUX[0:6],
SCT1_INMUX[0:6],
SCT2_INMUX[0:2],
SCT3_INMUX[0:2]
SCTn_INMUXm
Table 127,
Table 128,
Table 129,
Table 130
Latched/sampled output
channel 3.
Table 194. SCTIPU abort sub-module pin description
Function
I/O
Type
Connected to
Use register
Reference Description
ABORT_IN[0:8]
I
internal
or
external
to pins
Any combination of
comparator outputs,
ADC threshold
compare outputs,
SCT outputs, and
abort pin inputs
through switch
matrix
PINASSIGN10.
Table 197,
Table 198
-
Inputs to abort channels 0
to 3.
ABORT_OUT0
O
internal
SCT0_INMUX[0:6]
SCT0_INMUXm
Table 127
SCTIPU abort output 0.
ABORT_OUT1
O
internal
SCT1_INMUX[0:6],
SCT1_INMUXm
Table 128
SCTIPU abort output 1.
ABORT_OUT2
O
internal
SCT2_INMUX[0:2]
SCT2_INMUXm
Table 129
SCTIPU abort output 2.
ABORT_OUT3
O
internal
SCT3_INMUX[0:2]
SCT3_INMUXm
Table 130
SCTIPU abort output 3.
14.5 General description
The SCTIPU is a companion block to the State Configurable Timers (SCTs), useful
predominantly when the SCTs are employed in control systems such as motor or power
control. The SCTIPU performs certain pre-processing on a selection of input signals
before they are passed-on as inputs to the various SCTs. The SCTIPU itself is comprised
of a SAMPLE sub-module and four ABORT sub-modules.
14.5.1 Abort sub-modules
The ABORT sub-module is essentially an AND-OR structure. Nine input sources are
shared among the four ABORT sub-modules. Each of these modules has a 9-bit enable
register which can be programmed to enable one or more of the nine inputs to contribute
to the ORed output from that particular sub-module. The four outputs are then routed to
inputs on the four SCTs.
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Chapter 14: LPC15xx SCT Input Processing Unit (SCTIPU)
This module is useful whenever a collection of multiple input sources trigger exactly the
same response in an SCT. Combining these input sources into a single SCT input
eliminates the need to waste multiple inputs and tie-up multiple events in order to
generate the same SCT reaction. A typical use of these inputs is to trigger SCT events
which implement an emergency shut-down procedures (hence the name ABORT).
14.5.2 Sample sub-module
This sub-module provides a set of latches which allow four SCT inputs to be sampled at
certain times and latched at others. Each of the four outputs from this module have two
alternative input sources and four alternative latch/sample-enable signals. It is also
possible to override latching on any of the four outputs and force its latch into transparent
mode.
The primary purpose of this module is to block signals from being passed-on to the SCT
inputs during periods when they are known to be invalid (eg. during switching). The four
latch/sample-enable inputs are driven by SCT outputs.
14.6 Register description
Table 195. Register overview: SCTIPU (base address 0x400B 8000)
Name
Access
Address
offset
Description
Reset
value
Reference
SAMPLE_CTRL
R/W
0x000
SCTIPU sample control register. Contains the input
mux selects, latch/sample-enable mux selects, and
sample override bits for the SAMPLE module.
0
Table 196
ABORT_ENABLE0
R/W
0x020
SCTIPU abort enable 0 register: Selects which input
source contributes to ORed Abort Output 0.
0
ABORT_SOURCE0
R/W
0x024
SCTIPU abort source 0 register: Status register
indicating which input source caused abort output 0.
0
ABORT_ENABLE1
R/W
0x040
SCTIPU abort enable 1 register: Selects which input
source contributes to ORed Abort Output 1.
0
ABORT_SOURCE1
R/W
0x044
SCTIPU abort source 1 register: Status register
indicating which input source caused abort output 1.
0
ABORT_ENABLE2
R/W
0x060
SCTIPU abort enable 2 register: Selects which input
source contributes to ORed Abort Output 2.
0
ABORT_SOURCE2
R/W
0x064
SCTIPU abort source 2 register: Status register
indicating which input source caused abort output 2.
0
ABORT_ENABLE3
R/W
0x080
SCTIPU abort enable 3 register: Selects which input
source contributes to ORed Abort Output 1.
0
ABORT_SOURCE3
R/W
0x084
SCTIPU abort source 3 register: Status register
indicating which input source caused abort output 3.
0
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Chapter 14: LPC15xx SCT Input Processing Unit (SCTIPU)
14.6.1 SCTIPU Sample control register
Table 196: SCTIPU Sample control register (SAMPLE_CTRL, address 0x400B 8000) bit description
Bit
Symbol
0
IN0SEL
1
2
3
5:4
7:6
Value Description
Select SCTIPU input source for output channel 0.
0
SAMPE_IN_A0. Select input SAMPLE_IN_A0.
1
SAMPE_IN_B0. Select input SAMPLE_IN_B0.
IN1SEL
0
SAMPE_IN_A1. Select input SAMPLE_IN_A1.
1
SAMPE_IN_B1. Select input SAMPLE_IN_B1.
0
Select SCTIPU input source for output channel 2.
0
SAMPE_IN_A2. Select input SAMPLE_IN_A2.
1
SAMPE_IN_B2. Select input SAMPLE_IN_B2.
IN3SEL
0
Select. SCTIPU input source for output channel 3.
0
SAMPE_IN_A3. Select input SAMPLE_IN_A3.
1
SAMPE_IN_B3. Select input SAMPLE_IN_B3.
SAMPLE_EN0SEL
0
Select the sample enable input as the latch/sample-enable control for the
Sample_Output(0) latch. Depending on the value of the corresponding
LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or
latched when the LATCHn_EN bit is 0.
0x0
Selects Sample_Enable_A as the latch/sample-enable control for the
Sample_Output(0) latch.
0x1
Selects Sample_Enable_B as the latch/sample-enable control for the
Sample_Output(0) latch.
0x2
Selects Sample_Enable_C as the latch/sample-enable control for the
Sample_Output(0) latch.
0x3
Selects Sample_Enable_D as the latch/sample-enable control for the
Sample_Output(0) latch.
SAMPLE_EN1SEL
User manual
0
Select SCTIPU input source for output channel 1.
IN2SEL
UM10736
Reset
value
Select the sample enable input as the latch/sample-enable control for the
Sample_Output(1) latch. Depending on the value of the corresponding
LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or
latched when the LATCHn_EN bit is 0.
0x0
Selects Sample_Enable_A as the latch/sample-enable control for the
Sample_Output(1) latch.
0x1
Selects Sample_Enable_B as the latch/sample-enable control for the
Sample_Output(1) latch.
0x2
Selects Sample_Enable_C as the latch/sample-enable control for the
Sample_Output(1) latch.
0x3
Selects Sample_Enable_D as the latch/sample-enable control for the
Sample_Output(1) latch.
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Chapter 14: LPC15xx SCT Input Processing Unit (SCTIPU)
Table 196: SCTIPU Sample control register (SAMPLE_CTRL, address 0x400B 8000) bit description …continued
Bit
Symbol
9:8
SAMPLE_EN2SEL
Value Description
Select the sample enable input as the latch/sample-enable control for the
Sample_Output(2) latch. Depending on the value of the corresponding
LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or
latched when the LATCHn_EN bit is 0.
0x0
Selects Sample_Enable_A as the latch/sample-enable control for the
Sample_Output(2) latch.
0x1
Selects Sample_Enable_B as the latch/sample-enable control for the
Sample_Output(2) latch.
0x2
Selects Sample_Enable_C as the latch/sample-enable control for the
Sample_Output(2) latch.
0x3
Selects Sample_Enable_D as the latch/sample-enable control for the
Sample_Output(2) latch.
11:10 SAMPLE_EN3SEL
12
13
14
0x0
Selects Sample_Enable_A as the latch/sample-enable control for the
Sample_Output(3) latch.
0x1
Selects Sample_Enable_B as the latch/sample-enable control for the
Sample_Output(3) latch.
0x2
Selects Sample_Enable_C as the latch/sample-enable control for the
Sample_Output(3) latch.
0x3
Selects Sample_Enable_D as the latch/sample-enable control for the
Sample_Output(3) latch.
0
Enable latch for output channel 0.
0
0
Transparent mode. Sample_Output(0) latch is forced into transparent mode. The
selected Sample_Input is passed directly through to Sample_Output(0). The
sample-enable control line selected for this latch has no effect.
1
Latched mode. The Sample_Output(0) latch is operational and will sample or
latch based on the state of the selected sample-enable control signal.
LATCHEN1
Enable latch for output channel 1.
0
0
Transparent mode. Sample_Output(1) latch is forced into transparent mode. The
selected Sample_Input is passed directly through to Sample_Output(1). The
sample-enable control line selected for this latch has no effect.
1
Latched mode. The Sample_Output(1) latch is operational and will sample or
latch based on the state of the selected sample-enable control signal.
LATCHEN2
User manual
0
Select the sample enable input as the latch/sample-enable control for the
Sample_Output(3) latch. Depending on the value of the corresponding
LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or
latched when the LATCHn_EN bit is 0.
LATCHEN0
UM10736
Reset
value
Enable latch for output channel 2.
0
0
Transparent mode. Sample_Output(2) latch is forced into transparent mode. The
selected Sample_Input is passed directly through to Sample_Output(2). The
sample-enable control line selected for this latch has no effect.
1
Latched mode. The Sample_Output(2) latch is operational and will sample or
latch based on the state of the selected sample-enable control signal.
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Chapter 14: LPC15xx SCT Input Processing Unit (SCTIPU)
Table 196: SCTIPU Sample control register (SAMPLE_CTRL, address 0x400B 8000) bit description …continued
Bit
Symbol
15
LATCHEN3
Value Description
Reset
value
Enable latch for output channel 3.
0
0
Transparent mode. Sample_Output(3) latch is forced into transparent mode. The
selected Sample_Input is passed directly through to Sample_Output(3). The
sample-enable control line selected for this latch has no effect.
1
Latched mode. The Sample_Output(3) latch is operational and will sample or
latch based on the state of the selected sample-enable control signal.
31:16
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
NA
14.6.2 SCT Abort enable registers 0 to 3
For each of the four abort sub-modules, this register selects which input sources will be
enabled to contribute to the ORed output.
Table 197: SCTIPU Abort enable register (ABORT_ENABLE[0:3], address 0x400B 8020 (ABORT_ENABLE0) to
0x400B 8080 (ABORT_ENABLE3)) bit description
Bit
Symbol
0
ENA0
1
Value Description
Enable abort source SCT_ABORT0. Select pin from switch matrix.
0
Disabled.
1
Enabled.
ENA1
Enable abort source SCT_ABORT1. Select pin from switch matrix.
0
1
2
3
4
5
ENA2
Disabled.
1
Enabled.
Enable abort source ADC0_THCMP_IRQ.
0
Disabled.
1
Enabled.
ENA4
Enable abort source ADC1_THCMP_IRQ.
0
Disabled.
1
Enabled.
ENA5
Enable abort source ACMP0_O output.
1
7
ENA6
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0
0
0
0
Disabled.
Enabled.
Enable abort source ACMP1_O output.
0
Disabled.
1
Enabled.
ENA7
0
Enabled.
0
ENA3
0
Disabled.
Enable abort source SCT0_OUT9.
0
6
Reset
value
Enable abort source ACMP2_O output.
0
Disabled.
1
Enabled.
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Chapter 14: LPC15xx SCT Input Processing Unit (SCTIPU)
Table 197: SCTIPU Abort enable register (ABORT_ENABLE[0:3], address 0x400B 8020 (ABORT_ENABLE0) to
0x400B 8080 (ABORT_ENABLE3)) bit description …continued
Bit
Symbol
8
ENA8
Value Description
Reset
value
Enable abort source ACMP3_O output.
0
Disabled.
1
Enabled.
31:9
0
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
NA
14.6.3 SCT Abort source registers 0 to 3
For each sub-module, this status register indicates which one (or more) abort inputs
occurred to cause the abort output to be activated.
Remark: The accuracy of the Abort Source Status register is not guaranteed under all
conditions. If an abort-enabled input is applied for a relatively short period of time, it is
possible that it may be captured in this register even if it wasn’t sustained long enough to
actually be recognized as a valid input by the SCT.
Table 198: SCTIPU Abort source register (ABORT_SOURCE[0:3], address 0x400B 8024 (ABORT_SOURCE0) to
0x400B 8084 (ABORT_SOURCE3)) bit description
Bit
Symbol
0
ACT0
1
2
3
4
Value Description
Source SCT_ABORT0 activated. This bit is set by hardware when the source is 0
active. Write 0 to clear. This function can be assigned to any pin via the
PINASSIGN10 register in the switch matrix.
0
Not activated.
1
Activated.
ACT1
Source SCT_ABORT1 activated. This bit is set by hardware when the source is 0
active. Write 0 to clear. This function can be assigned to any pin via the
PINASSIGN10 register in the switch matrix.
0
Not activated.
1
Activated.
ACT2
Source SCT0_OUT9 activated. This bit is set by hardware when the source is
active. Write 0 to clear.
0
Not activated.
1
Activated.
ACT3
Source ADC0_THCMP_IRQ activated. This bit is set by hardware when the
source is active. Write 0 to clear.
0
Not activated.
1
Activated.
ACT4
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Reset
value
Source ADC1_THCMP_IRQ activated. This bit is set by hardware when the
source is active. Write 0 to clear.
0
Not activated.
1
Activated.
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Chapter 14: LPC15xx SCT Input Processing Unit (SCTIPU)
Table 198: SCTIPU Abort source register (ABORT_SOURCE[0:3], address 0x400B 8024 (ABORT_SOURCE0) to
0x400B 8084 (ABORT_SOURCE3)) bit description …continued
Bit
Symbol
5
ACT5
6
7
8
Value Description
Source ACMP0_O output activated. This bit is set by hardware when the source 0
is active. Write 0 to clear.
0
Not activated.
1
Activated.
ACT6
Source ACMP1_O output activated. This bit is set by hardware when the source 0
is active. Write 0 to clear.
0
Not activated.
1
Activated.
ACT7
Source ACMP2_O output activated. This bit is set by hardware when the source 0
is active. Write 0 to clear.
0
Not activated.
1
Activated.
ACT8
31:9
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Reset
value
Source ACMP3_O output activated. This bit is set by hardware when the source 0
is active. Write 0 to clear.
0
Not activated.
1
Activated.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM,
SCTimer1/PWM)
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User manual
15.1 How to read this chapter
The large SCTs are available on all parts.
The SCT0 and SCT1 outputs #7 cannot be connected to external pins on the LQFP48 and
LQFP64 packages. (They are available for internal connections.)
15.2 Features
The following feature list summarizes the configuration for the two large SCTs. Each large
SCT has a companion small SCT (see Section 16.2) with fewer inputs and outputs and a
reduced feature set.
• Each SCT supports:
– 16 match/capture registers
– 16 events
– 16 states
– Match register 0 to 5 support a fractional component for the dither engine
– 8 inputs and 10 outputs
• Counter/timer features:
– Configurable as two 16-bit counters or one 32-bit counter.
– Counters clocked by bus clock or selected input.
– Up counters or up-down counters.
– Configurable number of match and capture registers. Up to 16 match and capture
registers total.
– Upon match create the following events: interrupt, stop, limit timer or change
direction; toggle outputs.
– Counter value can be loaded into capture register triggered by match or
input/output toggle.
• PWM features:
– Counters can be used in conjunction with match registers to toggle outputs and
create time-proportioned PWM signals.
– Up to 8 single-edge or dual-edge controlled PWM outputs with independent duty
cycles and common PWM cycle length.
• Event creation features:
– The following conditions define an event: a counter match condition, an input (or
output) condition, a combination of a match and/or and input/output condition in a
specified state.
– Selected events can limit, halt, start, or stop a counter.
– Events control state changes, outputs, interrupts, and DMA requests.
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
– Match register 0 can be used as an automatic limit.
– In bi-directional mode, events can be enabled based on the count direction.
– Match events can be held until another qualifying event occurs.
• State control features:
– A state is defined by events that can take place in the state while the counter is
running.
– A state changes into another state as result of an event.
– Each event can be assigned to one or more states.
– State variable allows sequencing across multiple counter cycles.
• Dither engine.
• Integrated with an input pre-processing unit (SCTIPU) to combine or delay input
events.
Inputs and outputs on the SCT0 and SCT1 are configured as follows:
• 8 inputs
– 7 inputs. Each input except input 7 can select one of 23 sources from an input
multiplexer.
– One input connected directly to the SCT PLL for a high-speed dedicated clock
input.
• 10 outputs (some outputs are connected to multiple locations)
– Three outputs connected to external pins through the switch matrix as movable
functions.
– Five outputs connected to external pins through the switch matrix as fixed-pin
functions.
– Two outputs connected to the SCTIPU to use as sample and abort inputs.
– One output connected to the other large SCT
– Four outputs connected to one small SCT
– Two outputs connected to each ADC trigger input
15.3 Basic configuration
Configure the SCT as follows:
• Use the SYSAHBCLKCTRL register (Table 51) to enable the clock to the SCT0/1
registers interface and peripheral clock. The system clock is the input clock to the
SCT clock processing and is the source of the SCT clock.
• Clear the SCT peripheral reset using the PRESETCTRL register (Table 36).
• The SCT0/1 combined interrupts are connected to slots #16/17 in the NVIC.
• SCT inputs are selected from the SCT0/1 input mux registers (see Table 127 and
Table 128).
• Use the switch matrix to connect the SCT outputs to pins (see Table 200).
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
Remark: For applications that require exact timing of the SCT outputs (for example
PWM), assign the outputs only to fixed-pin functions to ensure that the output skew is
nearly the same for all outputs.
• The SCT DMA request lines 0 and 1 are connected to the DMA trigger inputs via the
DMA_ITRIG_INMUX registers. See Table 132.
• For logically combining SCT input events for an abort function and blocking SCT
inputs for a fixed amount of time, see Section 15.3.5 “Use the SCT with the SCTIPU”.
6&7
6<6&21
V\VWHPFORFN
&/2&.
352&(66,1*
6&7B,1
,5&RVFLOODWRU
6&73//
V\VWHPRVFLOODWRU
6&7
&/2&.
352&(66,1*
6&73//&/.6(/
6&73//FORFNVHOHFW
6&7B,1
WR6&7
Fig 25. Large SCT clocking
6:0
SLQV
6&7RXWSXWV
6&7,38RXWSXWV
$&03RXWSXWV
$'&7+&03LQWHUUXSWV
FRUHLQWHUUXSW
SLQV
$'&75,**(5
6&7
,1387
08;
6&7,38
6&7
6&7,138708;
6&7,138708;
6&73//
'0$75,**(5
,138708;
Fig 26. SCT0 connections
6:0
SLQV
6&7RXWSXWV
6&7,38RXWSXWV
$&03RXWSXWV
$'&7+&03LQWHUUXSWV
FRUHLQWHUUXSW
SLQV
$'&75,**(5
6&7
,1387
08;
6&7,38
6&7
6&7,138708;
6&7,138708;
6&73//
'0$75,**(5
,138708;
Fig 27. SCT1 connections
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
15.3.1 SCT inputs and outputs
Each of the SCT inputs has a pre-selector that can select one of 23 possible input signals
(SCT input mux). The input signals are numbered 0 to 22 (see Figure 28), and the signal
number is programmed in the SCT0_INMUXn or SCT1_INMUXn register for any
particular input:
SCT0 inputs are selected through input muxes SCT0_INMUX[0:6]. See Table 127.
SCT1 inputs are selected through input muxes SCT1_INMUX[0:6]. See Table 128.
One SCT input (SCT_IN7) is dedicated to the high-speed clock signal generated by the
SCT PLL in the CGU (see Figure 3 and Section 3.6.44).
Each large SCT has 10 outputs. Eight outputs are connected to external pins through the
switch matrix. Some outputs are routed to the other SCT blocks, to the ADC trigger inputs,
and to the SCTIPU. An SCT output can be routed to multiple places.
8
external
pins
large SCT1
output 4
small SCT2
output 5:4
8
10:9
11
12
16:13
21:17
22
SCT0_INMUX0
7:0
0
0
1
2
3
4
5
6
7
2
ADC0_THCMP
ADC1_THCMP
ACMP[3:0]_OUT
SCT IPU
SWITCH
MATRIX
76
external
pins
4
5
DEBUG
7
SCT0
3
SCT0_INMUX6
7:0
8
10:9
11
12
16:13
21:17
22
3
SCT2_INMUX[2:0]
SCT IPU
SCT2_INMUX[2:0]
ADC1 TRIGGER
3
6
SCT2_INMUX[2:0]
ADC0 TRIGGER
8
9
CGU SCT PLL
SCT1_INMUX[6:0]
7
3
SCT2_INMUX[2:0]
ADC0 TRIGGER
ADC1 TRIGGER
SCTIPU ABORT_IN2
Fig 28. SCT0 inputs and outputs
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
8
external
pins
large SCT0
output 4
small SCT3
output 5:4
8
10:9
11
12
16:13
21:17
22
SCT1_INMUX0
7:0
0
0
1
2
3
4
5
6
7
2
ADC0_THCMP
ADC1_THCMP
ACMP[3:0]_OUT
SCT IPU
SWITCH
MATRIX
76
external
pins
4
5
DEBUG
7
SCT1
3
SCT1_INMUX6
3
7:0
8
10:9
11
12
16:13
21:17
22
3
6
8
9
3
SCT0_INMUX[6:0]
SCT3_INMUX[2:0]
SCT IPU
SCT3_INMUX[2:0]
SCT3_INMUX[2:0]
ADC0 TRIGGER
SCT3_INMUX[2:0]
ADC1 TRIGGER
ADC0 TRIGGER
ADC1 TRIGGER
CGU SCT PLL
7
Fig 29. SCT1 inputs and outputs
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15.3.2 Connections between large and small SCTs
One large and one small SCT can be chained together through their inputs and outputs.
Each large SCT has one associated small SCT. The two SCTs are connected through the
three outputs of the large SCT and the input pin muxes of the small SCT. Two outputs of
the small SCT are connected back to the input pin muxes of the associated large SCT.
3:0
0
4
5
6
SCT0 8:7 2
7:0
8
10:9
22:11
SCT1_INMUX0
7:0
8
10:9
22:11
SCT0_INMUX0
In addition, each large SCT has one output connected to the other large SCT. The small
SCTs are not connected to each other.
0
4
SCT1
5
6
8:7 2
6
7
7:0
8
10:9
22:11
SCT1_INMUX6
SCT0_INMUX6
9
7:0
8
10:9
22:11
3:0
9
6
0
5:4 2
SCT2
2
3:0
4
5
7:6
20:8
3:0
4
5
7:6
20:8
SCT3_INMUX0
3:0
SCT3_INMUX2
3:0
4
5
7:6
20:8
SCT2_INMUX2
3:0
4
5
7:6
20:8
SCT2_INMUX0
7
0
3:0
5:4 2
SCT3
2
Fig 30. SCT chaining
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10:0
11
12
22:13
0
4
5
6
7
8
9
15:10
7
8
9
SCT0
6
1:0
2
3
SCT1_INMUX6
10:0
11
12
22:13
SCT1_INMUX0
7
10:0
11
12
22:13
TRIGGER INPUT
5:0
6
ADC0
4
5
6
7
8
9
15:10
0
6:0
7
8
SCT1
9
ADC1
TRIGGER INPUT
10:0
11
12
22:13
SCT0_INMUX0
1:0
2
3
SCT0_INMUX6
ADC0_THCMP_IRQ
ADC1_THCMP_IRQ
15.3.3 Connections between the SCTs and the ADC trigger inputs
6
8
9
20:10
7:0
8
9
20:10
7:0
8
9
20:10
SCT2_INMUX2
7:0
SCT3_INMUX0
8
9
20:10
SCT3_INMUX2
7:0
SCT2_INMUX0
7
1:0
0
2
3
4
SCT2 5
2
0
SCT3
1:0
2
3
4
5
2
Fig 31. SCT to ADC connections
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15.3.4 Use the SCT as a simple timer
To configure the SCT as a simple timer with match or capture functionality, follow these
steps:
1. Set up the SCT as one 32-bit timer or one or two 16-bit timers. See Table 202.
2. Preload the 32-bit timer or the 16-bit timers with a count value. See Table 209.
3. If you want to create a match event when the timer reaches a match value:
a. Configure the register map for match registers. See Table 212.
b. Configure one or more match registers with a match value. See Table 222.
c. For each match value, create a match event. See Table 229.
d. If you want to create an interrupt on a match event, enable the event for interrupt.
See Table 219.
e. If you want to create a match output on a pin, connect the SCTn_OUTn function to
a pin (see Section 15.4) and select an output for the match event in the EVn_CTRL
register. See Table 229. The EVn_CTRL registers also control what type of output
signal is created.
4. If you want to capture a timer value on a capture signal:
a. Configure the register map for capture registers. See Table 212.
b. Create one or more capture events. See Table 229.
c. Connect the SCT_IN functions to pins (see Section 15.4) and configure the signal
to create an event. See Table 229.
5. Start the timer by writing to the CRTL register. See Table 203.
6. Read the capture registers to read the timer value at the time of the capture events.
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15.3.5 Use the SCT with the SCTIPU
The SCTIPU provides a pre-processing unit for the SCT inputs for two purposes:
• Combine signal transitions to one transition that always generates the same SCT
response. An example is aborting an SCT operation. See Section 14.5.1
• Provide latched inputs so that signals can be blocked for some fixed time before being
passed on to the SCT inputs. See Section 14.5.2.
15.3.5.1 Abort function
A set of transitions on the SCT_ABORT pins, the ADC threshold compare outputs, the
comparator outputs, or the SCT0 output 9 can be logically combined in the SCTIPU so
that any transition in the set triggers the same SCT response. The pre-processing
replaces many individual signal transitions from multiple SCT inputs by one transition
monitored on one input.
Remark: Signals on the SCT_ABORT pins must be active HIGH or rising edge and the
SCT0_OUT9 output must also be configured for active HIGH/rising edge if used. The
ADC interrupts and the comparator outputs are active HIGH.
To set up an abort function for SCT0 on input 5 SCT0_IN5, follow these steps:
1. In the SCTIPU ABORT_ENABLE0 register, enable one or more inputs. Any
LOW-HIGH transition on the enabled input produces a rising edge on the output of the
abort module 0.
2. If you want to use the SCT_ABORT0/SCT_ABORT1 pin function, connect pin
functions to a pin using the switch matrix PINASSIGN10 register.
3. In the SCT0_INMUX5 register, select the SCTIPU_ABORT input (#17).
4. Set up the SCT0 by defining SCT0_IN5 as rising edge or HIGH input and configure an
event that is triggered on SCT0_IN5. There are many possible actions in response to
this event:
– Stop counting.
– Change the count direction.
– Force any of the SCT0 outputs HIGH or LOW.
Remark: The same procedure can be used for applications other than an abort whenever
an SCT response to a fixed set of input transitions is required.
15.4 Pin description
See Section 8.3.1 “Connect an internal signal to a package pin” to assign the SCT
functions to external pins.
Remark: For applications that require exact timing of the SCT outputs (for example
PWM), assign the outputs only to fixed-pin functions to ensure that the output skew is
nearly the same for all outputs.
All SCT input signals are selected through the input mux except for input 7 which is
connected to the SCT PLL output. The signals from the external pins selected in the input
mux registers are connected directly to the SCT inputs and not routed through the switch
matrix.
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SCT outputs are routed to multiple places and can be connected to pins and inputs of the
other SCTs, SCTIPU, and ADC triggers at the same time.
Table 199. SCT0/1 pin description (inputs)
Function
Type
Connect to
Use register
Reference
SCT0_IN[0:6]
external to pins
or internal
one of the following:
8 pins, SCT1_OUT4,
SCT2_OUT[5:4],
SCT0_INMUX[0:6]
Table 127
ADC0_THCMP_IRQ,
ADC1_THCMP_IRQ,
ACMP_OUT[3:0],
SCT_IPU outputs,
DEBUG_HALTED
SCT0_IN7
internal
SCT PLL output
n/a
-
SCT1_IN[0:6]
external to pins
or internal
one of the following:
8 pins, SCT0_OUT4,
SCT3_OUT[5:4],
ADC0_THCMP_IRQ,
SCT1_INMUX[0:6]
Table 128
n/a
-
ADC1_THCMP_IRQ,
ACMP_OUT[3:0],
SCT_IPU outputs,
DEBUG_HALTED
SCT1_IN7
internal
SCT PLL output
Table 200. SCT0/1 pin description (outputs)
Function
Type
Connect to
Use register
Reference
SCT0_OUT[0:2]
external to pin
any pin
PINASSIGN7
Table 114
SCT0_OUT3
external to pin
PIO0_0
PINENABLE1
Table 124
SCT0_OUT4
external to pin
PIO0_1
PINENABLE1
Table 124
internal
SCT1 input mux
SCT1_INMUX[6:0]
Table 128
internal
SCT2 input mux
SCT2_INMUX[2:0]
Table 129
SCT0_OUT5
SCT0_OUT6
SCT0_OUT7
SCT0_OUT8
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external to pin
PIO0_18
PINENABLE1
Table 124
internal
SCTIPU
-
-
internal
SCT2 input mux
SCT2_INMUX[2:0]
Table 129
external to pin
PIO0_24
PINENABLE1
Table 124
internal
ADC1 trigger
SEQ_A, SEQ_B
Table 437,
Table 438
internal
SCT2 input mux
SCT2_INMUX[2:0]
Table 129
internal
ADC0 trigger
SEQ_A, SEQ_B
Table 437,
Table 438
external to pin
PIO1_14
PINENABLE1
Table 124
internal
ADC0 trigger
SEQ_A, SEQ_B
Table 437,
Table 438
internal
SCT2 input mux
SCT2_INMUX[2:0]
Table 129
external to pin
n/a
n/a
-
internal
SCT2 input mux
SCT2_INMUX[2:0]
Table 129
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
Table 200. SCT0/1 pin description (outputs)
Function
Type
Connect to
Use register
Reference
SCT0_OUT9
external to pin
n/a
n/a
-
internal
ADC0 trigger
SEQ_A, SEQ_B
Table 437,
Table 438
internal
ADC1 trigger
SEQ_A, SEQ_B
Table 437,
Table 438
internal
SCTIPU abort input 2 ABORT_ENABLE
Table 197
SCT1_OUT[0:2]
external to pin
any pin
PINASSIGN8
Table 114
SCT1_OUT3
external to pin
PIO0_2
PINENABLE1
Table 124
SCT1_OUT4
external to pin
PIO0_3
PINENABLE1
Table 124
internal
SCT0 input mux
SCT0_INMUX[6:0]
Table 127
internal
SCT3 input mux
SCT3_INMUX[2:0]
Table 130
external to pin
PIO0_14
PINENABLE1
Table 124
internal
SCTIPU
-
-
internal
SCT3 input mux
SCT3_INMUX[2:0]
Table 130
SCT1_OUT6
external to pin
PIO0_20
PINENABLE1
Table 124
SCT1_OUT7
external to pin
PIO1_17
PINENABLE1
Table 124
internal
SCT3_INMUX[2:0]
SCT3_INMUX[2:0]
Table 130
internal
ADC0 trigger
SEQ_A, SEQ_B
Table 437,
Table 438
external to pin
n/a
-
-
internal
SCT3_INMUX[2:0]
SCT3_INMUX[2:0]
Table 130
internal
ADC1 trigger
SEQ_A, SEQ_B
Table 437,
Table 438
external to pin
n/a
-
-
internal
ADC0 trigger
SEQ_A, SEQ_B
Table 437,
Table 438
internal
ADC1 trigger
SEQ_A, SEQ_B
Table 437,
Table 438
SCT1_OUT5
SCT1_OUT8
SCT1_OUT9
15.5 General description
The State Configurable Timer (SCT) allows a wide variety of timing, counting, output
modulation, and input capture operations.
The most basic user-programmable option is whether a SCT operates as two 16-bit
counters or a unified 32-bit counter. In the two-counter case, in addition to the counter
value the following operational elements are independent for each half:
• State variable
• Limit, halt, stop, and start conditions
• Values of Match/Capture registers, plus reload or capture control values
In the two-counter case, the following operational elements are global to the SCT:
• Clock selection
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
•
•
•
•
Inputs
Events
Outputs
Interrupts
Events, outputs, and interrupts can use match conditions from either counter.
Remark: In this chapter, the term bus error indicates an SCT response that makes the
processor take an exception.
V\VWHPFORFN
6&7FORFN
FORFN
SURFHVVLQJ
LQSXWV
V\QFHGLQSXWV
SUHVFDOHUV
FRQWURO
ORJLF
PDWFK
ORJLF
FRXQWHUV
HYHQW
JHQHUDWLRQ
PDWFK
FDSWXUH
UHJLVWHUV
RXWSXWV
VWDWH
ORJLF
LQWHUUXSWV
Fig 32. SCT block diagram
6&7FORFN
V\VWHPFORFN
FORFNORJLF
LQSXWHGJHV
LQSXWV
SUH&ORFN
&/.02'( &.6(/
,16<1&
HYHQWV
/,0,7B+
PX[
SUHVFDOHU
+
VHOHFW
FRXQWHU
+
+FRXQWHU
/,0,7B/
6723B+67$57B++$/7B+
VHOHFW
6723B/67$57B/+$/7B/
&75/B+
SUHVFDOHU
/
PX[
8QLILHG
FRXQWHU
FRXQWHU
/
/FRXQWHU
PX[
&75/B/
Fig 33. SCT counter and select logic
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
15.6 Register description
The register addresses of the State Configurable Timer are shown in Table 201. For most
of the SCT registers, the register function depends on the setting of certain other register
bits:
1. The UNIFY bit in the CONFIG register determines whether the SCT is used as one
32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit
counter/timers named L and H. The setting of the UNIFY bit is reflected in the register
map:
– UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer).
– UNIFY = 0: Access the L and H registers by a 32-bit read or write operation or can
be read or written to individually (for operation as two 16-bit counter/timers).
Typically, the UNIFY bit is configured by writing to the CONFIG register before any
other registers are accessed.
2. The REGMODEn bits in the REGMODE register determine whether each set of
Match/Capture registers uses the match or capture functionality:
– REGMODEn = 1: Registers operate as match and reload registers.
– REGMODEn = 0: Registers operate as capture and capture control registers.
Table 201. Register overview: State Configurable Timer (base address 0x1C01 8000 (SCT0) and 0x1C01 C000
(SCT1))
Name
Access Address Description
offset
Reset value Reference
CONFIG
R/W
0x000
SCT configuration register
0x0000 7E00 Table 202
CTRL
R/W
0x004
SCT control register
0x0004 0004 Table 203
CTRL_L
R/W
0x004
SCT control register low counter 16-bit
0x0004 0004 Table 203
CTRL_H
R/W
0x006
SCT control register high counter 16-bit
0x0004 0004 Table 203
LIMIT
R/W
0x008
SCT limit register
0x0000 0000 Table 204
LIMIT_L
R/W
0x008
SCT limit register low counter 16-bit
0x0000 0000 Table 204
LIMIT_H
R/W
0x00A
SCT limit register high counter 16-bit
0x0000 0000 Table 204
HALT
R/W
0x00C
SCT halt condition register
0x0000 0000 Table 205
HALT_L
R/W
0x00C
SCT halt condition register low counter 16-bit
0x0000 0000 Table 205
HALT_H
R/W
0x00E
SCT halt condition register high counter 16-bit
0x0000 0000 Table 205
STOP
R/W
0x010
SCT stop condition register
0x0000 0000 Table 206
STOP_L
R/W
0x010
SCT stop condition register low counter 16-bit
0x0000 0000 Table 206
STOP_H
R/W
0x012
SCT stop condition register high counter 16-bit
0x0000 0000 Table 206
START
R/W
0x014
SCT start condition register
0x0000 0000 Table 207
START_L
R/W
0x014
SCT start condition register low counter 16-bit
0x0000 0000 Table 207
START_H
R/W
0x016
SCT start condition register high counter 16-bit
0x0000 0000 Table 207
DITHER
R/W
0x018
SCT dither condition register
Table 208
DITHER_L
R/W
0x018
SCT dither condition register low counter 16-bit
Table 208
DITHER_H
R/W
0x01A
SCT dither condition register high counter 16-bit
Table 208
-
-
0x01C 0x03C
Reserved
-
COUNT
R/W
0x040
SCT counter register
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Table 201. Register overview: State Configurable Timer (base address 0x1C01 8000 (SCT0) and 0x1C01 C000
(SCT1)) …continued
Name
Access Address Description
offset
Reset value Reference
COUNT_L
R/W
0x040
SCT counter register low counter 16-bit
0x0000 0000 Table 209
COUNT_H
R/W
0x042
SCT counter register high counter 16-bit
0x0000 0000 Table 209
STATE
R/W
0x044
SCT state register
0x0000 0000 Table 210
STATE_L
R/W
0x044
SCT state register low counter 16-bit
0x0000 0000 Table 210
STATE_H
R/W
0x046
SCT state register high counter 16-bit
0x0000 0000 Table 210
INPUT
RO
0x048
SCT input register
0x0000 0000 Table 211
REGMODE
R/W
0x04C
SCT match/capture registers mode register
0x0000 0000 Table 212
REGMODE_L
R/W
0x04C
SCT match/capture registers mode register low
counter 16-bit
0x0000 0000 Table 212
REGMODE_H
R/W
0x04E
SCT match/capture registers mode register high
counter 16-bit
0x0000 0000 Table 212
OUTPUT
R/W
0x050
SCT output register
0x0000 0000 Table 213
OUTPUTDIRCTRL
R/W
0x054
SCT output counter direction control register
0x0000 0000 Table 214
RES
R/W
0x058
SCT conflict resolution register
0x0000 0000 Table 215
DMAREQ0
R/W
0x05C
SCT DMA request 0 register
0x0000 0000 Table 216
DMAREQ1
R/W
0x060
SCT DMA request 1 register
0x0000 0000 Table 217
-
-
0x064 0x0EC
Reserved
-
EVEN
R/W
0x0F0
SCT event enable register
0x0000 0000 Table 218
EVFLAG
R/W
0x0F4
SCT event flag register
0x0000 0000 Table 219
CONEN
R/W
0x0F8
SCT conflict enable register
0x0000 0000 Table 220
CONFLAG
R/W
0x0FC
SCT conflict flag register
0x0000 0000 Table 221
MATCH0 to
MATCH15
R/W
0x100 to SCT match value register of match channels 0 to
0x13C
15; REGMOD0 to REGMODE15 = 0
0x0000 0000 Table 221
MATCH0_L to
MATCH15_L
R/W
0x100 to SCT match value register of match channels 0 to
0x13C
15; low counter 16-bit; REGMOD0_L to
REGMODE15_L = 0
0x0000 0000 Table 221
MATCH0_H to
MATCH15_H
R/W
0x102 to SCT match value register of match channels 0 to
0x13E
15; high counter 16-bit; REGMOD0_H to
REGMODE15_H = 0
0x0000 0000 Table 221
CAP0 to CAP15
R
0x100 to SCT capture register of capture channel 0 to 15;
0x13C
REGMOD0 to REGMODE15 = 1
0x0000 0000 Table 224
CAP0_L to CAP15_L
R
0x100 to SCT capture register of capture channel 0 to 15;
0x13C
low counter 16-bit; REGMOD0_L to
REGMODE15_L = 1
0x0000 0000 Table 224
CAP0_H to CAP15_H R
0x102 to SCT capture register of capture channel 0 to 15;
0x13E
high counter 16-bit; REGMOD0_H to
REGMODE15_H = 1
0x0000 0000 Table 224
FRACMAT0 to 5
R/W
0x140 to Fractional match registers 0 to 5 for SCT match
0x154
value registers 0 to 5.
0x0000 0000 Table 223
FRACMAT0_L to
FRACMAT5_L
R/W
0x140 to Fractional match registers 0 to 5 for SCT match
0x154
value registers 0 to 5; low counter 16-bit.
0x0000 0000 Table 223
FRACMAT0_H to
FRACMAT5_H
R/W
0x142 to Fractional match registers 0 to 5 for SCT match
0x156
value registers 0 to 5; high counter 16-bit.
0x0000 0000 Table 223
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
Table 201. Register overview: State Configurable Timer (base address 0x1C01 8000 (SCT0) and 0x1C01 C000
(SCT1)) …continued
Name
Access Address Description
offset
Reset value Reference
MATCHREL0 to
MATCHREL15
R/W
0x200 to SCT match reload value register 0 to 15;
0x23C
REGMOD0 = 0 to REGMODE15 = 0
0x0000 0000 Table 225
MATCHREL0_L to
MATCHREL15_L
R/W
0x200 to SCT match reload value register 0 to 15; low
0x23C
counter 16-bit; REGMOD0_L = 0 to
REGMODE15_L = 0
0x0000 0000 Table 225
MATCHREL0_H to
MATCHREL15_H
R/W
0x202 to SCT match reload value register 0 to 15; high
0x23E
counter 16-bit; REGMOD0_H = 0 to
REGMODE15_H = 0
0x0000 0000 Table 225
CAPCTRL0 to
CAPCTRL15
R/W
0x200 to SCT capture control register 0 to 15; REGMOD0
0x23C
= 1 to REGMODE15 = 1
0x0000 0000 Table 227
CAPCTRL0_L to
CAPCTRL15_L
R/W
0x200 to SCT capture control register 0 to 15; low counter
0x23C
16-bit; REGMOD0_L = 1 to REGMODE15_L = 1
0x0000 0000 Table 227
CAPCTRL0_H to
CAPCTRL15_H
R/W
0x202 to SCT capture control register 0 to 15; high counter 0x0000 0000 Table 227
0x23E
16-bit; REGMOD0 = 1 to REGMODE15 = 1
FRACMATREL0 to
FRACMATREL5
R/W
0x240 to Fractional match reload registers 0 to 5 for SCT
0x254
match value registers 0 to 5.
0x0000 0000 Table 226
FRACMATREL0_L to R/W
FRACMATREL5_L
0x240 to Fractional match reload registers 0 to 5 for SCT
0x254
match value registers 0 to 5; low counter 16-bit.
0x0000 0000 Table 226
FRACMATREL0_H to R/W
FRACMATREL5_H
0x242 to Fractional match reload registers 0 to 5 for SCT
0x256
match value registers 0 to 5; high counter 16-bit.
0x0000 0000 Table 226
EV0_STATE
R/W
0x300
SCT event state register 0
0x0000 0000 Table 228
EV0_CTRL
R/W
0x304
SCT event control register 0
0x0000 0000 Table 229
EV1_STATE
R/W
0x308
SCT event state register 1
0x0000 0000 Table 228
EV1_CTRL
R/W
0x30C
SCT event control register 1
0x0000 0000 Table 229
EV2_STATE
R/W
0x310
SCT event state register 2
0x0000 0000 Table 228
EV2_CTRL
R/W
0x314
SCT event control register 2
0x0000 0000 Table 229
EV3_STATE
R/W
0x318
SCT event state register 3
0x0000 0000 Table 228
EV3_CTRL
R/W
0x31C
SCT event control register 3
0x0000 0000 Table 229
EV4_STATE
R/W
0x320
SCT event state register 4
0x0000 0000 Table 228
EV4_CTRL
R/W
0x324
SCT event control register4
0x0000 0000 Table 229
EV5_STATE
R/W
0x328
SCT event state register 5
0x0000 0000 Table 228
EV5_CTRL
R/W
0x32C
SCT event control register 5
0x0000 0000 Table 229
EV6_STATE
R/W
0x330
SCT event state register 6
0x0000 0000 Table 228
EV6_CTRL
R/W
0x334
SCT event control register 6
0x0000 0000 Table 229
EV7_STATE
R/W
0x338
SCT event state register 7
0x0000 0000 Table 228
EV7_CTRL
R/W
0x33C
SCT event control register 7
0x0000 0000 Table 229
EV8_STATE
R/W
0x340
SCT event state register 8
0x0000 0000 Table 228
EV8_CTRL
R/W
0x344
SCT event control register 8
0x0000 0000 Table 229
EV9_STATE
R/W
0x348
SCT event state register 9
0x0000 0000 Table 228
EV9_CTRL
R/W
0x34C
SCT event control register 9
0x0000 0000 Table 229
EV10_STATE
R/W
0x350
SCT event state register 10
0x0000 0000 Table 228
EV10_CTRL
R/W
0x354
SCT event control register 10
0x0000 0000 Table 229
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
Table 201. Register overview: State Configurable Timer (base address 0x1C01 8000 (SCT0) and 0x1C01 C000
(SCT1)) …continued
Name
Access Address Description
offset
Reset value Reference
EV11_STATE
R/W
0x358
SCT event state register 11
0x0000 0000 Table 228
EV11_CTRL
R/W
0x35C
SCT event control register 11
0x0000 0000 Table 229
EV12_STATE
R/W
0x360
SCT event state register 12
0x0000 0000 Table 228
EV12_CTRL
R/W
0x364
SCT event control register 12
0x0000 0000 Table 229
EV13_STATE
R/W
0x368
SCT event state register 13
0x0000 0000 Table 228
EV13_CTRL
R/W
0x36C
SCT event control register 13
0x0000 0000 Table 229
EV14_STATE
R/W
0x370
SCT event state register 14
0x0000 0000 Table 228
EV14_CTRL
R/W
0x374
SCT event control register 14
0x0000 0000 Table 229
EV15_STATE
R/W
0x378
SCT event state register 15
0x0000 0000 Table 228
EV15_CTRL
R/W
0x37C
SCT event control register 15
0x0000 0000 Table 229
OUT0_SET
R/W
0x500
SCT output 0 set register
0x0000 0000 Table 230
OUT0_CLR
R/W
0x504
SCT output 0 clear register
0x0000 0000 Table 231
OUT1_SET
R/W
0x508
SCT output 1 set register
0x0000 0000 Table 230
OUT1_CLR
R/W
0x50C
SCT output 1 clear register
0x0000 0000 Table 231
OUT2_SET
R/W
0x510
SCT output 2 set register
0x0000 0000 Table 230
OUT2_CLR
R/W
0x514
SCT output 2 clear register
0x0000 0000 Table 231
OUT3_SET
R/W
0x518
SCT output 3 set register
0x0000 0000 Table 230
OUT3_CLR
R/W
0x51C
SCT output 3 clear register
0x0000 0000 Table 231
OUT4_SET
R/W
0x520
SCT output 4 set register
0x0000 0000 Table 230
OUT4_CLR
R/W
0x524
SCT output 4 clear register
0x0000 0000 Table 231
OUT5_SET
R/W
0x528
SCT output 5 set register
0x0000 0000 Table 230
OUT5_CLR
R/W
0x52C
SCT output 5 clear register
0x0000 0000 Table 231
OUT6_SET
R/W
0x530
SCT output 6 set register
0x0000 0000 Table 230
OUT6_CLR
R/W
0x534
SCT output 6 clear register
0x0000 0000 Table 231
OUT7_SET
R/W
0x538
SCT output 7 set register
0x0000 0000 Table 230
OUT7_CLR
R/W
0x53C
SCT output 7 clear register
0x0000 0000 Table 231
OUT8_SET
R/W
0x540
SCT output 8 set register
0x0000 0000 Table 230
OUT8_CLR
R/W
0x544
SCT output 8 clear register
0x0000 0000 Table 231
OUT9_SET
R/W
0x548
SCT output 9 set register
0x0000 0000 Table 230
OUT9_CLR
R/W
0x54C
SCT output 9 clear register
0x0000 0000 Table 231
15.6.1 SCT configuration register
This register configures the overall operation of the SCT. Write to this register before any
other registers.
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Table 202. SCT configuration register (CONFIG, address 0x1C01 8000) bit description
Bit
Symbol
0
UNIFY
2:1
6:3
Value
Description
Reset
value
SCT operation
0
0
The SCT operates as two 16-bit counters named L and H.
1
The SCT operates as a unified 32-bit counter.
CLKMODE
SCT clock mode
00
0x0
System clock. The system clock clocks the SCT and prescalers.
0x1
Prescaled system clock. The SCT clock is the system clock, but the prescalers
are enabled to count only when sampling of the input selected by the CKSEL
field finds the selected edge. The minimum pulse width on the clock input is 1
bus clock period. This mode is the high-performance sampled-clock mode.
0x2
SCT input. The input selected by CKSEL clocks the SCT and prescalers. The
input is synchronized to the system clock and possibly inverted. The minimum
pulse width on the clock input is 1 bus clock period. This mode is the low-power
sampled-clock mode.
0x3
Prescaled SCT input. The SCT and prescalers are clocked by the input edge
selected by the CKSEL field. In this mode, most of the SCT is clocked by the
(selected polarity of the) input. The outputs are switched synchronously to the
input clock. The input clock rate must be at least half the system clock rate and
can be the same or faster than the system clock.
CKSEL
SCT clock select
0x0
Rising edges on input 0.
0x1
Falling edges on input 0.
0x2
Rising edges on input 1.
0x3
Falling edges on input 1.
0x4
Rising edges on input 2.
0x5
Falling edges on input 2.
0x6
Rising edges on input 3.
0x7
Falling edges on input 3.
0x8
Rising edges on input 4.
0x9
Falling edges on input 4.
0xA
Rising edges on input 5.
0xB
Falling edges on input 5.
0xC
Rising edges on input 6.
0xD
Falling edges on input 6.
0xE
Rising edges on input 7.
0xF
Falling edges on input 7.
0000
7
NORELAOD_L
-
A 1 in this bit prevents the lower match and fractional match registers from
being reloaded from their respective reload registers. Software can write to set
or clear this bit at any time. This bit applies to both the higher and lower
registers when the UNIFY bit is set.
0
8
NORELOAD_H
-
A 1 in this bit prevents the higher match and fractional match registers from
being reloaded from their respective reload registers. Software can write to set
or clear this bit at any time. This bit is not used when the UNIFY bit is set.
0
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Table 202. SCT configuration register (CONFIG, address 0x1C01 8000) bit description …continued
Bit
Symbol
Value
Description
Reset
value
16:9
INSYNC
-
Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1
1 in one of these bits subjects the corresponding input to synchronization to the
SCT clock, before it is used to create an event. If an input is synchronous to the
SCT clock, keep its bit 0 for faster response.
When the CKMODE field is 1x, the bit in this field, corresponding to the input
selected by the CKSEL field, is not used.
17
AUTOLIMIT_L
-
A one in this bit causes a match on match register 0 to be treated as a de-facto 0
LIMIT condition without the need to define an associated event.
As with any LIMIT event, this automatic limit causes the counter to be cleared to
zero in uni-directional mode or to change the direction of count in bi-directional
mode.
Software can write to set or clear this bit at any time. This bit applies to both the
higher and lower registers when the UNIFY bit is set.
18
AUTOLIMIT_H
-
A one in this bit will cause a match on match register 0 to be treated as a
de-facto LIMIT condition without the need to define an associated event.
0
As with any LIMIT event, this automatic limit causes the counter to be cleared to
zero in uni-directional mode or to change the direction of count in bi-directional
mode.
Software can write to set or clear this bit at any time. This bit is not used when
the UNIFY bit is set.
31:19
-
Reserved
-
15.6.2 SCT control register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CTRL_L and CTRL_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
All bits in this register can be written to when the counter is stopped or halted. When the
counter is running, the only bits that can be written are STOP or HALT. (Other bits can be
written in a subsequent write after HALT is set to 1.)
Remark: If CLKMODE = 0x3 is selected, wait at least 12 system clock cycles between a
write access to the H, L or unified version of this register and the next write access. This
restriction does not apply when writing to the HALT bit or bits and then writing to the CTRL
register again to restart the counters - for example because software must update the
MATCH register, which is only allowed when the counters are halted.
Remark: If the SCTimer/PWM is operating as two 16-bit counters, events can only modify
the state of the outputs when neither counter is halted. This is true regardless of what
triggered the event.
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Table 203. SCT control register (CTRL, address 0x1C01 8004) bit description
Bit
Symbol
Value Description
Reset
value
0
DOWN_L
-
This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
0
when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the
counter reaches 0 or when the counter is counting down and a limit condition occurs.
1
STOP_L
-
When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events 0
related to the counter can occur. If such an event matches the mask in the Start
register, this bit is cleared and counting resumes.
2
HALT_L
-
When this bit is 1, the L or unified counter does not run and no events related to the
L-counter can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L
bit is cleared. If you want to remove the halt condition and keep the SCT in the stop
condition (not running), then you can change the halt and stop condition with one
single write to this register.
1
Remark: Once set, only software can clear this bit to restore counter operation.
3
CLRCTR_L -
Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
0
4
BIDIR_L
L or unified counter direction select
0
12:5
PRE_L
0
The counter counts up to its limit condition, then is cleared to zero.
1
The counter counts up to its limit, then counts down to a limit condition or to 0.
-
Specifies the factor by which the SCT clock is prescaled to produce the L or unified
counter clock. The counter clock is clocked at the rate of the SCT clock divided by
PRE_L+1.
0
Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.
15:13
-
16
DOWN_H
-
This bit is 1 when the H counter is counting down. Hardware sets this bit when the
counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter
reaches 0 or when the counter is counting down and a limit condition occurs.
Reserved
17
STOP_H
-
When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to 0
the counter can occur. If such an event matches the mask in the Start register, this
bit is cleared and counting resumes.
18
HALT_H
-
When this bit is 1, the H counter does not run and no events related to the H counter 1
can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is
cleared. If you want to remove the halt condition and keep the SCT in the stop
condition (not running), then you can change the halt and stop condition with one
single write to this register.
0
Remark: Once set, this bit can only be cleared by software to restore counter
operation.
19
CLRCTR_H -
Writing a 1 to this bit clears the H counter. This bit always reads as 0.
0
20
BIDIR_H
Direction select
0
28:21
PRE_H
0
The H counter counts up to its limit condition, then is cleared to zero.
1
The H counter counts up to its limit, then counts down to a limit condition or to 0.
-
Specifies the factor by which the SCT clock is prescaled to produce the H counter
0
clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1.
Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.
31:29
-
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15.6.3 SCT limit register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
LIMIT_L and LIMIT_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
The bits in this register set which events act as counter limits. After a counter has reached
its limit, the counter is cleared to zero in unidirectional mode or changes its direction of
count in bidirectional mode. When the counter reaches all ones, this state is always
treated as a limit event, and the counter is cleared in unidirectional mode or, in
bidirectional mode, begins counting down on the next clock edge - even if no limit event as
defined by the SCT limit register has occurred.
In addition to using this register to specify events that serve as limits, it is also possible to
automatically cause a limit condition whenever a match register 0 match occurs. This
eliminates the need to define an event for the sole purpose of creating a limit. The
AUTOLIMIT_L and AUTOLIMIT_H bits in the configuration register enable/disable this
feature (see Table 202).
Table 204. SCT limit register (LIMIT, address 0x1C01 8008) bit description
Bit
Symbol
Description
Reset
value
15:0
LIMMSK_L
If bit n is one, event n is used as a counter limit event for the 0
L or unified counter (event 0 = bit 0, event 1 = bit 1, event
15 = bit 15).
31:16
LIMMSK_H
If bit n is one, event n is used as a counter limit event for the 0
H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit
31).
15.6.4 SCT halt condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
HALT_L and HALT_H. Both the L and H registers can be read or written individually or in a
single 32-bit read or write operation.
Remark: Any event halting the counter disables its operation until software clears the
HALT bit (or bits) in the CTRL register (Table 203).
Table 205. SCT halt condition register (HALT, address 0x1C01 800C) bit description
Bit
Symbol
Description
Reset
value
15:0
HALTMSK_L
If bit n is one, event n sets the HALT_L bit in the CTRL register 0
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
31:16 HALTMSK_H
If bit n is one, event n sets the HALT_H bit in the CTRL register 0
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
15.6.5 SCT stop condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
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If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
STOP_L and STOP_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
Table 206. SCT stop condition register (STOP, address 0x1C01 8010) bit description
Bit
Symbol
Description
Reset
value
15:0
STOPMSK_L
If bit n is one, event n sets the STOP_L bit in the CTRL register
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
0
31:16 STOPMSK_H
If bit n is one, event n sets the STOP_H bit in the CTRL register 0
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
15.6.6 SCT start condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
START_L and START_H. Both the L and H registers can be read or written individually or
in a single 32-bit read or write operation.
The bits in this register select which events, if any, clear the STOP bit in the Control
register. (Since no events can occur when HALT is 1, only software can clear the HALT bit
by writing the Control register.)
Table 207. SCT start condition register (START, address 0x1C01 8014) bit description
Bit
Symbol
Description
Reset
value
15:0
STARTMSK_L
If bit n is one, event n clears the STOP_L bit in the CTRL
register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
0
If bit n is one, event n clears the STOP_H bit in the CTRL
register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
0
31:16 STARTMSK_H
15.6.7 SCT dither condition register
If UNIFY = 1 in the CONFIG register, only the L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
DITHER_L and DITHER_H. Both the L and H registers can be read or written individually
or in a single 32-bit read or write operation.
When the Dither Condition register contains all zeroes (the default value), the dither
engine advances to the next count in the dither pattern every time the SCT counter
reaches zero (i.e. at the start of every new SCT counter cycle).
It is possible, using this register, to alter that behavior by qualifying the advancement
through the dither pattern with designated events. As with the other condition/mask
registers (HALT, STOP, LIMIT, etc.) each bit in this register corresponds to an event.
Setting one or more of the bits in this register to ones will cause the dither engine to
advance to the next element in the dither pattern (i.e. increment the 16-state cycle
counter) only following SCT counter cycles during which one or more of the designated
dither events have occurred.
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There is one, global Dither Condition register per 16-bit SCT. This register controls
advancement through the dither patterns for all of the match registers associated with that
half of the SCT.
For details on the dither engine and the dither pattern, see Section 15.7.9.1.
Table 208. SCT dither condition register (DITHER, address 0x1C01 8018) bit description
Bit
Symbol
Description
Reset
value
15:0
DITHMSK_L
If bit n is one, the event n causes the dither engine to advance 0
to the next element in the dither pattern at the start of the next
counter cycle of the 16-bit low counter or the unified counter
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are
set to 0, the dither pattern automatically advances at the start
of every new counter cycle.
31:16 DITHMSK_H
If bit n is one, the event n causes the dither engine to advance 0
to the next element in the dither pattern at the start of the next
counter cycle of the 16-bit high counter (event 0 = bit 0, event 1
= bit 1, event 15 = bit 15). If all bits are set to 0, the dither
pattern automatically advances at the start of every new
counter cycle.
15.6.8 SCT counter register
If UNIFY = 1 in the CONFIG register, the counter is a unified 32-bit register and both the
_L and _H bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
COUNT_L and COUNT_H. Both the L and H registers can be read or written individually
or in a single 32-bit read or write operation. In this case, the L and H registers count
independently under the control of the other registers.
Writing to the COUNT_L, COUNT_H, or unified register is only allowed when the
corresponding counter is halted (HALT bits are set to 1 in the CTRL register). Software
can read the counter registers at any time.
Table 209. SCT counter register (COUNT, address 0x1C01 8040) bit description
Bit
Symbol
Description
Reset
value
15:0
CTR_L
When UNIFY = 0, read or write the 16-bit L counter value. When
UNIFY = 1, read or write the lower 16 bits of the 32-bit unified
counter.
0
31:16
CTR_H
When UNIFY = 0, read or write the 16-bit H counter value. When
UNIFY = 1, read or write the upper 16 bits of the 32-bit unified
counter.
0
15.6.9 SCT state register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
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If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
STATE_L and STATE_H. Both the L and H registers can be read or written individually or
in a single 32-bit read or write operation.
Software can read the state associated with a counter at any time. Writing to the
STATE_L, STATE_H, or unified register is only allowed when the corresponding counter is
halted (HALT bits are set to 1 in the CTRL register).
The state variable is the main feature that distinguishes the SCT from other counter/timer/
PWM blocks. Events can be made to occur only in certain states. Events, in turn, can
perform the following actions:
•
•
•
•
set and clear outputs
limit, stop, and start the counter
cause interrupts and DMA requests
modify the state variable
The value of a state variable is completely under the control of the application. If an
application does not use states, the value of the state variable remains zero, which is the
default value.
A state variable can be used to track and control multiple cycles of the associated counter
in any desired operational sequence. The state variable is logically associated with a state
machine diagram which represents the SCT configuration. See Section 15.6.26 and
15.6.27 for more about the relationship between states and events.
The STATELD/STADEV fields in the event control registers of all defined events set all
possible values for the state variable. The change of the state variable during multiple
counter cycles reflects how the associated state machine moves from one state to the
next.
Table 210. SCT state register (STATE, address 0x1C01 8044) bit description
Bit
Symbol
Description
Reset
value
4:0
STATE_L
State variable.
0
15:5
-
Reserved.
0
20:16
STATE_H
State variable.
31:21
-
Reserved.
15.6.10 SCT input register
Software can read the state of the SCT inputs in this read-only register in slightly different
forms.
1. The AIN bit represents the input sampled by the SCT clock. This corresponds to a
nearly direct read-out of the input but can cause spurious fluctuations in case of an
asynchronous input signal.
2. The SIN bit represents the input sampled by the SCT clock after the INSYNC select
(this signal is also used for event generation):
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– If the INSYNC bit is set for the input, the input is synchronized to the SCT clock
using three SCT clock cycles resulting in a stable signal that is delayed by three
SCT clock cycles.
– If the INSYNC bit is not set, the SIN bit value is the same as the AIN bit value.
Table 211. SCT input register (INPUT, address 0x1C01 8048) bit description
Bit
Symbol
Description
Reset
value
0
AIN0
Input 0 state.Direct read.
-
1
AIN1
Input 1 state. Direct read.
-
2
AIN2
Input 2 state. Direct read.
-
3
AIN3
Input 3 state. Direct read.
-
4
AIN4
Input 4 state. Direct read.
-
5
AIN5
Input 5 state. Direct read.
-
6
AIN6
Input 6 state. Direct read.
-
7
AIN7
Input 7 state.Direct read.
-
15:8
-
Reserved.
-
16
SIN0
Input 0 state.
-
17
SIN1
Input 1 state.
-
18
SIN2
Input 2 state.
-
19
SIN3
Input 3 state.
-
20
SIN4
Input 4 state.
-
21
SIN5
Input 5 state.
-
22
SIN6
Input 6 state.
-
23
SIN7
Input 7 state.
-
31:24
-
Reserved
-
15.6.11 SCT match/capture registers mode register
If UNIFY = 1 in the CONFIG register, only the _L bits of this register are used. The L bits
control whether each set of match/capture registers operates as unified 32-bit
capture/match registers.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
REGMODE_L and REGMODE_H. Both the L and H registers can be read or written
individually or in a single 32-bit read or write operation. The _L bits/registers control the L
match/capture registers, and the _H bits/registers control the H match/capture registers.
The SCT contains 16 Match/Capture register pairs. The Register Mode register selects
whether each register pair acts as a Match register (see Section 15.6.20) or as a Capture
register (see Section 15.6.22). Each Match/Capture register has an accompanying
register which serves as a Reload register when the register is used as a Match register
(Section 15.6.23) or as a Capture-Control register when the register is used as a capture
register (Section 15.6.25). REGMODE_H is used only when the UNIFY bit is 0.
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Table 212. SCT match/capture registers mode register (REGMODE, address 0x1C01 804C)
bit description
Bit
Symbol
Description
Reset
value
15:0
REGMOD_L
Each bit controls one pair of match/capture registers (register 0 =
bit 0, register 1 = bit 1,..., register 15 = bit 15).
0
0 = registers operate as match registers.
1 = registers operate as capture registers.
31:16 REGMOD_H
Each bit controls one pair of match/capture registers (register 0 =
bit 16, register 1 = bit 17,..., register 15 = bit 31).
0
0 = registers operate as match registers.
1 = registers operate as capture registers.
15.6.12 SCT output register
The SCT supports 10 outputs, each of which has a corresponding bit in this register.
Software can write to any of the output registers when both counters are halted to control
the outputs directly. Writing to the OUT register is only allowed when all counters
(L-counter, H-counter, and unified counter) are halted (HALT bits are set to 1 in the CTRL
register).
Software can read this register at any time to sense the state of the outputs.
Table 213. SCT output register (OUTPUT, address 0x1C01 8050) bit description
Bit
Symbol
Description
Reset
value
9:0
OUT
Writing a 1 to bit n makes the corresponding output HIGH. 0 makes 0
the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,...,
output 9 = bit 9).
31:10
-
Reserved
15.6.13 SCT bidirectional output control register
This register specifies (for each output) the impact of the counting direction on the
meaning of set and clear operations on the output (see Section 15.6.28 and
Section 15.6.29).
Table 214. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x1C01 8054) bit description
Bit
Symbol
1:0
SETCLR0
3:2
Value Description
Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR1
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Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
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Table 214. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x1C01 8054) bit description
Bit
Symbol
5:4
SETCLR2
7:6
9:8
11:
10
13:
12
15:
14
17:
16
19:
18
Value Description
Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR3
Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR4
Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR5
Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR6
Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR7
Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR8
Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR9
31:2 0
Reset
value
Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0
0
0
0
0
0
0
0
Reserved.
15.6.14 SCT conflict resolution register
The registers OUTn_SET (Section 15.6.28) and OUTn_CLR (Section 15.6.29) allow both
setting and clearing to be indicated for an output in the same clock cycle, even for the
same event. This SCT conflict resolution register resolves this conflict.
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To enable an event to toggle an output, set the OnRES value to 0x3 in this register, and
set the event bits in both the Set and Clear registers.
Table 215. SCT conflict resolution register (RES, address 0x1C01 8058) bit description
Bit
Symbol
1:0
O0RES
3:2
Value Description
Effect of simultaneous set and clear on output 0.
0x0
No change.
0x1
Set output (or clear based on the SETCLR0 field).
0x2
Clear output (or set based on the SETCLR0 field).
0x3
Toggle output.
O1RES
7:6
Set output (or clear based on the SETCLR1 field).
0x2
Clear output (or set based on the SETCLR1 field).
0x3
Toggle output.
O2RES
11:
10
13:
12
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0
No change.
0x1
Effect of simultaneous set and clear on output 2.
0
0x0
No change.
0x1
Set output (or clear based on the SETCLR2 field).
0x2
Clear output n (or set based on the SETCLR2 field).
0x3
Toggle output.
O3RES
Effect of simultaneous set and clear on output 3.
0x0
No change.
0x1
Set output (or clear based on the SETCLR3 field).
0x2
Clear output (or set based on the SETCLR3 field).
0x3
9:8
0
Effect of simultaneous set and clear on output 1.
0x0
5:4
Reset
value
O4RES
Toggle output.
Effect of simultaneous set and clear on output 4.
0x0
No change.
0x1
Set output (or clear based on the SETCLR4 field).
0x2
Clear output (or set based on the SETCLR4 field).
0x3
Toggle output.
O5RES
Effect of simultaneous set and clear on output 5.
0x0
0
0
No change.
0x1
Set output (or clear based on the SETCLR5 field).
0x2
Clear output (or set based on the SETCLR5 field).
0x3
Toggle output.
O6RES
0
Effect of simultaneous set and clear on output 6.
0x0
No change.
0x1
Set output (or clear based on the SETCLR6 field).
0x2
Clear output (or set based on the SETCLR6 field).
0x3
Toggle output.
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Table 215. SCT conflict resolution register (RES, address 0x1C01 8058) bit description
Bit
Symbol
15:
14
O7RES
17:
16
Value Description
Effect of simultaneous set and clear on output 7.
0x0
No change.
0x1
Set output (or clear based on the SETCLR7 field).
0x2
Clear output (or set based on the SETCLR7 field).
0x3
Toggle output.
O8RES
0
Effect of simultaneous set and clear on output 8.
0x0
No change.
0x1
Set output (or clear based on the SETCLR8 field).
0x2
Clear output (or set based on the SETCLR8 field).
0x3
19:
18
Reset
value
O9RES
0
Toggle output.
Effect of simultaneous set and clear on output 9.
0x0
No change.
0x1
Set output (or clear based on the SETCLR9 field).
0x2
Clear output (or set based on the SETCLR9 field).
0x3
Toggle output.
31:2 0
0
Reserved.
15.6.15 SCT DMA request 0 and 1 registers
The SCT includes two DMA request outputs. These registers enable the DMA requests to
be triggered when a particular event occurs or when counter Match registers are loaded
from its Reload registers.
Table 216. SCT DMA 0 request register (DMAREQ0, address 0x1C01 805C) bit description
Bit
Symbol
Description
Reset
value
15:0
DEV_0
If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 0
1 = bit 1,..., event 15 = bit 15).
29:16
-
Reserved
30
DRL0
A 1 in this bit makes the SCT set DMA request 0 when it loads
the Match_L/Unified registers from the Reload_L/Unified
registers.
31
DRQ0
This read-only bit indicates the state of DMA Request 0
-
Table 217. SCT DMA 1 request register (DMAREQ1, address 0x1C01 8060) bit description
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Bit
Symbol
Description
15:0
DEV_1
If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 0
1 = bit 1,..., event 15 = bit 15).
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Table 217. SCT DMA 1 request register (DMAREQ1, address 0x1C01 8060) bit description
Bit
Symbol
Description
Reset
value
29:16
-
Reserved
-
30
DRL1
A 1 in this bit makes the SCT set DMA request 1 when it loads
the Match L/Unified registers from the Reload L/Unified
registers.
31
DRQ1
This read-only bit indicates the state of DMA Request 1.
15.6.16 SCT flag enable register
This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag
register (Section 15.6.17) is also set.
Table 218. SCT flag enable register (EVEN, address 0x1C01 80F0) bit description
Bit
Symbol
Description
Reset
value
15:0
IEN
The SCT requests interrupt when bit n of this register and the event 0
flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event
15 = bit 15).
31:16
-
Reserved
15.6.17 SCT event flag register
This register records events. Writing ones to this register clears the corresponding flags
and negates the SCT interrupt request if all enabled Flag bits are zero.
Table 219. SCT event flag register (EVFLAG, address 0x1C01 80F4) bit description
Bit
Symbol
Description
Reset
value
15:0 FLAG
Bit n is one if event n has occurred since reset or a 1 was last written to
this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
0
31:
16
Reserved
-
-
15.6.18 SCT conflict enable register
This register enables the “no change conflict” events specified in the SCT conflict
resolution register to request an interrupt.
Table 220. SCT conflict enable register (CONEN, address 0x1C01 80F8) bit description
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Bit
Symbol
Description
9:0
NCEN
The SCT requests interrupt when bit n of this register and the SCT 0
conflict flag register are both one (output 0 = bit 0, output 1 = bit
1,..., output 9 = bit 9).
31:10
-
Reserved
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15.6.19 SCT conflict flag register
This register records interrupt-enabled no-change conflict events and provides details of a
bus error. Writing ones to the NCFLAG bits clears the corresponding read bits and
negates the SCT interrupt request if all enabled Flag bits are zero.
Table 221. SCT conflict flag register (CONFLAG, address 0x1C01 80FC) bit description
Bit
Symbol
Description
Reset
value
9:0
NCFLAG
Bit n is one if a no-change conflict event occurred on output n
since reset or a 1 was last written to this bit (output 0 = bit 0,
output 1 = bit 1,..., output 9 = bit 9).
0
29:10
-
Reserved.
-
30
BUSERRL
The most recent bus error from this SCT involved writing CTR
L/Unified, STATE L/Unified, MATCH L/Unified, or the Output
register when the L/U counter was not halted. A word write to
certain L and H registers can be half successful and half
unsuccessful.
0
31
BUSERRH
The most recent bus error from this SCT involved writing CTR
H, STATE H, MATCH H, or the Output register when the H
counter was not halted.
0
15.6.20 SCT match registers 0 to 15 (REGMODEn bit = 0)
Match registers are compared to the counters to help create events. When the UNIFY bit
is 0, the L and H registers are independently compared to the L and H counters. When
UNIFY is 1, the L and H registers hold a 32-bit value that is compared to the unified
counter. A Match can only occur in a clock in which the counter is running (STOP and
HALT are both 0).
Match registers can be read at any time. Writing to the MATCH_L, MATCH_H, or unified
register is only allowed when the corresponding counter is halted (HALT bits are set to 1 in
the CTRL register). Match events occur in the SCT clock in which the counter is (or would
be) incremented to the next value. When a Match event limits its counter as described in
Section 15.6.3, the value in the Match register is the last value of the counter before it is
cleared to zero (or decremented if BIDIR is 1).
There is no “write-through” from Reload registers to Match registers. Before starting a
counter, software can write one value to the Match register used in the first cycle of the
counter and a different value to the corresponding Match Reload register used in the
second cycle.
Table 222. SCT match registers 0 to 15 (MATCH[0:15], address 0x1C01 8100 (MATCH0) to
0x1C01 813C (MATCH15)) bit description (REGMODEn bit = 0)
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Bit
Symbol
Description
15:0
MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to
the L counter. When UNIFY = 1, read or write the lower 16 bits of
the 32-bit value to be compared to the unified counter.
0
31:16
MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to
the H counter. When UNIFY = 1, read or write the upper 16 bits of
the 32-bit value to be compared to the unified counter.
0
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15.6.21 SCT fractional match registers 0 to 5
Fractional Match registers are provided for up to the first six of the match registers. The
values programmed in these registers provide higher average resolution over time by
applying a dither pattern as described in Section 15.7.9.1. This dither pattern results in
delaying recognition of a match for one counter clock for n (0 to 15) out of every 16
counter cycles. The value of n is programmed in these Fractional Match registers.
Fractional Match registers can be read at any time. Writing to the FRACMAT_L,
FRACMAT_H, or unified register is only allowed when the corresponding counter is halted
(HALT bits are set to 1 in the CTRL register).
Each Fractional Match register has a Fractional Match Reload register associated with it.
The contents of the reload registers are transferred into the Fractional Match registers at
the start of every new SCT counter cycle unless the NORELOAD bit for the appropriate
half-counter is set.
The reload registers may be written to at any time, regardless of whether or not the
counter is running.
There is no write-through from the Fractional Match Reload registers to the Fractional
Match registers. Before starting a counter, software can write one value to the Fractional
Match register that will be used in the first cycle or period of operation, and a different
value to the corresponding Fractional Match Reload register that will be used in the
second cycle or period.
Table 223. SCT fractional match registers 0 to 5 (FRACMAT[0:5], address 0x1C01 8140
(FRACMAT0) to 0x1C01 8154 (FRACMAT5)) bit description
Bit
Symbol
Description
Reset
value
3:0
FRACMAT_L
When UNIFY = 0, read or write the 4-bit value specifying the
dither pattern to be applied to the corresponding MATCHn_L
register (n = 0 to 5). When UNIFY = 1, the value applies to the
unified, 32-bit fractional match register.
0
15:4
-
Reserved.
-
19:16
FRACMAT_H
When UNIFY = 0, read or write 4-bit value specifying the dither
pattern to be applied to the corresponding MATCHn_H register
(n = 0 to 5).
0
31:20
-
Reserved.
-
[1]
See Section 15.7.9.1 for selecting the dither pattern.
15.6.22 SCT capture registers 0 to 15 (REGMODEn bit = 1)
These registers allow software to read the counter values at which the event selected by
the corresponding Capture Control registers occurred.
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Table 224. SCT capture registers 0 to 15 (CAP[0:15], address 0x1C01 8100 (CAP0) to 0x1C01
813C (CAP15)) bit description (REGMODEn bit = 1)
Bit
Symbol
Description
Reset
value
15:0
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this
0
register was last captured. When UNIFY = 1, read the lower 16 bits
of the 32-bit value at which this register was last captured.
31:16
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this
0
register was last captured. When UNIFY = 1, read the upper 16 bits
of the 32-bit value at which this register was last captured.
15.6.23 SCT match reload registers 0 to 15 (REGMODEn bit = 0)
A Match register (L, H, or unified 32-bit) is loaded from the corresponding Reload register
when BIDIR is 0 and the counter reaches its limit condition, or when BIDIR is 1 and the
counter reaches 0.
Table 225. SCT match reload registers 0 to 15 (MATCHREL[0:15], address 0x1C01 8200
(MATCHREL0) to 0x1C01 823C (MATCHREL15) bit description (REGMODEn bit =
0)
Bit
Symbol
Description
Reset
value
15:0
RELOADn_L When UNIFY = 0, read or write the 16-bit value to be loaded into
the MATCHn_L register. When UNIFY = 1, read or write the lower
16 bits of the 32-bit value to be loaded into the MATCHn register.
0
31:16 RELOADn_H When UNIFY = 0, read or write the 16-bit to be loaded into the
MATCHn_H register. When UNIFY = 1, read or write the upper 16
bits of the 32-bit value to be loaded into the MATCHn register.
0
15.6.24 SCT fractional match reload registers 0 to 5
A Fractional Match register (L, H, or unified 32-bit) is loaded from the corresponding
Fractional Match Reload register when BIDIR is 0 and the counter reaches its limit
condition, or BIDIR is 1 and the counter reaches 0, unless the appropriate NORELOAD bit
is set.
Table 226. SCT fractional match reload registers 0 to 5 (FRACMATREL[0:5], address 0x1C01
8240 (FRACMATREL0) to 0x1C01 8254 (FRACMATREL5) bit description
Bit
Symbol
Description
Reset
value
3:0
RELFRAC_L When UNIFY = 0, read or write the 4-bit value to be loaded into the 0
FRACMATn_L register. When UNIFY = 1, read or write the lower 4
bits to be loaded into the FRACMATn register.
15:4
-
Reserved.
-
19:16 RELFRAC_H When UNIFY = 0, read or write the 4-bit value to be loaded into the 0
FRACMATn_H register. When UNIFY = 1, read or write the upper 4
bits with the 4-bit value to be loaded into the FRACMATn register.
31:20 -
Reserved.
-
15.6.25 SCT capture control registers 0 to 15 (REGMODEn bit = 1)
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
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If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CAPCTRLn_L and CAPCTRLn_H. Both the L and H registers can be read or written
individually or in a single 32-bit read or write operation.
Each Capture Control register (L, H, or unified 32-bit) controls which events load the
corresponding Capture register from the counter.
Table 227. SCT capture control registers 0 to 15 (CAPCTRL[0:15], address 0x1C01 8200
(CAPCTRL0) to 0x1C01 823C (CAPCTRL15)) bit description (REGMODEn bit = 1)
Bit
Symbol
Description
Reset
value
15:0
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the 0
CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1
= bit 1,..., event 15 = bit 15).
31:16
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0)
0
register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event
15 = bit 31).
15.6.26 SCT event state mask registers 0 to 15
Each event has one associated SCT event state mask register that allows this event to
happen in one or more states of the counter selected by the HEVENT bit in the
corresponding EVCTRLn register.
An event n is disabled when its EVn_STATE register contains all zeros, since it is masked
regardless of the current state.
In simple applications that do not use states, write 0x01 to this register to enable an event.
Since the state always remains at its reset value of 0, writing 0x01 effectively permanently
state-enables this event.
Table 228. SCT event state mask registers 0 to 15 (EV[0:15]_STATE, addresses 0x1C01 8300
(EV0_STATE) to 0x1C01 8378 (EV15_STATE) (SCT0) and 0x1C01 C300
(EV0_STATE) to 0x1C01 C378 (EV15_STATE) (SCT1)) bit description
Bit
Symbol
Description
Reset
value
15:0
STATEMSKn
If bit m is one, event n (n= 0 to 15) happens in state m of the
counter selected by the HEVENT bit (m = state number; state 0
= bit 0, state 1= bit 1,..., state 15 = bit 15).
0
31:16
-
Reserved.
-
15.6.27 SCT event control registers 0 to 15
This register defines the conditions for event n to occur, other than the state variable
which is defined by the state mask register. Most events are associated with a particular
counter (high, low, or unified), in which case the event can depend on a match to that
register. The other possible ingredient of an event is a selected input or output signal.
When the UNIFY bit is 0, each event is associated with a particular counter by the
HEVENT bit in its event control register. An event cannot occur when its related counter is
halted nor when the current state is not enabled to cause the event as specified in its
event mask register. An event is permanently disabled when its event state mask register
contains all zeros.
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An enabled event can be programmed to occur based on a selected input or output edge
or level and/or based on its counter value matching a selected match register. In BIDR
mode, events can also be enabled based on the count direction.
Each event can modify its counter STATE value. If more than one event associated with
the same counter occurs in a given clock cycle, only the state change specified for the
highest-numbered event among them takes place. Other actions dictated by any
simultaneously occurring events all take place.
Table 229. SCT event control register 0 to 15 (EV[0:15]_CTRL, address 0x1C01 8304 (EV0_CTRL) to 0x1C01 837C
(EV15_CTRL) (SCT0) and EV[0:15]_CTRL, address 0x1C01 C304 (EV0_CTRL) to 0x1C01 C37C
(EV15_CTRL) (SCT1)) bit description
Bit
Symbol
Value Description
3:0
MATCHSEL
-
4
HEVENT
5
9:6
0
Selects the L state and the L match register selected by MATCHSEL.
1
Selects the H state and the H match register selected by MATCHSEL.
Input/output select
1
Selects the output selected by IOSEL.
-
Selects the input or output signal number associated with this event (if any). Do not
select an input in this register, if CKMODE is 1x. In this case the clock input is an
implicit ingredient of every event.
0
Selects the I/O condition for event n. (The detection of edges on outputs lags the
conditions that switch the outputs by one SCT clock). In order to guarantee proper
edge/state detection, an input must have a minimum pulse width of at least one SCT
clock period .
0
0x0
LOW
0x1
Rise
0x2
Fall
0x3
HIGH
Selects how the specified match and I/O condition are used and combined.
0x0
User manual
0
OR. The event occurs when either the specified match or I/O condition occurs.
0x1
MATCH. Uses the specified match only.
0x2
IO. Uses the specified I/O condition only.
0x3
AND. The event occurs when the specified match and I/O condition occur
simultaneously.
STATELD
UM10736
0
Selects the input selected by IOSEL.
13:12 COMBMODE
19:15 STATEV
0
0
11:10 IOCOND
14
Selects the Match register associated with this event (if any). A match can occur only 0
when the counter selected by the HEVENT bit is running.
Select L/H counter. Do not set this bit if UNIFY = 1.
OUTSEL
IOSEL
Reset
value
This bit controls how the STATEV value modifies the state selected by HEVENT when 0
this event is the highest-numbered event occurring for that state.
0
STATEV value is added into STATE (the carry-out is ignored).
1
STATEV value is loaded into STATE.
This value is loaded into or added to the state selected by HEVENT, depending on
STATELD, when this event is the highest-numbered event occurring for that state. If
STATELD and STATEV are both zero, there is no change to the STATE value.
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Table 229. SCT event control register 0 to 15 (EV[0:15]_CTRL, address 0x1C01 8304 (EV0_CTRL) to 0x1C01 837C
(EV15_CTRL) (SCT0) and EV[0:15]_CTRL, address 0x1C01 C304 (EV0_CTRL) to 0x1C01 C37C
(EV15_CTRL) (SCT1)) bit description
Bit
Symbol
20
MATCHMEM
Value Description
Reset
value
If this bit is one and the COMBMODE field specifies a match component to the
triggering of this event, then a match is considered to be active whenever the counter
value is GREATER THAN OR EQUAL TO the value specified in the match register
when counting up, LESS THEN OR EQUAL TO the match value when counting down.
If this bit is zero, a match is only be active during the cycle when the counter is equal
to the match value.
22:21 DIRECTION
Direction qualifier for event generation. This field only applies when the counters are
operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is
reserved.
0x0
Direction independent. This event is triggered regardless of the count direction.
0x1
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2
Counting down. This event is triggered only during down-counting when BIDIR = 1.
31:23 -
Reserved
15.6.28 SCT output set registers 0 to 9
Each output n has one set register that controls how events affect each output. Whether
outputs are set or cleared depends on the setting of the SETCLRn field in the
OUTPUTDIRCTRL register.
Remark: If the SCTimer/PWM is operating as two 16-bit counters, events can only modify
the state of the outputs when neither counter is halted. This is true regardless of what
triggered the event.
Table 230. SCT output set register 0 to 9 (OUT[0:9]_SET, address 0x1C01 8500 (OUT0_SET)
to 0x1C01 8548 (OUT9_SET) (SCT0) and 0x1C01 C500 (OUT0_SET) to 0x1C01
C548 (OUT9_SET) (SCT1) ) bit description
Bit
Symbol
Description
Reset
value
15:0
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
31:16
-
Reserved
15.6.29 SCT output clear registers 0 to 9
Each output n has one clear register that controls how events affect each output. Whether
outputs are set or cleared depends on the setting of the SETCLRn field in the
OUTPUTDIRCTRL register.
Remark: If the SCTimer/PWM is operating as two 16-bit counters, events can only modify
the state of the outputs when neither counter is halted. This is true regardless of what
triggered the event.
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Table 231. SCT output clear register 0 to 9 (OUT[0:9]_CLR, address 0x1C01 8504
(OUT0_CLR) to 0x1C01 854C (OUT9_CLR) (SCT0) and OUT[0:9]_CLR and 0x1C01
8504 (OUT0_CLR) to 0x1C01 854C (OUT9_CLR) (SCT1)) bit description
Bit
Symbol
Description
Reset
value
15:0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
31:16
-
Reserved
15.7 Functional description
15.7.1 Match logic
&RXQWHU+
0DWFK
5HORDG
L+
0DWFK
5HJL+
0DWFKL+
81,)<
0DWFK
5HORDG
L/
0DWFK
5HJL/
0DWFKL/
&RXQWHU/
Fig 34. Match logic
15.7.2 Capture logic
&RXQWHU+
FDSWXUH
FRQWURO
L+
FDSWXUH
UHJL+
VHOHFW
(YHQWV
81,)<
FDSWXUH
FRQWURO
L/
VHOHFW
6&7FORFN
FDSWXUH
UHJL/
&RXQWHU/
Fig 35. Capture logic
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
15.7.3 Event selection
State variables allow control of the SCT across more than one cycle of the counter.
Counter matches, input/output edges, and state values are combined into a set of
general-purpose events that can switch outputs, request interrupts, and change state
values.
+PDWFKHV
VHOHFW
/PDWFKHV
0$7&+6(/L
LQSXWV
RXWSXWV
HYHQW³L´
VHOHFW
,26(/L
2876(/L
,2&21'L
&20%02'(L
67$7(0$6.L
VHOHFW
+67$7(
/67$7(
+(9(17L
Fig 36. Event selection
15.7.4 Output generation
Figure 37 shows one output slice of the SCT.
(YHQWV
6HW
UHJLVWHU³L´
&OHDU
UHJLVWHU³L´
1R&KDQJH&RQIOLFW³L´
6(7&/5L
2L5(6
6HOHFW
287
UHJ
2XWSXW³L´
6&7FORFN
Fig 37. Output slice i
15.7.5 State logic
The SCT can be configured as a timer/counter with multiple programmable states. The
states are user-defined through the events that can be captured in each particular state. In
a multi-state SCT. the SCT can change from one state to another state when a
user-defined event triggers a state change. The state change is set up through each
event’s EV_CTRL register in one of the following ways:
• The event can increment the current state number by a new value.
• The event can write a new state value.
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If an event increments the state number beyond the number of available states, the SCT
enters a locked state in which all further events are ignored while the counter is still
running. Software must interfere to change out of this state.
Software can capture the counter value (and potentially create an interrupt and write to all
outputs) when the event moving the SCT into a locked state occurs. Later, while the SCT
is in the locked state, software can read the counter again to record the time passed since
the locking event and can also read the state variable to obtain the current state number
If the SCT registers an event that forces an abort, putting the SCT in a locked state can be
a safe way to record the time that has passed since the abort event while no new events
are allowed to occur. Since multiple states (any state number between the maximum
implemented state and 31) are locked states, multiple abort or error events can be defined
each incrementing the state number by a different value. Also see Section 15.3.5.1 “Abort
function”.
15.7.6 Interrupt generation
The SCT generates one interrupt to the NVIC.
(YHQWV
(QDEOH
UHJLVWHU
)ODJV
UHJLVWHU
1R&KDQJH
&RQIOLFW &RQIOLFWHYHQWV
(QDEOH
UHJLVWHU
6&7LQWHUUXSW
&RQIOLFW
)ODJV
UHJLVWHU
Fig 38. SCT interrupt generation
15.7.7 Clearing the prescaler
When enabled by a non-zero PRE field in the Control register, the prescaler acts as a
clock divider for the counter, like a fractional part of the counter value. The prescaler is
cleared whenever the counter is cleared or loaded for any of the following reasons:
•
•
•
•
Hardware reset
Software writing to the counter register
Software writing a 1 to the CLRCTR bit in the control register
an event selected by a 1 in the counter limit register when BIDIR = 0
When BIDIR is 0, a limit event caused by an I/O signal can clear a non-zero prescaler.
However, a limit event caused by a Match only clears a non-zero prescaler in one special
case as described Section 15.7.8.
A limit event when BIDIR is 1 does not clear the prescaler. Rather it clears the DOWN bit
in the Control register, and decrements the counter on the same clock if the counter is
enabled in that clock.
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15.7.8 Match vs. I/O events
Counter operation is complicated by the prescaler and by clock mode 01 in which the SCT
clock is the bus clock. However, the prescaler and counter are enabled to count only when
a selected edge is detected on a clock input.
• The prescaler is enabled when the clock mode is not 01, or when the input edge
selected by the CLKSEL field is detected.
• The counter is enabled when the prescaler is enabled, and (PRELIM=0 or the
prescaler is equal to the value in PRELIM).
An I/O component of an event can occur in any SCT clock when its counter HALT bit is 0.
In general, a Match component of an event can only occur in a UT clock when its counter
HALT and STOP bits are both 0 and the counter is enabled.
Table 232 shows when the various kinds of events can occur.
Table 232. Event conditions
COMBMODE IOMODE
Event can occur on clock:
IO
Any
Event can occur whenever HALT = 0 (type A).
MATCH
Any
Event can occur when HALT = 0 and STOP = 0 and the counter is
enabled (type C).
OR
Any
From the IO component: Event can occur whenever HALT = 0 (A).
From the match component: Event can occur when HALT = 0 and
STOP = 0 and the counter is enabled (C).
AND
LOW or HIGH
Event can occur when HALT = 0 and STOP = 0 and the counter is
enabled (C).
AND
RISE or FALL
Event can occur whenever HALT = 0 (A).
15.7.9 Fractional matches
The first 6 match registers may be configured to have a fractional portion to their match
values. Higher average resolution is achievable on the match registers with associated
fractional match register by using a dithering mechanism. The dither engine delays the
assertion of a match by one counter clock every n (0 to 15) out of 16 counter cycles. The
value of n is specified in the 4-bit FRACMAT register associated with each of the first six
match registers.
Dithering can be disabled on any of the match registers by loading all zeroes (the default
value) into its FRACMAT register.
15.7.9.1 Dithering
At the start of each new SCT counter cycle (i.e. when the counter counts-down to zero in
bi-directional mode or is cleared to zero by a limit event), the dither engine determines
which matches are to be delayed by one clock during the coming counter cycle. Delaying
the match effectively adds 1 to the designated match value when up-counting or subtracts
1 when down-counting, during that particular counter cycle.
For each dither-enabled match register, the value programmed in its associated
FRACMAT register specifies how many out of every 16 counter cycles its match is to be
delayed. An algorithm applied to the FRACMAT value distributes this number as evenly as
possible across the 16 counter cycles. This results in a unique dither pattern for each
match register (SeeTable 233).
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Additional control over the dithering process is provided to the user via a Dither Condition
(event-mask) register. Typically, the dither engine advances though the match dither
patterns at the start of every new SCT counter cycle. The Dither Condition register allows
the user to specify that advancement to the next element in the dither patterns will only
occur if one or more designated events occurred during the previous cycle of the counter.
The dither algorithm is designed to spread out the cycles in which the matches are
delayed as evenly as possible across the 16 counter cycles. The following table shows the
dither pattern that is applied for each value of FRACMAT. A ‘D’ indicates the counter
cycles where a match on the relevant match register is delayed.
Table 233. Dither pattern
Counter cycle
FRACMAT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0x0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x1
-
-
-
-
-
-
-
-
D
-
-
-
-
-
-
-
0x2
-
-
-
-
D
-
-
-
-
-
-
-
D
-
-
-
0x3
-
-
-
-
D
-
-
-
D
-
-
-
D
-
-
-
0x4
-
-
D
-
-
-
D
-
-
-
D
-
-
-
D
-
0x5
-
-
D
-
-
-
D
-
D
-
D
-
-
-
D
-
0x6
-
-
D
-
D
-
D
-
-
-
D
-
D
-
D
-
0x7
-
-
D
-
D
-
D
-
D
-
D
-
D
-
D
-
0x8
-
D
-
D
-
D
-
D
-
D
-
D
-
D
-
D
0x9
-
D
-
D
-
D
-
D
D
D
-
D
-
D
-
D
0xA
-
D
-
D
D
D
-
D
-
D
-
D
D
D
-
D
0xB
-
D
-
D
D
D
-
D
D
D
-
D
D
D
-
D
0xC
-
D
D
D
-
D
D
D
-
D
D
D
-
D
D
D
0xD
-
D
D
D
-
D
D
D
D
D
D
D
-
D
D
D
0xE
-
D
D
D
D
D
D
D
-
D
D
D
D
D
D
D
0xF
-
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
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15.7.10 SCT operation
In its simplest, single-state configuration, the SCT operates as an event controlled one- or
bidirectional counter. Events can be configured to be counter match events, an input or
output level, transitions on an input or output pin, or a combination of match and
input/output behavior. In response to an event, the SCT output or outputs can transition,
or the SCT can perform other actions such as creating an interrupt or starting, stopping, or
resetting the counter. Multiple simultaneous actions are allowed for each event.
Furthermore, any number of events can trigger one specific action of the SCT.
An action or multiple actions of the SCT uniquely define an event. A state is defined by
which events are enabled to trigger an SCT action or actions in any stage of the counter.
Events not selected for this state are ignored.
In a multi-state configuration, states change in response to events. A state change is an
additional action that the SCT can perform when the event occurs. When an event is
configured to change the state, the new state defines a new set of events resulting in
different actions of the SCT. Through multiple cycles of the counter, events can change
the state multiple times and thus create a large variety of event controlled transitions on
the SCT outputs and/or interrupts.
Once configured, the SCT can run continuously without software intervention and can
generate multiple output patterns entirely under the control of events.
• To configure the SCT, see Section 15.7.11.
• To start, run, and stop the SCT, see Section 15.7.12.
• To configure the SCT as simple event controlled counter/timer, see Section 15.7.13.
15.7.11 Configure the SCT
To set up the SCT for multiple events and states, perform the following configuration
steps:
15.7.11.1 Configure the counter
1. Configure the L and H counters in the CONFIG register by selecting two independent
16-bit counters (L counter and H counter) or one combined 32-bit counter in the
UNIFY field.
2. Select the SCT clock source in the CONFIG register (fields CLKMODE and CLKSEL)
from any of the inputs or an internal clock.
15.7.11.2 Configure the match and capture registers
1. Select how many match and capture registers the application uses (total of up to 5):
– In the REGMODE register, select for each of the 5 match/capture register pairs
whether the register is used as a match register or capture register.
2. Define match conditions for each match register selected:
– Each match register MATCH sets one match value, if a 32-bit counter is used, or
two match values, if the L and H 16-bit counters are used.
– Each match reload register MATCHRELOAD sets a reload value that is loaded into
the match register when the counter reaches a limit condition or the value 0.
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15.7.11.3 Configure events and event responses
1. Define when each event can occur in the following way in the EVn_CTRL registers
(up to 6, one register per event):
– Select whether the event occurs on an input or output changing, on an input or
output level, a match condition of the counter, or a combination of match and
input/output conditions in field COMBMODE.
– For a match condition:
Select the match register that contains the match condition for the event to occur.
Enter the number of the selected match register in field MATCHSEL.
If using L and H counters, define whether the event occurs on matching the L or
the H counter in field HEVENT.
– For an SCT input or output level or transition:
Select the input number or the output number that is associated with this event in
fields IOSEL and OUTSEL.
Define how the selected input or output triggers the event (edge or level sensitive)
in field IOCOND.
2. Define what the effect of each event is on the SCT outputs in the OUTn_SET or
OUTn_CLR registers (up to 4 outputs, one register per output):
– For each SCT output, select which events set or clear this output. More than one
event can change the output, and each event can change multiple outputs.
3. Define how each event affects the counter:
– Set the corresponding event bit in the LIMIT register for the event to set an upper
limit for the counter.
When a limit event occurs in unidirectional mode, the counter is cleared to zero
and begins counting up on the next clock edge.
When a limit event occurs in bidirectional mode, the counter begins to count down
from the current value on the next clock edge.
– Set the corresponding event bit in the HALT register for the event to halt the
counter. If the counter is halted, it stops counting and no new events can occur.
The counter operation can only be restored by clearing the HALT_L and/or the
HALT_H bits in the CTRL register.
– Set the corresponding event bit in the STOP register for the event to stop the
counter. If the counter is stopped, it stops counting. However, an event that is
configured as a transition on an input/output can restart the counter.
– Set the corresponding event bit in the START register for the event to restart the
counting. Only events that are defined by an input changing can be used to restart
the counter.
4. Define which events contribute to the SCT interrupt:
– Set the corresponding event bit in the EVEN and the EVFLAG registers to enable
the event to contribute to the SCT interrupt.
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15.7.11.4 Configure multiple states
1. In the EVn_STATE register for each event (up to 6 events, one register per event),
select the state or states (up to 2) in which this event is allowed to occur. Each state
can be selected for more than one event.
2. Determine how the event affects the system state:
In the EVn_CTRL registers (up to 6 events, one register per event), set the new state
value in the STATEV field for this event. If the event is the highest numbered in the
current state, this value is either added to the existing state value or replaces the
existing state value, depending on the field STATELD.
Remark: If there are higher numbered events in the current state, this event cannot
change the state.
If the STATEV and STATELD values are set to zero, the state does not change.
15.7.11.5 Miscellaneous options
• There are a certain (selectable) number of capture registers. Each capture register
can be programmed to capture the counter contents when one or more events occur.
• If the counter is in bidirectional mode, the effect of set and clear of an output can be
made to depend on whether the counter is counting up or down by writing to the
OUTPUTDIRCTRL register.
15.7.12 Run the SCT
1. Configure the SCT (see Section 15.7.11 “Configure the SCT”).
2. Write to the STATE register to define the initial state. By default the initial state is state
0.
3. To start the SCT, write to the CTRL register:
– Clear the counters.
– Clear or set the STOP_L and/or STOP_H bits.
Remark: The counter starts counting once the STOP bit is cleared as well. If the
STOP bit is set, the SCT waits instead for an event to occur that is configured to
start the counter.
– For each counter, select unidirectional or bidirectional counting mode (field
BIDIR_L and/or BIDIR_H).
– Select the prescale factor for the counter clock (CTRL register).
– Clear the HALT_L and/or HALT_H bit. By default, the counters are halted and no
events can occur.
4. To stop the counters by software at any time, stop or halt the counter (write to
STOP_L and/or STOP_H bits or HALT_L and/or HALT_H bits in the CTRL register).
– When the counters are stopped, both an event configured to clear the STOP bit or
software writing a zero to the STOP bit can start the counter again.
– When the counter are halted, only a software write to clear the HALT bit can start
the counter again. No events can occur.
– When the counters are halted, software can set any SCT output HIGH or LOW
directly by writing to the OUT register.
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The current state can be read at any time by reading the STATE register.
To change the current state by software (that is independently of any event occurring), set
the HALT bit and write to the STATE register to change the state value. Writing to the
STATE register is only allowed when the counter is halted (the HALT_L and/or HALT_H
bits are set) and no events can occur.
15.7.13 Configure the SCT without using states
The SCT can be used as standard counter/timer with external capture inputs and match
outputs without using the state logic. To operate the SCT without states, configure the
SCT as follows:
• Write zero to the STATE register (zero is the default).
• Write zero to the STATELD and STATEV fields in the EVCTRL registers for each
event.
• Write 0x1 to the EVn_STATE register of each event. Writing 0x1 enables the event.
In effect, the event is allowed to occur in a single state which never changes while the
counter is running.
15.7.14 SCT Example
Figure 39 shows a simple application of the SCT using two sets of match events (EV0/1
and EV3/4) to set/clear SCT output 0. The timer is automatically reset whenever it
reaches the MAT0 match value.
In the initial state 0, match event EV0 sets output 0 to HIGH and match event EV1 clears
output 0. The SCT input 0 is monitored: If input0 is found LOW by the next time the timer
is reset (EV2), the state is changed to state 1, and EV3/4 are enabled, which create the
same output but triggered by different match values. If input 0 is found HIGH by the next
time the timer is reset, the associated event (EV5) causes the state to change back to
state 0where the events EV0 and EV1 are enabled.
The example uses the following SCT configuration:
•
•
•
•
•
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1 input
1 output
5 match registers
6 events and match 0 used with autolimit function
2 states
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
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Fig 39. SCT configuration example
This application of the SCT uses the following configuration (all register values not listed
in Table 234 are set to their default values):
Table 234. SCT configuration example
Configuration
Registers
Setting
Counter
CONFIG
Uses one counter (UNIFY = 1).
CONFIG
Enable the autolimit for MAT0. (AUTOLIMIT = 1).
CTRL
Uses unidirectional counter (BIDIR_L = 0).
Clock base
CONFIG
Uses default values for clock configuration.
Match/Capture registers
REGMODE
Configure one match register for each match event by setting
REGMODE_L bits 0,1, 2, 3, 4 to 0. This is the default.
Define match values
MATCH0/1/2/3/4
Set a match value MATCH0/1/2/3/4_L in each register. The match 0
register serves as an automatic limit event that resets the counter
without using an event. To enable the automatic limit, set the
AUTOLIMIT bit in the CONFIG register.
Define match reload
values
MATCHREL0/1/2/3/4
Set a match reload value RELOAD0/1/2/3/4_L in each register
(same as the match value in this example).
Define when event 0
occurs
EV0_CTRL
Define when event 1
occurs
EV1_CTRL
UM10736
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•
•
Set COMBMODE = 0x1. Event 0 uses match condition only.
•
•
Set COMBMODE = 0x1. Event 1 uses match condition only.
Set MATCHSEL = 1. Select match value of match register 1.
The match value of MAT1 is associated with event 0.
Set MATCHSEL = 2 Select match value of match register 2. The
match value of MAT2 is associated with event 1.
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Chapter 15: Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM)
Table 234. SCT configuration example
Configuration
Registers
Define when event 2
occurs
EV2_CTRL
Define how event 2
changes the state
EV2_CTRL
Define when event 3
occurs
EV3_CTRL
Define when event 4
occurs
EV4_CTRL
Define when event 5
occurs
EV5_CTRL
Setting
•
Set COMBMODE = 0x3. Event 2 uses match condition and I/O
condition.
•
•
•
Set IOSEL = 0. Select input 0.
Set IOCOND = 0x0. Input 0 is LOW.
Set MATCHSEL = 0. Chooses match register 0 to qualify the
event.
Set STATEV bits to 1 and the STATED bit to 1. Event 2 changes the
state to state 1.
•
•
Set COMBMODE = 0x1. Event 3 uses match condition only.
•
•
Set COMBMODE = 0x1. Event 4 uses match condition only.
•
Set COMBMODE = 0x3. Event 5 uses match condition and I/O
condition.
•
•
•
Set IOSEL = 0. Select input 0.
Set MATCHSEL = 0x3. Select match value of match register 3.
The match value of MAT3 is associated with event 3..
Set MATCHSEL = 0x4. Select match value of match register
4.The match value of MAT4 is associated with event 4.
Set IOCOND = 0x3. Input 0 is HIGH.
Set MATCHSEL = 0. Chooses match register 0 to qualify the
event.
Define how event 5
changes the state
EV5_CTRL
Set STATEV bits to 0 and the STATED bit to 1. Event 5 changes the
state to state 0.
Define by which events
output 0 is set
OUT0_SET
Set SET0 bits 0 (for event 0) and 3 (for event 3) to one to set the
output when these events 0 and 3 occur.
Define by which events
output 0 is cleared
OUT0_CLR
Set CLR0 bits 1 (for events 1) and 4 (for event 4) to one to clear the
output when events 1 and 4 occur.
Configure states in
EV0_STATE
which event 0 is enabled
Set STATEMSK0 bit 0 to 1. Set all other bits to 0. Event 0 is enabled
in state 0.
Configure states in
EV1_STATE
which event 1 is enabled
Set STATEMSK1 bit 0 to 1. Set all other bits to 0. Event 1 is enabled
in state 0.
Configure states in
EV2_STATE
which event 2 is enabled
Set STATEMSK2 bit 0 to 1. Set all other bits to 0. Event 2 is enabled
in state 0.
Configure states in
EV3_STATE
which event 3 is enabled
Set STATEMSK3 bit 1 to 1. Set all other bits to 0. Event 3 is enabled
in state 1.
Configure states in
EV4_STATE
which event 4 is enabled
Set STATEMSK4 bit 1 to 1. Set all other bits to 0. Event 4 is enabled
in state 1.
Configure states in
EV5_STATE
which event 5 is enabled
Set STATEMSK5 bit 1 to 1. Set all other bits to 0. Event 5 is enabled
in state 1.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM,
SCTimer3/PWM)
Rev. 1.1 — 3 March 2014
User manual
16.1 How to read this chapter
The small SCTs are available on all parts. The SCT2 and SCT3 outputs #5 cannot be
connected to external pins on the LQFP48 and LQFP64 packages. The SCT3 output #4
cannot be connected to a pin on the LQFP48 package. (All outputs are available for
internal connections.)
16.2 Features
The following feature list summarizes the configuration for the two small SCTs. Each small
SCT has a companion large SCT (see Section 15.2) with more inputs and outputs and a
dither engine.
• Each SCT supports:
– 8 match/capture registers
– 10 events
– 10 states
– 3 inputs and 6 outputs
– DMA support
• Counter/timer features:
– Configurable as two 16-bit counters or one 32-bit counter.
– Counters clocked by bus clock or selected input.
– Up counters or up-down counters.
– Configurable number of match and capture registers. Up to 16 match and capture
registers total.
– Upon match create the following events: interrupt, stop, limit timer or change
direction; toggle outputs; change state.
– Counter value can be loaded into capture register triggered by match or
input/output toggle.
• PWM features:
– Counters can be used in conjunction with match registers to toggle outputs and
create time-proportioned PWM signals.
– Up to six single-edge or dual-edge controlled PWM outputs with independent duty
cycles if configured as 32-bit timers.
• Event creation features:
– The following conditions define an event: a counter match condition, an input (or
output) condition, a combination of a match and/or and input/output condition in a
specified state.
– Selected events can limit, halt, start, or stop a counter.
– Events control state changes, outputs, interrupts, and DMA requests.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
– Match register 0 can be used as an automatic limit.
– In bi-directional mode, events can be enabled based on the count direction.
– Match events can be held until another qualifying event occurs.
• State control features:
– A state is defined by events that can take place in the state while the counter is
running.
– A state changes into another state as result of an event.
– Each event can be assigned to one or more states.
– State variable allows sequencing across multiple counter cycles.
• Integrated with an input pre-processing unit (SCTIPU) to combine or delay input
events.
Inputs and outputs on the SCT2 and SCT3 are configured as follows:
• 3 inputs. Each input selects one of 21 sources from an input multiplexer.
• 6 outputs (some outputs are connected to multiple locations)
– Three outputs connected to external pins through the switch matrix as movable
functions.
– Three outputs connected to external pins through the switch matrix as fixed-pin
functions.
– Two outputs connected to the SCT IPU to use as sample and abort inputs.
– Four outputs connected to the accompanying large SCT
– Two outputs connected to each ADC trigger input
16.3 Basic configuration
Configure the SCT2/3 as follows:
• Use the SYSAHBCLKCTRL1 register (Table 51) to enable the clock to the SCT
register interface and peripheral clock.
• Clear the SCT2/3 peripheral resets using the PRESETCTRL1 register (Table 36).
• The SCT2/3 combined interrupts are connected to slot #18/19 in the NVIC.
• Use the switch matrix and SCT2/3_INMUX registers to connect the SCT inputs and
outputs to external pins or internally (see Section 16.4).
Remark: For applications that require exact timing of the SCT outputs (for example
PWM), assign the outputs only to fixed-pin functions to ensure that the output skew is
nearly the same for all outputs.
• The SCT DMA request lines 2 and 3 are connected to the DMA trigger inputs via the
DMA_ITRIG_INMUX registers. See Table 132 “DMA input trigger Input mux registers
0 to 17 (DMA_ITRIG_INMUX[0:17], address 0x4001 40E0 (DMA_ITRIG_INMUX0) to
0x4001 4124 (DMA_ITRIG_INMUX17)) bit description”.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
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,138708;
Fig 42. SCT3 connections
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
16.3.1 SCT inputs and outputs
Each of the SCT inputs has a pre-selector that can select one of 21 possible input signals
(SCT input mux). The input signals are numbered 0 to 20 (see Figure 43), and the signal
number is programmed in the SCT2_INMUXn or SCT3_INMUXn register for any
particular input:
SCT2 inputs are selected through input muxes SCT2_INMUX[0:2]. See Table 129.
SCT3 inputs are selected through input muxes SCT3_INMUX[0:2]. See Table 130.
Each large SCT has 6 outputs. All outputs are connected to external pins through the
switch matrix. Some outputs are routed to the other SCT blocks, to the ADC trigger inputs,
and to the SCT IPU. An SCT output can be routed to multiple places.
external
pins
large SCT0
output 4/5
large SCT0
output 7/8
4
2
5:4
7:6
8
9
13:10
18:14
19
20
SCT2_INMUX0
3:0
0
0
1
2
3
4
5
2
SWITCH
MATRIX
64
external
pins
ADC0_THCMP_IRQ
ADC1_THCMP_IRQ
ACMP[3:0]_OUT
SCT IPU
4
5
USB_FRAME_TOGGLE
DEBUG_HALTED
ADC1 TRIGGER
SCT2
SCT2_INMUX2
ADC0 TRIGGER
3:0
5:4
7:6
8
9
13:10
18:14
19
20
7
SCT0_INMUX[6:0]
ADC0 TRIGGER
2
7
SCT0_INMUX[6:0]
ADC1 TRIGGER
SCTIPU SAMPLE_ENABLE
Fig 43. SCT2 inputs and outputs
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
external
pins
large SCT1
output 4/5
large SCT1
output 7/8
4
2
5:4
7:6
8
9
13:10
18:14
19
20
SCT3_INMUX0
3:0
0
0
1
2
3
4
5
2
SWITCH
MATRIX
64
external
pins
ADC0_THCMP_IRQ
ADC1_THCMP_IRQ
ACMP[3:0]_OUT
SCT IPU
4
5
USB_FRAME_TOGGLE
DEBUG_HALTED
ADC1 TRIGGER
SCT3
ADC0 TRIGGER
7
SCT3_INMUX2
3:0
5:4
7:6
8
9
13:10
18:14
19
20
SCT1_INMUX[6:0]
ADC0 TRIGGER
2
7
SCT1_INMUX[6:0]
ADC1 TRIGGER
SCTIPU SAMPE_ENABLE
Fig 44. SCT3 inputs and outputs
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
16.3.2 Use the SCT with the SCTIPU
The SCTIPU provides a pre-processing unit for the SCT inputs for two purposes:
• Combine signal transitions to one transition that always generates the same SCT
response. An example is aborting an SCT operation. See Section 14.5.1
• Provide latched inputs so that signals can be blocked for some fixed time before being
passed on to the SCT inputs. See Section 14.5.2.
See Section 15.3.5 for details.
16.4 Pin description
The SCT inputs and outputs are movable functions and are assigned to external pins
through the switch matrix.
Remark: For applications that require exact timing of the SCT outputs (for example
PWM), assign the outputs only to fixed-pin functions to ensure that the output skew is
nearly the same for all outputs.
See Section 8.3.1 “Connect an internal signal to a package pin” to assign the SCT
functions to package pins.
16.5 General description
The small SCTs are functionally the same as the large SCTs. However, the dither engine
is not implemented. For a description of the SCT, see Section 15.5.
16.6 Register description
The register addresses of the State Configurable Timer are shown in Table 235. For most
of the SCT registers, the register function depends on the setting of certain other register
bits:
1. The UNIFY bit in the CONFIG register determines whether the SCT is used as one
32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit
counter/timers named L and H. The setting of the UNIFY bit is reflected in the register
map:
– UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer).
– UNIFY = 0: Access the L and H registers by a 32-bit read or write operation or can
be read or written to individually (for operation as two 16-bit counter/timers).
Typically, the UNIFY bit is configured by writing to the CONFIG register before any
other registers are accessed.
2. The REGMODEn bits in the REGMODE register determine whether each set of
Match/Capture registers uses the match or capture functionality:
– REGMODEn = 1: Registers operate as match and reload registers.
– REGMODEn = 0: Registers operate as capture and capture control registers.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
Table 235. Register overview: State Configurable Timer (base address 0x1C02 0000 (SCT2) and 0x1C02 4000)
Name
Access Address Description
offset
Reset value Reference
CONFIG
R/W
0x000
SCT configuration register
0x0000 7E00 Table 236
CTRL
R/W
0x004
SCT control register
0x0004 0004 Table 237
CTRL_L
R/W
0x004
SCT control register low counter 16-bit
0x0004 0004 Table 237
CTRL_H
R/W
0x006
SCT control register high counter 16-bit
0x0004 0004 Table 237
LIMIT
R/W
0x008
SCT limit register
0x0000 0000 Table 238
LIMIT_L
R/W
0x008
SCT limit register low counter 16-bit
0x0000 0000 Table 238
LIMIT_H
R/W
0x00A
SCT limit register high counter 16-bit
0x0000 0000 Table 238
HALT
R/W
0x00C
SCT halt condition register
0x0000 0000 Table 239
HALT_L
R/W
0x00C
SCT halt condition register low counter 16-bit
0x0000 0000 Table 239
HALT_H
R/W
0x00E
SCT halt condition register high counter 16-bit
0x0000 0000 Table 239
STOP
R/W
0x010
SCT stop condition register
0x0000 0000 Table 240
STOP_L
R/W
0x010
SCT stop condition register low counter 16-bit
0x0000 0000 Table 240
STOP_H
R/W
0x012
SCT stop condition register high counter 16-bit
0x0000 0000 Table 240
START
R/W
0x014
SCT start condition register
0x0000 0000 Table 241
START_L
R/W
0x014
SCT start condition register low counter 16-bit
0x0000 0000 Table 241
START_H
R/W
0x016
SCT start condition register high counter 16-bit
0x0000 0000 Table 241
-
-
0x018 0x03C
Reserved
COUNT
R/W
0x040
SCT counter register
0x0000 0000 Table 242
COUNT_L
R/W
0x040
SCT counter register low counter 16-bit
0x0000 0000 Table 242
COUNT_H
R/W
0x042
SCT counter register high counter 16-bit
0x0000 0000 Table 242
STATE
R/W
0x044
SCT state register
0x0000 0000 Table 243
STATE_L
R/W
0x044
SCT state register low counter 16-bit
0x0000 0000 Table 243
-
STATE_H
R/W
0x046
SCT state register high counter 16-bit
0x0000 0000 Table 243
INPUT
RO
0x048
SCT input register
0x0000 0000 Table 244
REGMODE
R/W
0x04C
SCT match/capture registers mode register
0x0000 0000 Table 245
REGMODE_L
R/W
0x04C
SCT match/capture registers mode register low
counter 16-bit
0x0000 0000 Table 245
REGMODE_H
R/W
0x04E
SCT match/capture registers mode register high
counter 16-bit
0x0000 0000 Table 245
OUTPUT
R/W
0x050
SCT output register
0x0000 0000 Table 246
OUTPUTDIRCTRL
R/W
0x054
SCT output counter direction control register
0x0000 0000 Table 247
RES
R/W
0x058
SCT conflict resolution register
0x0000 0000 Table 248
DMAREQ0
R/W
0x05C
SCT DMA request 0 register
0x0000 0000 Table 249
DMAREQ1
R/W
0x060
SCT DMA request 1 register
0x0000 0000 Table 250
-
-
0x064 0x0EC
Reserved
-
EVEN
R/W
0x0F0
SCT event enable register
0x0000 0000 Table 251
EVFLAG
R/W
0x0F4
SCT event flag register
0x0000 0000 Table 252
CONEN
R/W
0x0F8
SCT conflict enable register
0x0000 0000 Table 253
CONFLAG
R/W
0x0FC
SCT conflict flag register
0x0000 0000 Table 254
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
Table 235. Register overview: State Configurable Timer (base address 0x1C02 0000 (SCT2) and 0x1C02 4000)
Name
Access Address Description
offset
Reset value Reference
MATCH0 to MATCH7 R/W
0x100 to SCT match value register of match channels 0 to
0x11C
7; REGMOD0 to REGMODE7 = 0
0x0000 0000 Table 254
MATCH0_L to
MATCH7_L
R/W
0x100 to SCT match value register of match channels 0 to
0x11C
7; low counter 16-bit; REGMOD0_L to
REGMODE7_L = 0
0x0000 0000 Table 254
MATCH0_H to
MATCH7_H
R/W
0x102 to SCT match value register of match channels 0 to
0x11E
7; high counter 16-bit; REGMOD0_H to
REGMODE7_H = 0
0x0000 0000 Table 254
CAP0 to CAP7
0x100 to SCT capture register of capture channel 0 to 7;
0x11C
REGMOD0 to REGMODE7 = 1
0x0000 0000 Table 256
CAP0_L to CAP7_L
0x100 to SCT capture register of capture channel 0 to 7;
0x11C
low counter 16-bit; REGMOD0_L to
REGMODE7_L = 1
0x0000 0000 Table 256
CAP0_H to CAP7_H
0x102 to SCT capture register of capture channel 0 to 7;
0x11E
high counter 16-bit; REGMOD0_H to
REGMODE7_H = 1
0x0000 0000 Table 256
MATCHREL0 to
MATCHREL7
R/W
0x200 to SCT match reload value register 0 to 7;
0x21C
REGMOD0 = 0 to REGMODE7 = 0
0x0000 0000 Table 257
MATCHREL0_L to
MATCHREL7_L
R/W
0x200 to SCT match reload value register 0 to 7; low
0x21C
counter 16-bit; REGMOD0_L = 0 to
REGMODE7_L = 0
0x0000 0000 Table 257
MATCHREL0_H to
MATCHREL7_H
R/W
0x202 to SCT match reload value register 0 to 7; high
0x21E
counter 16-bit; REGMOD0_H = 0 to
REGMODE7_H = 0
0x0000 0000 Table 257
CAPCTRL0 to
CAPCTRL7
0x200 to SCT capture control register 0 to 7; REGMOD0 = 0x0000 0000 Table 258
0x21C
1 to REGMODE7 = 1
CAPCTRL0_L to
CAPCTRL7_L
0x200 to SCT capture control register 0 to 7; low counter
0x21C
16-bit; REGMOD0_L = 1 to REGMODE7_L = 1
0x0000 0000 Table 258
CAPCTRL0_H to
CAPCTRL7_H
0x202 to SCT capture control register 0 to 7; high counter
0x21E
16-bit; REGMOD0 = 1 to REGMODE7 = 1
0x0000 0000 Table 258
EV0_STATE
R/W
0x300
SCT event state register 0
0x0000 0000 Table 259
EV0_CTRL
R/W
0x304
SCT event control register 0
0x0000 0000 Table 260
EV1_STATE
R/W
0x308
SCT event state register 1
0x0000 0000 Table 259
EV1_CTRL
R/W
0x30C
SCT event control register 1
0x0000 0000 Table 260
EV2_STATE
R/W
0x310
SCT event state register 2
0x0000 0000 Table 259
EV2_CTRL
R/W
0x314
SCT event control register 2
0x0000 0000 Table 260
EV3_STATE
R/W
0x318
SCT event state register 3
0x0000 0000 Table 259
EV3_CTRL
R/W
0x31C
SCT event control register 3
0x0000 0000 Table 260
EV4_STATE
R/W
0x320
SCT event state register 4
0x0000 0000 Table 259
EV4_CTRL
R/W
0x324
SCT event control register4
0x0000 0000 Table 260
EV5_STATE
R/W
0x328
SCT event state register 5
0x0000 0000 Table 259
EV5_CTRL
R/W
0x32C
SCT event control register 5
0x0000 0000 Table 260
EV6_STATE
R/W
0x330
SCT event state register 6
0x0000 0000 Table 259
EV6_CTRL
R/W
0x334
SCT event control register 6
0x0000 0000 Table 260
EV7_STATE
R/W
0x338
SCT event state register 7
0x0000 0000 Table 259
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
Table 235. Register overview: State Configurable Timer (base address 0x1C02 0000 (SCT2) and 0x1C02 4000)
Name
Access Address Description
offset
Reset value Reference
EV7_CTRL
R/W
0x33C
SCT event control register 7
0x0000 0000 Table 260
EV8_STATE
R/W
0x340
SCT event state register 8
0x0000 0000 Table 259
EV8_CTRL
R/W
0x344
SCT event control register 8
0x0000 0000 Table 260
EV9_STATE
R/W
0x348
SCT event state register 9
0x0000 0000 Table 259
EV9_CTRL
R/W
0x34C
SCT event control register 9
0x0000 0000 Table 260
OUT0_SET
R/W
0x500
SCT output 0 set register
0x0000 0000 Table 261
OUT0_CLR
R/W
0x504
SCT output 0 clear register
0x0000 0000 Table 262
OUT1_SET
R/W
0x508
SCT output 1 set register
0x0000 0000 Table 261
OUT1_CLR
R/W
0x50C
SCT output 1 clear register
0x0000 0000 Table 262
OUT2_SET
R/W
0x510
SCT output 2 set register
0x0000 0000 Table 261
OUT2_CLR
R/W
0x514
SCT output 2 clear register
0x0000 0000 Table 262
OUT3_SET
R/W
0x518
SCT output 3 set register
0x0000 0000 Table 261
OUT3_CLR
R/W
0x51C
SCT output 3 clear register
0x0000 0000 Table 262
OUT4_SET
R/W
0x520
SCT output 4 set register
0x0000 0000 Table 261
OUT4_CLR
R/W
0x524
SCT output 4 clear register
0x0000 0000 Table 262
OUT5_SET
R/W
0x528
SCT output 5 set register
0x0000 0000 Table 261
OUT5_CLR
R/W
0x52C
SCT output 5 clear register
0x0000 0000 Table 262
16.6.1 SCT configuration register
This register configures the overall operation of the SCT. Write to this register before any
other registers.
Table 236. SCT configuration register (CONFIG, address 0x1C02 0000 (SCT2) and 0x1C02 4000 (SCT3)) bit
description
Bit
Symbol
0
UNIFY
2:1
Value
User manual
Reset
value
SCT operation
0
0
The SCT operates as two 16-bit counters named L and H.
1
The SCT operates as a unified 32-bit counter.
CLKMODE
UM10736
Description
SCT clock mode
00
0x0
The bus clock clocks the SCT and prescalers.
0x1
The SCT clock is the bus clock, but the prescalers are enabled to count only
when sampling of the input selected by the CKSEL field finds the selected
edge. The minimum pulse width on the clock input is 1 bus clock period. This
mode is the high-performance sampled-clock mode.
0x2
The input selected by CKSEL clocks the SCT and prescalers. The input is
synchronized to the system clock and possibly inverted. The minimum pulse
width on the clock input is 1 bus clock period. This mode is the low-power
sampled-clock mode.
0x3
Prescaled SCT input. The SCT and prescalers are clocked by the input edge
selected by the CKSEL field. In this mode, most of the SCT is clocked by the
(selected polarity of the) input. The outputs are switched synchronously to the
input clock. The input clock rate must be at least half the system clock rate and
can the same or faster than the system clock.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
Table 236. SCT configuration register (CONFIG, address 0x1C02 0000 (SCT2) and 0x1C02 4000 (SCT3)) bit
description …continued
Bit
Symbol
6:3
CKSEL
Value
Description
Reset
value
SCT clock select
0000
0x0
Rising edges on input 0.
0x1
Falling edges on input 0.
0x2
Rising edges on input 1.
0x3
Falling edges on input 1.
0x4
Rising edges on input 2.
0x5
Falling edges on input 2.
0x6
Rising edges on input 3.
0x7
Falling edges on input 3.
7
NORELAOD_L
-
A 1 in this bit prevents the lower match registers from being reloaded from their 0
respective reload registers. Software can write to set or clear this bit at any
time. This bit applies to both the higher and lower registers when the UNIFY bit
is set.
8
NORELOAD_H
-
A 1 in this bit prevents the higher match registers from being reloaded from their 0
respective reload registers. Software can write to set or clear this bit at any
time. This bit is not used when the UNIFY bit is set.
16:9
INSYNC
-
Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). 1
A 1 in one of these bits subjects the corresponding input to synchronization to
the SCT clock, before it is used to create an event. If an input is synchronous to
the SCT clock, keep its bit 0 for faster response.
When the CKMODE field is 1x, the bit in this field, corresponding to the input
selected by the CKSEL field, is not used.
17
AUTOLIMIT_L
-
A one in this bit causes a match on match register 0 to be treated as a de-facto
LIMIT condition without the need to define an associated event.
As with any LIMIT event, this automatic limit causes the counter to be cleared to
zero in uni-directional mode or to change the direction of count in bi-directional
mode.
Software can write to set or clear this bit at any time. This bit applies to both the
higher and lower registers when the UNIFY bit is set.
18
AUTOLIMIT_H
-
A one in this bit will cause a match on match register 0 to be treated as a
de-facto LIMIT condition without the need to define an associated event.
As with any LIMIT event, this automatic limit causes the counter to be cleared to
zero in uni-directional mode or to change the direction of count in bi-directional
mode.
Software can write to set or clear this bit at any time. This bit is not used when
the UNIFY bit is set.
31:19
-
Reserved
-
16.6.2 SCT control register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CTRL_L and CTRL_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
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All bits in this register can be written to when the counter is stopped or halted. When the
counter is running, the only bits that can be written are STOP or HALT.(Other bits can be
written in a subsequent write after HALT is set to 1.)
Remark: If CLKMODE = 0x3 is selected, wait at least 12 system clock cycles between a
write access to the H, L or unified version of this register and the next write access. This
restriction does not apply when writing to the HALT bit or bits and then writing to the CTRL
register again to restart the counters - for example because software must update the
MATCH register, which is only allowed when the counters are halted.
Remark: If the SCTimer/PWM is operating as two 16-bit counters, events can only modify
the state of the outputs when neither counter is halted. This is true regardless of what
triggered the event.
Table 237. SCT control register (CTRL, address 0x1C02 0004 (SCT2) and 0x1C02 4004 (SCT3)) bit description
Bit
Symbol
Value Description
Reset
value
0
DOWN_L
-
This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
0
when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the
counter is counting down and a limit condition occurs or when the counter reaches 0.
1
STOP_L
-
When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events 0
related to the counter can occur. If such an event matches the mask in the Start
register, this bit is cleared and counting resumes.
2
HALT_L
-
When this bit is 1, the L or unified counter does not run and no events can occur. A
reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you
want to remove the halt condition and keep the SCT in the stop condition (not
running), then you can change the halt and stop condition with one single write to
this register.
1
Remark: Once set, only software can clear this bit to restore counter operation.
3
CLRCTR_L -
Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
0
4
BIDIR_L
L or unified counter direction select
0
12:5
PRE_L
0
The counter counts up to its limit condition, then is cleared to zero.
1
The counter counts up to its limit, then counts down to a limit condition or to 0.
-
Specifies the factor by which the SCT clock is prescaled to produce the L or unified
counter clock. The counter clock is clocked at the rate of the SCT clock divided by
PRE_L+1.
0
Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.
15:13
-
Reserved
16
DOWN_H
-
This bit is 1 when the H counter is counting down. Hardware sets this bit when the 0
counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is
counting down and a limit condition occurs or when the counter reaches 0.
17
STOP_H
-
When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related 0
to the counter can occur. If such an event matches the mask in the Start register, this
bit is cleared and counting resumes.
18
HALT_H
-
When this bit is 1, the H counter does not run and no events can occur. A reset sets 1
this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to
remove the halt condition and keep the SCT in the stop condition (not running), then
you can change the halt and stop condition with one single write to this register.
Remark: Once set, this bit can only be cleared by software to restore counter
operation.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
Table 237. SCT control register (CTRL, address 0x1C02 0004 (SCT2) and 0x1C02 4004 (SCT3)) bit description
Bit
Symbol
19
CLRCTR_H -
Writing a 1 to this bit clears the H counter. This bit always reads as 0.
0
20
BIDIR_H
Direction select
0
28:21
PRE_H
Value Description
Reset
value
0
The H counter counts up to its limit condition, then is cleared to zero.
1
The H counter counts up to its limit, then counts down to a limit condition or to 0.
-
Specifies the factor by which the SCT clock is prescaled to produce the H counter
0
clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1.
Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.
31:29
-
Reserved
16.6.3 SCT limit register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
LIMIT_L and LIMIT_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
The bits in this register set which events act as counter limits. When a limit event occurs,
the counter is cleared to zero in unidirectional mode or changes the direction of count in
bidirectional mode. When the counter reaches all ones, this state is always treated as a
limit event, and the counter is cleared in unidirectional mode or, in bidirectional mode,
begins counting down on the next clock edge - even if no limit event as defined by the
SCT limit register has occurred.
Note that in addition to using this register to specify events that serve as limits, it is also
possible to automatically cause a limit condition whenever a match register 0 match
occurs. This eliminates the need to define an event for the sole purpose of creating a limit.
The AUTOLIMITL and AUTOLIMITH bits in the configuration register enable/disable this
feature (see Table 236).
Table 238. SCT limit register (LIMIT, address 0x1C02 0008 (SCT2) and 0x1C02 4008 (SCT3))
bit description
Bit
Symbol
Description
Reset
value
15:0
LIMMSK_L
If bit n is one, event n is used as a counter limit for the L or
unified counter (event 0 = bit 0, event 1 = bit 1, event 15 =
bit 15).
0
31:16
LIMMSK_H
If bit n is one, event n is used as a counter limit for the H
counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit
31).
0
16.6.4 SCT halt condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
HALT_L and HALT_H. Both the L and H registers can be read or written individually or in a
single 32-bit read or write operation.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
Remark: Any event halting the counter disables its operation until software clears the
HALT bit (or bits) in the CTRL register (Table 237).
Table 239. SCT halt condition register (HALT, address 0x1C02 000C (SCT2) and 0x1C02 400C
(SCT3)) bit description
Bit
Symbol
Description
Reset
value
15:0
HALTMSK_L
If bit n is one, event n sets the HALT_L bit in the CTRL register 0
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
31:16 HALTMSK_H
If bit n is one, event n sets the HALT_H bit in the CTRL register 0
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
16.6.5 SCT stop condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
STOPT_L and STOP_H. Both the L and H registers can be read or written individually or
in a single 32-bit read or write operation.
Table 240. SCT stop condition register (STOP, address 0x1C02 0010 (SCT2) and 0x1C02 4010
(SCT3)) bit description
Bit
Symbol
Description
Reset
value
15:0
STOPMSK_L
If bit n is one, event n sets the STOP_L bit in the CTRL register
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
0
31:16 STOPMSK_H
If bit n is one, event n sets the STOP_H bit in the CTRL register 0
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
16.6.6 SCT start condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
START_L and START_H. Both the L and H registers can be read or written individually or
in a single 32-bit read or write operation.
The bits in this register select which events, if any, clear the STOP bit in the Control
register. (Since no events can occur when HALT is 1, only software can clear the HALT bit
by writing the Control register.)
Table 241. SCT start condition register (START, address 0x1C02 0014 (SCT2) and 0x1C02
4014 (SCT3)) bit description
Bit
Symbol
Description
Reset
value
15:0
STARTMSK_L
If bit n is one, event n clears the STOP_L bit in the CTRL
register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
0
If bit n is one, event n clears the STOP_H bit in the CTRL
register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
0
31:16 STARTMSK_H
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16.6.7 SCT counter register
If UNIFY = 1 in the CONFIG register, the counter is a unified 32-bit register and both the
_L and _H bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
COUNT_L and COUNT_H. Both the L and H registers can be read or written individually
or in a single 32-bit read or write operation. In this case, the L and H registers count
independently under the control of the other registers.
Writing to the COUNT_L, COUNT_H, or unified register is only allowed when the
corresponding counter is halted (HALT bits are set to 1 in the CTRL register).
Table 242. SCT counter register (COUNT, address 0x1C02 0040 (SCT2) and 0x1C02 4040
(SCT3)) bit description
Bit
Symbol
Description
Reset
value
15:0
CTR_L
When UNIFY = 0, read or write the 16-bit L counter value. When
UNIFY = 1, read or write the lower 16 bits of the 32-bit unified
counter.
0
31:16
CTR_H
When UNIFY = 0, read or write the 16-bit H counter value. When
UNIFY = 1, read or write the upper 16 bits of the 32-bit unified
counter.
0
16.6.8 SCT state register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
STATE_L and STATE_H. Both the L and H registers can be read or written individually or
in a single 32-bit read or write operation.
Software can read the state associated with a counter at any time. Writing to the
STATE_L, STATE_H, or unified register is only allowed when the corresponding counter is
halted (HALT bits are set to 1 in the CTRL register).
The state variable is the main feature that distinguishes the SCT from other counter/timer/
PWM blocks. Events can be made to occur only in certain states. Events, in turn, can
perform the following actions:
•
•
•
•
set and clear outputs
limit, stop, and start the counter
cause interrupts and DMA requests
modify the state variable
The value of a state variable is completely under the control of the application. If an
application does not use states, the value of the state variable remains zero, which is the
default value.
A state variable can be used to track and control multiple cycles of the associated counter
in any desired operational sequence. The state variable is logically associated with a state
machine diagram which represents the SCT configuration. See Section 16.6.23 and
16.6.24 for more about the relationship between states and events.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
The STATELD/STADEV fields in the event control registers of all defined events set all
possible values for the state variable. The change of the state variable during multiple
counter cycles reflects how the associated state machine moves from one state to the
next.
Table 243. SCT state register (STATE, address 0x1C02 0044 (SCT2) and 0x1C02 4044 (SCT3))
bit description
Bit
Symbol
Description
Reset
value
4:0
STATE_L
State variable.
0
15:5
-
Reserved.
-
20:16
STATE_H
State variable.
0
31:21
-
Reserved.
16.6.9 SCT input register
Software can read the state of the SCT inputs in this read-only register in slightly different
forms.
1. The AIN bit represents the input sampled by the SCT clock. This corresponds to a
nearly direct read-out of the input but can cause spurious fluctuations in case of an
asynchronous input signal.
2. The SIN bit represents the input sampled by the SCT clock after the INSYNC select
(this signal is also used for event generation):
– If the INSYNC bit is set for the input, the input is synchronized to the SCT clock
using three SCT clock cycles resulting in a stable signal that is delayed by three
SCT clock cycles.
– If the INSYNC bit is not set, the SIN bit value is the same as the AIN bit value.
Table 244. SCT input register (INPUT, address 0x1C02 0048 (SCT2) and 0x1C02 4048 (SCT3))
bit description
Bit
Symbol
Description
Reset
value
0
AIN0
Input 0 state. Direct read.
-
1
AIN1
Input 1 state. Direct read.
-
2
AIN2
Input 2 state. Direct read.
-
15:3
-
Reserved.
-
16
SIN0
Input 0 state.
-
17
SIN1
Input 1 state.
-
18
SIN2
Input 2 state.
-
31:19
-
Reserved
-
16.6.10 SCT match/capture registers mode register
If UNIFY = 1 in the CONFIG register, only the _L bits of this register are used. The L bits
control whether each set of match/capture registers operates as unified 32-bit
capture/match registers.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
REGMODE_L and REGMODE_H. Both the L and H registers can be read or written
individually or in a single 32-bit read or write operation.The _L bits/registers control the L
match/capture registers, and the _H bits/registers control the H match/capture registers.
The SCT contains 16 Match/Capture register pairs. The Register Mode register selects
whether each register pair acts as a Match register (see Section 16.6.19) or as a Capture
register (see Section 16.6.20). Each Match/Capture register has an accompanying
register which serves as a Reload register when the register is used as a Match register
(Section 16.6.21) or as a Capture-Control register when the register is used as a capture
register (Section 16.6.22). REGMODE_H is used only when the UNIFY bit is 0.
Table 245. SCT match/capture registers mode register (REGMODE, address 0x1C02 004C
(SCT2) and 0x1C02 404C (SCT3)) bit description
Bit
Symbol
Description
Reset
value
15:0
REGMOD_L
Each bit controls one pair of match/capture registers (register 0 =
bit 0, register 1 = bit 1,..., register 15 = bit 15).
0
0 = registers operate as match registers.
1 = registers operate as capture registers.
31:16 REGMOD_H
Each bit controls one pair of match/capture registers (register 0 =
bit 16, register 1 = bit 17,..., register 15 = bit 31).
0
0 = registers operate as match registers.
1 = registers operate as capture registers.
16.6.11 SCT output register
The SCT supports 6 outputs, each of which has a corresponding bit in this register.
Software can write to any of the output registers when both counters are halted to control
the outputs directly. Writing to the OUT register is only allowed when all counters
(L-counter, H-counter, and unified counter) are halted (HALT bits are set to 1 in the CTRL
register).
Software can read this register at any time to sense the state of the outputs.
Table 246. SCT output register (OUTPUT, address 0x1C02 0050 (SCT2) and 0x1C02 4050
(SCT3)) bit description
Bit
Symbol
Description
Reset
value
5:0
OUT
Writing a 1 to bit n makes the corresponding output HIGH. 0 makes 0
the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,...,
output 5 = bit 5).
31:6
-
Reserved
16.6.12 SCT bidirectional output control register
This register specifies (for each output) the impact of the counting direction on the
meaning of set and clear operations on the output (see Section 16.6.25 and
Section 16.6.26).
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Table 247. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x1C02 0054 (SCT2) and 0x1C02
4054 (SCT3)) bit description
Bit
Symbol
1:0
SETCLR0
3:2
5:4
7:6
9:8
Value Description
Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR1
Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR2
Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR3
Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
SETCLR4
Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
11:10 SETCLR5
31:1
2
-
Reset
value
Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
0x0
Set and clear do not depend on any counter.
0x1
Set and clear are reversed when counter L or the unified counter is counting down.
0x2
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Reserved
0
0
0
0
0
0
-
16.6.13 SCT conflict resolution register
The registers OUTn_SET (Section 16.6.25) and OUTn_CLR (Section 16.6.26) allow both
setting and clearing to be indicated for an output in the same clock cycle, even for the
same event. This SCT conflict resolution register resolves this conflict.
To enable an event to toggle an output, set the OnRES value to 0x3 in this register, and
set the event bits in both the Set and Clear registers.
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Table 248. SCT conflict resolution register (RES, address 0x1C02 0058 (SCT2) and 0x1C02
4058 (SCT3)) bit description
Bit
Symbol
1:0
O0RES
3:2
5:4
Value Description
Effect of simultaneous set and clear on output 0.
9:8
No change.
0x1
Set output (or clear based on the SETCLR0 field).
0x2
Clear output (or set based on the SETCLR0 field).
0x3
Toggle output.
O1RES
Effect of simultaneous set and clear on output 1.
0
0x0
No change.
0x1
Set output (or clear based on the SETCLR1 field).
0x2
Clear output (or set based on the SETCLR1 field).
0x3
Toggle output.
O2RES
Effect of simultaneous set and clear on output 2.
0
0x0
No change.
0x1
Set output (or clear based on the SETCLR2 field).
0x2
Clear output n (or set based on the SETCLR2 field).
O3RES
Toggle output.
Effect of simultaneous set and clear on output 3.
0
0x0
No change.
0x1
Set output (or clear based on the SETCLR3 field).
0x2
Clear output (or set based on the SETCLR3 field).
0x3
Toggle output.
O4RES
Effect of simultaneous set and clear on output 4.
0
0x0
No change.
0x1
Set output (or clear based on the SETCLR4 field).
0x2
Clear output (or set based on the SETCLR4 field).
0x3
Toggle output.
11:10 O5RES
31:12 -
0
0x0
0x3
7:6
Reset
value
Effect of simultaneous set and clear on output 5.
0
0x0
No change.
0x1
Set output (or clear based on the SETCLR5 field).
0x2
Clear output (or set based on the SETCLR5 field).
0x3
Toggle output.
-
Reserved
-
16.6.14 SCT DMA request 0 and 1 registers
The SCT includes two DMA request outputs. These registers enable the DMA requests to
be triggered when a particular event occurs or when counter Match registers are loaded
from its Reload registers.
Event-triggered DMA requests are particularly useful for launching DMA activity to or from
other peripherals under the control of the SCT.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
Table 249. SCT DMA 0 request register (DMAREQ0, address 0x1C02 005C (SCT2) and
0x1C02 405C (SCT3)) bit description
Bit
Symbol
Description
Reset
value
15:0
DEV_0
If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 0
1 = bit 1,..., event 15 = bit 15).
29:16
-
Reserved
30
DRL0
A 1 in this bit makes the SCT set DMA request 0 when it loads
the Match_L/Unified registers from the Reload_L/Unified
registers.
-
31
DRQ0
This read-only bit indicates the state of DMA Request 0
Table 250. SCT DMA 1 request register (DMAREQ1, address 0x1C02 0060 (SCT2) and 0x1C02
4060 (SCT3)) bit description
Bit
Symbol
Description
Reset
value
15:0
DEV_1
If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 0
1 = bit 1,..., event 15 = bit 15).
29:16
-
Reserved
30
DRL1
A 1 in this bit makes the SCT set DMA request 1 when it loads
the Match L/Unified registers from the Reload L/Unified
registers.
31
DRQ1
This read-only bit indicates the state of DMA Request 1.
-
16.6.15 SCT flag enable register
This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag
register (Section 16.6.16) is also set.
Table 251. SCT flag enable register (EVEN, address 0x1C02 00F0 (SCT2) and 0x1C02 40F0
(SCT3)) bit description
Bit
Symbol
Description
Reset
value
15:0
IEN
The SCT requests interrupt when bit n of this register and the event 0
flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event
15 = bit 15).
31:16
-
Reserved
16.6.16 SCT event flag register
This register records events. Writing ones to this register clears the corresponding flags
and negates the SCT interrupt request if all enabled Flag bits are zero.
Table 252. SCT event flag register (EVFLAG, address 0x1C02 00F4 (SCT2) and 0x1C02 40F4
(SCT3)) bit description
Bit
UM10736
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Symbol
Description
Reset
value
15:0 FLAG
Bit n is one if event n has occurred since reset or a 1 was last written to
this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
0
31:
16
Reserved
-
-
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
16.6.17 SCT conflict enable register
This register enables the “no change conflict” events specified in the SCT conflict
resolution register to request an IRQ.
Table 253. SCT conflict enable register (CONEN, address 0x1C02 00F8 (SCT2) and 0x1C02
40F8 (SCT3)) bit description
Bit
Symbol
Description
Reset
value
15:0
NCEN
The SCT requests interrupt when bit n of this register and the SCT 0
conflict flag register are both one (output 0 = bit 0, output 1 = bit
1,..., output 15 = bit 15).
31:16
-
Reserved
16.6.18 SCT conflict flag register
This register records interrupt-enabled no-change conflict events and provides details of a
bus error. Writing ones to the NCFLAG bits clears the corresponding read bits and
negates the SCT interrupt request if all enabled Flag bits are zero.
Table 254. SCT conflict flag register (CONFLAG, address 0x1C02 00FC (SCT2) and 0x1C02
40FC (SCT3)) bit description
Bit
Symbol
Description
Reset
value
5:0
NCFLAG
Bit n is one if a no-change conflict event occurred on output n
since reset or a 1 was last written to this bit (output 0 = bit 0,
output 1 = bit 1,..., output 5 = bit 5).
0
29:6
-
Reserved.
-
30
BUSERRL
The most recent bus error from this SCT involved writing CTR
L/Unified, STATE L/Unified, MATCH L/Unified, or the Output
register when the L/U counter was not halted. A word write to
certain L and H registers can be half successful and half
unsuccessful.
0
31
BUSERRH
The most recent bus error from this SCT involved writing CTR
H, STATE H, MATCH H, or the Output register when the H
counter was not halted.
0
16.6.19 SCT match registers 0 to 7 (REGMODEn bit = 0)
Match registers are compared to the counters to help create events. When the UNIFY bit
is 0, the L and H registers are independently compared to the L and H counters. When
UNIFY is 1, the L and H registers hold a 32-bit value that is compared to the unified
counter. A Match can only occur in a clock in which the counter is running (STOP and
HALT are both 0).
Match registers can be read at any time. Writing to the MATCH_L, MATCH_H, or unified
register is only allowed when the corresponding counter is halted (HALT bits are set to 1 in
the CTRL register). Match events occur in the SCT clock in which the counter is (or would
be) incremented to the next value. When a Match event limits its counter as described in
Section 16.6.3, the value in the Match register is the last value of the counter before it is
cleared to zero (or decremented if BIDIR is 1).
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There is no “write-through” from Reload registers to Match registers. Before starting a
counter, software can write one value to the Match register used in the first cycle of the
counter and a different value to the corresponding Match Reload register used in the
second cycle.
Table 255. SCT match registers 0 to 7 (MATCH[0:7], address 0x1C02 0100 (MATCH0) to
0x1C02 011C (MATCH7) (SCT2) and address 0x1C02 4100 (MATCH0) to 0x1C02
411C (MATCH7) (SCT3)) bit description (REGMODEn bit = 0)
Bit
Symbol
Description
Reset
value
15:0
MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to
the L counter. When UNIFY = 1, read or write the lower 16 bits of
the 32-bit value to be compared to the unified counter.
0
31:16
MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to
the H counter. When UNIFY = 1, read or write the upper 16 bits of
the 32-bit value to be compared to the unified counter.
0
16.6.20 SCT capture registers 0 to 7 (REGMODEn bit = 1)
These registers allow software to read the counter values at which the event selected by
the corresponding Capture Control registers occurred.
Table 256. SCT capture registers 0 to 7 (CAP[0:7], address 0x1C02 0100 (CAP0) to 0x1C02
011C (CAP7) (SCT2) and address 0x1C02 4100 (CAP0) to 0x1C02 411C (CAP7)
(SCT3)) bit description (REGMODEn bit = 1)
Bit
Symbol
Description
Reset
value
15:0
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this
0
register was last captured. When UNIFY = 1, read the lower 16 bits
of the 32-bit value at which this register was last captured.
31:16
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this
0
register was last captured. When UNIFY = 1, read the upper 16 bits
of the 32-bit value at which this register was last captured.
16.6.21 SCT match reload registers 0 to 7 (REGMODEn bit = 0)
A Match register (L, H, or unified 32-bit) is loaded from the corresponding Reload register
when BIDIR is 0 and the counter reaches its limit condition, or when BIDIR is 1 and the
counter reaches 0.
Table 257. SCT match reload registers 0 to 7 (MATCHREL[0:7], address 0x1C02 0200
(MATCHREL0) to 0x1C02 021C (MATCHREL7) (SCT2) and 0x1C02 4200
(MATCHREL0) to 0x1C02 421C (MATCHREL7) (SCT3)) bit description
(REGMODEn bit = 0)
Bit
Symbol
Description
Reset
value
15:0
RELOADn_L When UNIFY = 0, read or write the 16-bit value to be loaded into
the SCTMATCHn_L register. When UNIFY = 1, read or write the
lower 16 bits of the 32-bit value to be loaded into the MATCHn
register.
31:16 RELOADn_H When UNIFY = 0, read or write the 16-bit to be loaded into the
MATCHn_H register. When UNIFY = 1, read or write the upper 16
bits of the 32-bit value to be loaded into the MATCHn register.
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16.6.22 SCT capture control registers 0 to 7 (REGMODEn bit = 1)
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CAPCTRLn_L and CAPCTRLn_H. Both the L and H registers can be read or written
individually or in a single 32-bit read or write operation.
Each Capture Control register (L, H, or unified 32-bit) controls which events load the
corresponding Capture register from the counter.
Table 258. SCT capture control registers 0 to 7 (CAPCTRL[0:7], address 0x1C02 0200
(CAPCTRL0) to 0x1C02 021C (CAPCTRL7) (SCT2) and 0x1C02 4200 (CAPCTRL0)
to 0x1C02 421C (CAPCTRL7) (SCT3)) bit description (REGMODEn bit = 1)
Bit
Symbol
Description
Reset
value
9:0
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the 0
CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1
= bit 1,..., event 9 = bit 9).
15:10
-
Reserved.
24:16
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0)
0
register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event
9 = bit 24).
31:25
-
Reserved.
-
-
16.6.23 SCT event state registers 0 to 9
Each event has one associated SCT event state mask register that allow this event to
happen in one or more states of the counter selected by the HEVENT bit in the
corresponding EVCTRLn register.
An event n is disabled when its EVn_STATE register contains all zeros, since it is masked
regardless of the current state.
In simple applications that do not use states, write 0x01 to this register to enable an event.
Since the state always remains at its reset value of 0, writing 0x01 effectively permanently
state-enables this event.
Table 259. SCT event state mask registers 0 to 9 (EV[0:9]_STATE, addresses 0x1C02 0300
(EV0_STATE) to 0x1C02 0348 (EV9_STATE) (SCT2) and 0x1C02 4300 (EV0_STATE)
to 0x1C02 4348 (EV9_STATE) (SCT3)) bit description
Bit
Symbol
Description
Reset
value
9:0
STATEMSKn
If bit m is one, event n (n= 0 to 9) happens in state m of the
0
counter selected by the HEVENT bit (m = state number; state 0 =
bit 0, state 1= bit 1,..., state 9 = bit 9).
31:10
-
Reserved.
-
16.6.24 SCT event control registers 0 to 9
This register defines the conditions for event n to occur, other than the state variable
which is defined by the state mask register. Most events are associated with a particular
counter (high, low, or unified), in which case the event can depend on a match to that
register. The other possible ingredient of an event is a selected input or output signal.
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When the UNIFY bit is 0, each event is associated with a particular counter by the
HEVENT bit in its event control register. An event cannot occur when its related counter is
halted nor when the current state is not enabled to cause the event as specified in its
event mask register. An event is permanently disabled when its event state mask register
contains all 0s.
An enabled event can be programmed to occur based on a selected input or output edge
or level and/or based on its counter value matching a selected match register (STOP bit =
0). An event can be enabled by the event counter’s HALT bit and STATE register. In
bi-directional mode, events can also be enabled based on the direction of count.
Each event can modify its counter STATE value. If more than one event associated with
the same counter occurs in a given clock cycle, only the state change specified for the
highest-numbered event among them takes place. Other actions dictated by any
simultaneously occurring events all take place.
Table 260. SCT event control register 0 to 9 (EV[0:9]_CTRL, address 0x1C02 0304 (EV0_CTRL) to 0x1C02 034C
(EV9_CTRL) (SCT2) and 0x1C02 4304 (EV0_CTRL) to 0x1C02 434C (EV9_CTRL) (SCT3)) bit description
Bit
Symbol
Value Description
3:0
MATCHSEL
-
4
HEVENT
5
9:6
0
Selects the L state and the L match register selected by MATCHSEL.
1
Selects the H state and the H match register selected by MATCHSEL.
Input/output select
1
Selects the outputs selected by IOSEL.
-
Selects the input or output signal associated with this event (if any). Do not select an
input in this register, if CKMODE is 1x. In this case the clock input is an implicit
ingredient of every event.
0
Selects the I/O condition for event n. (The detection of edges on outputs lag the
conditions that switch the outputs by one SCT clock). In order to guarantee proper
edge/state detection, an input must have a minimum pulse width of at least one SCT
clock period .
0
0x0
LOW
0x1
Rise
0x2
Fall
0x3
HIGH
Selects how the specified match and I/O condition are used and combined.
0x0
OR. The event occurs when either the specified match or I/O condition occurs.
0x1
MATCH. Uses the specified match only.
0x2
IO. Uses the specified I/O condition only.
0x3
AND. The event occurs when the specified match and I/O condition occur
simultaneously.
STATELD
User manual
0
Selects the inputs elected by IOSEL.
13:12 COMBMODE
UM10736
0
0
11:10 IOCOND
14
Selects the Match register associated with this event (if any). A match can occur only 0
when the counter selected by the HEVENT bit is running.
Select L/H counter. Do not set this bit if UNIFY = 1.
OUTSEL
IOSEL
Reset
value
This bit controls how the STATEV value modifies the state selected by HEVENT when
this event is the highest-numbered event occurring for that state.
0
STATEV value is added into STATE (the carry-out is ignored).
1
STATEV value is loaded into STATE.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
Table 260. SCT event control register 0 to 9 (EV[0:9]_CTRL, address 0x1C02 0304 (EV0_CTRL) to 0x1C02 034C
(EV9_CTRL) (SCT2) and 0x1C02 4304 (EV0_CTRL) to 0x1C02 434C (EV9_CTRL) (SCT3)) bit description
Bit
Symbol
Value Description
Reset
value
19:15 STATEV
This value is loaded into or added to the state selected by HEVENT, depending on
STATELD, when this event is the highest-numbered event occurring for that state. If
STATELD and STATEV are both zero, there is no change to the STATE value.
20
If this bit is one and the COMBMODE field specifies a match component to the
triggering of this event, then a match is considered to be active whenever the counter
value is GREATER THAN OR EQUAL TO the value specified in the match register
when counting up, LESS THEN OR EQUAL TO the match value when counting down.
MATCHMEM
If this bit is zero, a match is only be active during the cycle when the counter is equal
to the match value.
22:21 DIRECTION
Direction qualifier for event generation. This field only applies when the counters are
operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is
reserved.
0x0
Direction independent. This event is triggered regardless of the count direction.
0x1
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2
Counting down. This event is triggered only during down-counting when BIDIR = 1.
31:23 -
Reserved
16.6.25 SCT output set registers 0 to 5
Each output n has one set register that controls how events affect each output. Whether
outputs are set or cleared depends on the setting of the SETCLRn field in the
OUTPUTDIRCTRL register.
Remark: If the SCTimer/PWM is operating as two 16-bit counters, events can only modify
the state of the outputs when neither counter is halted. This is true regardless of what
triggered the event.
Table 261. SCT output set register (OUT[0:5]_SET, address 0x1C02 0500 (OUT0_SET) to
0x1C02 0528 (OUT5_SET) (SCT2) and 0x1C02 4500 (OUT0_SET) to 0x1C02 4528
(OUT5_SET) (SCT3)) bit description
Bit
Symbol
Description
Reset
value
9:0
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 9 = bit 9.
31:10
-
Reserved
16.6.26 SCT output clear registers 0 to 5
Each output n has one clear register that controls how events affect each output. Whether
outputs are set or cleared depends on the setting of the SETCLRn field in the
OUTPUTDIRCTRL register.
Remark: If the SCTimer/PWM is operating as two 16-bit counters, events can only modify
the state of the outputs when neither counter is halted. This is true regardless of what
triggered the event.
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Chapter 16: Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM)
Table 262. SCT output clear register (OUT[0:5]_CLR, address 0x1C02 0504 (OUT0_CLR) to
0x1C02 052C (OUT5_CLR) (SCT2) and 0x1C02 4504 (OUT0_CLR) to 0x1C02452C
(OUT5_CLR) (SCT2)) bit description
Bit
Symbol
Description
Reset
value
9:0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 9 = bit 9.
31:10
-
Reserved
16.7 Functional description
The small SCTs are functionally the same as the large SCTs. However, the dither engine
is not implemented. For a functional description of the SCT, see Section 15.7.
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Chapter 17: LPC15xx Windowed Watchdog Timer (WWDT)
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User manual
17.1 How to read this chapter
The watchdog timer is identical on all LPC15xx parts.
17.2 Features
• Internally resets chip if not reloaded during the programmable time-out period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time-out period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Programmable 24-bit timer with internal fixed pre-scaler.
• Selectable time period from 1,024 watchdog clocks (TWDCLK  256  4) to over 67
million watchdog clocks (TWDCLK  224  4) in increments of 4 watchdog clocks.
• “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog
reset to be disabled.
• Incorrect feed sequence causes immediate watchdog event if enabled.
• The watchdog reload value can optionally be protected such that it can only be
changed after the “warning interrupt” time is reached.
• Flag to indicate Watchdog reset.
• The Watchdog clock (WDCLK) source is the fixed 503 kHz clock (+/- 40 %) provided
by the low-power watchdog oscillator.
• The Watchdog timer can be configured to run in Deep-sleep or Power-down mode.
• Debug mode.
17.3 Basic configuration
The WWDT is configured through the following registers:
• Power to the register interface (WWDT PCLK clock): In the SYSAHBCLKCTRL0
register, set bit 22 in Table 50.
• Enable the WWDT clock source (the watchdog oscillator) in the PDRUNCFG register
(Table 75). This is the clock source for the timer base.
• For waking up from a WWDT interrupt, enable the watchdog interrupt for wake-up in
the STARTERP0 register (Table 76).
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Chapter 17: LPC15xx Windowed Watchdog Timer (WWDT)
::'7
6<6&21
V\VWHPFORFN
::'7UHJLVWHUV
6<6$+%&/.&75/
::'7FORFNHQDEOH
N+]
ZDWFKGRJRVFLOODWRU
ELWWLPHU
79
3'581&)*
HQDEOHZDWFKGRJRVFLOODWRU
:'726&B3'
Fig 45. WWDT timing
17.4 Pin description
The WWDT has no external pins.
17.5 General description
The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a
programmable time if it enters an erroneous state. When enabled, a watchdog reset is
generated if the user program fails to feed (reload) the Watchdog within a predetermined
amount of time.
When a watchdog window is programmed, an early watchdog feed is also treated as a
watchdog event. This allows preventing situations where a system failure may still feed
the watchdog. For example, application code could be stuck in an interrupt service that
contains a watchdog feed. Setting the window such that this would result in an early feed
will generate a watchdog event, allowing for system recovery.
The Watchdog consists of a fixed (divide by 4) pre-scaler and a 24-bit counter which
decrements when clocked. The minimum value from which the counter decrements is
0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence the
minimum Watchdog interval is (TWDCLK  256  4) and the maximum Watchdog interval is
(TWDCLK  224  4) in multiples of (TWDCLK  4). The Watchdog should be used in the
following manner:
• Set the Watchdog timer constant reload value in the TC register.
• Set the Watchdog timer operating mode in the MOD register.
• Set a value for the watchdog window time in the WINDOW register if windowed
operation is desired.
• Set a value for the watchdog warning interrupt in the WARNINT register if a warning
interrupt is desired.
• Enable the Watchdog by writing 0xAA followed by 0x55 to the FEED register.
• The Watchdog must be fed again before the Watchdog counter reaches zero in order
to prevent a watchdog event. If a window value is programmed, the feed must also
occur after the watchdog counter passes that value.
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Chapter 17: LPC15xx Windowed Watchdog Timer (WWDT)
When the Watchdog Timer is configured so that a watchdog event will cause a reset and
the counter reaches zero, the CPU will be reset, loading the stack pointer and program
counter from the vector table as for an external reset. The Watchdog time-out flag
(WDTOF) can be examined to determine if the Watchdog has caused the reset condition.
The WDTOF flag must be cleared by software.
When the Watchdog Timer is configured to generate a warning interrupt, the interrupt will
occur when the counter matches the value defined by the WARNINT register.
17.5.1 Block diagram
The block diagram of the Watchdog is shown below in the Figure 46. The synchronization
logic (PCLK - WDCLK) is not shown in the block diagram.
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Fig 46. Windowed Watchdog timer block diagram
17.5.2 Clocking and power control
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers and is derived from the system clock (see Figure 3).
The WDCLK is used for the watchdog timer counting and is derived from the watchdog
oscillator.
The synchronization logic between the two clock domains works as follows: When the
MOD and TC registers are updated by APB operations, the new value will take effect in 3
WDCLK cycles on the logic in the WDCLK clock domain.
When the watchdog timer is counting on WDCLK, the synchronization logic will first lock
the value of the counter on WDCLK and then synchronize it with PCLK, so that the CPU
can read the WDTV register.
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Chapter 17: LPC15xx Windowed Watchdog Timer (WWDT)
Remark: Because of the synchronization step, software must add a delay of three
WDCLK clock cycles between the feed sequence and the time the WDPROTECT bit is
enabled in the MOD register. The length of the delay depends on the selected watchdog
clock WDCLK.
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Chapter 17: LPC15xx Windowed Watchdog Timer (WWDT)
17.5.3 Using the WWDT lock features
The WWDT supports the following lock features which can be enabled to ensure that the
WWDT is running at all times:
• Disabling the WWDT clock source
• Changing the WWDT reload value
17.5.3.1 Disabling the WWDT clock source
If bit 5 in the WWDT MOD register is set, the WWDT clock source is locked and the
watchdog oscillator can not be disabled either by software or by hardware when Sleep,
Deep-sleep or Power-down modes are entered.
17.5.3.2 Changing the WWDT reload value
If bit 4 is set in the WWDT MOD register, the watchdog time-out value (TC) can be
changed only after the counter is below the value of WDWARNINT and WDWINDOW.
The reload overwrite lock mechanism can only be disabled by a reset of any type.
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Chapter 17: LPC15xx Windowed Watchdog Timer (WWDT)
17.6 Register description
The Watchdog Timer contains the registers shown in Table 263.
The reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Table 263. Register overview: Watchdog timer (base address 0x4002 C000)
Name
Access Address Description
offset
MOD
R/W
0x000
Watchdog mode register. This
0
register contains the basic mode and
status of the Watchdog Timer.
Table 264
TC
R/W
0x004
Watchdog timer constant register.
This 24-bit register determines the
time-out value.
Table 266
FEED
WO
0x008
Watchdog feed sequence register.
NA
Writing 0xAA followed by 0x55 to this
register reloads the Watchdog timer
with the value contained in WDTC.
Table 267
TV
RO
0x00C
Watchdog timer value register. This
24-bit register reads out the current
value of the Watchdog timer.
0xFF
Table 268
-
-
0x010
Reserved
-
-
WARNINT R/W
0x014
Watchdog Warning Interrupt compare 0
value.
WINDOW
0x018
Watchdog Window compare value.
R/W
Reset
value
0xFF
Reference
Table 269
0xFF FFFF Table 270
17.6.1 Watchdog mode register
The WDMOD register controls the operation of the Watchdog. Note that a watchdog feed
must be performed before any changes to the WDMOD register take effect.
Table 264. Watchdog mode register (MOD, 0x4002 C000) bit description
Bit
Symbol
0
WDEN
1
2
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Value Description
Watchdog enable bit. Once this bit has been written with 0
a 1, it cannot be re-written with a 0. Once this bit is set
to one and performing a watchdog feed, the watchdog
timer starts running permanently.
0
Stop. The watchdog timer is stopped.
1
Run. The watchdog timer is running.
WDRESET
WDTOF
Reset
value
Watchdog reset enable bit. Once this bit has been
written with a 1 it cannot be re-written with a 0.
0
Interrupt. A watchdog time-out will not cause a chip
reset.
1
Reset. A watchdog time-out will cause a chip reset.
Watchdog time-out flag. Set when the watchdog timer
times out, by a feed error, or by events associated with
WDPROTECT. Cleared by software. Causes a chip
reset if WDRESET = 1.
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0 (only
after
external
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Chapter 17: LPC15xx Windowed Watchdog Timer (WWDT)
Table 264. Watchdog mode register (MOD, 0x4002 C000) bit description
Bit
Symbol
3
WDINT
Warning interrupt flag. Set when the timer reaches the
value in WDWARNINT. Cleared by software.
0
4
WDPROTECT
Watchdog update mode. This bit can be set once by
software and is only cleared by a reset.
0
5
Value Description
Reset
value
0
Flexible. The watchdog time-out value (TC) can be
changed at any time.
1
Threshold. The watchdog time-out value (TC) can be
changed only after the counter is below the value of
WDWARNINT and WDWINDOW.
LOCK
A 1 in this bit prevents disabling or powering down the 0
watchdog oscillator. This bit can be set once by software
and is only cleared by any reset.
31:6 -
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
Once the WDEN, WDPROTECT, or WDRESET bits are set they can not be cleared by
software. Both flags are cleared by an external reset or a Watchdog timer reset.
WDTOF The Watchdog time-out flag is set when the Watchdog times out, when a feed
error occurs, or when PROTECT =1 and an attempt is made to write to the TC register.
This flag is cleared by software writing a 0 to this bit.
WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value
specified by WARNINT. This flag is cleared when any reset occurs, and is cleared by
software by writing a 0 to this bit.
In all power modes except Deep power-down mode, a Watchdog reset or interrupt can
occur when the watchdog is running and has an operating clock source. The watchdog
oscillator can be configured to keep running in Sleep, Deep-sleep modes, and
Power-down modes.
If a watchdog interrupt occurs in Sleep, Deep-sleep mode, or Power-down mode, and the
WWDT interrupt is enabled in the NVIC, the device will wake up. Note that in Deep-sleep
and Power-down modes, the WWDT interrupt must be enabled in the STARTERP0
register in addition to the NVIC.
See the following registers:
Table 76 “Start logic 0 wake-up enable register 0 (STARTERP0, address 0x4007 4218) bit
description”
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Chapter 17: LPC15xx Windowed Watchdog Timer (WWDT)
Table 265. Watchdog operating modes selection
WDEN WDRESET Mode of Operation
0
X (0 or 1)
Debug/Operate without the Watchdog running.
1
0
Watchdog interrupt mode: the watchdog warning interrupt will be generated
but watchdog reset will not.
When this mode is selected, the watchdog counter reaching the value
specified by WDWARNINT will set the WDINT flag and the Watchdog
interrupt request will be generated.
1
1
Watchdog reset mode: both the watchdog interrupt and watchdog reset are
enabled.
When this mode is selected, the watchdog counter reaching the value
specified by WDWARNINT will set the WDINT flag and the Watchdog
interrupt request will be generated, and the watchdog counter reaching zero
will reset the microcontroller. A watchdog feed prior to reaching the value of
WDWINDOW will also cause a watchdog reset.
17.6.2 Watchdog Timer Constant register
The TC register determines the time-out value. Every time a feed sequence occurs the
value in the TC is loaded into the Watchdog timer. The TC resets to 0x00 00FF. Writing a
value below 0xFF will cause 0x00 00FF to be loaded into the TC. Thus the minimum
time-out interval is TWDCLK  256  4.
If the WDPROTECT bit in WDMOD = 1, an attempt to change the value of TC before the
watchdog counter is below the values of WDWARNINT and WDWINDOW will cause a
watchdog reset and set the WDTOF flag.
Table 266. Watchdog Timer Constant register (TC, 0x4002 C004) bit description
Bit
Symbol Description
Reset
Value
23:0
COUNT Watchdog time-out value.
0x00 00FF
31:24 -
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
17.6.3 Watchdog Feed register
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
Watchdog. A valid feed sequence must be completed after setting WDEN before the
Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
errors.
After writing 0xAA to WDFEED, access to any Watchdog register other than writing 0x55
to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled, and sets
the WDTOF flag. The reset will be generated during the second PCLK following an
incorrect access to a Watchdog register during a feed sequence.
It is good practice to disable interrupts around a feed sequence, if the application is such
that an interrupt might result in rescheduling processor control away from the current task
in the middle of the feed, and then lead to some other access to the WDT before control is
returned to the interrupted task.
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Chapter 17: LPC15xx Windowed Watchdog Timer (WWDT)
Table 267. Watchdog Feed register (FEED, 0x4002 C008) bit description
Bit
Symbol
Description
Reset Value
7:0
FEED
Feed value should be 0xAA followed by 0x55.
NA
31:8
-
Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
17.6.4 Watchdog Timer Value register
The WDTV register is used to read the current value of Watchdog timer counter.
When reading the value of the 24-bit counter, the lock and synchronization procedure
takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the
actual value of the timer when it's being read by the CPU.
Table 268. Watchdog Timer Value register (TV, 0x4002 C00C) bit description
Bit
Symbol Description
Reset
Value
23:0
COUNT Counter timer value.
0x00 00FF
31:24 -
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
17.6.5 Watchdog Timer Warning Interrupt register
The WDWARNINT register determines the watchdog timer counter value that will
generate a watchdog interrupt. When the watchdog timer counter matches the value
defined by WARNINT, an interrupt will be generated after the subsequent WDCLK.
A match of the watchdog timer counter to WARNINT occurs when the bottom 10 bits of
the counter have the same value as the 10 bits of WARNINT, and the remaining upper bits
of the counter are all 0. This gives a maximum time of 1,023 watchdog timer counts (4,096
watchdog clocks) for the interrupt to occur prior to a watchdog event. If WARNINT is 0, the
interrupt will occur at the same time as the watchdog event.
Table 269. Watchdog Timer Warning Interrupt register (WARNINT, 0x4002 C014) bit
description
Bit
Symbol
9:0
WARNINT Watchdog warning interrupt compare value.
31:10 -
Description
Reset
Value
0
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
17.6.6 Watchdog Timer Window register
The WINDOW register determines the highest WDTV value allowed when a watchdog
feed is performed. If a feed sequence occurs when WDTV is greater than the value in
WINDOW, a watchdog event will occur.
WINDOW resets to the maximum possible WDTV value, so windowing is not in effect.
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Chapter 17: LPC15xx Windowed Watchdog Timer (WWDT)
Table 270. Watchdog Timer Window register (WINDOW, 0x4002 C018) bit description
Bit
Symbol
Description
23:0
WINDOW Watchdog window value.
31:24 -
Reset
Value
0xFF FFFF
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
17.7 Functional description
The following figures illustrate several aspects of Watchdog Timer operation.
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Chapter 18: LPC15xx Real-Time Clock (RTC)
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User manual
18.1 How to read this chapter
18.2 Features
• The RTC resides in a separate always-on voltage domain with battery back-up. The
RTC uses an independent oscillator, also in the always-on voltage domain, which has
the following clock outputs:
– 32 kHz clock, selectable for system clock and CLKOUT pin.
– 1 Hz clock for RTC timing.
– 1 kHz clock for high-resolution RTC timing.
• 32-bit, 1 Hz RTC counter and associated match register for alarm generation.
• Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution
with a more that one minute maximum time-out period.
• RTC alarm and high-resolution/wake-up timer time-out each generate independent
interrupt requests. Either time-out can wake up the part from any of the low power
modes, including Deep power-down.
18.3 Basic configuration
Configure the RTC as follows:
• Use the SYSAHBCLKCTRL0 register (Table 50) to enable the clock to the RTC
register interface and peripheral clock.
• For RTC software reset use the RTC CTRL register. See Table 272.
• The RTC provides two interrupt lines to the NVIC:
a. Interrupt raised on a match of the RTC 1 Hz counter connected to NVIC slot #45
(RTC_ALARM).
b. Interrupt raised on a match of the RTC 1 kHz counter connected to NVIC slot #46
(RTC_WAKE).
• To enable the RTC interrupts for waking up from Deep-sleep and Power-down modes,
enable the interrupts in the STARTLOGIC1 register (Table 77) and the NVIC.
• To enable the RTC interrupts for waking up from Deep power-down, enable the
appropriate RTC clock and wake-up in the RTC CTRL register (Table 272).
• The RTC has no external pins.
• The RTC oscillator is always running, and therefore the 32 kHz output is always
available to be enabled for syscon clock generation (see Table 67). Once enabled, the
32 kHz clock can be selected for the system clock or be observed through the
CLKOUT pin. The 1 Hz output is enabled in the RTC CTRL register (RTC_EN bit).
Once the 1 Hz output is enabled, you can enable the 1 KHz output for the
high-resolution wake-up timer.
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Chapter 18: LPC15xx Real-Time Clock (RTC)
• Enable the RTC oscillator that provides the RTC’s 1 Hz and 1 kHz clocks in the
syscon block. See Table 67.
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Fig 50. RTC clocking
18.3.1 RTC timers
The RTC contains two timers:
1. The main RTC timer. This 32-bit timer uses a 1 Hz clock and is intended to run
continuously as a real-time clock. When the timer value reaches a match value, an
interrupt is raised. The alarm interrupt can also wake up the part from any low power
mode if enabled.
2. The high-resolution/wake-up timer. This 16-bit timer uses a 1 kHz clock and operates
as a one-shot down timer. Once the timer is loaded, it starts counting down to 0 at
which point an interrupt is raised. The interrupt can wake up the part from any low
power mode if enabled. This timer is intended to be used for timed wake-up from
Deep-sleep, power-down, or Deep power-down modes. The high-resolution wake-up
timer can be disabled to conserve power if not used.
18.4 General description
18.4.1 Real-time clock
The real-time clock is a 32-bit up-counter which can be cleared or initialized by software.
Once enabled, it counts continuously at a 1 Hz clock rate as long as the RTC module
remains powered and enabled.
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Chapter 18: LPC15xx Real-Time Clock (RTC)
The main purpose of the RTC is to count seconds and generate an alarm interrupt to the
processor whenever the counter value equals the value programmed into the associated
32-bit match register.
If the part is in one of the reduced-power modes (deep-sleep, power-down, deep
power-down) an RTC alarm interrupt can also wake up the part to exit the power mode
and begin normal operation.
18.4.2 High-resolution/wake-up timer
The time interval required for many applications, including waking the part up from a
low-power mode, will often demand a greater degree of resolution than the one-second
minimum interval afforded by the main RTC counter. For these applications, a higher
frequency secondary timer has been provided.
This secondary timer is an independent, stand-alone wake-up or general-purpose timer
for timing intervals of up to 64 seconds with approximately one millisecond of resolution.
The High-Resolution/Wake-up Timer is a 16-bit down counter which is clocked at a 1 kHz
rate when it is enabled. Writing any non-zero value to this timer will automatically enable
the counter and launch a countdown sequence. When the counter is being used as a
wake-up timer, this write can occur just prior to entering a reduced power mode.
When a starting count value is loaded, the High-Resolution/Wake-up Timer will turn on,
count from the pre-loaded value down to zero, generate an interrupt and/or a wake-up
command, and then turn itself off until re-launched by a subsequent software write.
18.4.3 RTC power domain
The RTC module and the 1 Hz/1 kHz clock that drives it, reside in the battery backup
always-on voltage domain. As a result, the RTC will continue operating in deep
power-down mode when power is removed from the rest of the part. The RTC will also
continue to operate in the event that power fails, until the backup battery runs out.
18.5 Register description
Reset Values pertain to initial power-up of the always-on power domain or when an RTC
software reset is applied (except where noted). This block is not initialized by a standard
POR, pad reset, or by any other system reset.
Table 271. Register overview: RTC (base address 0x4002 8000)
UM10736
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Name
Access
Offset
Description
Reset
value
Reference
CTRL
R/W
0x000
RTC control register
0xF
Table 272
MATCH
R/W
0x004
RTC match register
0xFFFF
Table 273
COUNT
R/W
0x008
RTC counter register
0
Table 274
WAKE
R/W
0x00C
RTC high-resolution/wake-up timer
control register
0
Table 275
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Chapter 18: LPC15xx Real-Time Clock (RTC)
18.5.1 RTC CTRL register
This register controls which clock the RTC uses (1 kHz or 1 Hz) and enables the two RTC
interrupts to wake up the part from Deep power-down. To wake up the part from
Deep-sleep or Power-down modes, enable the RTC interrupts in the system control block
STARTLOGIC1 register.
Table 272. RTC control register (CTRL, address 0x4002 8000) bit description
Bit
Symbol
0
SWRESET
Value
Description
Reset
value
Software reset control
1
0
Not in reset. The RTC is not held in reset. This bit must be cleared prior
to configuring or initiating any operation of the RTC.
1
In reset. The RTC is held in reset.
All register bits within the RTC will be forced to their reset value except
the OFD bit.
This bit must be cleared before writing to any register in the RTC including writes to set any of the other bits within this register.
Do not attempt to write to any bits of this register at the same time that
the reset bit is being cleared.
Remark: This bit may also serve as a Power Fail Detect flag for the
always-on voltage domain.
1
2
3
4
5
OFD
Oscillator fail detect status. There is a delay before this bit is updated.
0
Run. The RTC oscillator is running properly. Writing a 0 has no effect.
1
Fail. RTC oscillator fail detected. Clear this flag after the following
power-up. Writing a 1 clears this bit.
0
No match. No match has occurred on the 1 Hz RTC timer. Writing a 0
has no effect.
1
Match. A match condition has occurred on the 1 Hz RTC timer. This flag
generates an RTC alarm interrupt request RTC_ALARM which can also
wake up the part from any low power mode. Writing a 1 clears this bit.
ALARM1HZ
RTC 1 Hz timer alarm flag status.
WAKE1KHZ
User manual
1
0
Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.
1
Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This
flag generates an RTC wake-up interrupt request RTC-WAKE which can
also wake up the part from any low power mode. Writing a 1 clears this
bit.
RTC 1 Hz timer alarm enable for Deep power-down.
0
0
Disable. A match on the 1 Hz RTC timer will not bring the part out of
Deep power-down mode.
1
Enable. A match on the 1 Hz RTC timer bring the part out of Deep
power-down mode.
WAKEDPD_EN
UM10736
1
RTC 1 kHz timer wake-up flag status.
ALARMDPD_EN
RTC 1 kHz timer wake-up enable for Deep power-down.
0
0
Disable. A match on the 1 kHz RTC timer will not bring the part out of
Deep power-down mode.
1
Enable. A match on the 1 kHz RTC timer bring the part out of Deep
power-down mode.
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Chapter 18: LPC15xx Real-Time Clock (RTC)
Table 272. RTC control register (CTRL, address 0x4002 8000) bit description
Bit
Symbol
6
RTC1KHZ_EN
Value
Description
Reset
value
RTC 1 kHz clock enable.
0
This bit can be set to 0 to conserve power if the 1 kHz timer is not used.
This bit has no effect when the RTC is disabled (bit 7 of this register is 0).
7
31:8
0
Disable. A match on the 1 kHz RTC timer will not bring the part out of
Deep power-down mode.
1
Enable. The 1 kHz RTC timer is enabled.
RTC_EN
RTC enable.
0
0
Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC
operation is disabled. This bit should be 0 when writing to load a value in
the RTC counter register.
1
Enable. The 1 Hz RTC clock is running and RTC operation is enabled.
You must set this bit to initiate operation of the RTC. The first clock to the
RTC counter occurs 1 s after this bit is set. To also enable the
high-resolution, 1 kHz clock, set bit 6 in this register.
-
Reserved
0
18.5.2 RTC match register
Table 273. RTC match register (MATCH, address 0x4002 8004) bit description
Bit
Symbol
Description
Reset
value
31:0
MATVAL
Contains the match value against which the 1 Hz RTC timer will
be compared to generate set the alarm flag RTC_ALARM and
generate an alarm interrupt/wake-up if enabled.
0xFFFF
18.5.3 RTC counter register
Table 274. RTC counter register (COUNT, address 0x4002 8008) bit description
Bit
Symbol
Description
Reset
value
31:0
VAL
A read reflects the current value of the main, 1 Hz RTC timer.
0
A write loads a new initial value into the timer.
The RTC counter will count up continuously at a 1 Hz rate once the
RTC Software Reset is removed (by clearing bit 0 of the CTRL
register).
Remark: Only write to this register when the RTC_EN bit in the RTC
CTRL Register is 0.
The counter increments one second after the RTC_EN bit is set.
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Chapter 18: LPC15xx Real-Time Clock (RTC)
18.5.4 RTC high-resolution/wake-up register
Table 275. RTC high-resolution/wake-up register (WAKE, address 0x4002 800C) bit
description
Bit
Symbol
Description
Reset
value
15:0
VAL
A read reflects the current value of the high-resolution/wake-up timer. 0
A write pre-loads a start count value into the wake-up timer and
initializes a count-down sequence.
Do not write to this register while counting is in progress.
31:16
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Chapter 19: LPC15xx Multi-Rate Timer (MRT)
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User manual
19.1 How to read this chapter
The MRT is available on all LPC15xx parts.
19.2 Features
• 24-bit interrupt timer
• Four channels independently counting down from individually set values
• Repeat and one-shot interrupt modes
19.3 Basic configuration
Configure the MRT using the following registers:
• In the SYSAHBCLKCTRL1 register, set bit 0 (Table 51) to enable the clock to the
register interface.
• Clear the MRT reset using the PRESETCTRL1 register (Table 36).
• The global MRT interrupt is connected to interrupt #20 in the NVIC.
057
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Fig 51. MRT clocking
19.4 Pin description
The MRT has no configurable pins.
19.5 General description
The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each
channel can be programmed with an independent time interval.
Each channel operates independently from the other channels in one of the following
modes:
• Repeat interrupt mode. See Section 19.5.1.
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Chapter 19: LPC15xx Multi-Rate Timer (MRT)
• One-shot interrupt mode. See Section 19.5.2.
The modes for each timer are set in the timer’s control register. See Table 279.
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Fig 52. MRT block diagram
19.5.1 Repeat interrupt mode
The repeat interrupt mode generates repeated interrupts after a selected time interval.
This mode can be used for software-based PWM or PPM applications.
When the timer n is in idle state, writing a non-zero value IVALUE to the INTVALn register
immediately loads the time interval value IVALUE - 1, and the timer begins to count down
from this value. When the timer reaches zero, an interrupt is generated, the value in the
INTVALn register IVALUE - 1 is reloaded automatically, and the timer starts to count down
again.
While the timer is running in repeat interrupt mode, you can perform the following actions:
• Change the interval value on the next timer cycle by writing a new value (>0) to the
INTVALn register and setting the LOAD bit to 0. An interrupt is generated when the
timer reaches zero. On the next cycle, the timer counts down from the new value.
• Change the interval value on-the-fly immediately by writing a new value (>0) to the
INTVALn register and setting the LOAD bit to 1. The timer immediately starts to count
down from the new timer interval value. An interrupt is generated when the timer
reaches 0.
• Stop the timer at the end of time interval by writing a 0 to the INTVALn register and
setting the LOAD bit to 0. An interrupt is generated when the timer reaches zero.
• Stop the timer immediately by writing a 0 to the INTVALn register and setting the
LOAD bit to 1. No interrupt is generated when the INTVALn register is written.
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Chapter 19: LPC15xx Multi-Rate Timer (MRT)
19.5.2 One-shot interrupt mode
The one-shot interrupt generates one interrupt after a one-time count. With this mode, you
can generate a single interrupt at any point. This mode can be used to introduce a specific
delay in a software task.
When the timer is in the idle state, writing a non-zero value IVALUE to the INTVALn
register immediately loads the time interval value IVALUE - 1, and the timer starts to count
down. When the timer reaches 0, an interrupt is generated and the timer stops and enters
the idle state.
While the timer is running in the one-shot interrupt mode, you can perform the following
actions:
• Update the INTVALn register with a new time interval value (>0) and set the LOAD bit
to 1. The timer immediately reloads the new time interval, and starts counting down
from the new value. No interrupt is generated when the TIME_INTVALn register is
updated.
• Write a 0 to the INTVALn register and set the LOAD bit to 1. The timer immediately
stops counting and moves to the idle state. No interrupt is generated when the
INTVALn register is updated.
19.6 Register description
The reset values shown in Table 276 are POR reset values.
Table 276. Register overview: MRT (base address 0x400A 0000)
Name
Access
Address Description
offset
Reset value
Reference
INTVAL0
R/W
0x0
MRT0 Time interval value register. This value is
loaded into the TIMER0 register.
0
Table 277
TIMER0
R
0x4
MRT0 Timer register. This register reads the value
of the down-counter.
0xFF FFFF
Table 278
CTRL0
R/W
0x8
MRT0 Control register. This register controls the
MRT0 modes.
0
Table 279
STAT0
R/W
0xC
MRT0 Status register.
0
Table 280
INTVAL1
R/W
0x10
MRT1 Time interval value register. This value is
loaded into the TIMER1 register.
0
Table 277
TIMER1
R/W
0x14
MRT1 Timer register. This register reads the value
of the down-counter.
0xFF FFFF
Table 278
CTRL1
R/W
0x18
MRT1 Control register. This register controls the
MRT1 modes.
0
Table 279
STAT1
R/W
0x1C
MRT1 Status register.
0
Table 280
INTVAL2
R/W
0x20
MRT2 Time interval value register. This value is
loaded into the TIMER2 register.
0
Table 277
TIMER2
R/W
0x24
MRT2 Timer register. This register reads the value
of the down-counter.
0xFF FFFF
Table 278
CTRL2
R/W
0x28
MRT2 Control register. This register controls the
MRT2 modes.
0
Table 279
STAT2
R/W
0x2C
MRT2 Status register.
0
Table 280
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Chapter 19: LPC15xx Multi-Rate Timer (MRT)
Table 276. Register overview: MRT (base address 0x400A 0000)
Name
Access
Address Description
offset
Reset value
Reference
INTVAL3
R/W
0x30
MRT3 Time interval value register. This value is
loaded into the TIMER3 register.
0
Table 277
TIMER3
R/W
0x34
MRT3 Timer register. This register reads the value
of the down-counter.
0xFF FFFF
Table 278
CTRL3
R/W
0x38
MRT3 Control register. This register controls the
MRT modes.
0
Table 279
STAT3
R/W
0x3C
MRT3 Status register.
0
Table 280
IDLE_CH
R
0xF4
Idle channel register. This register returns the
number of the first idle channel.
0
Table 281
IRQ_FLAG
R/W
0xF8
Global interrupt flag register
0
Table 282
19.6.1 Time interval register
This register contains the MRT load value and controls how the timer is reloaded. The
load value is IVALUE -1.
Table 277. Time interval register (INTVAL[0:3], address 0x400A 0000 (INTVAL0) to 0x400A
0030 (INTVAL3)) bit description
Bit
Symbol Value
Description
Reset
value
23:0
IVALUE
Time interval load value. This value is loaded into the
TIMERn register and the MRT channel n starts counting
down from IVALUE -1.
0
If the timer is idle, writing a non-zero value to this bit field
starts the timer immediately.
If the timer is running, writing a zero to this bit field does the
following:
•
•
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If LOAD = 1, the timer stops immediately.
If LOAD = 0, the timer stops at the end of the time
interval.
30:24
-
Reserved.
-
31
LOAD
Determines how the timer interval value IVALUE -1 is
loaded into the TIMERn register. This bit is write-only.
Reading this bit always returns 0.
0
0
No force load. The load from the INTVALn register to the
TIMERn register is processed at the end of the time interval
if the repeat mode is selected.
1
Force load. The INTVALn interval value IVALUE -1 is
immediately loaded into the TIMERn register while TIMERn
is running.
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Chapter 19: LPC15xx Multi-Rate Timer (MRT)
19.6.2 Timer register
The timer register holds the current timer value. This register is read-only.
Table 278. Timer register (TIMER[0:3], address 0x400A 0004 (TIMER0) to 0x400A 0034
(TIMER3)) bit description
Bit
Symbol Description
Reset
value
23:0
VALUE
0x00FF
FFFF
Holds the current timer value of the down-counter. The initial value
of the TIMERn register is loaded as IVALUE - 1 from the INTVALn
register either at the end of the time interval or immediately in the
following cases:
INTVALn register is updated in the idle state.
INTVALn register is updated with LOAD = 1.
When the timer is in idle state, reading this bit fields returns -1
(0x00FF FFFF).
31:24
-
Reserved.
0
19.6.3 Control register
The control register configures the mode for each MRT and enables the interrupt.
Table 279. Control register (CTRL[0:3], address 0x400A 0008 (CTRL0) to 0x400A 0038
(CTRL3)) bit description
Bit
Symbol
0
INTEN
Value
0
1
2:1
31:3
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MODE
-
Description
Reset
value
Enable the TIMERn interrupt.
0
Disable.
Enable.
Selects timer mode.
0x0
Repeat interrupt mode.
0x1
One-shot interrupt mode.
0x2
Reserved.
0x3
Reserved.
Reserved.
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Chapter 19: LPC15xx Multi-Rate Timer (MRT)
19.6.4 Status register
This register indicates the status of each MRT.
Table 280. Status register (STAT[0:3], address 0x400A 000C (STAT0) to 0x400A 003C
(STAT3)) bit description
Bit
Symbol
0
INTFLAG
Value
Description
Reset
value
Monitors the interrupt flag.
0
0
No pending interrupt. Writing a zero is equivalent to no
operation.
1
Pending interrupt. The interrupt is pending because
TIMERn has reached the end of the time interval. If the
INTEN bit in the CONTROLn is also set to 1, the
interrupt for timer channel n and the global interrupt are
raised.
Writing a 1 to this bit clears the interrupt request.
1
31:2
RUN
Indicates the state of TIMERn. This bit is read-only.
0
Idle state. TIMERn is stopped.
1
Running. TIMERn is running.
-
Reserved.
0
0
19.6.5 Idle channel register
The idle channel register returns the lowest idle channel number. The channel is
considered idle when both flags in the STATUS register (RUN and INTFLAG) are zero.
In an application with multiple timers running independently, you can calculate the register
offset of the next idle timer by reading the idle channel number in this register. The idle
channel register allows you set up the next idle timer without checking the idle state of
each timer.
Table 281. Idle channel register (IDLE_CH, address 0x400A 00F4) bit description
Bit
Symbol
Description
Reset
value
3:0
-
Reserved.
0
7:4
CHAN
Idle channel. Reading the CHAN bits, returns the lowest idle timer
channel. If all timer channels are running, CHAN = 0xF.
0
To make sure that all outstanding interrupt requests have been
serviced, a channel is considered idle only when both the
corresponding RUN bit and the interrupt flag are zero in the STATUS
register.
31:8
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Chapter 19: LPC15xx Multi-Rate Timer (MRT)
19.6.6 Global interrupt flag register
The global interrupt register combines the interrupt flags from the individual timer
channels in one register. Setting and clearing each flag behaves in the same way as
setting and clearing the INTFLAG bit in each of the STATUSn registers.
Table 282. Global interrupt flag register (IRQ_FLAG, address 0x400A 00F8) bit description
Bit
Symbol
0
GFLAG0
Value Description
Reset
value
Monitors the interrupt flag of TIMER0.
0
0
No pending interrupt. Writing a zero is equivalent to no
operation.
1
Pending interrupt. The interrupt is pending because TIMER0
has reached the end of the time interval. If the INTEN bit in the
CONTROL0 register is also set to 1, the interrupt for timer
channel 0 and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt request.
1
GFLAG1
Monitors the interrupt flag of TIMER1.
0
0
No pending interrupt. Writing a zero is equivalent to no
operation.
1
Pending interrupt. The interrupt is pending because TIMER1
has reached the end of the time interval. If the INTEN bit in the
CONTROL1 register is also set to 1, the interrupt for timer
channel 1 and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt request.
2
GFLAG2
Monitors the interrupt flag of TIMER2.
0
0
No pending interrupt. Writing a zero is equivalent to no
operation.
1
Pending interrupt. The interrupt is pending because TIMER2
has reached the end of the time interval. If the INTEN bit in the
CONTROL2 register is also set to 1, the interrupt for timer
channel 2 and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt request.
3
GFLAG3
Monitors the interrupt flag of TIMER3.
0
0
No pending interrupt. Writing a zero is equivalent to no
operation.
1
Pending interrupt. The interrupt is pending because TIMER3
has reached the end of the time interval. If the INTEN bit in the
CONTROL3 register is also set to 1, the interrupt for timer
channel 3 and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt request.
31:4
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Chapter 20: LPC15xx Repetitive Interrupt Timer (RIT)
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User manual
20.1 How to read this chapter
20.2 Features
• 48-bit counter running from the main clock. Counter can be free-running or be reset
by a generated interrupt.
• 48-bit compare value.
• 48-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
20.3 Basic configuration
The RI timer is configured through the following registers:
• Power to the register interface (RI timer clock): In the SYSAHBCLKCTRL1 register,
set bit 1 in Table 51.
20.4 General description
The Repetitive Interrupt Timer (RIT) provides a versatile means of generating interrupts at
specified time intervals, without using a standard timer. It is intended for repeating
interrupts that aren’t related to Operating System interrupts. The RIT could also be used
as an alternative to the Cortex-M3 System Tick Timer if there are different system
requirements.
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Chapter 20: LPC15xx Repetitive Interrupt Timer (RIT)
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Fig 53. Repetitive Interrupt Timer (RI Timer) block diagram
20.5 Register description
Table 283. Register overview: Repetitive Interrupt Timer (RIT) (base address 0x400B 4000)
Reset value[1] Reference
Name
Access
Address
Description
COMPVAL
R/W
0x000
Compare value LSB register. Holds the 32 LSBs of the 0xFFFF FFFF Table 284
compare value.
MASK
R/W
0x004
Mask LSB register. This register holds the 32 LSB s of 0
the mask value. A 1 written to any bit will force the
compare to be true for the corresponding bit of the
counter and compare register.
CTRL
R/W
0x008
Control register.
0xC
Table 286
COUNTER
R/W
0x00C
Counter LSB register. 32 LSBs of the counter.
0
Table 287
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Chapter 20: LPC15xx Repetitive Interrupt Timer (RIT)
Table 283. Register overview: Repetitive Interrupt Timer (RIT) (base address 0x400B 4000)
Address
Description
Reset value[1] Reference
COMPVAL_H R/W
0x010
Compare value MSB register. Holds the 16 MSBs of
the compare value.
0x0000 FFFF
MASK_H
R/W
0x014
Mask MSB register. This register holds the 16 MSBs of 0
the mask value. A ‘1’ written to any bit will force a
compare on the corresponding bit of the counter and
compare register.
Table 285
COUNTER_H R/W
0x01C
Counter MSB register. 16 MSBs of the counter.
Table 287
Name
[1]
Access
0
Table 284
Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.
20.5.1 RI Compare Value LSB register
Table 284. RI Compare Value LSB register (COMPVAL, address 0x400B 4000) bit description
Bit
Symbol
Description
Reset value
31:0
RICOMP
Compare register. Holds the 32 LSBs of the compare value
which is compared to the counter.
0xFFFF FFFF
20.5.2 RI Mask LSB register
Table 285. RI Mask LSB register (MASK, address 0x400B 4004) bit description
Bit
Symbol
Description
Reset
value
31:0
RIMASK
Mask register. This register holds the 32 LSBs of the mask value. A
one written to any bit overrides the result of the comparison for the
corresponding bit of the counter and compare register (causes the
comparison of the register bits to be always true).
0
20.5.3 RI Control register
Table 286. RI Control register (CTRL, address 0x400B 4008) bit description
Bit
Symbol
0
RITINT
Value
1
Description
Reset
value
Interrupt flag
0
This bit is set to 1 by hardware whenever the counter value
equals the masked compare value specified by the contents
of RICOMPVAL and RIMASK registers.
Writing a 1 to this bit will clear it to 0. Writing a 0 has no
effect.
0
1
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RITENCLR
The counter value does not equal the masked compare
value.
Timer enable clear
1
The timer will be cleared to 0 whenever the counter value
0
equals the masked compare value specified by the contents
of COMPVAL/COMPVAL_H and MASK/MASK_H registers.
This will occur on the same clock that sets the interrupt flag.
0
The timer will not be cleared to 0.
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Chapter 20: LPC15xx Repetitive Interrupt Timer (RIT)
Table 286. RI Control register (CTRL, address 0x400B 4008) bit description
Bit
Symbol
2
RITENBR
3
Value
Description
Reset
value
Timer enable for debug
1
1
The timer is halted when the processor is halted for
debugging.
0
Debug has no effect on the timer operation.
RITEN
Timer enable.
1
1
Timer enabled.
Remark: This can be overruled by a debug halt if enabled in
bit 2.
31:4
-
0
Timer disabled.
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
20.5.4 RI Counter LSB register
Table 287. RI Counter register (COUNTER, address 0x400B 400C) bit description
Bit
Symbol
Description
Reset
value
31:0
RICOUNTER
32 LSBs of the up counter. Counts continuously unless RITEN bit
in CTRL register is cleared or debug mode is entered (if enabled
by the RITNEBR bit in RICTRL). Can be loaded to any value in
software.
0
20.5.5 RI Compare Value MSB register
Table 288. RI Compare Value MSB register (COMPVAL_H, address 0x400B 4010) bit
description
Bit
Symbol
Description
Reset value
15:0
RICOMP
Compare value MSB register. Holds the 16 MSBs of the
compare value which is compared to the counter.
0x0000 FFFF
Reserved.
-
31:16 -
20.5.6 RI Mask MSB register
Table 289. RI Mask MSB register (MASK_H, address 0x400B 4014) bit description
UM10736
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Bit
Symbol
Description
15:0
RIMASK
Mask register. This register holds the 16 MSBs of the mask value. A 0
one written to any bit overrides the result of the comparison for the
corresponding bit of the counter and compare register (causes the
comparison of the register bits to be always true).
31:16
-
Reserved.
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value
-
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Chapter 20: LPC15xx Repetitive Interrupt Timer (RIT)
20.5.7 RI Counter MSB register
Table 290. RI Counter MSB register (COUNTER_H, address 0x400B 401C) bit description
UM10736
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Bit
Symbol
Description
15:0
RICOUNTER
16 LSBs of the up counter. Counts continuously unless RITEN bit 0
in RICTRL register is cleared or debug mode is entered (if
enabled by the RITNEBR bit in RICTRL). Can be loaded to any
value in software.
31:16
-
Reserved.
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-
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Chapter 20: LPC15xx Repetitive Interrupt Timer (RIT)
20.6 RI timer operation
Following reset, the counter begins counting up from 0. (The RIT bit must be set in the
SYSAHBCLKCTRL1 register to enable the clock to the RIT.) Whenever the counter value
equals the 48-bit value programmed into the COMPVAL and COMPVAL_H registers, the
interrupt flag will be set. Any bit or combination of bits can be removed from this
comparison (i.e. forced to compare) by writing a 1 to the corresponding bit(s) in the MASK
and MASK_H registers. If the RITENCLR bit is low (default state), a valid comparison
ONLY causes the interrupt flag to be set. It has no effect on the count sequence. Counting
continues as usual. When the counter reaches 0xFFFF FFFF FFFF it rolls-over to 0 on
the next clock and continues counting. If the RITENCLR bit is set to 1 a valid comparison
will also cause the counter to be reset to zero. Counting will resume from there on the next
clock edge.
Counting can be halted in software by writing a ‘0’ to the RITEN bit. Counting will also be
halted when the processor is halted for debugging provided the RITENBR bit is set. Both
the RITEN and RITENBR bits are set on reset.
The interrupt flag can be cleared in software by writing a 1 to the RITINT bit.
Software must stop the counter before reloading it with a new value.
The counter (COUNTER/COUNTER_H), COMPVAL/COMPVAL_H registers,
MASK/MASK_H registers, and the CTRL register can all be read by software at any time.
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Chapter 21: LPC15xx ARM Cortex-M3 Systick timer
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21.1 How to read this chapter
The system tick timer (SysTick timer) is part of the ARM Cortex-M3 core and is identical
for all LPC15xx parts.
21.2 Basic configuration
The system tick timer is configured using the following registers:
1. Pins: The system tick timer uses no external pins.
2. Power: The system tick timer is enabled through the SysTick control register). The
system tick timer clock is fixed to half the frequency of the system clock.
3. Enable the clock source for the SysTick timer in the SYST_CSR register.
21.3 Features
• Simple 24-bit timer.
• Uses dedicated exception vector.
• Clocked internally by the system clock or the SYSTICKCLK.
21.4 General description
The block diagram of the SysTick timer is shown below in the Figure 54.
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Chapter 21: LPC15xx ARM Cortex-M3 Systick timer
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The SysTick timer is an integral part of the Cortex-M3. The SysTick timer is intended to
generate a fixed 10 millisecond interrupt for use by an operating system or other system
management software.
Since the SysTick timer is a part of the Cortex-M3, it facilitates porting of software by
providing a standard timer that is available on Cortex-M3 based devices. The SysTick
timer can be used for:
• An RTOS tick timer which fires at a programmable rate (for example 100 Hz) and
invokes a SysTick routine.
• A high-speed alarm timer using the core clock.
• A simple counter. Software can use this to measure time to completion and time used.
• An internal clock source control based on missing/meeting durations. The
COUNTFLAG bit-field in the control and status register can be used to determine if an
action completed within a set duration, as part of a dynamic clock management
control loop.
Refer to the Cortex-M3 User Guide for details.
21.5 Register description
The systick timer registers are located on the ARM Cortex-M3 private peripheral bus (see
Figure 3), and are part of the ARM Cortex-M3 core peripherals. For details, see Ref. 1.
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Chapter 21: LPC15xx ARM Cortex-M3 Systick timer
Table 291. Register overview: SysTick timer (base address 0xE000 E000)
Name
Access
Address
offset
Description
Reset value[1] Reference
SYST_CSR
R/W
0x010
System Timer Control and status register
0x000 0000
Table 292
SYST_RVR
R/W
0x014
System Timer Reload value register
0
Table 293
SYST_CVR
R/W
0x018
System Timer Current value register
0
Table 294
SYST_CALIB
R/W
0x01C
System Timer Calibration value register
0x0
Table 295
[1]
Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.
21.5.1 System Timer Control and status register
The SYST_CSR register contains control information for the SysTick timer and provides a
status flag. This register is part of the ARM Cortex-M3 core system timer register block.
For a detailed bit description of this register, see Ref. 1.
This register determines the clock source for the system tick timer.
Table 292. SysTick Timer Control and status register (SYST_CSR, 0xE000 E010) bit
description
Bit
Symbol
Description
Reset
value
0
ENABLE
System Tick counter enable. When 1, the counter is enabled.
When 0, the counter is disabled.
0
1
TICKINT
System Tick interrupt enable. When 1, the System Tick interrupt 0
is enabled. When 0, the System Tick interrupt is disabled. When
enabled, the interrupt is generated when the System Tick counter
counts down to 0.
2
CLKSOURCE System Tick clock source selection. When 1, the system clock
(CPU) clock is selected. When 0, the output clock from the
system tick clock divider (SYSTICKDIV) is selected as the
reference clock. In this case, the core clock must be at least 2.5
times faster than the reference clock otherwise the count values
are unpredictable.
0
15:3
-
NA
16
COUNTFLAG Returns 1 if the SysTick timer counted to 0 since the last read of
this register.
31:17 -
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
0
NA
21.5.2 System Timer Reload value register
The SYST_RVR register is set to the value that will be loaded into the SysTick timer
whenever it counts down to zero. This register is loaded by software as part of timer
initialization. The SYST_CALIB register may be read and used as the value for
SYST_RVR register if the CPU is running at the frequency intended for use with the
SYST_CALIB value.
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Chapter 21: LPC15xx ARM Cortex-M3 Systick timer
Table 293. System Timer Reload value register (SYST_RVR, 0xE000 E014) bit description
Bit
Symbol
Description
Reset
value
23:0
RELOAD
This is the value that is loaded into the System Tick counter when it 0
counts down to 0.
31:24
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
21.5.3 System Timer Current value register
The SYST_CVR register returns the current count from the System Tick counter when it is
read by software.
Table 294. System Timer Current value register (SYST_CVR, 0xE000 E018) bit description
Bit
Symbol
Description
Reset
value
23:0
CURRENT Reading this register returns the current value of the System Tick
counter. Writing any value clears the System Tick counter and the
COUNTFLAG bit in SYST_CSR.
31:24
-
0
Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
21.5.4 System Timer Calibration value register
The value of the SYST_CALIB register is driven by the value of the SYSTCKCAL register
in the system configuration block (see Table 32).
Table 295. System Timer Calibration value register (SYST_CALIB, 0xE000 E01C) bit
description
Bit
Symbol
23:0
Value
Description
Reset
value
TENMS
Reload value set by the SYSCON block.
0x4
29:24
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
30
SKEW
Reload value set by the SYSCON block.
0
31
NOREF
Reload value set by the SYSCON block.
0
21.6 Functional description
The SysTick timer is a 24-bit timer that counts down to zero and generates an interrupt.
The intent is to provide a fixed 10 millisecond time interval between interrupts. The
SysTick timer is clocked from the CPU clock (the system clock, see Figure 3) or from the
reference clock, which is fixed to half the frequency of the CPU clock. In order to generate
recurring interrupts at a specific interval, the SYST_RVR register must be initialized with
the correct value for the desired interval. A default value is provided in the SYST_CALIB
register and may be changed by software.
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Chapter 21: LPC15xx ARM Cortex-M3 Systick timer
21.7 Example timer calculations
To use the system tick timer, do the following:
1. Program the LOAD register with the reload value RELOAD to obtain the desired time
interval.
2. Clear the VAL register by writing to it. This ensures that the timer will count from the
LOAD value rather than an arbitrary value when the timer is enabled.
The following examples illustrate selecting SysTick timer reload values for different
system configurations. All of the examples calculate an interrupt interval of
10 milliseconds, as the SysTick timer is intended to be used, and there are no rounding
errors.
System clock = 72 MHz
Program the CTRL register with the value 0x7 which selects the system clock as the clock
source and enables the SysTick timer and the SysTick timer interrupt.
RELOAD = (system clock frequency  10 ms) 1 = (72 MHz  10 ms) 1 = 720000 1 =
719999 = 0x000AFC7F
System tick timer clock = 24 MHz
Program the CTRL register with the value 0x3 which selects the clock from the system tick
clock divider (use DIV = 3) as the clock source and enables the SysTick timer and the
SysTick timer interrupt.
RELOAD = (system tick timer clock frequency  10 ms) 1 = (24 MHz  10 ms) 1 =
240000 1 = 239999 = 0x0003A97F
System clock = 12 MHz
Program the CTRL register with the value 0x7 which selects the system clock as the clock
source and enables the SysTick timer and the SysTick timer interrupt.
In this case the system clock is derived from the IRC clock.
RELOAD = (system clock frequency  10 ms) 1 = (12 MHz  10 ms) 1 = 120000 1 =
119999 = 0x0001 D4BF
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
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22.1 How to read this chapter
The quadrature encoder interface is available on all parts.
22.2 Features
•
•
•
•
•
•
•
•
•
•
Tracks encoder position.
Increments/ decrements depending on direction.
Programmable for 2X or 4X position counting.
Velocity capture using built-in timer.
Velocity compare function with less than interrupt.
Uses 32-bit registers for position and velocity.
Three position compare registers with interrupts.
Index counter for revolution counting.
Index compare register with interrupts.
Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.
• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clock and direction).
22.3 Basic configuration
• Use the SYSAHBCLKCTRL1 register (Table 51) to enable the clock to the QEI
interface.
• Clear the peripheral reset for the entire comparator block using the PRESETCTRL1
register (Table 36).
• The QEI creates one interrupt connected to slot #44 in the NVIC.
• Use the switch matrix to assign the QEI inputs to pins. See Table 296.
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Fig 55. QEI timing
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
22.4 General description
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, you can track the position, direction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. This quadrature encoder interface module decodes the digital pulses from a
quadrature encoder wheel to integrate position over time and determine direction of
rotation. In addition, it can capture the velocity of the encoder wheel.
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
22.5 Pin description
The QEI control signals are movable functions and are assigned to pins through the
switch matrix.
Table 296. QEI pin description
Function
Direction Type
Connect Use register
to
Reference Description
QEI0_PHA
I
external
to pin
any pin
PINASSIGN14
Table 121
Phase A (PhA) input to the
Quadrature Encoder Interface.
QEI0_PHB
I
external
to pin
any pin
PINASSIGN14
Table 121
Phase B (PhB) input to the
Quadrature Encoder Interface.
QEI0_IDX
I
external
to pin
any pin
PINASSIGN14
Table 121
Index (IDX) input to the Quadrature
Encoder Interface.
22.6 Register description
Table 297. Register overview: QEI (base address 0x4005 8000)
Name
Access
Address
offset
Description
Reset value
Reference
Control registers
CON
WO
0x000
Control register
0
Table 298
STAT
RO
0x004
Encoder status register
0
Table 299
CONF
R/W
0x008
Configuration register
0x000F 0000
Table 300
Position, index, and timer registers
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POS
RO
0x00C
Position register
0
Table 301
MAXPOS
R/W
0x010
Maximum position register
0
Table 302
CMPOS0
R/W
0x014
position compare register 0
0xFFFF FFFF Table 303
CMPOS1
R/W
0x018
position compare register 1
0xFFFF FFFF Table 304
CMPOS2
R/W
0x01C
position compare register 2
0xFFFF FFFF Table 305
INXCNT
RO
0x020
Index count register
0
INXCMP0
R/W
0x024
Index compare register 0
0xFFFF FFFF Table 307
LOAD
R/W
0x028
Velocity timer reload register
0xFFFF FFFF Table 308
TIME
RO
0x02C
Velocity timer register
0xFFFF FFFF Table 309
VEL
RO
0x030
Velocity counter register
0
CAP
RO
0x034
Velocity capture register
0xFFFF FFFF Table 311
VELCOMP
R/W
0x038
Velocity compare register
0
Table 312
FILTERPHA R/W
0x03C
Digital filter register on input
phase A (QEI_A)
0
Table 313
FILTERPHB R/W
0x040
Digital filter register on input
phase B (QEI_B)
0
Table 314
FILTERINX
R/W
0x044
Digital filter register on input
index (QEI_IDX)
0
Table 315
WINDOW
R/W
0x048
Index acceptance window
register
0x0000 0000
Table 316
INXCMP1
R/W
0x04C
Index compare register 1
0xFFFF FFFF Table 317
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
Table 297. Register overview: QEI (base address 0x4005 8000)
Name
Access
Address
offset
Description
Reset value
Reference
INXCMP2
R/W
0x050
Index compare register 2
0xFFFF FFFF Table 318
Interrupt registers
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IEC
WO
0xFD8
Interrupt enable clear register
0
Table 319
IES
WO
0xFDC
Interrupt enable set register
0
Table 320
INTSTAT
RO
0xFE0
Interrupt status register
0
Table 321
IE
RO
0xFE4
Interrupt enable register
0
Table 322
CLR
WO
0xFE8
Interrupt status clear register
0
Table 323
SET
WO
0xFEC
Interrupt status set register
0
Table 324
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
22.6.1 Control registers
22.6.1.1 QEI Control register
This register contains bits which control the operation of the position and velocity counters
of the QEI module.
Table 298: QEI Control register (CON, address 0x4005 8000) bit description
Bit
Symbol
Description
Reset
value
0
RESP
Reset position counter. When set = 1, resets the position counter to
all zeros. Auto-clears when the position counter is cleared.
0
1
RESPI
Reset position counter on index. When set = 1, resets the position
counter to all zeros when an index pulse occurs. Auto-clears when
the position counter is cleared.
0
2
RESV
Reset velocity. When set = 1, resets the velocity counter to all zeros 0
and reloads the velocity timer. Auto-clears when the velocity counter
is cleared.
3
RESI
Reset index counter. When set = 1, resets the index counter to all
zeros. Auto-clears when the index counter is cleared.
0
31:4
-
reserved
0
22.6.1.2 QEI Status register
This register provides the status of the encoder interface.
Table 299: QEI Interrupt Status register (STAT, address 0x4005 8004) bit description
Bit
Symbol
Description
Reset
value
0
DIR
Direction bit. In combination with DIRINV bit indicates forward or
reverse direction. See Table 327.
31:1
-
reserved
0
22.6.1.3 QEI Configuration register
This register contains the configuration of the QEI module.
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
Table 300: QEI Configuration register (CONF, address 0x4005 8008) bit description
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Bit
Symbol
Description
Reset
value
0
DIRINV
Direction invert. When = 1, complements the DIR bit.
0
1
SIGMODE
Signal Mode. When = 0, PhA and PhB function as quadrature
encoder inputs. When = 1, PhA functions as the direction signal
and PhB functions as the clock signal.
0
2
CAPMODE Capture Mode. When = 0, only PhA edges are counted (2X).
When = 1, BOTH PhA and PhB edges are counted (4X),
increasing resolution but decreasing range.
0
3
INVINX
Invert Index. When set, inverts the sense of the index input.
0
4
CRESPI
Continuously reset position counter on index. When set = 1,
resets the position counter to all zeros when an index pulse
occurs at the next position increase (recalibration). Auto-clears
when the position counter is cleared.
0
15:5
-
Reserved
0
19:16
INXGATE
Index gating configuration:
when INXGATE(19)=1, pass the index when Pha=0 and Phb=0,
else block.
when INXGATE(18)=1, pass the index when Pha=0 and Phb=1,
else block.
when INXGATE(17)=1, pass the index when Pha=1 and Phb=1,
else block.
when INXGATE(16)=1, pass the index when Pha=1 and Phb=0,
else block.
1111
31:20
-
reserved
0
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
22.6.2 Position, index and timer registers
22.6.2.1 QEI Position register
This register contains the current value of the encoder position. Increments or decrements
when encoder counts occur, depending on the direction of rotation.
Table 301. QEI Position register (POS, address 0x4005 800C) bit description
Bit
Symbol
Description
Reset value
31:0
POS
Current position value.
0
22.6.2.2 QEI Maximum Position register
This register contains the maximum value of the encoder position. In forward rotation the
position register resets to zero when the position register exceeds this value. In reverse
rotation the position register resets to this value when the position register decrements
from zero.
Table 302. QEI Maximum Position register (MAXPOS, address 0x4005 8010) bit description
Bit
Symbol
Description
Reset value
31:0
MAXPOS
Maximum position value.
0
22.6.2.3 QEI Position Compare register 0
This register contains a position compare value. This value is compared against the
current value of the position register. Interrupts can be enabled to interrupt when the
compare value is less than, equal to, or greater than the current value of the position
register.
Table 303. QEI Position Compare register 0 (CMPOS0, address 0x4005 8014) bit description
Bit
Symbol
Description
Reset value
31:0
PCMP0
Position compare value 0.
0xFFFF FFFF
22.6.2.4 QEI Position Compare register 1
This register contains a position compare value. This value is compared against the
current value of the position register. Interrupts can be enabled to interrupt when the
compare value is less than, equal to, or greater than the current value of the position
register.
Table 304. QEI Position Compare register 1 (CMPOS1, address 0x4005 8018) bit description
Bit
Symbol
Description
Reset value
31:0
PCMP1
Position compare value 1.
0xFFFF FFFF
22.6.2.5 QEI Position Compare register 2
This register contains a position compare value. This value is compared against the
current value of the position register. Interrupts can be enabled to interrupt when the
compare value is less than, equal to, or greater than the current value of the position
register.
Table 305. QEI Position Compare register 2 (CMPOS2, address 0x4005 801C) bit description
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Bit
Symbol
Description
Reset value
31:0
PCMP2
Position compare value 2.
0xFFFF FFFF
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
22.6.2.6 QEI Index Count register
This register contains the current value of the encoder position. Increments or decrements
when encoder counts occur, depending on the direction of rotation.
Table 306. QEI Index Count register (INXCNT, address 0x4005 8020) bit description
Bit
Symbol
Description
Reset value
31:0
ENCPOS
Current encoder position value.
0
22.6.2.7 QEI Index Compare register 0
This register contains an index compare value. This value is compared against the current
value of the index count register. Interrupts can be enabled to interrupt when the compare
value is less than, equal to, or greater than the current value of the index count register.
Table 307. QEI Index Compare register 0 (INXCMP0, address 0x4005 8024) bit description
Bit
Symbol
Description
Reset value
31:0
ICMP0
Index compare value.
0xFFFF FFFF
22.6.2.8 QEI Timer Reload register
This register contains the reload value of the velocity timer. When the timer (TIME)
reaches zero or the RESV bit is asserted, this value is loaded into the timer (TIME).
Table 308. QEI Timer Load register (LOAD, address 0x4005 8028) bit description
Bit
Symbol
Description
Reset value
31:0
VELLOAD
Current velocity timer pre-load value.The velocity
timer counts down from this value.
0xFFFF FFFF
22.6.2.9 QEI Timer register
This register contains the current value of the velocity timer. When this timer reaches zero,
the value of velocity register (VEL) is stored in the velocity capture register (CAP), the
timer is reloaded with the value stored in the velocity reload register (LOAD), and the
velocity interrupt (TIM_Int) is asserted.
Table 309. QEI Timer register (TIME, address 0x4005 802C) bit description
Bit
Symbol
Description
Reset value
31:0
VELVAL
Current velocity timer value.
0xFFFF FFFF
22.6.2.10 QEI Velocity register
This register contains the running count of velocity pulses for the current time period.
When the velocity timer (TIME) reaches zero, the content of this register is captured in the
velocity capture register (CAP). After capture, this register is set to zero. This register is
also reset when the velocity reset bit (RESV) is asserted.
Table 310. QEI Velocity register (VEL, address 0x4005 8030) bit description
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Bit
Symbol
Description
Reset value
31:0
VELPC
Current velocity pulse count.
0x0
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
22.6.2.11 QEI Velocity Capture register
This register contains the most recently measured velocity of the encoder. This
corresponds to the number of velocity pulses counted in the previous velocity timer
period.The current velocity count is latched into this register when the velocity timer
overflows.
Table 311. QEI Velocity Capture register (CAP, address 0x4005 8034) bit description
Bit
Symbol
Description
Reset value
31:0
VELCAP
Velocity capture value.
0xFFFF FFFF
22.6.2.12 QEI Velocity Compare register
This register contains a velocity compare value. This value is compared against the
captured velocity in the velocity capture register. If the capture velocity is less than the
value in this compare register, a velocity compare interrupt (VELC_Int) will be asserted, if
enabled.
Table 312. QEI Velocity Compare register (VELCOMP, address 0x4005 8038) bit description
Bit
Symbol
Description
Reset value
31:0
VELCMP
Velocity compare value.
0x0
22.6.2.13 QEI Digital filter on phase A input register
This register contains the sampling count for the digital filter. A sampling count of zero
bypasses the filter.
Table 313. QEI Digital filter on phase A input register (FILTERPHA, 0x4005 803C) bit
description
Bit
Symbol
Description
Reset
value
31:0
FILTA
Digital filter sampling delay
0x0
22.6.2.14 QEI Digital filter on phase B input register
This register contains the sampling count for the digital filter. A sampling count of zero
bypasses the filter.
Table 314. QEI Digital filter on phase B input register (FILTERPHB, 0x4005 8040) bit
description
Bit
Symbol
Description
Reset
value
31:0
FILTB
Digital filter sampling delay
0x0
22.6.2.15 QEI Digital filter on index input register
This register contains the sampling count for the digital filter. A sampling count of zero
bypasses the filter.
Table 315. QEI Digital filter on index input register (FILTERINX, 0x4005 8044) bit description
UM10736
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Bit
Symbol
Description
Reset
value
31:0
FITLINX
Digital filter sampling delay
0x0
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22.6.2.16 QEI Index acceptance window register
This register contains the width of the index acceptance window, when the index and the
phase / clock edges fall nearly together. If the activating phase / clock edge falls before
the Index, but within the window, the (re)calibration will be activated on that clock/phase
edge.
Table 316. QEI Index acceptance window register (WINDOW, 0x4005 8048) bit description
Bit
Symbol
Description
Reset
value
31:0
WINDOW
Index acceptance window width
0x0
22.6.2.17 QEI Index Compare register 1
This register contains an index compare value. This value is compared against the current
value of the index count register. Interrupts can be enabled to interrupt when the compare
value is less than, equal to, or greater than the current value of the index count register.
Table 317. QEI Index Compare register 1 (INXCMP1, address 0x4005 804C) bit description
Bit
Symbol
Description
Reset value
31:0
ICMP1
Index compare value 1.
0xFFFF FFFF
22.6.2.18 QEI Index Compare register 2
This register contains an index compare value. This value is compared against the current
value of the index count register. Interrupts can be enabled to interrupt when the compare
value is less than, equal to, or greater than the current value of the index count register.
Table 318. QEI Index Compare register 2 (INXCMP2, address 0x4005 8050) bit description
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Bit
Symbol
Description
Reset value
31:0
ICMP2
Index compare value 2.
0xFFFF FFFF
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
22.6.3 Interrupt registers
22.6.3.1 QEI Interrupt Enable Clear register
Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Enable
register (QEIIE).
Table 319: QEI Interrupt Enable Clear register (IEC, address 0x4005 8FD8) bit description
Bit
Symbol
Description
Reset
value
0
INX_EN
Indicates that an index pulse was detected.
0
1
TIM_EN
Indicates that a velocity timer overflow occurred
0
2
VELC_EN
Indicates that captured velocity is less than compare velocity.
0
3
DIR_EN
Indicates that a change of direction was detected.
0
4
ERR_EN
Indicates that an encoder phase error was detected.
0
5
ENCLK_EN
Indicates that and encoder clock pulse was detected.
0
6
POS0_INT
Indicates that the position 0 compare value is equal to the current position.
0
7
POS1_INT
Indicates that the position 1compare value is equal to the current position.
0
8
POS2_INT
Indicates that the position 2 compare value is equal to the current position.
0
9
REV0_INT
Indicates that the index 0 compare value is equal to the current index count.
0
10
POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set 0
and the REV0_Int is set.
11
POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set 0
and the REV1_INT is set.
12
POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set 0
and the REV2_INT is set.
13
REV1_INT
Indicates that the index 1 compare value is equal to the current index count.
0
14
REV2_INT
Indicates that the index 2 compare value is equal to the current index count.
0
15
MAXPOS_INT
Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.
0
Reserved
0
31:16 -
22.6.3.2 QEI Interrupt Enable Set register
Writing a 1 to a bit in this register sets the corresponding bit in the QEI Interrupt Enable
register (QEIIE).
Table 320: QEI Interrupt Enable Set register (IES, address 0x4005 8FDC) bit description
Bit
Symbol
Description
Reset
value
0
INX_EN
Indicates that an index pulse was detected.
0
1
TIM_EN
Indicates that a velocity timer overflow occurred
0
2
VELC_EN
Indicates that captured velocity is less than compare velocity.
0
3
DIR_EN
Indicates that a change of direction was detected.
0
4
ERR_EN
Indicates that an encoder phase error was detected.
0
5
ENCLK_EN
Indicates that and encoder clock pulse was detected.
0
6
POS0_INT
Indicates that the position 0 compare value is equal to the current position.
0
7
POS1_INT
Indicates that the position 1 compare value is equal to the current position.
0
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
Table 320: QEI Interrupt Enable Set register (IES, address 0x4005 8FDC) bit description
Bit
Symbol
Description
Reset
value
8
POS2_INT
Indicates that the position 2 compare value is equal to the current position.
0
9
REV0_INT
Indicates that the index compare value is equal to the current index count.
0
10
POS0REV_INT
Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is
set and the REV0_INT is set.
0
11
POS1REV_INT
Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is
set and the REV1_INT is set.
0
12
POS2REV_INT
Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is
set and the REV2_INT is set.
0
13
REV1_INT
Indicates that the index 1 compare value is equal to the current index count.
0
14
REV2_INT
Indicates that the index 2 compare value is equal to the current index count.
0
15
MAXPOS_INT
Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.
0
31:16
-
Reserved
0
22.6.3.3 QEI Interrupt Status register
This register provides the status of the encoder interface and the current set of interrupt
sources that are asserted to the controller. Bits set to 1 indicate the latched events that
have occurred; a zero bit indicates that the event in question has not occurred. Writing a 0
to a bit position clears the corresponding interrupt.
Table 321: QEI Interrupt Status register (INTSTAT, address 0x4005 8FE0) bit description
Bit
Symbol
Description
Reset
value
0
INX_INT
Indicates that an index pulse was detected.
0
1
TIM_INT
Indicates that a velocity timer overflow occurred
0
2
VELC_INT
Indicates that captured velocity is less than compare velocity.
0
3
DIR_INT
Indicates that a change of direction was detected.
0
4
ERR_INT
Indicates that an encoder phase error was detected.
0
5
ENCLK_INT
Indicates that and encoder clock pulse was detected.
0
6
POS0_INT
Indicates that the position 0 compare value is equal to the current position.
0
7
POS1_INT
Indicates that the position 1compare value is equal to the current position.
0
8
POS2_INT
Indicates that the position 2 compare value is equal to the current position.
0
9
REV0_INT
Indicates that the index compare value is equal to the current index count.
0
10
POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is
set and the REV0_INT is set.
0
11
POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is
set and the REV1_INT is set.
0
12
POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is
set and the REV2_INT is set.
0
13
REV1_INT
Indicates that the index 1 compare value is equal to the current index count.
0
14
REV2_INT
Indicates that the index 2 compare value is equal to the current index count.
0
15
MAXPOS_INT
Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.
0
31:16
-
Reserved
0
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22.6.3.4 QEI Interrupt Enable register
This register enables interrupt sources. Bits set to 1 enable the corresponding interrupt; a
0 bit disables the corresponding interrupt.
Table 322: QEI Interrupt Enable register (IE, address 0x4005 8FE4) bit description
Bit
Symbol
Description
Reset
value
0
INX_INT
Indicates that an index pulse was detected.
0
1
TIM_INT
Indicates that a velocity timer overflow occurred
0
2
VELC_INT
Indicates that captured velocity is less than compare velocity.
0
3
DIR_INT
Indicates that a change of direction was detected.
0
4
ERR_INT
Indicates that an encoder phase error was detected.
0
5
ENCLK_INT
Indicates that and encoder clock pulse was detected.
0
6
POS0_INT
Indicates that the position 0 compare value is equal to the current position.
0
7
POS1_INT
Indicates that the position 1compare value is equal to the current position.
0
8
POS2_INT
Indicates that the position 2 compare value is equal to the current position.
0
9
REV0_INT
Indicates that the index compare value is equal to the current index count.
0
10
POS0REV_INT
Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is
set and the REV0_INT is set.
0
11
POS1REV_INT
Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is
set and the REV1_INT is set.
0
12
POS2REV_INT
Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is
set and the REV2_INT is set.
0
13
REV1_INT
Indicates that the index 1 compare value is equal to the current index count.
0
14
REV2_INT
Indicates that the index 2 compare value is equal to the current index count.
0
15
MAXPOS_INT
Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.
0
31:16
-
Reserved
0
22.6.3.5 QEI Interrupt Status Clear register
Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Status
register (QEISTAT).
Table 323: QEI Interrupt Status Clear register (CLR, 0x4005 8FE8) bit description
Bit
Symbol
Description
Reset
value
0
INX_INT
Indicates that an index pulse was detected.
0
1
TIM_INT
Indicates that a velocity timer overflow occurred
0
2
VELC_INT
Indicates that captured velocity is less than compare velocity.
0
3
DIR_INT
Indicates that a change of direction was detected.
0
4
ERR_INT
Indicates that an encoder phase error was detected.
0
5
ENCLK_INT
Indicates that and encoder clock pulse was detected.
0
6
POS0_INT
Indicates that the position 0 compare value is equal to the current position.
0
7
POS1_INT
Indicates that the position 1compare value is equal to the current position.
0
8
POS2_INT
Indicates that the position 2 compare value is equal to the current position.
0
9
REV0_INT
Indicates that the index compare value is equal to the current index count.
0
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
Table 323: QEI Interrupt Status Clear register (CLR, 0x4005 8FE8) bit description
Bit
Symbol
Description
Reset
value
10
POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is
set and the REV0_INT is set.
0
11
POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is
set and the REV1_INT is set.
0
12
POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is
set and the REV2_INT is set.
0
13
REV1_INT
Indicates that the index 1 compare value is equal to the current index count.
0
14
REV2_INT
Indicates that the index 2 compare value is equal to the current index count.
0
15
MAXPOS_INT
Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.
31:16
-
Reserved
0
22.6.3.6 QEI Interrupt Status Set register
Writing a one to a bit in this register sets the corresponding bit in the QEI Interrupt Status
register (STAT).
Table 324: QEI Interrupt Status Set register (SET, address 0x4005 8FEC) bit description
Bit
Symbol
Description
Reset
value
0
INX_INT
Indicates that an index pulse was detected.
0
1
TIM_INT
Indicates that a velocity timer overflow occurred
0
2
VELC_INT
Indicates that captured velocity is less than compare velocity.
0
3
DIR_INT
Indicates that a change of direction was detected.
0
4
ERR_INT
Indicates that an encoder phase error was detected.
0
5
ENCLK_INT
Indicates that and encoder clock pulse was detected.
6
POS0_INT
Indicates that the position 0 compare value is equal to the current position.
0
7
POS1_INT
Indicates that the position 1compare value is equal to the current position.
0
8
POS2_INT
Indicates that the position 2 compare value is equal to the current position.
0
9
REV0_INT
Indicates that the index compare value is equal to the current index count.
0
10
POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is
set and the REV0_INT is set.
0
11
POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is
set and the REV1_INT is set.
0
12
POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is
set and the REV2_INT is set.
0
13
REV1_INT
Indicates that the index 1 compare value is equal to the current index count.
0
14
REV2_INT
Indicates that the index 2 compare value is equal to the current index count.
0
15
MAXPOS_INT
Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.
0
31:16
-
Reserved
0
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
22.7 Functional description
The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel
to integrate position over time and determine direction of rotation. In addition, it can
capture the velocity of the encoder wheel.
22.7.1 Input signals
The QEI module supports two modes of signal operation: quadrature phase mode and
clock/direction mode. In quadrature phase mode, the encoder produces two clocks that
are 90 degrees out of phase; the edge relationship is used to determine the direction of
rotation. In clock/direction mode, the encoder produces a clock signal to indicate steps
and a direction signal to indicate the direction of rotation.).
This mode is determined by the SigMode bit of the QEI Control (CON) register (See
Table 298). When the SigMode bit = 1, the quadrature decoder is bypassed and the PhA
pin functions as the direction signal and PhB pin functions as the clock signal for the
counters, etc. When the SigMode bit = 0, the PhA pin and PhB pins are decoded by the
quadrature decoder. In this mode the quadrature decoder produces the direction and
clock signals for the counters, etc. In both modes the direction signal is subject to the
effects of the direction invert (DIRINV) bit.
The input signals are synchronized to the QEI peripheral clock QEI_CLK, which is
identical to the system clock, see Figure 55. In order for the single-stage synchronizer to
capture the input signal, the two phase inputs have to overlap at least one clock cycle of
the QEI_PCLK. The signal minimum HIGH and LOW times should also be one clock cycle
of the QEI_PCLK. Since the frequency of the input signals is typically much lower than the
system clock, these conditions are always met in practical applications,
22.7.1.1 Quadrature input signals
When edges on PhA lead edges on PhB, the position counter is incremented. When
edges on PhB lead edges on PhA, the position counter is decremented. When a rising
and falling edge pair is seen on one of the phases without any edges on the other, the
direction of rotation has changed.
Table 325. Encoder states
Phase A
Phase B
state
1
0
1
1
1
2
0
1
3
0
0
4
Table 326. Encoder state transitions[1]
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from state
to state
Direction
1
2
positive
2
3
3
4
4
1
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
Table 326. Encoder state transitions[1]
from state
to state
Direction
4
3
negative
3
2
2
1
1
4
[1]
All other state transitions are illegal and should set the ERR bit.
Interchanging of the PhA and PhB input signals are compensated by complementing the
DIR bit. When set = 1, the direction inversion bit (DIRINV) complements the DIR bit.
Table 327. Encoder direction
DIR bit
DIRINV bit
direction
0
0
forward
1
0
reverse
0
1
reverse
1
1
forward
Figure 57 shows how quadrature encoder signals equate to direction and count.
Fig 57. Quadrature Encoder basic operation
22.7.1.2 Digital input filtering
All three encoder inputs (PhA, PhB, and index) require digital filtering. The number of
sample clocks is user programmable from 1 to 4,294,967,295 (0xFFFF FFFF). In order for
a transition to be accepted, the input signal must remain in new state for the programmed
number of sample clocks.
22.7.2 Position capture
The capture mode for the position integrator can be set to update the position counter on
every edge of the PhA signal or to update on every edge of both PhA and PhB. Updating
the position counter on every PhA and PhB provides more positional resolution at the cost
of less range in the positional counter.
The position integrator and velocity capture can be independently enabled. Alternatively,
the phase signals can be interpreted as a clock and direction signal as output by some
encoders.
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
The position counter is automatically reset on one of three conditions. Incrementing past
the maximum position value (MAXPOS) will reset the position counter to zero. If the reset
on index bit (RESPI) is set, sensing the index pulse for the first time will once reset the
position counter to zero after the next positional increase (calibrate). If the continuously
reset on index bit (CRESPI) is set, sensing the index pulse will continuously reset the
position counter to zero after the next positional increase (recalibrate).
22.7.3 Velocity capture
The velocity capture has a programmable timer and a capture register. It counts the
number of phase edges (using the same configuration as for the position integrator) in a
given time period. When the velocity timer (TIME) reaches zero, the contents of the
velocity counter (VEL) are transferred to the capture (CAP) register. The velocity counter
is then cleared. The velocity timer is loaded with the contents of the velocity reload
register (LOAD). Finally, the velocity interrupt (TIM_Int) is asserted. The number of edges
counted in a given time period is directly proportional to the velocity of the encoder.
Setting the reset velocity bit (RESV) will clear the velocity counter, reset the velocity
capture register to 0xFFFF FFFF, and load the velocity timer with the contents of the
velocity reload register (LOAD).
The following equation converts the velocity counter value into an RPM value:
RPM = (PCLK  Speed  60) / Load  PPR  Edges)
where:
• PCLK is the QEI controller clock.
• PPR is the number of pulses per revolution of the physical encoder.
• Edges is 2 or 4, based on the capture mode set in the CON register (2 for CapMode
set to 0 and 4 for CapMode set to 1)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution
quadrature encoder is attached to the motor, producing 8192 phase edges per revolution.
With clocking on both PhA and PhB edges, this results in 81,920 pulses per second (the
motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load
value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the
above equation:
RPM = (10000  20480  60) / (2500  2048  4) = 600 RPM
Now, consider that the motor is sped up to 3000 RPM. This results in 409,600 pulses per
second, or 102,400 every ¼ of a second. Again, the above equation gives:
RPM = (10000  102400  60) / (2500  2048  4) = 3000 RPM
22.7.4 Velocity compare
In addition to velocity capture, the velocity measurement system includes a
programmable velocity compare register. After every velocity capture event the contents
of the velocity capture register (CAP) is compared with the contents of the velocity
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Chapter 22: LPC15xx Quadrature Encoder Interface (QEI)
compare register (VELCOMP). If the captured velocity is less than the compare value an
interrupt is asserted provided that the velocity compare interrupt enable bit is set. This can
be used to determine if a motor shaft is either stalled or moving too slow.
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Chapter 23: LPC15xx USB
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User manual
23.1 How to read this chapter
The USB controller is only available on parts LPC1549/48/47.
23.2 Features
•
•
•
•
•
USB2.0 full-speed device controller.
Supports 10 physical (5 logical) endpoints including one control endpoint.
Single and double-buffering supported.
Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
Supports wake-up from Deep-sleep and Power-down modes on USB activity and
remote wake-up.
• SoftConnect and serial 33 Ω resistors on USB_DP and USB_DM implemented
internally.
23.3 Basic configuration
Configure the USB as follows:
• Use the SYSAHBCLKCTRL1 register (Table 51) to enable the clock to the USB
register interface.
• Clear the USB peripheral reset using the PRESETCTRL1 register (Table 36).
• Turn on the USB PHY by setting the USB_PHY bit in the PDRUNCFG register
(Table 75).
• Configure the USBPLL to create a 48 MHz USB clock.
• The USB block creates three interrupts which are connected to slot #28 (USB_INT),
slot #29 (USB_FIQ), and slot #30 (USB_WAKE) in the NVIC.
• Use the switch matrix to connect the USB functions USB_VBUS, and
USB_FTOGGLE to pins. The USB_DP and USB_DM pins are dedicated pins. Do not
assign the USB_FTOGGLE function to a pin until a USB device is connected and the first SOF
interrupt has been received by the device.
• The USB_FTOGGLE output is connected to the SCT2/3 input muxes.
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Chapter 23: LPC15xx USB
86%
6<6&21
5(*,67(5
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V\VWHPRVFLOODWRU
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Fig 58. USB clocking
23.4 Pin description
The device controller can access one USB port.
The USB control signals are movable functions and are assigned to pins through the
switch matrix.
Table 328. USB pin description
Function
Direction Type
Connect Use register
to
Reference Description
VBUS
I
external
to pin
any pin
PINASSIGN7
Table 114
VBUS status input. When this
function is not enabled via its
corresponding IOCON register, it is
driven HIGH internally.
external
to pin
any pin
PINASSIGN14
Table 121
USB 1 ms SoF signal. Do not assign
this function to a pin until a USB
device is connected and the first
SOF interrupt has been received by
the device.
internal
SCT2
SCT2_INMUX[2:0]
Table 129
USB 1 ms SoF signal.
internal
SCT3
SCT3_INMUX[2:0]
Table 130
USB 1 ms SoF signal.
-
-
-
Positive differential data. Pad
includes internal 33 Ω series
termination resistor.
-
-
Negative differential data. Pad
includes internal 33 Ω series
termination resistor.
USB_FTOGGLE O
USB_DP
I/O
pin
USB_DM
I/O
pin
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Chapter 23: LPC15xx USB
23.5 General description
The Universal Serial Bus (USB) is a four-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The host schedules transactions in 1 ms frames. Each frame contains a Start-Of-Frame
(SOF) marker and transactions that transfer data to or from device endpoints. Each device
can have a maximum of 16 logical or 32 physical endpoints. The device controller
supports up to 10 physical endpoints. There are four types of transfers defined for the
endpoints. Control transfers are used to configure the device.
Interrupt transfers are used for periodic data transfer. Bulk transfers are used when the
latency of transfer is not critical. Isochronous transfers have guaranteed delivery time but
no error correction.
For more information on the Universal Serial Bus, see the USB Implementers Forum
website.
The USB device controller on the LPC15xx enables full-speed (12 Mb/s) data exchange
with a USB host controller.
Figure 59 shows the block diagram of the USB device controller.
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Chapter 23: LPC15xx USB
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Fig 59. USB block diagram
The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX
sends/receives the bi-directional USB_DP and USB_DM signals of the USB bus.
The SIE implements the full USB protocol layer. It is completely hardwired for speed and
needs no software intervention. It handles transfer of data between the endpoint buffers in
USB RAM and the USB bus. The functions of this block include: synchronization pattern
recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation,
PID verification/generation, address recognition, and handshake evaluation/generation.
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Chapter 23: LPC15xx USB
23.5.1 USB software interface
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Fig 60. USB software interface
23.5.2 Fixed endpoint configuration
Table 329 shows the supported endpoint configurations. The packet size is configurable
up to the maximum value shown in Table 329 for each type of end point.
Table 329. Fixed endpoint configuration
Logical
endpoint
Physical
endpoint
Endpoint type
Direction
Max packet
size (byte)
Double
buffer
0
0
Control
Out
64
No
0
1
Control
In
64
No
1
2
Interrupt/Bulk/Isochronous
Out
64/64/1023
Yes
1
3
Interrupt/Bulk/Isochronous
In
64/64/1023
Yes
2
4
Interrupt/Bulk/Isochronous
Out
64/64/1023
Yes
2
5
Interrupt/Bulk/Isochronous
In
64/64/1023
Yes
3
6
Interrupt/Bulk/Isochronous
Out
64/64/1023
Yes
3
7
Interrupt/Bulk/Isochronous
In
64/64/1023
Yes
4
8
Interrupt/Bulk/Isochronous
Out
64/64/1023
Yes
4
9
Interrupt/Bulk/Isochronous
In
64/64/1023
Yes
23.5.3 SoftConnect
The softConnect signal is implemented internally. An external pull-up resistor between
USB_DP and VDD is not necessary.
Software can control the USB_CONNECT signal by setting the DCON bit in the
DEVCMDSTAT register. If the DCON bit is set to 1, the USB_DP line is pulled up to VDD
through an internal 1.5 KOhm pull-up resistor.
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The purpose of the soft connect feature using USB_CONNECT is to control when the
device connects to the bus. When the device detects a USB_VBUS signal on the bus, it
can finish processing if necessary, and then under software control indicate its presence
to the host by pulling the USB_DP line HIGH. In a similar way, software can re-initialize a
USB connection without the necessity to unplug the USB cable.
23.5.4 Interrupts
The USB controller has two interrupt lines USB_Int_Req_IRQ and USB_Int_Req_FIQ.
Software can program the corresponding bit in the USB interrupt routing register to route
the interrupt condition to one of these entries in the NVIC table Table 2. An interrupt is
generated by the hardware if both the interrupt status bit and the corresponding interrupt
enable bit are set. The interrupt status bit is set by hardware if the interrupt condition
occurs (regardless of the interrupt enable bit setting).
23.5.5 Suspend and resume
The USB protocol insists on power management by the USB device. This becomes even
more important if the device draws power from the bus (bus-powered device). The
following constraints should be met by the bus-powered device.
• A device in the non-configured state should draw a maximum of 100 mA from the
USB bus.
• A configured device can draw only up to what is specified in the Max Power field of
the configuration descriptor. The maximum value is 500 mA.
• A suspended device should draw a maximum of 500 A.
A device will go into the L2 suspend state if there is no activity on the USB bus for more
than 3 ms. A suspended device wakes up, if there is transmission from the host
(host-initiated wake up). The USB controller also supports software initiated remote
wake-up. To initiate remote wake-up, software on the device must enable all clocks and
clear the suspend bit. This will cause the hardware to generate a remote wake-up signal
upstream.
The USB controller supports Link Power Management. Link Power Management defines
an additional link power management state L1 that supplements the existing L2 state by
utilizing most of the existing suspend/resume infrastructure but provides much faster
transitional latencies between L1 and L0 (On).
The assertion of USB suspend signal indicates that there was no activity on the USB bus
for the last 3 ms. At this time an interrupt is sent to the processor on which the software
can start preparing the device for suspend.
If there is no activity for the next 2 ms, the USB need_clock signal will go low. This
indicates that the USB main clock can be switched off.
When activity is detected on the USB bus, the USB suspend signal is deactivated and
USB need_clock signal is activated. This process is fully combinatorial and hence no USB
main clock is required to activate the US B need_clock signal.
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Chapter 23: LPC15xx USB
23.5.6 Frame toggle output
The USB_FTOGGLE output pin reflects the 1 kHz clock derived from the incoming
Start-of-Frame (SOF) tokens sent by the USB host. When the USB is connected to a host,
the rising edge of the USB_FTOGGLE signal is aligned with the middle of the SOF token
which is received on the USB bus. The signal can be monitored on a pin (connected
through the switch matrix) or on the inputs of timers SCT2 or SCT3.
When no tokens are coming in, the USB_FTOGGLE input is a 1 KHz signal based on the
USB main clock.
23.5.7 Clocking
The LPC15xx USB device controller has the following clock connections:
• USB main clock: The USB main clock is the 48 MHz +/- 500 ppm clock from the
dedicated USB PLL or the main clock (see Table 42). If the main clock is used, the
system PLL output must be 48 MHz and derived from the system oscillator. The USB
main clock is used to recover the 12 MHz clock from the USB bus.
• AHB clock: This is the AHB system bus clock. The minimum frequency of the AHB
clock is 6 MHz when the USB device controller is receiving or transmitting USB
packets.
23.6 Register description
Table 330. Register overview: USB (base address: 0x1C00 C000)
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Name
Access Address Description
offset
Reset
value
Reference
DEVCMDSTAT
R/W
0x000
USB Device Command/Status 0x0000080 Table 331
register
0
INFO
R/W
0x004
USB Info register
0
Table 332
EPLISTSTART
R/W
0x008
USB EP Command/Status List 0
start address
Table 333
DATABUFSTART
R/W
0x00C
USB Data buffer start address
0
Table 334
LPM
R/W
0x010
Link Power Management
register
0
Table 335
EPSKIP
R/W
0x014
USB Endpoint skip
0
Table 336
EPINUSE
R/W
0x018
USB Endpoint Buffer in use
0
Table 337
EPBUFCFG
R/W
0x01C
USB Endpoint Buffer
Configuration register
0
Table 338
INTSTAT
R/W
0x020
USB interrupt status register
0
Table 339
INTEN
R/W
0x024
USB interrupt enable register
0
Table 340
INTSETSTAT
R/W
0x028
USB set interrupt status
register
0
Table 341
INTROUTING
R/W
0x02C
USB interrupt routing register
0
Table 342
EPTOGGLE
R
0x034
USB Endpoint toggle register
0
Table 343
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Chapter 23: LPC15xx USB
23.6.1 USB Device Command/Status register
Table 331. USB Device Command/Status register (DEVCMDSTAT, address 0x1C00 C000) bit description
Bit
Symbol
6:0
DEV_ADDR
USB device address. After bus reset, the address is reset to
0
0x00. If the enable bit is set, the device will respond on packets
for function address DEV_ADDR. When receiving a SetAddress
Control Request from the USB host, software must program the
new address before completing the status phase of the
SetAddress Control Request.
RW
7
DEV_EN
USB device enable. If this bit is set, the USB block will start
responding on packets for function address DEV_ADDR.
RW
8
SETUP
9
PLL_ON
Value
Description
0
Disabled.
1
Enabled. USB device operation enabled.
Reset
value
0
Access
0
SETUP token received. If a SETUP token is received and
acknowledged by the device, this bit is set. As long as this bit is
set all received IN and OUT tokens will be NAKed by HW. SW
must clear this bit by writing a one. If this bit is zero, HW will
handle the tokens to the CTRL EP0 as indicated by the CTRL
EP0 IN and OUT data information programmed by SW.
RWC
Always PLL Clock on:
0
RW
0
Functional. USB_NeedClk functional.
1
High. USB_NeedClk always 1. Clock will not be stopped in case
of suspend.
10
-
Reserved.
0
RO
11
LPM_SUP
LPM Support.:
1
RW
0
RW
0
RW
0
RW
0
RW
12
13
14
15
0
No. LPM not supported.
1
Yes.LPM supported.
0
AK only. Only acknowledged packets generate an interrupt
1
Ak and Nak. Both acknowledged and NAKed packets generate
interrupts.
0
AK only. Only acknowledged packets generate an interrupt
1
Ak and NAK. Both acknowledged and NAKed packets generate
interrupts.
0
AK only. Only acknowledged packets generate an interrupt
1
AK and NAK. Both acknowledged and NAKed packets generate
interrupts.
0
AK only. Only acknowledged packets generate an interrupt
1
AK and NAK. Both acknowledged and NAKed packets generate
interrupts.
INTONNAK_AO
Interrupt on NAK for interrupt and bulk OUT EP
INTONNAK_AI
Interrupt on NAK for interrupt and bulk IN EP
INTONNAK_CO
Interrupt on NAK for control OUT EP
INTONNAK_CI
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Chapter 23: LPC15xx USB
Table 331. USB Device Command/Status register (DEVCMDSTAT, address 0x1C00 C000) bit description
Bit
Symbol
16
DCON
Value
Description
Reset
value
Access
Device status - connect.
0
RW
0
Not connected.
1
Connect. The connect bit must be set by software to indicate
that the device must signal a connect. The pull-up resistor on
USB_DP will be enabled when this bit is set and the
VBUSDEBOUNCED bit is one.
17
DSUS
Device status - suspend.
0
The suspend bit indicates the current suspend state. It is set to
1 when the device hasn’t seen any activity on its upstream port
for more than 3 milliseconds. It is reset to 0 on any activity.
When the device is suspended (Suspend bit DSUS = 1) and the
software writes a 0 to it, the device will generate a remote
wake-up. This will only happen when the device is connected
(Connect bit = 1). When the device is not connected or not
suspended, a writing a 0 has no effect. Writing a 1 never has an
effect.
RW
18
-
Reserved.
0
RO
19
LPM_SUS
Device status - LPM Suspend.
0
This bit represents the current LPM suspend state. It is set to 1
by HW when the device has acknowledged the LPM request
from the USB host and the Token Retry Time of 10us has
elapsed. When the device is in the LPM suspended state (LPM
suspend bit = 1) and the software writes a zero to this bit, the
device will generate a remote walk-up. Software can only write
a zero to this bit when the LPM_REWP bit is set to 1. HW resets
this bit when it receives a host initiated resume. HW only
updates the LPM_SUS bit when the LPM_SUPP bit is equal to
one.
RW
20
LPM_REWP
LPM Remote Wake-up Enabled by USB host.
0
HW sets this bit to one when the bRemoteWake bit in the LPM
extended token is set to 1. HW will reset this bit to 0 when it
receives the host initiated LPM resume, when a remote
wake-up is sent by the device or when a USB bus reset is
received. Software can use this bit to check if the remote
wake-up feature is enabled by the host for the LPM transaction.
RO
23:21
-
Reserved.
0
RO
24
DCON_C
Device status - connect change.
The Connect Change bit is set when the device’s pull-up
resistor is disconnected because VBus disappeared. The bit is
reset by writing a one to it.
0
RWC
25
DSUS_C
Device status - suspend change.
The suspend change bit is set to 1 when the suspend bit
toggles. The suspend bit can toggle because:
- The device goes in the suspended state
- The device is disconnected
- The device receives resume signaling on its upstream port.
The bit is reset by writing a one to it.
0
RWC
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Chapter 23: LPC15xx USB
Table 331. USB Device Command/Status register (DEVCMDSTAT, address 0x1C00 C000) bit description
Bit
Symbol
26
DRES_C
Value
Description
Reset
value
Access
Device status - reset change.
0
This bit is set when the device received a bus reset. On a bus
reset the device will automatically go to the default state
(unconfigured and responding to address 0). The bit is reset by
writing a one to it.
RWC
27
-
Reserved.
0
RO
28
VBUSDEBOUNCED
This bit indicates if VBUS is detected or not. The bit raises
0
immediately when VBUS becomes high. It drops to zero if
VBUS is low for at least 3 ms. If this bit is high and the DCon bit
is set, the HW will enable the pull-up resistor to signal a
connect.
RO
31:29
-
Reserved.
RO
0
23.6.2 USB Info register
Table 332. USB Info register (INFO, address 0x1C00 C004) bit description
Bit
Symbol
10:0
FRAME_NR
Frame number. This contains the frame number of the last
0
successfully received SOF. In case no SOF was received by the
device at the beginning of a frame, the frame number returned is
that of the last successfully received SOF. In case the SOF frame
number contained a CRC error, the frame number returned will be
the corrupted frame number as received by the device.
RO
14:11
ERR_CODE
The error code which last occurred:
0
RW
Reserved.
0
RO
Reserved
-
RO
15
-
31:16
-
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Value
Description
Reset
value
0x0
No error
0x1
PID encoding error
0x2
PID unknown
0x3
Packet unexpected
0x4
Token CRC error
0x5
Data CRC error
0x6
Time out
0x7
Babble
0x8
Truncated EOP
0x9
Sent/Received NAK
0xA
Sent Stall
0xB
Overrun
0xC
Sent empty packet
0xD
Bitstuff error
0xE
Sync error
0xF
Wrong data toggle
-
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23.6.3 USB EP Command/Status List start address
This 32-bit register indicates the start address of the USB EP Command/Status List.
Only a subset of these bits is programmable by software. The 8 least-significant bits are
hardcoded to zero because the list must start on a 256 byte boundary. The bits 31 to 8
can be programmed by software.
Table 333. USB EP Command/Status List start address (EPLISTSTART, address
0x1C00 C008) bit description
Bit
Symbol
Description
Reset
value
Access
7:0
-
Reserved
0
RO
31:8
EP_LIST
Start address of the USB EP Command/Status List.
0
R/W
23.6.4 USB Data buffer start address
This register indicates the page of the AHB address where the endpoint data can be
located.
Table 334. USB Data buffer start address (DATABUFSTART, address 0x1C00 C00C) bit
description
Bit
Symbol
Description
Reset
value
Access
21:0
-
Reserved
0
R
31:22
DA_BUF
Start address of the buffer pointer page where all
endpoint data buffers are located.
0
R/W
23.6.5 Link Power Management register
Table 335. Link Power Management register (LPM, address 0x1C00 C010) bit description
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Bit
Symbol
Description
Reset
value
Access
3:0
HIRD_HW
Host Initiated Resume Duration - HW. This is
the HIRD value from the last received LPM
token
0
RO
7:4
HIRD_SW
Host Initiated Resume Duration - SW. This is
the time duration required by the USB device
system to come out of LPM initiated suspend
after receiving the host initiated LPM resume.
0
R/W
8
DATA_PENDING
As long as this bit is set to one and LPM
0
supported bit is set to one, HW will return a
NYET handshake on every LPM token it
receives.
If LPM supported bit is set to one and this bit is
zero, HW will return an ACK handshake on
every LPM token it receives.
If SW has still data pending and LPM is
supported, it must set this bit to 1.
R/W
31:9
-
Reserved
RO
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Chapter 23: LPC15xx USB
23.6.6 USB Endpoint skip
Table 336. USB Endpoint skip (EPSKIP, address 0x1C00 C014) bit description
Bit
Symbol
Description
Reset
value
29:0
SKIP
Endpoint skip: Writing 1 to one of these bits, will indicate 0
to HW that it must deactivate the buffer assigned to this
endpoint and return control back to software. When HW
has deactivated the endpoint, it will clear this bit, but it
will not modify the EPINUSE bit.
An interrupt will be generated when the Active bit goes
from 1 to 0.
Note: In case of double-buffering, HW will only clear the
Active bit of the buffer indicated by the EPINUSE bit.
R/W
31:30
-
Reserved
R
0
Access
23.6.7 USB Endpoint Buffer in use
Table 337. USB Endpoint Buffer in use (EPINUSE, address 0x1C00 C018) bit description
Bit
Symbol
Description
Reset
value
Access
1:0
-
Reserved. Fixed to zero because the control endpoint
zero is fixed to single-buffering for each physical
endpoint.
0
R
9:2
BUF
Buffer in use: This register has one bit per physical
endpoint.
0: HW is accessing buffer 0.
1: HW is accessing buffer 1.
0
R/W
31:10
-
Reserved
0
R
23.6.8 USB Endpoint Buffer Configuration
Table 338. USB Endpoint Buffer Configuration (EPBUFCFG, address 0x1C00 C01C) bit
description
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Bit
Symbol
Description
Reset
value
Access
1:0
-
Reserved. Fixed to zero because the control endpoint
zero is fixed to single-buffering for each physical
endpoint.
0
R
9:2
BUF_SB
Buffer usage: This register has one bit per physical
endpoint.
0: Single-buffer.
1: Double-buffer.
If the bit is set to single-buffer (0), it will not toggle the
corresponding EPINUSE bit when it clears the active bit.
If the bit is set to double-buffer (1), HW will toggle the
EPINUSE bit when it clears the Active bit for the buffer.
0
R/W
31:10
-
Reserved
0
R
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Chapter 23: LPC15xx USB
23.6.9 USB interrupt status register
Table 339. USB interrupt status register (INTSTAT, address 0x1C00 C020) bit description
Bit
Symbol
Description
0
EP0OUT
Interrupt status register bit for the Control EP0 OUT direction.
0
This bit will be set if NBytes transitions to zero or the skip bit is set by software
or a SETUP packet is successfully received for the control EP0.
If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted
for the Control EP0 OUT direction.
Software can clear this bit by writing a one to it.
R/WC
1
EP0IN
Interrupt status register bit for the Control EP0 IN direction.
This bit will be set if NBytes transitions to zero or the skip bit is set by
software.
If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted
for the Control EP0 IN direction.
Software can clear this bit by writing a one to it.
0
R/WC
2
EP1OUT
Interrupt status register bit for the EP1 OUT direction.
This bit will be set if the corresponding Active bit is cleared by HW. This is
done in case the programmed NBytes transitions to zero or the skip bit is set
by software.
If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted
for the EP1 OUT direction.
Software can clear this bit by writing a one to it.
0
R/WC
3
EP1IN
Interrupt status register bit for the EP1 IN direction.
This bit will be set if the corresponding Active bit is cleared by HW. This is
done in case the programmed NBytes transitions to zero or the skip bit is set
by software.
If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted
for the EP1 IN direction.
Software can clear this bit by writing a one to it.
0
R/WC
4
EP2OUT
Interrupt status register bit for the EP2 OUT direction.
This bit will be set if the corresponding Active bit is cleared by HW. This is
done in case the programmed NBytes transitions to zero or the skip bit is set
by software.
If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted
for the EP2 OUT direction.
Software can clear this bit by writing a one to it.
0
R/WC
5
EP2IN
Interrupt status register bit for the EP2 IN direction.
This bit will be set if the corresponding Active bit is cleared by HW. This is
done in case the programmed NBytes transitions to zero or the skip bit is set
by software.
If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted
for the EP2 IN direction.
Software can clear this bit by writing a one to it.
0
R/WC
6
EP3OUT
Interrupt status register bit for the EP3 OUT direction.
This bit will be set if the corresponding Active bit is cleared by HW. This is
done in case the programmed NBytes transitions to zero or the skip bit is set
by software.
If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted
for the EP3 OUT direction.
Software can clear this bit by writing a one to it.
0
R/WC
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Chapter 23: LPC15xx USB
Table 339. USB interrupt status register (INTSTAT, address 0x1C00 C020) bit description
Bit
Symbol
Description
Reset
value
Access
7
EP3IN
Interrupt status register bit for the EP3 IN direction.
This bit will be set if the corresponding Active bit is cleared by HW. This is
done in case the programmed NBytes transitions to zero or the skip bit is set
by software.
If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted
for the EP3 IN direction.
Software can clear this bit by writing a one to it.
0
R/WC
8
EP4OUT
Interrupt status register bit for the EP4 OUT direction.
This bit will be set if the corresponding Active bit is cleared by HW. This is
done in case the programmed NBytes transitions to zero or the skip bit is set
by software.
If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted
for the EP4 OUT direction.
Software can clear this bit by writing a one to it.
0
R/WC
9
EP4IN
Interrupt status register bit for the EP4 IN direction.
This bit will be set if the corresponding Active bit is cleared by HW. This is
done in case the programmed NBytes transitions to zero or the skip bit is set
by software.
If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted
for the EP4 IN direction.
Software can clear this bit by writing a one to it.
0
R/WC
29:10
-
Reserved
0
RO
30
FRAME_INT
Frame interrupt.
This bit is set to one every millisecond when the VbusDebounced bit and the
DCON bit are set. This bit can be used by software when handling
isochronous endpoints.
Software can clear this bit by writing a one to it.
0
R/WC
31
DEV_INT
Device status interrupt. This bit is set by HW when one of the bits in the
0
Device Status Change register are set. Software can clear this bit by writing a
one to it.
R/WC
23.6.10 USB interrupt enable register
Table 340. USB interrupt enable register (INTEN, address 0x1C00 C024) bit description
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Bit
Symbol
Description
Reset
value
Access
9:0
EP_INT_EN
If this bit is set and the corresponding USB
interrupt status bit is set, a HW interrupt is
generated on the interrupt line indicated by the
corresponding USB interrupt routing bit.
0
R/W
29:10
-
Reserved
0
RO
30
FRAME_INT_EN If this bit is set and the corresponding USB
interrupt status bit is set, a HW interrupt is
generated on the interrupt line indicated by the
corresponding USB interrupt routing bit.
0
R/W
31
DEV_INT_EN
0
R/W
If this bit is set and the corresponding USB
interrupt status bit is set, a HW interrupt is
generated on the interrupt line indicated by the
corresponding USB interrupt routing bit.
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Chapter 23: LPC15xx USB
23.6.11 USB set interrupt status register
Table 341. USB set interrupt status register (INTSETSTAT, address 0x1C00 C028) bit
description
Bit
Symbol
Description
Reset
value
Access
9:0
EP_SET_INT
If software writes a one to one of these bits, the 0
corresponding USB interrupt status bit is set.
When this register is read, the same value as the
USB interrupt status register is returned.
R/W
29:10
-
Reserved
RO
30
FRAME_SET_INT
If software writes a one to one of these bits, the 0
corresponding USB interrupt status bit is set.
When this register is read, the same value as the
USB interrupt status register is returned.
R/W
31
DEV_SET_INT
If software writes a one to one of these bits, the 0
corresponding USB interrupt status bit is set.
When this register is read, the same value as the
USB interrupt status register is returned.
R/W
0
23.6.12 USB interrupt routing register
Table 342. USB interrupt routing register (INTROUTING, address 0x1C00 C02C) bit
description
Bit
Symbol
Description
Reset
value
Access
9:0
ROUTE_INT
This bit can control on which hardware interrupt line
the interrupt will be generated:
0: IRQ interrupt line is selected for this interrupt bit
1: FIQ interrupt line is selected for this interrupt bit
0
R/W
29:10
-
Reserved
0
RO
30
ROUTE_INT30 This bit can control on which hardware interrupt line
the interrupt will be generated:
0: IRQ interrupt line is selected for this interrupt bit
1: FIQ interrupt line is selected for this interrupt bit
0
R/W
31
ROUTE_INT31 This bit can control on which hardware interrupt line
the interrupt will be generated:
0: IRQ interrupt line is selected for this interrupt bit
1: FIQ interrupt line is selected for this interrupt bit
0
R/W
23.6.13 USB Endpoint toggle
Table 343. USB Endpoint toggle (EPTOGGLE, address 0x1C00 C034) bit description
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Bit
Symbol
Description
Reset
value
Access
9:0
TOGGLE
Endpoint data toggle: This field indicates the current
value of the data toggle for the corresponding
endpoint.
0
R
31:10
-
Reserved
0
R
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Chapter 23: LPC15xx USB
23.7 Functional description
23.7.1 Endpoint command/status list
Figure 61 gives an overview on how the Endpoint List is organized in memory. The USB
EP Command/Status List start register points to the start of the list that contains all the
endpoint information in memory. The order of the endpoints is fixed as shown in the
picture.
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Chapter 23: LPC15xx USB
Table 344. Endpoint commands
Symbol
Access
Description
A
RW
Active
The buffer is enabled. HW can use the buffer to store received OUT data or
to transmit data on the IN endpoint.
Software can only set this bit to ‘1’. As long as this bit is set to one,
software is not allowed to update any of the values in this 32-bit word. In
case software wants to deactivate the buffer, it must write a one to the
corresponding “skip” bit in the USB Endpoint skip register. Hardware can
only write this bit to zero. It will do this when it receives a short packet or
when the NBytes field transitions to zero or when software has written a
one to the “skip” bit.
D
RW
Disabled
0: The selected endpoint is enabled.
1: The selected endpoint is disabled.
If a USB token is received for an endpoint that has the disabled bit set,
hardware will ignore the token and not return any data or handshake.
When a bus reset is received, software must set the disable bit of all
endpoints to 1.
Software can only modify this bit when the active bit is zero.
S
RW
Stall
0: The selected endpoint is not stalled
1: The selected endpoint is stalled
The Active bit has always higher priority than the Stall bit. This means that
a Stall handshake is only sent when the active bit is zero and the stall bit is
one.
Software can only modify this bit when the active bit is zero.
TR
RW
Toggle Reset
When software sets this bit to one, the HW will set the toggle value equal to
the value indicated in the “toggle value” (TV) bit.
For the control endpoint zero, this is not needed to be used because the
hardware resets the endpoint toggle to one for both directions when a
setup token is received.
For the other endpoints, the toggle can only be reset to zero when the
endpoint is reset.
RF / TV
RW
Rate Feedback mode / Toggle value
For bulk endpoints and isochronous endpoints this bit is reserved and must
be set to zero.
For the control endpoint zero this bit is used as the toggle value. When the
toggle reset bit is set, the data toggle is updated with the value
programmed in this bit.
When the endpoint is used as an interrupt endpoint, it can be set to the
following values.
0: Interrupt endpoint in ‘toggle mode’
1: Interrupt endpoint in ‘rate feedback mode’. This means that the data
toggle is fixed to zero for all data packets.
When the interrupt endpoint is in ‘rate feedback mode’, the TR bit must
always be set to zero.
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Chapter 23: LPC15xx USB
Table 344. Endpoint commands
Symbol
Access
Description
T
RW
Endpoint Type
0: Generic endpoint. The endpoint is configured as a bulk or interrupt
endpoint
1: Isochronous endpoint
NBytes
RW
For OUT endpoints this is the number of bytes that can be received in this
buffer.
For IN endpoints this is the number of bytes that must be transmitted.
HW decrements this value with the packet size every time when a packet is
successfully transferred.
Note: If a short packet is received on an OUT endpoint, the active bit will be
cleared and the NBytes value indicates the remaining buffer space that is
not used. Software calculates the received number of bytes by subtracting
the remaining NBytes from the programmed value.
Address
Offset
RW
Bits 21 to 6 of the buffer start address.
If the endpoint type is set to ‘0’ (generic endpoint) this address is
incremented every time a packet has been successfully
received/transmitted.
If the endpoint type is set to ‘1’ (isochronous endpoint), the address is not
incremented.
Remark: When receiving a SETUP token for endpoint zero, the HW will only read the
SETUP bytes Buffer Address offset to know where it has to store the received SETUP
bytes. The hardware will ignore all other fields. In case the SETUP stage contains more
than 8 bytes, it will only write the first 8 bytes to memory. A USB compliant host must
never send more than 8 bytes during the SETUP stage.
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Chapter 23: LPC15xx USB
23.7.2 Control endpoint 0
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Chapter 23: LPC15xx USB
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Fig 63. Flowchart of control endpoint 0 - IN direction
23.7.3 Generic endpoint: single-buffering
To enable single-buffering, software must set the corresponding "USB EP Buffer Config"
bit to zero. In the "USB EP Buffer in use" register, software can indicate which buffer is
used in this case.
When software wants to transfer data, it programs the different bits in the Endpoint
command/status entry and sets the active bits. The hardware will transmit/receive multiple
packets for this endpoint until the NBytes value is equal to zero. When NBytes goes to
zero, hardware clears the active bit and sets the corresponding interrupt status bit.
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Chapter 23: LPC15xx USB
Software must wait until hardware has cleared the Active bit to change some of the
command/status bits. This prevents hardware from overwriting a new value programmed
by software with some old values that were still cached.
If software wants to disable the active bit before the hardware has finished handling the
complete buffer, it can do this by setting the corresponding endpoint skip bit in USB
endpoint skip register.
23.7.4 Generic endpoint: double-buffering
To enable double-buffering, software must set the corresponding "USB EP Buffer Config"
bit to one. The "USB EP Buffer in use" register indicates which buffer will be used by HW
when the next token is received.
When HW clears the active bit of the current buffer in use, it will switch the buffer in use.
Software can also force HW to use a certain buffer by writing to the "USB EP Buffer in
use" bit.
23.7.5 Special cases
23.7.5.1 Use of the Active bit
The use of the Active bit is a bit different between OUT and IN endpoints.
When data must be received for the OUT endpoint, the software will set the Active bit to
one and program the NBytes field to the maximum number of bytes it can receive.
When data must be transmitted for an IN endpoint, the software sets the Active bit to one
and programs the NBytes field to the number of bytes that must be transmitted.
23.7.5.2 Generation of a STALL handshake
Special care must be taken when programming the endpoint to send a STALL handshake.
A STALL handshake is only sent in the following situations:
• The endpoint is enabled (Disabled bit = 0)
• The active bit of the endpoint is set to 0. (No packet needs to be received/transmitted
for that endpoint).
• The stall bit of the endpoint is set to one.
23.7.5.3 Clear Feature (endpoint halt)
When a non-control endpoint has returned a STALL handshake, the host will send a Clear
Feature (Endpoint Halt) for that endpoint. When the device receives this request, the
endpoint must be unstalled and the toggle bit for that endpoint must be reset back to zero.
In order to do that the software must program the following items for the endpoint that is
indicated.
If the endpoint is used in single-buffer mode, program the following:
• Set STALL bit (S) to 0.
• Set toggle reset bit (TR) to 1 and set toggle value bit (TV) to 0.
If the endpoint is used in double-buffer mode, program the following:
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Chapter 23: LPC15xx USB
• Set the STALL bit of both buffer 0 and buffer 1 to 0.
• Read the buffer in use bit for this endpoint.
• Set the toggle reset bit (TR) to 1 and set the toggle value bit (TV) to 0 for the buffer
indicated by the buffer in use bit.
23.7.5.4 Set configuration
When a SetConfiguration request is received with a configuration value different from
zero, the device software must enable all endpoints that will be used in this configuration
and reset all the toggle values. To do so, it must generate the procedure explained in
Section 23.7.5.3 for every endpoint that will be used in this configuration.
For all endpoints that are not used in this configuration, it must set the Disabled bit (D) to
one.
23.7.6 USB wake-up
23.7.6.1 Waking up from Deep-sleep and Power-down modes on USB activity
To allow the part to wake up from Deep-sleep or Power-down mode on USB activity,
complete the following steps:
1. Set bit AP_CLK in the USBCLKCTRL register (Table 62) to 0 (default) to enable
automatic control of the USB need_clock signal.
2. Wait until USB activity is suspended by polling the DSUS bit in the DSVCMD_STAT
register (DSUS = 1).
3. The USB need_clock signal will be deasserted after another 2 ms. Poll the
USBCLKST register until the USB need_clock status bit is 0 (Table 63).
4. Once the USBCLKST register returns 0, enable the USB activity wake-up interrupt in
the NVIC (# 30) and clear it.
5. Set bit 1 in the USBCLKCTRL register to 1 to trigger the USB activity wake-up
interrupt on the rising edge of the USB need_clock signal.
6. Enable the wake-up from Deep-sleep or Power-down modes on this interrupt by
enabling the USB need_clock signal in the STARTERP0 register (Table 76, bit 30).
7. Enter Deep-sleep or Power-down modes by writing to the power configuration API.
8. Execute a WFI instruction.
The part will automatically wake up and resume execution on USB activity.
23.7.6.2 Remote wake-up
To issue a remote wake-up when the USB activity is suspended, complete the following
steps:
1. Set bit AP_CLK in the USBCLKCTRL register to 0 (Table 62, default) to enable
automatic control of the USB need_clock signal.
2. When it is time to issue a remote wake-up, turn on the USB clock and enable the USB
clock source.
3. Force the USB clock on by writing a 1 to bit AP_CLK (Table 62, bit 0) in the
USBCLKCTRL register.
4. Write a 0 to the DSUS bit in the DSVCMD_STAT register.
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Chapter 23: LPC15xx USB
5. Wait until the USB leaves the suspend state by polling the DSUS bit in the
DSVCMD_STAT register (DSUS =0).
6. Clear the AP_CLK bit (Table 62, bit 0) in the USBCLKCTRL to enable automatic USB
clock control.
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Chapter 24: LPC15xx USART0/1/2
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User manual
24.1 How to read this chapter
Read this chapter for a description of the USART peripheral and the software interface.
The LPC15xx also supports an on-chip ROM-based USART API to configure and operate
the USART. See Chapter 36.
24.2 Features
• 7, 8, or 9 data bits and 1 or 2 stop bits
• Synchronous mode with master or slave operation. Includes data phase selection and
continuous clock option.
•
•
•
•
•
•
Multiprocessor/multidrop (9-bit) mode with software address compare.
•
•
•
•
•
•
Received data and status can optionally be read from a single register
RS-485 transceiver output enable.
Parity generation and checking: odd, even, or none.
Software selectable oversampling from 5 to 16 clocks in asynchronous mode.
One transmit and one receive data buffer.
RTS/CTS for hardware signaling for automatic flow control. Software flow control can
be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an
RTS output.
Break generation and detection.
Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.
Built-in Baud Rate Generator with auto-baud function.
A fractional rate divider is shared among all USARTs.
Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in
receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS
detect, and receiver sample noise detected.
• Loopback mode for testing of data and flow control.
• UART transmit and receive functions can operated with the system DMA controller.
• Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC
oscillator as the UART clock. This mode can be used while the device is in
Power-down mode and can wake-up the device when a character is received.
• UARTn transmit and receive functions can operated with the system DMA controller.
24.3 Basic configuration
Remark: The on-chip USART API provides software routines to configure and use the
USART. See Chapter 36.
Configure USART0/1/2 for receiving and transmitting data:
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Chapter 24: LPC15xx USART0/1/2
• In the SYSAHBCLKCTRL1 register, set bit 17 to 19 (Table 51) to enable the clock to
the register interface.
• Clear the USART0/1/2 peripheral resets using the PRESETCTRL1 register
(Table 36).
•
•
•
•
Enable or disable the USART0/1/2 interrupts in slots #21 to 23 in the NVIC.
Configure the USART0/1/2 pin functions through the switch matrix. See Section 24.4.
Configure the USART clock and baud rate. See Section 24.3.1.
Send and receive lines are connected to DMA request lines. See Table 167.
Configure the USART0/1/2 to wake up the part from low power modes:
• Configure the USART to receive and transmit data in synchronous slave mode. See
Section 24.3.2.
24.3.1 Configure the USART clock and baud rate
All three USARTs use a common peripheral clock (U_PCLK) and, if needed, a fractional
baud rate generator. The peripheral clock and the fractional divider for the baud rate
calculation are set up in the SYSCON block as follows (see Figure 64):
1. Configure the UART clock by writing a value UARTCLKDIV > 0 in the USART
peripheral clock divider register. This is the divided main clock common to all
USARTs.
Section 3.6.25 “USART clock divider register”
2. If a fractional value is needed to obtain a particular baud rate, program the fractional
divider. The fractional divider value is the fraction of MULT/DIV. The MULT and DIV
values are programmed in the FRGCTRL register. The DIV value must be
programmed with the fixed value of 256.
U_PCLK = UARTCLKDIV/(1+(MULT/DIV))
The following rules apply for MULT and DIV:
– Always set DIV to 256 by programming the FRGCTRL register with the value of
0xFF.
– Set the MULT to any value between 0 and 255.
Table 61 “USART fractional baud rate generator register (FRGCTRL, address
0x4007 4128) bit description”
3. In asynchronous mode: Configure the baud rate divider BRGVAL in the USARTn BRG
register. The baud rate divider divides the common USART peripheral clock by a
factor of 16 multiplied by the baud rate value to provide the
baud rate = U_PCLK/16 x BRGVAL.
Section 24.6.9 “USART Baud Rate Generator register”
4. In synchronous mode: The serial clock is Un_SCLK = U_PCLK/BRGVAL.
The USART can also be clocked by the 32 kHz RTC oscillator. Set the MODE32K bit to
enable this 32 kHz mode. See also Section 24.7.1.4 “32 kHz mode”.
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Chapter 24: LPC15xx USART0/1/2
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For details on the clock configuration see:
Section 24.7.1 “Clocking and baud rates”
24.3.2 Configure the USART for wake-up
The USART can wake up the system from sleep mode in asynchronous or synchronous
mode on any enabled USART interrupt.
In Deep-sleep or power-down mode, you have two options for configuring USART for
wake-up:
• If the USART is configured for synchronous slave mode, the USART block can create
an interrupt on a received signal even when the USART block receives no clocks from
the ARM Cortex-M3 core - that is in Deep-sleep or Power-down mode.
As long as the USART receives a clock signal from the master, it can receive up to
one byte in the RXDAT register while in Deep-sleep or Power-down mode. Any
interrupt raised as part of the receive data process can then wake up the part.
• If the 32 kHz mode is enabled, the USART can run in asynchronous mode using the
32 kHz RTC oscillator and create interrupts.
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Chapter 24: LPC15xx USART0/1/2
24.3.2.1 Wake-up from Sleep mode
• Configure the USART in either asynchronous mode or synchronous mode. See
Table 347.
• Enable the USART interrupt in the NVIC.
• Any USART interrupt wakes up the part from sleep mode. Enable the USART
interrupt in the INTENSET register (Table 350).
24.3.2.2 Wake-up from Deep-sleep or Power-down mode
• Configure the USART in synchronous slave mode. See Table 347. You must connect
the SCLK function to a pin and connect the pin to the master. Alternatively, you can
enable the 32 kHz mode and use the USART in asynchronous mode with the 32 kHz
RTC oscillator.
• Enable the USART interrupt in the STARTERP1 register. See Table 76 “Start logic 0
wake-up enable register 0 (STARTERP0, address 0x4007 4218) bit description”.
• Enable the USART interrupt in the NVIC.
• In the PDAWAKE register, configure all peripherals that need to be running when the
part wakes up.
• The USART wakes up the part from Deep-sleep or Power-down mode on all events
that cause an interrupt and are also enabled in the INTENSET register. Typical
wake-up events are:
– A start bit has been received.
– The RXDAT buffer has received a byte.
– Data is ready to be transmitted in the TXDAT buffer and a serial clock from the
master has been received.
– A change in the state of the CTS pin if the CTS function is connected.
– Remark: By enabling or disabling the interrupt in the INTENSET register
(Table 350), you can customize when the wake-up occurs in the USART
receive/transmit protocol.
24.4 Pin description
The USART receive, transmit, and control signals are movable functions and are
assigned to external pins through the switch matrix.
See Section 8.3.1 “Connect an internal signal to a package pin” to assign the USART
functions to pins on the LPC15xx package.
Table 345. USART pin description
Function
Direction Pin
Description
SWM register
Reference
U0_TXD
O
any
Transmitter output for USART0. Serial transmit data.
PINASSIGN0
Table 107
U0_RXD
I
any
Receiver input for USART0. Serial receive data.
PINASSIGN0
Table 107
U0_RTS
O
any
Request To Send output for USART0. This signal supports PINASSIGN0
inter-processor communication through the use of hardware
flow control. This feature is active when the USART RTS
signal is configured to appear on a device pin.
Table 107
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Chapter 24: LPC15xx USART0/1/2
Table 345. USART pin description
Function
Direction Pin
Description
SWM register
Reference
U0_CTS
I
any
Clear To Send input for USART0. Active low signal indicates PINASSIGN0
that the external device that is in communication with the
USART is ready to accept data. This feature is active when
enabled by the CTSEn bit in CFG register and when
configured to appear on a device pin. When deasserted
(high) by the external device, the USART will complete
transmitting any character already in progress, then stop
until CTS is again asserted (low).
Table 107
U0_SCLK
I/O
any
Serial clock input/output for USART0 in synchronous mode. PINASSIGN1
Clock input or output in synchronous mode.
Table 108
U1_TXD
O
any
Transmitter output for USART1. Serial transmit data.
PINASSIGN1
Table 108
U1_RXD
I
any
Receiver input for USART1.
PINASSIGN1
Table 108
U1_RTS
O
any
Request To Send output for USART1.
PINASSIGN1
Table 108
U1_CTS
I
any
Clear To Send input for USART1.
PINASSIGN2
Table 109
U1_SCLK
I/O
any
Serial clock input/output for USART1 in synchronous mode. PINASSIGN2
Table 109
U2_TXD
O
any
Transmitter output for USART2. Serial transmit data.
PINASSIGN2
Table 109
U2_RXD
I
any
Receiver input for USART2.
PINASSIGN2
Table 109
U2_SCLK
I/O
any
Serial clock input/output for USART2 in synchronous mode. PINASSIGN3
Table 110
24.5 General description
The USART receiver block monitors the serial input line, Un_RXD, for valid input. The
receiver shift register assembles characters as they are received, after which they are
passed to the receiver buffer register to await access by the CPU or the DMA controller.
When RTS signal is configured as an RS-485 output enable, it is asserted at the
beginning of an transmitted character, and deasserted either at the end of the character,
or after a one character delay (selected by software).
The USART transmitter block accepts data written by the CPU or DMA controllers and
buffers the data in the transmit holding register. When the transmitter is available, the
transmit shift register takes that data, formats it, and serializes it to the serial output,
Un_TXD.
The Baud Rate Generator block divides the incoming clock to create a 16x baud rate
clock in the standard asynchronous operating mode. The BRG clock input source is the
shared Fractional Rate Generator that runs from the common USART peripheral clock
U_PCLK). The 32 kHz operating mode generates a specially timed internal clock based
on the RTC oscillator frequency.
In synchronous slave mode, data is transmitted and received using the serial clock
directly. In synchronous master mode, data is transmitted and received using the baud
rate clock without division.
Status information from the transmitter and receiver is saved and provided via the Stat
register. Many of the status flags are able to generate interrupts, as selected by software.
Remark: The fractional value and the USART peripheral clock are shared between all
USARTs.
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Chapter 24: LPC15xx USART0/1/2
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U_PCLK = UARTCLKDIV/(1+MULT/DIV)
Fig 65. USART block diagram
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Chapter 24: LPC15xx USART0/1/2
24.6 Register description
The reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Table 346: Register overview: USART (base address 0x4004 0000 (USART0), 0x4004 4000 (USART1), 0x400C 0000
(USART2))
Name
Access Offset
Description
Reset
value
Reference
CFG
R/W
0x000
USART Configuration register. Basic USART configuration
settings that typically are not changed during operation.
0
Table 347
CTL
R/W
0x004
USART Control register. USART control settings that are more
likely to change during operation.
0
Table 348
STAT
R/W
0x008
USART Status register. The complete status value can be read
here. Writing ones clears some bits in the register. Some bits
can be cleared by writing a 1 to them.
0x000E
Table 349
INTENSET
R/W
0x00C
Interrupt Enable read and Set register. Contains an individual
0
interrupt enable bit for each potential USART interrupt. A
complete value may be read from this register. Writing a 1 to any
implemented bit position causes that bit to be set.
Table 350
INTENCLR
W
0x010
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented
bit position causes the corresponding bit to be cleared.
Table 351
RXDAT
R
0x014
Receiver Data register. Contains the last character received.
-
Table 352
RXDATSTAT
R
0x018
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or
software to recover incoming data and status together.
Table 353
TXDAT
R/W
0x01C
Transmit Data register. Data to be transmitted is written here.
0
Table 354
BRG
R/W
0x020
Baud Rate Generator register. 16-bit integer baud rate divisor
value.
0
Table 355
INTSTAT
R
0x024
Interrupt status register. Reflects interrupts that are currently
enabled.
0x0005
Table 356
OSR
R/W
0x028
Oversample selection register for asynchronous
communication.
0xF
Table 357
ADDR
R/W
0x02C
Address register for automatic address matching.
0
Table 358
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Chapter 24: LPC15xx USART0/1/2
24.6.1 USART Configuration register
The CFG register contains communication and mode settings for aspects of the USART
that would normally be configured once in an application.
Remark: If software needs to change configuration values, the following sequence should
be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable
the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3)
Write the new configuration value, with the ENABLE bit set to 1.
Table 347. USART Configuration register (CFG, address 0x4004 0000 (USART0), 0x4004 4000
(USART1), 0x400C 0000 (USART2)) bit description
Bit
Symbol
0
ENABLE
-
3:2
DATALEN
6
User manual
Reset
Value
USART Enable.
1
5:4
UM10736
Value Description
0
0
Disabled. The USART is disabled and the internal state
machine and counters are reset. While Enable = 0, all
USART interrupts and DMA transfers are disabled. When
Enable is set again, CFG and most other control bits remain
unchanged. For instance, when re-enabled, the USART will
immediately generate a TxRdy interrupt (if enabled in the
INTENSET register) or a DMA transfer request because the
transmitter has been reset and is therefore available.
1
Enabled. The USART is enabled for operation.
Reserved. Read value is undefined, only zero should be
written.
NA
Selects the data size for the USART.
00
0x0
7 bit Data length.
0x1
8 bit Data length.
0x2
9 bit data length. The 9th bit is commonly used for
addressing in multidrop mode. See the ADDRDET bit in the
CTL register.
0x3
Reserved.
PARITYSEL
Selects what type of parity is used by the USART.
00
0x0
No parity.
0x1
Reserved.
0x2
Even parity. Adds a bit to each character such that the
number of 1s in a transmitted character is even, and the
number of 1s in a received character is expected to be even.
0x3
Odd parity. Adds a bit to each character such that the
number of 1s in a transmitted character is odd, and the
number of 1s in a received character is expected to be odd.
STOPLEN
Number of stop bits appended to transmitted data. Only a
single stop bit is required for received data.
0
1 stop bit.
1
2 stop bits. This setting should only be used for
asynchronous communication.
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Chapter 24: LPC15xx USART0/1/2
Table 347. USART Configuration register (CFG, address 0x4004 0000 (USART0), 0x4004 4000
(USART1), 0x400C 0000 (USART2)) bit description …continued
Bit
Symbol
7
MODE32K
Selects standard or 32 kHz clocking mode.
0
0
UART uses standard clocking.
1
UART uses the 32 kHz clock from the RTC oscillator as the
clock source to the BRG, and uses a special bit clocking
scheme.
-
Reserved. Read value is undefined, only zero should be
written.
9
CTSEN
0
CTS Enable. Determines whether CTS is used for flow
control. CTS can be from the input pin, or from the USART’s
own RTS if loopback mode is enabled. See Section 24.7.4
for more information.
NA
0
No flow control. The transmitter does not receive any
automatic flow control signal.
1
Flow control enabled. The transmitter uses the CTS input
(or RTS output in loopback mode) for flow control purposes.
10
-
Reserved. Read value is undefined, only zero should be
written.
NA
11
SYNCEN
Selects synchronous or asynchronous operation.
0
0
Asynchronous mode is selected.
1
Synchronous mode is selected.
CLKPOL
Selects the clock polarity and sampling edge of received
data in synchronous mode.
13
-
14
SYNCMST
15
0
Falling edge. Un_RXD is sampled on the falling edge of
SCLK.
1
Rising edge. Un_RXD is sampled on the rising edge of
SCLK.
0
Reserved. Read value is undefined, only zero should be
written.
NA
Synchronous mode Master select.
0
0
Slave. When synchronous mode is enabled, the USART is a
slave.
1
Master. When synchronous mode is enabled, the USART is
a master.
LOOP
17:16 -
User manual
Reset
Value
8
12
UM10736
Value Description
Selects data loopback mode.
0
0
Normal operation.
1
Loopback mode. This provides a mechanism to perform
diagnostic loopback testing for USART data. Serial data
from the transmitter (Un_TXD) is connected internally to
serial input of the receive (Un_RXD). Un_TXD and Un_RTS
activity will also appear on external pins if these functions
are configured to appear on device pins. The receiver RTS
signal is also looped back to CTS and performs flow control
if enabled by CTSEN.
Reserved. Read value is undefined, only zero should be
written.
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Chapter 24: LPC15xx USART0/1/2
Table 347. USART Configuration register (CFG, address 0x4004 0000 (USART0), 0x4004 4000
(USART1), 0x400C 0000 (USART2)) bit description …continued
Bit
Symbol
18
OETA
19
20
21
22
23
Value Description
Output Enable Turnaround time enable for RS-485
operation.
0
Disabled. If selected by OESEL, the Output Enable signal
deasserted at the end of the last stop bit of a transmission.
1
Enabled. If selected by OESEL, the Output Enable signal
remains asserted for one character time after the end of the
last stop bit of a transmission. OE will also remain asserted if
another transmit begins before it is deasserted.
0
Disabled. When addressing is enabled by ADDRDET,
address matching is done by software. This provides the
possibility of versatile addressing (e.g. respond to more than
one address).
1
Enabled. When addressing is enabled by ADDRDET,
address matching is done by hardware, using the value in
the ADDR register as the address to match.
AUTOADDR
0
Automatic Address matching enable.
OESEL
0
Output Enable Select.
0
0
Standard. The RTS signal is used as the standard flow
control function.
1
RS-485. The RTS signal configured to provide an output
enable signal to control an RS-485 transceiver.
OEPOL
Output Enable Polarity.
0
0
Low. If selected by OESEL, the output enable is active low.
1
High. If selected by OESEL, the output enable is active high.
RXPOL
Receive data polarity.
0
0
Standard. The RX signal is used as it arrives from the pin.
This means that the RX rest value is 1, start bit is 0, data is
not inverted, and the stop bit is 1.
1
Inverted. The RX signal is inverted before being used by the
UART. This means that the RX rest value is 0, start bit is 1,
data is inverted, and the stop bit is 0.
TXPOL
31:24 -
Reset
Value
Transmit data polarity.
0
0
Standard. The TX signal is sent out without change. This
means that the TX rest value is 1, start bit is 0, data is not
inverted, and the stop bit is 1.
1
Inverted. The TX signal is inverted by the UART before
being sent out. This means that the TX rest value is 0, start
bit is 1, data is inverted, and the stop bit is 0.
Reserved. Read value is undefined, only zero should be
written.
NA
24.6.2 USART Control register
The CTL register controls aspects of USART operation that are more likely to change
during operation.
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Table 348. USART Control register (CTL, address 0x4004 0004 (USART0), 0x4004 4004
(USART1), 0x400C 0004 (USART2)) bit description
Bit
Symbol
Value Description
0
-
1
TXBRKEN
Reset
Value
Reserved. Read value is undefined, only zero should be
written.
NA
Break Enable.
0
0
Normal operation.
1
Continuous break is sent immediately when this bit is set,
and remains until this bit is cleared.
A break may be sent without danger of corrupting any
currently transmitting character if the transmitter is first
disabled (TXDIS in CTL is set) and then waiting for the
transmitter to be disabled (TXDISINT in STAT = 1) before
writing 1 to TXBRKEN.
2
ADDRDET
0
Disabled. The USART presents all incoming data.
1
Enabled. The USART receiver ignores incoming data that
does not have the most significant bit of the data (typically
the 9th bit) = 1. When the data MSB bit = 1, the receiver
treats the incoming data normally, generating a received
data interrupt. Software can then check the data to see if
this is an address that should be handled. If it is, the
ADDRDET bit is cleared by software and further incoming
data is handled normally.
-
Reserved. Read value is undefined, only zero should be
written.
6
TXDIS
Transmit Disable.
NA
0
0
Not disabled. USART transmitter is not disabled.
1
Disabled. USART transmitter is disabled after any
character currently being transmitted is complete. This
feature can be used to facilitate software flow control.
7
-
Reserved. Read value is undefined, only zero should be
written.
8
CC
Continuous Clock generation. By default, SCLK is only
output while data is being transmitted in synchronous
mode.
NA
0
0
Clock on character. In synchronous mode, SCLK cycles
only when characters are being sent on Un_TXD or to
complete a character that is being received.
1
Continuous clock. SCLK runs continuously in
synchronous mode, allowing characters to be received on
Un_RxD independently from transmission on Un_TXD).
CLRCCONRX
15:10 -
User manual
0
5:3
9
UM10736
Enable address detect mode.
Clear Continuous Clock.
0
0
No affect on the CC bit.
1
Auto-clear. The CC bit is automatically cleared when a
complete character has been received. This bit is cleared
at the same time.
Reserved. Read value is undefined, only zero should be
written.
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Chapter 24: LPC15xx USART0/1/2
Table 348. USART Control register (CTL, address 0x4004 0004 (USART0), 0x4004 4004
(USART1), 0x400C 0004 (USART2)) bit description
Bit
Symbol
Value Description
16
AUTOBAUD
Reset
Value
Autobaud enable.
0
0
Disabled. UART is in normal operating mode.
1
Enabled. UART is in autobaud mode. This bit should only
be set when the UART receiver is idle. The first start bit of
RX is measured and used the update the BRG register to
match the received data rate. AUTOBAUD is cleared once
this process is complete, or if there is an AERR.
31:17 -
Reserved. Read value is undefined, only zero should be
written.
NA
24.6.3 USART Status register
The STAT register primarily provides a complete set of USART status flags for software to
read. Flags other than read-only flags may be cleared by writing ones to corresponding
bits of STAT. Interrupt status flags that are read-only and cannot be cleared by software,
can be masked using the INTENCLR register (see Table 351).
The error flags for received noise, parity error, framing error, and overrun are set
immediately upon detection and remain set until cleared by software action in STAT.
Table 349. USART Status register (STAT, address 0x4004 0008 (USART0), 0x4004 4008 (USART1), 0x400C 0008
(USART2)) bit description
Bit
Symbol
Description
Reset
value
Access
[1]
0
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from
the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT
registers.
0
RO
1
RXIDLE
Receiver Idle. When 0, indicates that the receiver is currently in the process of 1
receiving data. When 1, indicates that the receiver is not currently in the
process of receiving data.
RO
2
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to
the transmit buffer. Previous data may still be in the process of being
transmitted. Cleared when data is written to TXDAT. Set when the data is
moved from the transmit buffer to the transmit shift register.
1
RO
3
TXIDLE
Transmitter Idle. When 0, indicates that the transmitter is currently in the
process of sending data.When 1, indicate that the transmitter is not currently
in the process of sending data.
1
RO
4
CTS
This bit reflects the current state of the CTS signal, regardless of the setting of NA
the CTSEN bit in the CFG register. This will be the value of the CTS input pin
unless loopback mode is enabled.
RO
5
DELTACTS
This bit is set when a change in the state is detected for the CTS flag above.
This bit is cleared by software.
0
W1
6
TXDISSTAT
Transmitter Disabled Status flag. When 1, this bit indicates that the UART
transmitter is fully idle after being disabled via the TXDIS bit in the CFG
register (TXDIS = 1).
0
RO
7
-
Reserved. Read value is undefined, only zero should be written.
NA
NA
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Table 349. USART Status register (STAT, address 0x4004 0008 (USART0), 0x4004 4008 (USART1), 0x400C 0008
(USART2)) bit description
Bit
Symbol
Description
Reset
value
Access
[1]
8
OVERRUNINT
Overrun Error interrupt flag. This flag is set when a new character is received
while the receiver buffer is still in use. If this occurs, the newly received
character in the shift register is lost.
0
W1
9
-
Reserved. Read value is undefined, only zero should be written.
NA
NA
10
RXBRK
Received Break. This bit reflects the current state of the receiver break
0
detection logic. It is set when the Un_RXD pin remains low for 16 bit times.
Note that FRAMERRINT will also be set when this condition occurs because
the stop bit(s) for the character would be missing. RXBRK is cleared when the
Un_RXD pin goes high.
RO
11
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.
Cleared by software.
0
W1
12
START
This bit is set when a start is detected on the receiver input. Its purpose is
0
primarily to allow wake-up from Deep-sleep or Power-down mode immediately
when a start is detected. Cleared by software.
W1
13
FRAMERRINT
Framing Error interrupt flag. This flag is set when a character is received with
a missing stop bit at the expected location. This could be an indication of a
baud rate or configuration mismatch with the transmitting source.
0
W1
14
PARITYERRINT
Parity Error interrupt flag. This flag is set when a parity error is detected in a
received character..
0
W1
15
RXNOISEINT
0
Received Noise interrupt flag. Three samples of received data are taken in
order to determine the value of each received data bit, except in synchronous
mode. This acts as a noise filter if one sample disagrees. This flag is set when
a received data bit contains one disagreeing sample. This could indicate line
noise, a baud rate or character format mismatch, or loss of synchronization
during data reception.
W1
16
ABERR
0
Auto baud Error. An auto baud error can occur if the BRG counts to its limit
before the end of the start bit that is being measured, essentially an auto baud
time-out.
W1
Reserved. Read value is undefined, only zero should be written.
NA
31:17 [1]
NA
RO = Read-only, W1 = write 1 to clear.
24.6.4 USART Interrupt Enable read and set register
The INTENSET register is used to enable various USART interrupt sources. Enable bits in
INTENSET are mapped in locations that correspond to the flags in the STAT register. The
complete set of interrupt enables may be read from this register. Writing ones to
implemented bits in this register causes those bits to be set. The INTENCLR register is
used to clear bits in this register.
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Table 350. USART Interrupt Enable read and set register (INTENSET, address
0x4004 000C(USART0), 0x4004 400C (USART1), 0x400C 000C (USART2)) bit
description
Bit
Symbol
Description
0
RXRDYEN
When 1, enables an interrupt when there is a received
character available to be read from the RXDAT register.
0
1
-
Reserved. Read value is undefined, only zero should be
written.
NA
2
TXRDYEN
When 1, enables an interrupt when the TXDAT register is
available to take another character to transmit.
0
3
TXIDLEEN
When 1, enables an interrupt when the transmitter becomes
idle (TXIDLE = 1).
0
4
-
Reserved. Read value is undefined, only zero should be
written.
5
DELTACTSEN
When 1, enables an interrupt when there is a change in the
state of the CTS input.
0
6
TXDISEN
When 1, enables an interrupt when the transmitter is fully
disabled as indicated by the TXDISINT flag in STAT. See
description of the TXDISINT bit for details.
0
7
-
Reserved. Read value is undefined, only zero should be
written.
NA
8
OVERRUNEN
When 1, enables an interrupt when an overrun error
occurred.
10:9
-
Reserved. Read value is undefined, only zero should be
written.
NA
11
DELTARXBRKEN
When 1, enables an interrupt when a change of state has
occurred in the detection of a received break condition
(break condition asserted or deasserted).
0
12
STARTEN
When 1, enables an interrupt when a received start bit has
been detected.
0
13
FRAMERREN
When 1, enables an interrupt when a framing error has been
detected.
0
14
PARITYERREN
When 1, enables an interrupt when a parity error has been
detected.
0
15
RXNOISEEN
When 1, enables an interrupt when noise is detected. See
description of the RXNOISEINT bit in Table 349.
0
16
ABERREN
When 1, enables an interrupt when an auto baud error
occurs.
31:17 -
Reset
Value
Reserved. Read value is undefined, only zero should be
written.
NA
0
0
NA
24.6.5 USART Interrupt Enable Clear register
The INTENCLR register is used to clear bits in the INTENSET register.
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Table 351. USART Interrupt Enable clear register (INTENCLR, address 0x4000 0010
(USART0), 0x4004 4010 (USART1), 0x400C 0010 (USART2)) bit description
Bit
Symbol
Description
0
RXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET
register.
0
1
-
Reserved. Read value is undefined, only zero should be
written.
NA
2
TXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET
register.
0
3
TXIDLECLR
Writing 1 clears the corresponding bit in the INTENSET
register.
0
4
-
Reserved. Read value is undefined, only zero should be
written.
NA
5
DELTACTSCLR
Writing 1 clears the corresponding bit in the INTENSET
register.
0
6
TXDISCLR
Writing 1 clears the corresponding bit in the INTENSET
register.
0
7
-
Reserved. Read value is undefined, only zero should be
written.
NA
8
OVERRUNCLR
Writing 1 clears the corresponding bit in the INTENSET
register.
0
10:9
-
Reserved. Read value is undefined, only zero should be
written.
NA
11
DELTARXBRKCLR
Writing 1 clears the corresponding bit in the INTENSET
register.
0
12
STARTCLR
Writing 1 clears the corresponding bit in the INTENSET
register.
0
13
FRAMERRCLR
Writing 1 clears the corresponding bit in the INTENSET
register.
0
14
PARITYERRCLR
Writing 1 clears the corresponding bit in the INTENSET
register.
0
15
RXNOISECLR
Writing 1 clears the corresponding bit in the INTENSET
register.
0
16
ABERRCLR
Writing 1 clears the corresponding bit in the INTENSET
register.
31:17 -
Reset
Value
Reserved. Read value is undefined, only zero should be
written.
0
NA
24.6.6 USART Receiver Data register
The RXDAT register contains the last character received before any overrun.
Remark: Reading this register changes the status flags in the RXDATSTAT register.
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Table 352. USART Receiver Data register (RXDAT, address 0x4004 0014 (USART0),
0x4004 4014 (USART1), 0x400C 0014 (USART2)) bit description
Bit
Symbol Description
8:0
DATA
The USART Receiver Data register contains the next received
character. The number of bits that are relevant depends on the
USART configuration settings.
Reset Value
31:9
-
Reserved, the value read from a reserved bit is not defined.
0
NA
24.6.7 USART Receiver Data with Status register
The RXDATSTAT register contains the next complete character to be read and its relevant
status flags. This allows getting all information related to a received character with one
16-bit read, which may be especially useful when the DMA is used with the USART
receiver.
Remark: Reading this register changes the status flags.
Table 353. USART Receiver Data with Status register (RXDATSTAT, address 0x4004 0018
(USART0), 0x4004 4018 (USART1), 0x400C 0018 (USART2)) bit description
Bit
Symbol
Description
8:0
RXDATA
The USART Receiver Data register contains the next received
character. The number of bits that are relevant depends on the
USART configuration settings.
12:9
-
Reserved, the value read from a reserved bit is not defined.
13
FRAMERR
Framing Error status flag. This bit is valid when there is a character
to be read in the RXDAT register and reflects the status of that
character. This bit will set when the character in RXDAT was
received with a missing stop bit at the expected location. This
could be an indication of a baud rate or configuration mismatch
with the transmitting source.
0
14
PARITYERR
Parity Error status flag. This bit is valid when there is a character to
be read in the RXDAT register and reflects the status of that
character. This bit will be set when a parity error is detected in a
received character.
0
15
RXNOISE
Received Noise flag. See description of the RxNoiseInt bit in
Table 349.
0
Reserved, the value read from a reserved bit is not defined.
NA
31:16 -
Reset
Value
0
NA
24.6.8 USART Transmitter Data Register
The TXDAT register is written in order to send data via the USART transmitter. That data
will be transferred to the transmit shift register when it is available, and another character
may then be written to TXDAT.
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Table 354. USART Transmitter Data Register (TXDAT, address 0x4004 001C (USART0),
0x4004 401C (USART1), 0x400C 001C (USART2)) bit description
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Bit
Symbol
Description
8:0
TXDATA
Writing to the USART Transmit Data Register causes the data to be
transmitted as soon as the transmit shift register is available and any
conditions for transmitting data are met: CTS low (if CTSEN bit = 1),
TXDIS bit = 0.
31:9
-
Reserved. Only zero should be written.
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Value
0
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24.6.9 USART Baud Rate Generator register
The Baud Rate Generator is a simple 16-bit integer divider controlled by the BRG register.
The BRG register contains the value used to divide the base clock in order to produce the
clock used for USART internal operations.
A 16-bit value allows producing standard baud rates from 300 baud and lower at the
highest frequency of the device, up to 921,600 baud from a base clock as low as 14.7456
MHz.
Typically, the baud rate clock is 16 times the actual baud rate. This overclocking allows for
centering the data sampling time within a bit cell, and for noise reduction and detection by
taking three samples of incoming data.
Note that in 32 kHz mode, the baud rate generator is still used and must be set to 0 if 9600
baud is required.
Details on how to select the right values for BRG can be found later in this chapter, see
Section 24.7.1.
Remark: If software needs to change the baud rate, the following sequence should be
used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable the
USART by writing a 0 to the Enable bit (0 may be written to the entire registers). 3) Write
the new BRGVAL. 4) Write to the CFG register to set the Enable bit to 1.
Table 355. USART Baud Rate Generator register (BRG, address 0x4004 0020 (USART0),
0x4004 4020 (USART1), 0x400C 0020 (USART2)) bit description
Bit
Symbol
Description
Reset
Value
15:0
BRGVAL
This value is used to divide the USART input clock to determine the
baud rate, based on the input clock from the FRG.
0
0 = The FRG clock is used directly by the USART function.
1 = The FRG clock is divided by 2 before use by the USART function.
2 = The FRG clock is divided by 3 before use by the USART function.
...
0xFFFF = The FRG clock is divided by 65,536 before use by the
USART function.
31:16 -
Reserved. Read value is undefined, only zero should be written.
NA
24.6.10 USART Interrupt Status register
The read-only INTSTAT register provides a view of those interrupt flags that are currently
enabled. This can simplify software handling of interrupts. See Table 349 for detailed
descriptions of the interrupt flags.
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Table 356. USART Interrupt Status register (INTSTAT, address 0x4004 0024 (USART0),
0x4004 4024 (USART1), 0x400C 0024 (USART2)) bit description
Bit
Symbol
Description
0
RXRDY
Receiver Ready flag.
1
-
Reserved. Read value is undefined, only zero should be
written.
2
TXRDY
Transmitter Ready flag.
1
3
TXIDLE
Transmitter Idle status.
0
4
-
Reserved. Read value is undefined, only zero should be
written.
5
DELTACTS
This bit is set when a change in the state of the CTS input is
detected.
0
6
TXDISINT
Transmitter Disabled Interrupt flag.
0
7
-
Reserved. Read value is undefined, only zero should be
written.
8
OVERRUNINT
Overrun Error interrupt flag.
10:9
-
Reserved. Read value is undefined, only zero should be
written.
11
DELTARXBRK
This bit is set when a change in the state of receiver break
detection occurs.
0
12
START
This bit is set when a start is detected on the receiver input.
0
User manual
0
NA
NA
NA
0
NA
13
FRAMERRINT
Framing Error interrupt flag.
0
14
PARITYERRINT
Parity Error interrupt flag.
0
15
RXNOISEINT
Received Noise interrupt flag.
0
16
ABERRINT
Auto baud Error Interrupt flag.
31:17 -
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Value
0
Reserved. Read value is undefined, only zero should be
written.
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24.6.11 Oversample selection register
The OSR register allows selection of oversampling in asynchronous modes. The
oversample value is the number of BRG clocks used to receive one data bit. The default is
industry standard 16x oversampling.
Changing the oversampling can sometimes allow better matching of baud rates in cases
where the peripheral clock rate is not a multiple of 16 times the expected maximum baud
rate. For all modes where the OSR setting is used, the UART receiver takes three
consecutive samples of input data in the approximate middle of the bit time. Smaller
values of OSR can make the sampling position within a data bit less accurate and may
potentially cause more noise errors or incorrect data.
Table 357. Oversample selection register (OSR, address 0x4004 0028 (USART0), 0x4004
4028 (USART1), 0x400C 0028 (USART2)) bit description
Bit
Symbol
Description
3:0
OSRVAL Oversample Selection Value.
Reset
value
0xF
0 to 3 = not supported
0x4 = 5 peripheral clocks are used to transmit and receive each data bit.
0x5 = 6 peripheral clocks are used to transmit and receive each data bit.
...
0xF= 16 peripheral clocks are used to transmit and receive each data
bit.
31:4 -
Reserved, the value read from a reserved bit is not defined.
NA
24.6.12 Address register
The ADDR register holds the address for hardware address matching in address detect
mode with automatic address matching enabled.
Table 358. Address register (ADDR, address 0x4004 002C (USART0), 0x4004 402C (USART1),
0x400C 002C (USART2)) bit description
Bit
Symbol
Description
Reset
value
7:0
ADDRESS 8-bit address used with automatic address matching. Used when
0
address detection is enabled (ADDRDET in CTL = 1) and automatic
address matching is enabled (AUTOADDR in CFG = 1).
31:8
-
Reserved, the value read from a reserved bit is not defined.
NA
24.7 Functional description
24.7.1 Clocking and baud rates
In order to use the USART, clocking details must be defined such as setting up the BRG,
and typically also setting up the FRG. See Figure 64.
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24.7.1.1 Fractional Rate Generator (FRG)
The Fractional Rate Generator can be used to obtain more precise baud rates when the
peripheral clock is not a good multiple of standard (or otherwise desirable) baud rates.
The FRG is typically set up to produce an integer multiple of the highest required baud
rate, or a very close approximation. The BRG is then used to obtain the actual baud rate
needed.
The FRG register controls the USART Fractional Rate Generator, which provides the
base clock for the USART. The Fractional Rate Generator creates a lower rate output
clock by suppressing selected input clocks. When not needed, the value of 0 can be set
for the FRG, which will then not divide the input clock.
The FRG output clock is defined as the inputs clock divided by 1 + (MULT / 256), where
MULT is in the range of 1 to 255. This allows producing an output clock that ranges from
the input clock divided by 1+1/256 to 1+255/256 (just more than 1 to just less than 2). Any
further division can be done specific to each USART block by the integer BRG divider
contained in each USART.
The base clock produced by the FRG cannot be perfectly symmetrical, so the FRG
distributes the output clocks as evenly as is practical. Since the USART normally uses 16x
overclocking, the jitter in the fractional rate clock in these cases tends to disappear in the
ultimate USART output.
For setting up the fractional divider use the following registers:
Table 61 “USART fractional baud rate generator register (FRGCTRL, address
0x4007 4128) bit description”
For details see Section 24.3.1 “Configure the USART clock and baud rate”.
24.7.1.2 Baud Rate Generator (BRG)
The Baud Rate Generator (see Section 24.6.9) is used to divide the base clock to produce
a rate 16 times the desired baud rate. Typically, standard baud rates can be generated by
integer divides of higher baud rates.
24.7.1.3 Baud rate calculations
Base clock rates are 16x for asynchronous mode and 1x for synchronous mode.
24.7.1.4 32 kHz mode
In order to use a 32 kHz clock to operate a USART at any reasonable speed, a number of
adaptations need to be made. First, 16x overclocking has to be abandoned. Otherwise,
the maximum data rate would be very low. For the same reason, multiple samples of each
data bit must be reduced to one. Finally, special clocking has to be used for individual bit
times because 32 kHz is not particularly close to an even multiple of any standard baud
rate.
When 32 kHz mode is enabled, clocking comes from the RTC oscillator. The FRG is
bypassed, and the BRG can be used to divide down the default 9600 baud to lower rates.
Other adaptations required to make the UART work for rates up to 9600 baud are done
internally. Rate error will be less than one half percent in this mode, provided the RTC
oscillator is operating at the intended frequency of 32.768 kHz.
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24.7.2 DMA
A DMA request is provided for each USART direction, and can be used in lieu of interrupts
for transferring data by configuring the DMA controller appropriately. The DMA controller
provides an acknowledgement signal that clears the related request when it completes
handling a that request. The transmitter DMA request is asserted when the transmitter
can accept more data. The receiver DMA request is asserted when received data is
available to be read.
When DMA is used to perform USART data transfers, other mechanisms can be used to
generate interrupts when needed. For instance, completion of the configured DMA
transfer can generate an interrupt from the DMA controller. Also, interrupts for special
conditions, such as a received break, can still generate useful interrupts.
24.7.3 Synchronous mode
Remark: Synchronous mode transmit and receive operate at the incoming clock rate in
slave mode and the BRG selected rate (not divided by 16) in master mode.
24.7.4 Flow control
The USART supports both hardware and software flow control.
24.7.4.1 Hardware flow control
The USART supports hardware flow control using RTS and/or CTS signalling. If RTS is
configured to appear on a device pin so that it can be sent to an external device, it
indicates to an external device the ability of the receiver to receive more data.
If connected to a pin, and if enabled to do so, the CTS input can allow an external device
to throttle the USART transmitter.
Figure 66 shows an overview of RTS and CTS within the USART.
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Fig 66. Hardware flow control using RTS and CTS
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24.7.4.2 Software flow control
Software flow control could include XON / XOFF flow control, or other mechanisms. these
are supported by the ability to check the current state of the CTS input, and/or have an
interrupt when CTS changes state (via the CTS and DELTACTS bits, respectively, in the
STAT register), and by the ability of software to gracefully turn off the transmitter (via the
TXDIS bit in the CTL register).
24.7.5 Autobaud function
The autobaud functions attempts to measure the start bit time of the next received
character. For this to work, the measured character must have a 1 in the least significant
bit position, so that the start bit is bounded by a falling and rising edge. The measurement
is made using the current clocking settings, including the oversampling configuration. The
result is that a value is stored in the BRG register that is as close as possible to the correct
setting for the sampled character and the current clocking settings. The sampled
character is provided in the RXDAT and RXDATSTAT registers, allowing software to
double check for the expected character.
Autobaud includes a time-out that is flagged by ABERR if no character is received at the
expected time. It is recommended that autobaud only be enabled when the USART
receiver is idle. Once enabled, either RXRDY or ABERR will be asserted at some point, at
which time software should turn off autobaud.
Autobaud has no meaning, and should not be enabled, if the USART is in synchronous
mode.
24.7.6 RS-485 support
RS-485 support requires some form of address recognition and data direction control.
This USART has provisions for hardware address recognition (see the AUTOADDR bit in
the CFG register in Section 24.6.1 and the ADDR register in Section 24.6.12), as well as
software address recognition (see the ADDRDET bit in the CTL register in
Section 24.6.2).
Automatic data direction control with the RTS pin can be set up using the OESEL OEPOL
and OETA bits in the CFG register (Section 24.6.1). Data direction control can also be
implemented in software using a GPIO pin.
24.7.7 Oversampling
Typical industry standard UARTs use a 16x oversample clock to transmit and receive
asynchronous data. This is the number of BRG clocks used for one data bit. The
Oversample Select Register (OSR) allows this UART to use a 16x down to a 5x
oversample clock. There is no oversampling in synchronous modes.
Reducing the oversampling can sometimes help in getting better baud rate matching
when the baud rate is very high, or the peripheral clock is very low. For example, the
closest actual rate near 115,200 baud with a 12 MHz peripheral clock and 16x
oversampling is 107,143 baud, giving a rate error of 7%. Changing the oversampling to
15x gets the actual rate to 114,286 baud, a rate error of 0.8%. Reducing the oversampling
to 13x gets the actual rate to 115,385 baud, a rate error of only 0.16%.
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There is a cost for altering the oversampling. In asynchronous modes, the UART takes
three samples of incoming data on consecutive oversample clocks, as close to the center
of a bit time as can be done. When the oversample rate is reduced, the three samples
spread out and occupy a larger proportion of a bit time. For example, with 5x
oversampling, there is one oversample clock, then three data samples taken, then one
more oversample clock before the end of the bit time. Since the oversample clock is
running asynchronously from the input data, skew of the input data relative to the
expected timing has little room for error. At 16x oversampling, there are several
oversample clocks before actual data sampling is done, making the sampling more
robust. Generally speaking, it is recommended to use the highest oversampling where the
rate error is acceptable in the system.
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25.1 How to read this chapter
SPI0 and SPI1 are available on all parts. SPI0 supports four slave select lines. SPI1
supports two slave select lines.
25.2 Features
• Data transmits of 1 to 16 bits supported directly. Larger frames supported by software.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data. This can
be useful while setting up an SPI memory.
• Control information can optionally be written along with data. This allows very
versatile operation, including frames of arbitrary length.
• Up to four Slave Select input/outputs with selectable polarity and flexible usage.
• Supports DMA transfers: SPIn transmit and receive functions can operated with the
system DMA controller.
Remark: Texas Instruments SSI and National Microwire modes are not supported.
25.3 Basic configuration
Configure SPI0/1 using the following registers:
• In the SYSAHBCLKCTRL1 register, set bit 9 and 10 (Table 51) to enable the clock to
the register interface.
•
•
•
•
Clear the SPI0/1 peripheral resets using the PRESETCTRL1 register (Table 36).
Enable/disable the SPI0/1 interrupts in interrupt slots #25 and 26 in the NVIC.
Configure the SPI0/1 pin functions through the switch matrix. See Section 25.4.
The peripheral clock for both SPIs is the system clock (see Figure 3 “Clock
generation”).
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Chapter 25: LPC15xx SPI0/1
25.3.1 Configure the SPI for wake-up
In sleep mode, any signal that triggers an SPI interrupt can wake up the part, provided
that the interrupt is enabled in the INTENSET register and the NVIC. As long as the SPI
clock SPI_PCLK remains active in sleep mode, the SPI can wake up the part
independently of whether the SPI block is configured in master or slave mode.
In Deep-sleep or Power-down mode, the SPI clock is turned off as are all peripheral
clocks. However, if the SPI is configured in slave mode and an external master on the
provides the clock signal, the SPI can create an interrupt asynchronously. This interrupt, if
enabled in the NVIC and in the SPI’s INTENSET register, can then wake up the core.
25.3.1.1 Wake-up from Sleep mode
• Configure the SPI in either master or slave mode. See Table 361.
• Enable the SPI interrupt in the NVIC.
• Any SPI interrupt wakes up the part from sleep mode. Enable the SPI interrupt in the
INTENSET register (Table 364).
25.3.1.2 Wake-up from Deep-sleep or Power-down mode
• Configure the SPI in slave mode. See Table 361. You must connect the SCK function
to a pin and connect the pin to the master.
• Enable the SPI interrupt in the STARTERP0 register. See Table 76 “Start logic 0
wake-up enable register 0 (STARTERP0, address 0x4007 4218) bit description”.
• In the PDAWAKE register, configure all peripherals that need to be running when the
part wakes up.
• Enable the SPI interrupt in the NVIC.
• Enable the interrupt in the INTENSET register which configures the interrupt as
wake-up event (Table 364). Examples are the following wake-up events:
– A change in the state of the SSEL pins.
– Data available to be received.
– Receiver overrun.
25.4 Pin description
The SPI signals are movable functions and are assigned to external pins through the
switch matrix.
See Section 8.3.1 “Connect an internal signal to a package pin” to assign the SPI
functions to pins on the LPC15xx package.
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Chapter 25: LPC15xx SPI0/1
Table 359: SPI Pin Description
Function
I/O
Type
Connect
to
Use register
Reference Description
SPI0_SCK
I/O
external
to pin
any
PINASSIGN3
Table 110
Serial Clock. SCK is a clock signal used to
synchronize the transfer of data. It is driven by the
master and received by the slave. When the SPI
interface is used, the clock is programmable to be
active-high or active-low. SCK only switches during
a data transfer. It is driven whenever the Master bit
in CFG equals 1, regardless of the state of the
Enable bit.
SPI0_MOSI
I/O
external
to pin
any
PINASSIGN3
Table 110
Master Out Slave In. The MOSI signal transfers
serial data from the master to the slave. When the
SPI is a master, it outputs serial data on this signal.
When the SPI is a slave, it clocks in serial data
from this signal. MOSI is driven whenever the
Master bit in SPInCfg equals 1, regardless of the
state of the Enable bit.
SPI0_MISO
I/O
external
to pin
any
PINASSIGN3
Table 110
Master In Slave Out. The MISO signal transfers
serial data from the slave to the master. When the
SPI is a master, serial data is input from this signal.
When the SPI is a slave, serial data is output to this
signal. MISO is driven when the SPI block is
enabled, the Master bit in CFG equals 0, and when
the slave is selected by one or more SSEL signals.
SPI0_SSEL0
I/O
external
to pin
any
PINASSIGN4
Table 111
Slave Select 0. When the SPI interface is a master,
it will drive the SSEL signals to an active state
before the start of serial data and then release
them to an inactive state after the serial data has
been sent. By default, this signal is active low but
can be selected to operate as active high. When
the SPI is a slave, any SSEL in an active state
indicates that this slave is being addressed. The
SSEL pin is driven whenever the Master bit in the
CFG register equals 1, regardless of the state of
the Enable bit.
SPI0_SSEL1
I/O
external
to pin
any
PINASSIGN4
Table 111
Slave Select 1.
SPI0_SSEL2
I/O
external
to pin
any
PINASSIGN4
Table 111
Slave Select 2.
SPI0_SSEL3
I/O
external
to pin
any
PINASSIGN4
Table 111
Slave Select 3.
SPI1_SCK
I/O
external
to pin
any
PINASSIGN5
Table 112
Serial Clock.
SPI1_MOSI
I/O
external
to pin
any
PINASSIGN5
Table 112
Master Out Slave In.
SPI1_MISO
I/O
external
to pin
any
PINASSIGN5
Table 112
Master In Slave Out.
SPI1_SSEL0
I/O
external
to pin
any
PINASSIGN5
Table 112
Slave Select 0.
SPI1_SSEL1
I/O
external
to pin
any
PINASSIGN6
Table 113
Slave Select 1.
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25.5 General description
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(1) Includes CPOL, CPHA, LSBF, FLEN, master, enable, transfer_delay, frame_delay, pre_delay, post_delay, SOT, EOT, EOF,
RXIGNORE, individual interrupt enables.
Fig 68. SPI block diagram
25.6 Register description
The Reset Value reflects the data stored in used bits only. It does not include reserved bits
content.
Table 360. Register overview: SPI (base address 0x4004 8000 (SPI0) and 0x4008 C000
(SPI1))
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Name
Access
Offset
Description
Reset
value
Reference
CFG
R/W
0x000
SPI Configuration register
0
Table 361
DLY
R/W
0x004
SPI Delay register
0
Table 362
STAT
R/W
0x008
SPI Status. Some status flags can be
cleared by writing a 1 to that bit
position
0x0102
Table 363
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Chapter 25: LPC15xx SPI0/1
Table 360. Register overview: SPI (base address 0x4004 8000 (SPI0) and 0x4008 C000 (SPI1))
…continued
Name
Access
Offset
Description
Reset
value
Reference
INTENSET
R/W
0x00C
SPI Interrupt Enable read and Set. A
complete value may be read from this
register. Writing a 1 to any
implemented bit position causes that
bit to be set.
0
Table 364
INTENCLR
W
0x010
SPI Interrupt Enable Clear. Writing a 1 NA
to any implemented bit position causes
the corresponding bit in INTENSET to
be cleared.
Table 365
RXDAT
R
0x014
SPI Receive Data
NA
Table 366
TXDATCTL
R/W
0x018
SPI Transmit Data with Control
0
Table 367
TXDAT
R/W
0x01C
SPI Transmit Data
0
Table 368
TXCTL
R/W
0x020
SPI Transmit Control
0
Table 369
DIV
R/W
0x024
SPI clock Divider
0
Table 370
INTSTAT
R
0x028
SPI Interrupt Status
0x02
Table 371
25.6.1 SPI Configuration register
The CFG register contains information for the general configuration of the SPI. Typically,
this information is not changed during operation. Some configurations, such as CPOL,
CPHA, and LSBF should not be made while the SPI is not fully idle. See the description of
the master idle status (MSTIDLE in Table 363) for more information.
Remark: If the interface is re-configured from Master mode to Slave mode or the reverse
(an unusual case), the SPI should be disabled and re-enabled with the new configuration.
Table 361. SPI Configuration register (CFG, addresses 0x4004 8000 (SPI0), 0x4004 C000 (SPI1)) bit
description
Bit
Symbol
0
ENABLE
Value Description
Reset
value
SPI enable.
0
0
Disabled. The SPI is disabled and the internal state machine and counters are reset.
1
Enabled. The SPI is enabled for operation.
1
-
Reserved. Read value is undefined, only zero should be written.
NA
2
MASTER
Master mode select.
0
3
0
Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are
inputs, MISO is an output.
1
Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals
are outputs, MISO is an input.
LSBF
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LSB First mode enable.
0
Standard. Data is transmitted and received in standard MSB first order.
1
Reverse. Data is transmitted and received in reverse order (LSB first).
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Chapter 25: LPC15xx SPI0/1
Table 361. SPI Configuration register (CFG, addresses 0x4004 8000 (SPI0), 0x4004 C000 (SPI1)) bit
description …continued
Bit
Symbol
4
CPHA
5
Value Description
Reset
value
Clock Phase select.
0
0
Change. The SPI captures serial data on the first clock transition of the transfer (when
the clock changes away from the rest state). Data is changed on the following edge.
1
Capture. The SPI changes serial data on the first clock transition of the transfer (when
the clock changes away from the rest state). Data is captured on the following edge.
CPOL
Clock Polarity select.
0
0
Low. The rest state of the clock (between transfers) is low.
1
High. The rest state of the clock (between transfers) is high.
6
-
Reserved. Read value is undefined, only zero should be written.
NA
7
LOOP
Loopback mode enable. Loopback mode applies only to Master mode, and connects
transmit and receive data connected together to allow simple software testing.
0
0
1
8
9
10
11
SPOL0
Enabled.
SSEL0 Polarity select.
0
0
Low. The SSEL0 pin is active low. The value in the SSEL0 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL0 is not inverted relative to the pins.
1
High. The SSEL0 pin is active high. The value in the SSEL0 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL0 is inverted relative to the pins.
SPOL1
SSEL1 Polarity select.
0
0
Low. The SSEL1 pin is active low. The value in the SSEL1 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL1 is not inverted relative to the pins.
1
High. The SSEL1 pin is active high. The value in the SSEL1 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL1 is inverted relative to the pins.
SPOL2
SSEL2 Polarity select.
0
0
Low. The SSEL2 pin is active low. The value in the SSEL2 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL2 is not inverted relative to the pins.
1
High. The SSEL2 pin is active high. The value in the SSEL2 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL2 is inverted relative to the pins.
SPOL3
31:12 -
Disabled.
SSEL3 Polarity select.
0
0
Low. The SSEL3 pin is active low. The value in the SSEL3 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL3 is not inverted relative to the pins.
1
High. The SSEL3 pin is active high. The value in the SSEL3 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL3 is inverted relative to the pins.
Reserved. Read value is undefined, only zero should be written.
NA
25.6.2 SPI Delay register
The DLY register controls several programmable delays related to SPI signalling. These
delays apply only to master mode, and are all stated in SPI clocks.
Timing details are shown in:
Section 25.7.2.1 “Pre_delay and Post_delay”
Section 25.7.2.2 “Frame_delay”
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Section 25.7.2.3 “Transfer_delay”
Table 362. SPI Delay register (DLY, addresses 0x4004 8004 (SPI0), 0x4004 C004 (SPI1)) bit description
Bit
Symbol
Description
Reset
value
3:0
PRE_DELAY
Controls the amount of time between SSEL assertion and the beginning of a data
transfer.
0
There is always one SPI clock time between SSEL assertion and the first clock edge.
This is not considered part of the pre-delay.
0x0 = No additional time is inserted.
0x1 = 1 SPI clock time is inserted.
0x2 = 2 SPI clock times are inserted.
...
0xF = 15 SPI clock times are inserted.
7:4
POST_DELAY
Controls the amount of time between the end of a data transfer and SSEL
deassertion.
0
0x0 = No additional time is inserted.
0x1 = 1 SPI clock time is inserted.
0x2 = 2 SPI clock times are inserted.
...
0xF = 15 SPI clock times are inserted.
11:8
FRAME_DELAY
If the EOF flag is set, controls the minimum amount of time between the current frame 0
and the next frame (or SSEL deassertion if EOT).
0x0 = No additional time is inserted.
0x1 = 1 SPI clock time is inserted.
0x2 = 2 SPI clock times are inserted.
...
0xF = 15 SPI clock times are inserted.
15:12 TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers. 0
0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added
time.)
0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times.
0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times.
...
0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.
31:16 -
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Reserved. Read value is undefined, only zero should be written.
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25.6.3 SPI Status register
The STAT register provides SPI status flags for software to read, and a control bit for
forcing an end of transfer. Flags other than read-only flags may be cleared by writing ones
to corresponding bits of STAT.
STAT contains 2 error flags (in slave mode only): RXOV and TXUR. These are receiver
overrun and transmit underrun, respectively. If either of these errors occur during
operation, the SPI should be disabled, then re-enabled in order to make sure all internal
states are cleared before attempting to resume operation.
In this register, the following notation is used: RO = Read-only, W1 = write 1 to clear.
Table 363. SPI Status register (STAT, addresses 0x4004 8008 (SPI0), 0x4004 C008 (SPI1)) bit description
Bit
Symbol
Description
Reset Access
value [1]
0
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from
the receiver buffer. Cleared after a read of the RXDAT register.
0
RO
1
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to
1
the transmit buffer. Previous data may still be in the process of being
transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data
is moved to the transmit shift register.
RO
2
RXOV
Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0
0). This flag is set when the beginning of a received character is detected while
the receiver buffer is still in use. If this occurs, the receiver buffer contents are
preserved, and the incoming data is lost. Data received by the SPI should be
considered undefined if RxOv is set.
W1
3
TXUR
Transmitter Underrun interrupt flag. This flag applies only to slave mode
0
(Master = 0). In this case, the transmitter must begin sending new data on the
next input clock if the transmitter is idle. If that data is not available in the
transmitter holding register at that point, there is no data to transmit and the
TXUR flag is set. Data transmitted by the SPI should be considered undefined if
TXUR is set.
W1
4
SSA
Slave Select Assert. This flag is set whenever any slave select transitions from 0
deasserted to asserted, in both master and slave modes. This allows
determining when the SPI transmit/receive functions become busy, and allows
waking up the device from reduced power modes when a slave mode access
begins. This flag is cleared by software.
W1
5
SSD
Slave Select Deassert. This flag is set whenever any asserted slave selects
transition to deasserted, in both master and slave modes. This allows
determining when the SPI transmit/receive functions become idle. This flag is
cleared by software.
0
W1
6
STALLED
Stalled status flag. This indicates whether the SPI is currently in a stall
condition.
0
RO
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Chapter 25: LPC15xx SPI0/1
Table 363. SPI Status register (STAT, addresses 0x4004 8008 (SPI0), 0x4004 C008 (SPI1)) bit description
Bit
Symbol
7
ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current 0
transfer when the transmitter finishes any activity already in progress, as if the
EOT flag had been set prior to the last transmission. This capability is included
to support cases where it is not known when transmit data is written that it will
be the end of a transfer. The bit is cleared when the transmitter becomes idle as
the transfer comes to an end. Forcing an end of transfer in this manner causes
any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
RO/W1
8
MSTIDLE
Master idle status flag. This bit is 1 whenever the SPI master function is fully
idle. This means that the transmit holding register is empty and the transmitter
is not in the process of sending data.
1
RO
31:9
-
Reserved. Read value is undefined, only zero should be written.
NA
NA
[1]
Description
Reset Access
value [1]
RO = Read-only, W1 = write 1 to clear.
25.6.4 SPI Interrupt Enable read and Set register
The INTENSET register is used to enable various SPI interrupt sources. Enable bits in
INTENSET are mapped in locations that correspond to the flags in the STAT register. The
complete set of interrupt enables may be read from this register. Writing ones to
implemented bits in this register causes those bits to be set. The INTENCLR register is
used to clear bits in this register. See Table 363 for details of the interrupts.
Table 364. SPI Interrupt Enable read and Set register (INTENSET, addresses 0x4004 800C (SPI0), 0x4004 C00C
(SPI1)) bit description
Bit
Symbol
0
RXRDYEN
1
2
Value Description
Reset
value
Determines whether an interrupt occurs when receiver data is available.
0
0
No interrupt will be generated when receiver data is available.
1
An interrupt will be generated when receiver data is available in the RXDAT register.
TXRDYEN
Determines whether an interrupt occurs when the transmitter holding register is
available.
0
No interrupt will be generated when the transmitter holding register is available.
1
An interrupt will be generated when data may be written to TXDAT.
RXOVEN
0
Determines whether an interrupt occurs when a receiver overrun occurs. This happens
in slave mode when there is a need for the receiver to move newly received data to the
RXDAT register when it is already in use.
0
The interface prevents receiver overrun in Master mode by not allowing a new
transmission to begin when a receiver overrun would otherwise occur.
3
0
No interrupt will be generated when a receiver overrun occurs.
1
An interrupt will be generated if a receiver overrun occurs.
TXUREN
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Determines whether an interrupt occurs when a transmitter underrun occurs. This
happens in slave mode when there is a need to transmit data when none is available.
0
No interrupt will be generated when the transmitter underruns.
1
An interrupt will be generated if the transmitter underruns.
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Table 364. SPI Interrupt Enable read and Set register (INTENSET, addresses 0x4004 800C (SPI0), 0x4004 C00C
(SPI1)) bit description
Bit
Symbol
4
SSAEN
5
31:6
Value Description
Reset
value
Determines whether an interrupt occurs when the Slave Select is asserted.
0
0
No interrupt will be generated when any Slave Select transitions from deasserted to
asserted.
1
An interrupt will be generated when any Slave Select transitions from deasserted to
asserted.
SSDEN
Determines whether an interrupt occurs when the Slave Select is deasserted.
0
0
No interrupt will be generated when all asserted Slave Selects transition to deasserted.
1
An interrupt will be generated when all asserted Slave Selects transition to deasserted.
-
Reserved. Read value is undefined, only zero should be written.
NA
25.6.5 SPI Interrupt Enable Clear register
The INTENCLR register is used to clear interrupt enable bits in the INTENSET register.
Table 365. SPI Interrupt Enable clear register (INTENCLR, addresses 0x4004 8010 (SPI0),
0x4004 C010 (SPI1)) bit description
Bit
Symbol
Description
Reset
value
0
RXRDYEN Writing 1 clears the corresponding bits in the INTENSET register.
0
1
TXRDYEN Writing 1 clears the corresponding bits in the INTENSET register.
0
2
RXOVEN
Writing 1 clears the corresponding bits in the INTENSET register.
0
3
TXUREN
Writing 1 clears the corresponding bits in the INTENSET register.
0
4
SSAEN
Writing 1 clears the corresponding bits in the INTENSET register.
0
5
SSDEN
Writing 1 clears the corresponding bits in the INTENSET register.
0
31:6
-
Reserved. Read value is undefined, only zero should be written.
NA
25.6.6 SPI Receiver Data register
The read-only RXDAT register provides the means to read the most recently received
data. The value of SSEL can be read along with the data.
For details on the slave select process, see Section 25.7.4.
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Table 366. SPI Receiver Data register (RXDAT, addresses 0x4004 8014 (SPI0), 0x4004 C014
(SPI1)) bit description
Bit
Symbol
Description
Reset
value
15:0
RXDAT
Receiver Data. This contains the next piece of received data.
The number of bits that are used depends on the LEN setting
in TXCTL / TXDATCTL.
undefined
16
RXSSEL0_N
Slave Select for receive. This field allows the state of the
undefined
SSEL0 pin to be saved along with received data. The value
will reflect the SSEL0 pin for both master and slave operation.
A zero indicates that a slave select is active. The actual
polarity of each slave select pin is configured by the related
SPOL bit in CFG.
17
RXSSEL1_N
Slave Select for receive. This field allows the state of the
undefined
SSEL1 pin to be saved along with received data. The value
will reflect the SSEL1 pin for both master and slave operation.
A zero indicates that a slave select is active. The actual
polarity of each slave select pin is configured by the related
SPOL bit in CFG.
18
RXSSEL2_N
Slave Select for receive. This field allows the state of the
undefined
SSEL2 pin to be saved along with received data. The value
will reflect the SSEL2 pin for both master and slave operation.
A zero indicates that a slave select is active. The actual
polarity of each slave select pin is configured by the related
SPOL bit in CFG.
19
RXSSEL3_N
undefined
Slave Select for receive. This field allows the state of the
SSEL3 pin to be saved along with received data. The value
will reflect the SSEL3 pin for both master and slave operation.
A zero indicates that a slave select is active. The actual
polarity of each slave select pin is configured by the related
SPOL bit in CFG.
20
SOT
Start of Transfer flag. This flag will be 1 if this is the first data
after the SSELs went from deasserted to asserted (i.e., any
previous transfer has ended). This information can be used to
identify the first piece of data in cases where the transfer
length is greater than 16 bit.
31:21 -
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25.6.7 SPI Transmitter Data and Control register
The TXDATCTL register provides a location where both transmit data and control
information can be written simultaneously. This allows detailed control of the SPI without a
separate write of control information for each piece of data, which can be especially useful
when the SPI is used with DMA.
Remark: The SPI has no receiver control registers. Hence software needs to set the data
length in the transmitter control or transmitter data and control register first in order to
handle reception with correct data length. The programmed data length becomes active
only when data is actually transmitted. Therefore, this must be done before any data can
be received.
When control information remains static during transmit, the TXDAT register should be
used (see Section 25.6.8) instead of the TXDATCTL register. Control information can then
be written separately via the TXCTL register (see Section 25.6.9). The upper part of
TXDATCTL (bits 27 to 16) are the same bits contained in the TXCTL register. The two
registers simply provide two ways to access them.
For details on the slave select process, see Section 25.7.4.
For details on using multiple consecutive data transmits for transfer lengths larger than 16
bit, see Section 25.7.6 “Data lengths greater than 16 bits”.
Table 367. SPI Transmitter Data and Control register (TXDATCTL, addresses 0x4004 8018 (SPI0), 0x4004 C018
(SPI1)) bit description
Bit
Symbol
15:0
16
Value
Description
Reset
value
TXDAT
Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0
TXSSEL0_N
Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the 0
pin is active LOW by default.
Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.
0
1
17
TXSSEL1_N
SSEL0 asserted.
SSEL0 not asserted.
Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the 0
pin is active LOW by default.
Remark: The active state of the SSEL1 pin is configured by bits in the CFG register.
18
0
SSEL1 asserted.
1
SSEL1 not asserted.
TXSSEL2_N
Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the 0
pin is active LOW by default.
Remark: The active state of the SSEL2 pin is configured by bits in the CFG register.
0
1
19
TXSSEL3_N
SSEL2 asserted.
SSEL2 not asserted.
Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the 0
pin is active LOW by default.
Remark: The active state of the SSEL3 pin is configured by bits in the CFG register.
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SSEL3 asserted.
1
SSEL3 not asserted.
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Chapter 25: LPC15xx SPI0/1
Table 367. SPI Transmitter Data and Control register (TXDATCTL, addresses 0x4004 8018 (SPI0), 0x4004 C018
(SPI1)) bit description …continued
Bit
Symbol
20
EOT
21
22
23
Value
0
SSEL not deasserted. This piece of data is not treated as the end of a transfer.
SSEL will not be deasserted at the end of this data.
1
SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will
be deasserted at the end of this piece of data.
End of Frame. Between frames, a delay may be inserted, as defined by the
0
FRAME_DELAY value in the DLY register. The end of a frame may not be
particularly meaningful if the FRAME_DELAY value = 0. This control can be used as
part of the support for frame lengths greater than 16 bits.
0
Data not EOF. This piece of data transmitted is not treated as the end of a frame.
1
Data EOF. This piece of data is treated as the end of a frame, causing the
FRAME_DELAY time to be inserted before subsequent data is transmitted.
RXIGNORE
27:24 LEN
Reset
value
End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and 0
remain so for at least the time specified by the Transfer_delay value in the DLY
register.
EOF
-
Description
Receive Ignore. This allows data to be transmitted using the SPI without the need to 0
read unneeded data from the receiver.Setting this bit simplifies the transmit process
and can be used with the DMA.
0
Read received data. Received data must be read in order to allow transmission to
progress. In slave mode, an overrun error will occur if received data is not read
before new data is received.
1
Ignore received data. Received data is ignored, allowing transmission without
reading unneeded received data. No receiver flags are generated.
Reserved. Read value is undefined, only zero should be written.
NA
Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths
greater than 16 bits are supported by implementing multiple sequential transmits.
0x0
0x0 = Data transfer is 1 bit in length.
0x1 = Data transfer is 2 bits in length.
0x2 = Data transfer is 3 bits in length.
...
0xF = Data transfer is 16 bits in length.
31:28 -
Reserved. Read value is undefined, only zero should be written.
NA
25.6.8 SPI Transmitter Data Register
The TXDAT register is written in order to send data via the SPI transmitter when control
information is not changing during the transfer (see Section 25.6.7). That data will be sent
to the transmit shift register when it is available, and another character may then be
written to TXDAT.
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Chapter 25: LPC15xx SPI0/1
Table 368. SPI Transmitter Data Register (TXDAT, addresses 0x4004 801C (SPI0), 0x4004
C01C (SPI1)) bit description
Bit
Symbol
Description
Reset
value
15:0
DATA
Transmit Data. This field provides from 4 to 16 bits of data to be
transmitted.
0
Reserved. Only zero should be written.
NA
31:16 -
25.6.9 SPI Transmitter Control register
The TXCTL register provides a way to separately access control information for the SPI.
These bits are another view of the same-named bits in the TXDATCTL register (see
Section 25.6.7). Changing bits in TXCTL has no effect unless data is later written to the
TXDAT register. Data written to TXDATCTL overwrites the TXCTL register.
When control information needs to be changed during transmission, the TXDATCTL
register should be used (see Section 25.6.7) instead of TXDAT. Control information can
then be written along with data.
Table 369. SPI Transmitter Control register (TXCTL, addresses 0x4004 8020 (SPI0), 0x4004
C020 (SPI1)) bit description
Bit
Symbol
Description
Reset
value
15:0
-
Reserved. Read value is undefined, only zero should be
written.
NA
16
TXSSEL0_N
Transmit Slave Select 0.
0x0
17
TXSSEL1_N
Transmit Slave Select 1.
0x0
18
TXSSEL2_N
Transmit Slave Select 2.
0x0
19
TXSSEL3_n
Transmit Slave Select 3.
0x0
20
EOT
End of Transfer.
0
21
EOF
End of Frame.
0
22
RXIGNORE
Receive Ignore.
0
23
-
Reserved. Read value is undefined, only zero should be
written.
NA
27:24 LEN
Data transfer Length.
0x0
31:28 -
Reserved. Read value is undefined, only zero should be
written.
NA
25.6.10 SPI Divider register
The DIV register determines the clock used by the SPI in master mode.
For details on clocking, see Section 25.7.3 “Clocking and data rates”.
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Table 370. SPI Divider register (DIV, addresses 0x4004 8024 (SPI0), 0x4004 C024 (SPI1)) bit
description
Bit
Symbol
Description
Reset
Value
15:0
DIVVAL
Rate divider value. Specifies how the PCLK for the SPI is divided to
produce the SPI clock rate in master mode.
0
DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the
value 1 results in PCLK/2, up to the maximum possible divide value
of 0xFFFF, which results in PCLK/65536.
31:16 -
Reserved. Read value is undefined, only zero should be written.
NA
25.6.11 SPI Interrupt Status register
The read-only INTSTAT register provides a view of those interrupt flags that are currently
enabled. This can simplify software handling of interrupts. See Table 363 for detailed
descriptions of the interrupt flags.
Table 371. SPI Interrupt Status register (INTSTAT, addresses 0x4004 8028 (SPI0), 0x4004
C028 (SPI1)) bit description
Bit
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Symbol
Description
Reset
value
0
RXRDY
Receiver Ready flag.
0
1
TXRDY
Transmitter Ready flag.
1
2
RXOV
Receiver Overrun interrupt flag.
0
3
TXUR
Transmitter Underrun interrupt flag.
0
4
SSA
Slave Select Assert.
0
5
SSD
Slave Select Deassert.
0
31:6
-
Reserved. Read value is undefined, only zero should be written.
NA
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Chapter 25: LPC15xx SPI0/1
25.7 Functional description
25.7.1 Operating modes: clock and phase selection
SPI interfaces typically allow configuration of clock phase and polarity. These are
sometimes referred to as numbered SPI modes, as described in Table 372 and shown in
Figure 69. CPOL and CPHA are configured by bits in the CFG register (Section 25.6.1).
Table 372: SPI mode summary
CPOL CPHA
SPI
Description
Mode
SCK rest
SCK data
SCK data
state
change edge sample edge
0
0
0
The SPI captures serial data on the first clock transition of
the transfer (when the clock changes away from the rest
state). Data is changed on the following edge.
low
falling
rising
0
1
1
The SPI changes serial data on the first clock transition of
the transfer (when the clock changes away from the rest
state). Data is captured on the following edge.
low
rising
falling
1
0
2
Same as mode 0 with SCK inverted.
high
rising
falling
1
1
3
Same as mode 1 with SCK inverted.
high
falling
rising
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Fig 69. Basic SPI operating modes
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Chapter 25: LPC15xx SPI0/1
25.7.2 Frame delays
Several delays can be specified for SPI frames. These include:
•
•
•
•
Pre_delay: delay after SSEL is asserted before data clocking begins
Post_delay: delay at the end of a data frame before SSEL is deasserted
Frame_delay: delay between data frames when SSEL is not deasserted
Transfer_delay: minimum duration of SSEL in the deasserted state between transfers
25.7.2.1 Pre_delay and Post_delay
Pre_delay and Post_delay are illustrated by the examples in Figure 70. The Pre_delay
value controls the amount of time between SSEL being asserted and the beginning of the
subsequent data frame. The Post_delay value controls the amount of time between the
end of a data frame and the deassertion of SSEL.
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Fig 70. Pre_delay and Post_delay
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Chapter 25: LPC15xx SPI0/1
25.7.2.2 Frame_delay
The Frame_delay value controls the amount of time at the end of each frame. This delay
is inserted when the EOF bit = 1. Frame_delay is illustrated by the examples in Figure 71.
Note that frame boundaries occur only where specified. This is because frame lengths
can be any size, involving multiple data writes. See Section 25.7.6 for more information.
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Fig 71. Frame_delay
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Chapter 25: LPC15xx SPI0/1
25.7.2.3 Transfer_delay
The Transfer_delay value controls the minimum amount of time that SSEL is deasserted
between transfers, because the EOT bit = 1. When Transfer_delay = 0, SSEL may be
deasserted for a minimum of one SPI clock time. Transfer_delay is illustrated by the
examples in Figure 72.
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Fig 72. Transfer_delay
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Chapter 25: LPC15xx SPI0/1
25.7.3 Clocking and data rates
In order to use the SPI, clocking details must be defined. This includes configuring the
system clock and selection of the clock divider value in DIV. See Figure 67.
25.7.3.1 Data rate calculations
The SPI interface is designed to operate asynchronously from any on-chip clocks, and
without the need for overclocking.
In slave mode, this means that the SCK from the external master is used directly to run
the transmit and receive shift registers and other logic.
In master mode, the SPI rate clock produced by the SPI clock divider is used directly as
the outgoing SCK.
The SPI clock divider is an integer divider. The SPI in master mode can be set to run at
the same speed as the selected PCLK, or at lower integer divide rates. The SPI rate will
be = PCLK_SPIn / DIVVAL.
In slave mode, the clock is taken from the SCK input and the SPI clock divider is not used.
25.7.4 Slave select
The SPI block provides for four Slave Select inputs in slave mode or outputs in master
mode. Each SSEL can be set for normal polarity (active low), or can be inverted (active
high). Representation of the 4 SSELs in a register is always active low. If an SSEL is
inverted, this is done as the signal leaves/enters the SPI block.
In slave mode, any asserted SSEL that is connected to a pin will activate the SPI. In
master mode, all SSELs that are connected to a pin will be output as defined in the SPI
registers. In the latter case, the SSELs could potentially be decoded externally in order to
address more than four slave devices. Note that at least one SSEL is asserted when data
is transferred in master mode.
In master mode, Slave Selects come from the SSELN field, which appears in both the
CTL and DATCTL registers. In slave mode, the state of all four SSELs is saved along with
received data in the RXSSEL_N field of the RXDAT register.
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Chapter 25: LPC15xx SPI0/1
25.7.5 DMA operation
A DMA request is provided for each SPI direction, and can be used in lieu of interrupts for
transferring data by configuring the DMA controller appropriately, and enabling the Rx
and/or Tx DMA via the CFG register. The DMA controller provides an acknowledgement
signal that clears the related request when it completes handling that request.
The transmitter DMA request is asserted when Tx DMA is enabled and the transmitter can
accept more data.
The receiver DMA request is asserted when Rx DMA is enabled and received data is
available to be read.
25.7.6 Data lengths greater than 16 bits
The SPI interface handles data frame sizes from 1 to 16 bits directly. Larger sizes can be
handled by splitting data up into groups of 16 bits or less. For example, 24 bits can be
supported as 2 groups of 16 bits and 8 bits or 2 groups of 12 bits, among others. Frames
of any size, including greater than 32 bits, can supported in the same way.
Details of how to handle larger data widths depend somewhat on other SPI configuration
options. For instance, if it is intended for Slave Selects to be deasserted between frames,
then this must be suppressed when a larger frame is split into more than one part.
Sending 2 groups of 12 bits with SSEL deasserted between 24-bit increments, for
instance, would require changing the value of the EOF bit on alternate 12-bit frames.
25.7.7 Data stalls
A stall for Master transmit data can happen in modes 0 and 2 when SCK cannot be
returned to the rest state until the MSB of the next data frame can be driven on MOSI. In
this case, the stall happens just before the final clock edge of data if the next piece of data
is not yet available.
A stall for Master receive can happen when a receiver overrun would otherwise occur if
the transmitter was not stalled. In modes 0 and 2, this occurs if the previously received
data is not read before the end of the next piece of is received. This stall happens one
clock edge earlier than the transmitter stall.
In modes 1 and 3, the same kind of receiver stall can occur, but just before the final clock
edge of the received data. Also, a transmitter stall will not happen in modes 1 and 3
because the transmitted data is complete at the point where a stall would otherwise occur,
so it is not needed.
Stalls are reflected in the STAT register by the Stalled status flag, which indicates the
current SPI status.
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Chapter 25: LPC15xx SPI0/1
7UDQVPLWWHUVWDOO&3+$ )UDPH BGHOD\ 3UHBGHOD\ 3RVWBGHOD\ FORFNVWDOO
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Fig 73. Examples of data stalls
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Chapter 26: LPC15xx I2C-bus interface
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User manual
26.1 How to read this chapter
The I2C-bus interface is available on all parts.
Read this chapter if you want to understand the I2C operation and the software interface
and want to learn how to use the I2C for wake-up from reduced power modes.
The LPC15xx provides an on-chip ROM-based I2C API to configure and operate the I2C.
See Chapter 38.
26.2 Features
•
•
•
•
Independent Master, Slave, and Monitor functions.
Supports both Multi-master and Multi-master with Slave functions.
Multiple I2C slave addresses supported in hardware.
One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I2C bus addresses.
• 10-bit addressing supported with software assist.
• Supports SMBus.
• Supports the I2C-bus specification up to Fast-mode Plus (up to 1 MHz).
26.3 Pin description
The I2C pins are fixed-pin functions and enabled through the switch matrix.
If the I2C-bus interface is used in Fast-mode Plus mode, configure the I2C-pins for this
mode in the IOCON block: Table 101 “Digital open-drain pin control registers
(PIO0_[22:23], address 0x400F 805C (PIO0_22) to 0x400F 8060 (PIO0_23)) bit
description”.
Table 373. I2C-bus pin description
Function
Direction Type
Connect
to
Use register
Reference Description
I2C0_SCL
I/O
external
to pin
P0_22
PINENABLE1
Table 124
I2C0 serial clock.
I2C0_SDA
I/O
external
to pin
P0_23
PINENABLE1
Table 124
I2C0 serial data.
26.4 Basic configuration
Configure I2C using the following registers:
• In the SYSAHBCLKCTRL1 register, set bit 13 (Table 51) to enable the clock to the
register interface.
• Clear the I2C peripheral reset using the PRESETCTRL1 register (Table 36).
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Chapter 26: LPC15xx I2C-bus interface
• Enable/disable the I2C interrupt in interrupt slots #24 in the NVIC.
• Configure the I2C pin functions through the switch matrix. See Table 124.
• The peripheral clock for the I2C is the system clock (see Figure 74).
,&
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Fig 74. I2C clocking
26.4.1 I2C transmit/receive in master mode
Remark: See Section 44.2 “Code examples I2C” for code examples.
In this example, the I2C is configured as the master. The master sends 8 bits to the slave
and then receives 8 bits from the slave. The system clock is set to 30 MHz and the bit rate
is approximately 400 KHz. You must enable the I2C0_SCL and I2C0_SDA functions on
pins PIO0_22 and PIO0_23 through the switch matrix. See Table 124.
For a 400 KHz bit rate, the pins can be configured in standard mode in the IOCON block.
See Table 101 “Digital open-drain pin control registers (PIO0_[22:23], address 0x400F
805C (PIO0_22) to 0x400F 8060 (PIO0_23)) bit description”.
The transmission of the address and data bits is controlled by the state of the
MSTPENDING status bit. Whenever the status is Master pending, the master can read or
write to the MSTDAT register and go to the next step of the transmission protocol by
writing to the MSTCTL register.
Configure the I2C bit rate:
• Divide the system clock (I2C_PCLK) by a factor of 2. See Table 382 “I2C Clock
Divider register (CLKDIV, address 0x4005 0014) bit description”.
• Set the SCL high and low times to 2 clock cycles each. This is the default. See
Table 385 “Master Time register (MSTTIME, address 0x4005 0024) bit description”.
The result is an SCL clock of 375 kHz.
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Chapter 26: LPC15xx I2C-bus interface
26.4.1.1 Master write to slave
Configure the I2C as master: Set the MSTEN bit to 1 in the CFG register. See Table 375.
Write data to the slave:
1. Write the slave address with the RW bit set to 0 to the Master data register MSTDAT.
See Table 386.
2. Start the transmission by setting the MSTSTART bit to 1 in the Master control register.
See Table 384. The following happens:
– The pending status is cleared and the I2C-bus is busy.
– The I2C master sends the start bit and address with the RW bit to the slave.
3. Wait for the pending status to be set (MSTPENDING = 1) by polling the STAT register.
4. Write 8 bits of data to the MSTDAT register.
5. Continue with the transmission of data by setting the MSTCONT bit to 1 in the Master
control register. See Table 384. The following happens:
– The pending status is cleared and the I2C-bus is busy.
– The I2C master sends the data bits to the slave address.
6. Wait for the pending status to be set (MSTPENDING = 1) by polling the STAT register.
7. Stop the transmission by setting the MSTSTOP bit to 1 in the Master control register.
See Table 384.
26.4.1.2 Master read from slave
Configure the I2C as master: Set the MSTEN bit to 1 in the CFG register. See Table 375.
Read data from the slave:
1. Write the slave address with the RW bit set to 1 to the Master data register MSTDAT.
See Table 386.
2. Start the transmission by setting the MSTSTART bit to 1 in the Master control register.
See Table 384. The following happens:
– The pending status is cleared and the I2C-bus is busy.
– The I2C master sends the start bit and address with the RW bit to the slave.
– The slave sends 8 bit of data.
3. Wait for the pending status to be set (MSTPENDING = 1) by polling the STAT register.
4. Read 8 bits of data from the MSTDAT register.
5. Stop the transmission by setting the MSTSTOP bit to 1 in the Master control register.
See Table 384.
26.4.2 I2C receive/transmit in slave mode
In this example, the I2C is configured as the slave. The slave receives 8 bits from the
master and sends 8 bits to the slave. The system clock is set to 30 MHz and the bit rate is
approximately 400 KHz. You must enable the I2C0_SCL and I2C0_SDA functions on pins
PIO0_22 and PIO0_23 through the switch matrix. See Table 124.
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Chapter 26: LPC15xx I2C-bus interface
For a 400 KHz bit rate, the pins can be configured in standard mode in the IOCON block.
See Table 101 “Digital open-drain pin control registers (PIO0_[22:23], address 0x400F
805C (PIO0_22) to 0x400F 8060 (PIO0_23)) bit description”.
The transmission of the address and data bits is controlled by the state of the
SLVPENDING status bit. Whenever the status is Slave pending, the slave can
acknowledge (“ack”) or send or receive an address and data. The received data or the
data to be sent to the master are available in the SLVDAT register. After sending and
receiving data, continue to the next step of the transmission protocol by writing to the
SLVCTL register.
26.4.2.1 Slave read from master
Configure the I2C as slave with address x:
• Set the SLVEN bit to 1 in the CFG register. See Table 375.
• Write the slave address x to the address 0 match register. See Table 389.
Read data from the master:
1. Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register.
2. Acknowledge (“ack”) the address by setting SLVCONTINUE = 1 in the slave control
register. See Table 387.
3. Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register.
4. Read 8 bits of data from the SLVDAT register. See Table 388.
5. Acknowledge (“ack”) the data by setting SLVCONTINUE = 1 in the slave control
register. See Table 387.
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Chapter 26: LPC15xx I2C-bus interface
26.4.2.2 Slave write to master
• Set the SLVEN bit to 1 in the CFG register. See Table 375.
• Write the slave address x to the address 0 match register. See Table 389.
Write data to the master:
1. Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register.
2. ACK the address by setting SLVCONTINUE = 1 in the slave control register. See
Table 387.
3. Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register.
4. Write 8 bits of data to SLVDAT register. See Table 388.
5. Continue the transaction by setting SLVCONTINUE = 1 in the slave control register.
See Table 387.
26.4.3 Configure the I2C for wake-up
In sleep mode, any activity on the I2C-bus that triggers an I2C interrupt can wake up the
part, provided that the interrupt is enabled in the INTENSET register and the NVIC. As
long as the I2C clock I2C_PCLK remains active in sleep mode, the I2C can wake up the
part independently of whether the I2C block is configured in master or slave mode.
In Deep-sleep or Power-down mode, the I2C clock is turned off as are all peripheral
clocks. However, if the I2C is configured in slave mode and an external master on the
I2C-bus provides the clock signal, the I2C block can create an interrupt asynchronously.
This interrupt, if enabled in the NVIC and in the I2C block’s INTENCLR register, can then
wake up the core.
26.4.3.1 Wake-up from Sleep mode
• Enable the I2C interrupt in the NVIC.
• Enable the I2C wake-up event in the I2C INTENSET register. Wake-up on any
enabled interrupts is supported (see the INTENSET register). Examples are the
following events:
– Master pending
– Change to idle state
– Start/stop error
– Slave pending
– Address match (in slave mode)
– Data available/ready
26.4.3.2 Wake-up from Deep-sleep and Power-down modes
• Enable the I2C interrupt in the NVIC.
• Enable the I2C interrupt in the STARTERP1 register in the SYSCON block to create
the interrupt signal asynchronously while the core and the peripheral are not clocked.
See Table 77 “Start logic 1 wake-up enable register (STARTERP1, address
0x4007 421C) bit description”.
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Chapter 26: LPC15xx I2C-bus interface
• In the PDAWAKE register, configure all peripherals that need to be running when the
part wakes up.
• Configure the I2C in slave mode.
• Enable the I2C the interrupt in the I2C INTENCLR register which configures the
interrupt as wake-up event. Examples are the following events:
– Slave deselect
– Slave pending (wait for read, write, or ACK)
– Address match
– Data available/ready for the monitor
26.5 General description
The architecture of the I2C-bus interface is shown in Figure 75.
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Fig 75. I2C block diagram
26.6 Register description
The register functions can be grouped as follows:
• Common registers:
– Table 375 “I2C Configuration register (CFG, address 0x4005 0000) bit description”
– Table 376 “I2C Status register (STAT, address 0x4005 0004) bit description”
– Table 383 “I2C Interrupt Status register (INTSTAT, address 0x4005 0018) bit
description”
– Table 379 “Interrupt Enable Set and read register (INTENSET, address 0x4005
0008) bit description”
– Table 380 “Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit
description”
– Table 381 “Time-out value register (TIMEOUT, address 0x4005 0010) bit
description”
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– Table 382 “I2C Clock Divider register (CLKDIV, address 0x4005 0014) bit
description”
• Master function registers:
– Table 384 “Master Control register (MSTCTL, address 0x4005 0020) bit
description”
– Table 385 “Master Time register (MSTTIME, address 0x4005 0024) bit description”
– Table 386 “Master Data register (MSTDAT, address 0x4005 0028) bit description”
• Slave function registers:
– Table 387 “Slave Control register (SLVCTL, address 0x4005 0040) bit description”
– Table 387 “Slave Control register (SLVCTL, address 0x4005 0040) bit description”
– Table 389 “Slave Address registers (SLVADR[0:3], address 0x4005 0048
(SLVADR0) to 0x4005 0054 (SLVADR3)) bit description”
– Table 390 “Slave address Qualifier 0 register (SLVQUAL0, address 0x4005 0058)
bit description”
• Monitor function register: Table 391 “Monitor data register (MONRXDAT, address
0x4005 0080) bit description”
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Chapter 26: LPC15xx I2C-bus interface
Table 374: Register overview: I2C (base address 0x4005 0000)
Name
Access Offset
Description
Reset
value
Reference
CFG
R/W
0x00
Configuration for shared functions.
0
Table 375
STAT
R/W
0x04
Status register for Master, Slave, and Monitor functions.
0x00080 Table 376
1
INTENSET
R/W
0x08
Interrupt Enable Set and read register.
0
Table 379
INTENCLR
W
0x0C
Interrupt Enable Clear register.
NA
Table 380
TIMEOUT
R/W
0x10
Time-out value register.
0xFFFF
Table 381
I2C
CLKDIV
R/W
0x14
Clock pre-divider for the entire
block. This determines what
time increments are used for the MSTTIME and SLVTIME
registers.
0
Table 382
INTSTAT
R
0x18
Interrupt Status register for Master, Slave, and Monitor
functions.
0
Table 383
MSTCTL
R/W
0x20
Master control register.
0
Table 384
MSTTIME
R/W
0x24
Master timing configuration.
0x77
Table 385
MSTDAT
R/W
0x28
Combined Master receiver and transmitter data register.
NA
Table 386
SLVCTL
R/W
0x40
Slave control register.
0
Table 387
SLVDAT
R/W
0x44
Combined Slave receiver and transmitter data register.
NA
Table 388
SLVADR0
R/W
0x48
Slave address 0.
0x01
Table 389
SLVADR1
R/W
0x4C
Slave address 1.
0x01
Table 389
SLVADR2
R/W
0x50
Slave address 2.
0x01
Table 389
SLVADR3
R/W
0x54
Slave address 3.
0x01
Table 389
SLVQUAL0
R/W
0x58
Slave Qualification for address 0.
0
Table 390
MONRXDAT
RO
0x80
Monitor receiver data register.
0
Table 391
26.6.1 I2C Configuration register
The CFG register contains mode settings that apply to Master, Slave, and Monitor
functions.
Table 375. I2C Configuration register (CFG, address 0x4005 0000) bit description
Bit
Symbol
0
MSTEN
1
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Value Description
Reset
Value
Master Enable. When disabled, configurations settings for
the Master function are not changed, but the Master
function is internally reset.
0
Disabled. The I2C Master function is disabled.
1
Enabled. The I2C Master function is enabled.
SLVEN
0
Slave Enable. When disabled, configurations settings for
0
the Slave function are not changed, but the Slave function
is internally reset.
0
Disabled. The I2C slave function is disabled.
1
Enabled. The I2C slave function is enabled.
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Table 375. I2C Configuration register (CFG, address 0x4005 0000) bit description
Bit
Symbol
2
MONEN
3
4
User manual
Reset
Value
Monitor Enable. When disabled, configurations settings for 0
the Monitor function are not changed, but the Monitor
function is internally reset.
0
Disabled. The I2C monitor function is disabled.
1
Enabled. The I2C monitor function is enabled.
I2C bus Time-out Enable. When disabled, the time-out
function is internally reset.
TIMEOUTEN
0
Disabled. Time-out function is disabled.
1
Enabled. Time-out function is enabled. Both types of
time-out flags will be generated and will cause interrupts if
they are enabled. Typically, only one time-out will be used
in a system.
MONCLKSTR
31:5 -
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Value Description
Monitor function Clock Stretching.
0
0
Disabled. The monitor function will not perform clock
stretching. Software or DMA may not always be able to
read data provided by the monitor function before it is
overwritten. This mode may be used when non-invasive
monitoring is critical.
1
Enabled. The monitor function will perform clock stretching
in order to ensure that software or DMA can read all
incoming data supplied by the monitor function.
Reserved. Read value is undefined, only zero should be
written.
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Chapter 26: LPC15xx I2C-bus interface
26.6.2 I2C Status register
The STAT register provides status flags and state information about all of the functions of
the I2C block. Some information in this register is read-only and some flags can be cleared
by writing a 1 to them.
Access to bits in this register varies. RO = Read-only, W1 = write 1 to clear.
Details on the master and slave states described in the MSTSTATE and SLVSTATE bits in
this register are listed in Table 377 and Table 378.
Table 376. I2C Status register (STAT, address 0x4005 0004) bit description
Bit
Symbol
0
MSTPENDING
3:1
4
Value Description
Reset
value
Master Pending. Indicates that the Master is waiting to continue
1
communication on the I2C-bus (pending) or is idle. When the master
is pending, the MSTSTATE bits indicate what type of software service
if any the master expects. This flag will cause an interrupt when set if,
enabled via the INTENSET register. The MSTPENDING flag is not
set when the DMA is handling an event (if the MSTDMA bit in the
MSTCTL register is set). If the master is in the idle state, and no
communication is needed, mask this interrupt.
0
In progress. Communication is in progress and the Master function is
busy and cannot currently accept a command.
1
Pending. The Master function needs software service or is in the idle
state. If the master is not in the idle state, it is waiting to receive or
transmit data or the NACK bit.
0
Master State code. The master state code reflects the master state
when the MSTPENDING bit is set, that is the master is pending or in
the idle state. Each value of this field indicates a specific required
service for the Master function. All other values are reserved.
MSTSTATE
0x0
Idle. The Master function is available to be used for a new
transaction.
0x1
Receive ready. Received data available (Master Receiver mode).
Address plus Read was previously sent and Acknowledged by slave.
0x2
Transmit ready. Data can be transmitted (Master Transmitter mode).
Address plus Write was previously sent and Acknowledged by slave.
0x3
NACK Address. Slave NACKed address.
0x4
NACK Data. Slave NACKed transmitted data.
MSTARBLOSS
Master Arbitration Loss flag. This flag can be cleared by software
writing a 1 to this bit. It is also cleared automatically a 1 is written to
MSTCONTINUE.
0
No loss. No Arbitration Loss has occurred.
1
Arbitration loss. The Master function has experienced an Arbitration
Loss.
Access
RO
RO
0
W1
NA
NA
At this point, the Master function has already stopped driving the bus
and gone to an idle state. Software can respond by doing nothing, or
by sending a Start in order to attempt to gain control of the bus when
it next becomes idle.
5
-
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Reserved. Read value is undefined, only zero should be written.
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Chapter 26: LPC15xx I2C-bus interface
Table 376. I2C Status register (STAT, address 0x4005 0004) bit description …continued
Bit
Symbol
6
MSTSTSTPERR
Value Description
Reset
value
Master Start/Stop Error flag. This flag can be cleared by software
writing a 1 to this bit. It is also cleared automatically a 1 is written to
MSTCONTINUE.
0
No Start/Stop Error has occurred.
1
Start/stop error has occurred. The Master function has experienced a
Start/Stop Error.
Access
0
W1
NA
NA
A Start or Stop was detected at a time when it is not allowed by the
I2C specification. The Master interface has stopped driving the bus
and gone to an idle state, no action is required. A request for a Start
could be made, or software could attempt to insure that the bus has
not stalled.
7
-
Reserved. Read value is undefined, only zero should be written.
8
SLVPENDING
Slave Pending. Indicates that the Slave function is waiting to continue 0
communication on the I2C-bus and needs software service. This flag
will cause an interrupt when set if enabled via INTENSET. The
SLVPENDING flag is not set when the DMA is handling an event (if
the SLVDMA bit in the SLVCTL register is set). The SLVPENDING
flag is read-only and is automatically cleared when a 1 is written to
the SLVCONTINUE bit in the MSTCTL register.
10:9
11
0
In progress. The Slave function does not currently need service.
1
Pending. The Slave function needs service. Information on what is
needed can be found in the adjacent SLVSTATE field.
SLVSTATE
Slave State code. Each value of this field indicates a specific required 0
service for the Slave function. All other values are reserved.
0x0
Slave address. Address plus R/W received. At least one of the four
slave addresses has been matched by hardware.
0x1
Slave receive. Received data is available (Slave Receiver mode).
0x2
Slave transmit. Data can be transmitted (Slave Transmitter mode).
0x3
Reserved.
Slave Not Stretching. Indicates when the slave function is stretching 1
the I2C clock. This is needed in order to gracefully invoke Deep Sleep
or Power-down modes during slave operation. This read-only flag
reflects the slave function status in real time.
SLVNOTSTR
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0
Stretching. The slave function is currently stretching the I2C bus
clock. Deep-Sleep or Power-down mode cannot be entered at this
time.
1
Not stretching. The slave function is not currently stretching the I2C
bus clock. Deep-sleep or Power-down mode could be entered at this
time.
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Chapter 26: LPC15xx I2C-bus interface
Table 376. I2C Status register (STAT, address 0x4005 0004) bit description …continued
Bit
Symbol
Value Description
Slave address match Index. This field is valid when the I2C slave
0
function has been selected by receiving an address that matches one
of the slave addresses defined by any enabled slave address
registers, and provides an identification of the address that was
matched. It is possible that more than one address could be
matched, but only one match can be reported here.
13:12 SLVIDX
0x0
Slave address 0 was matched.
0x1
Slave address 1 was matched.
0x2
Slave address 2 was matched.
0x3
14
15
16
17
18
SLVSEL
Slave Deselected flag. This flag will cause an interrupt when set if
0
enabled via INTENSET. This flag can be cleared by writing a 1 to this
bit.
W1
Not selected. The Slave function is not currently selected.
Selected. The Slave function is currently selected.
0
Not deselected. The Slave function has not become deselected. This
does not mean that it is currently selected. That information can be
found in the SLVSEL flag.
1
Deselected. The Slave function has become deselected. This is
specifically caused by the SLVSEL flag changing from 1 to 0. See the
description of SLVSEL for details on when that event occurs.
Monitor Ready. This flag is cleared when the MONRXDAT register is 0
read.
0
No data. The Monitor function does not currently have data available.
1
Data waiting. The Monitor function has data waiting to be read.
Monitor Overflow flag.
0
No overrun. Monitor data has not overrun.
1
Overrun. A Monitor data overrun has occurred. This can only happen
when Monitor clock stretching not enabled via the MONCLKSTR bit
in the CFG register. Writing 1 to this bit clears the flag.
MONACTIVE
User manual
RO
1
MONOV
RO
0
0
MONRDY
Access
Slave address 3 was matched.
Slave selected flag. SLVSEL is set after an address match when
software tells the Slave function to acknowledge the address. It is
cleared when another address cycle presents an address that does
not match an enabled address on the Slave function, when slave
software decides to NACK a matched address, or when there is a
Stop detected on the bus. SLVSEL is not cleared if software Nacks
data.
SLVDESEL
UM10736
Reset
value
Monitor Active flag. This flag indicates when the Monitor function
considers the I2C bus to be active. Active is defined here as when
some Master is on the bus: a bus Start has occurred more recently
than a bus Stop.
0
Inactive. The Monitor function considers the I2C bus to be inactive.
1
Active. The Monitor function considers the I2C bus to be active.
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Chapter 26: LPC15xx I2C-bus interface
Table 376. I2C Status register (STAT, address 0x4005 0004) bit description …continued
Bit
Symbol
Value Description
19
MONIDLE
Reset
value
Monitor Idle flag. This flag is set when the Monitor function sees the 0
I2C bus change from active to inactive. This can be used by software
to decide when to process data accumulated by the Monitor function.
This flag will cause an interrupt when set if enabled via the
INTENSET register . The flag can be cleared by writing a 1 to this bit.
0
Not idle. The I2C bus is not idle, or this flag has been cleared by
software.
1
Idle. The I2C bus has gone idle at least once since the last time this
flag was cleared by software.
Access
W1
23:20 -
Reserved. Read value is undefined, only zero should be written.
NA
NA
24
Event Time-out Interrupt flag. Indicates when the time between
events has been longer than the time specified by the TIMEOUT
register. Events include Start, Stop, and clock edges. The flag is
cleared by writing a 1 to this bit. No time-out is created when the
I2C-bus is idle.
0
W1
0
W1
NA
NA
25
EVENTTIMEOUT
0
No time-out. I2C bus events have not caused a time-out.
1
Event time-out. The time between I2C bus events has been longer
than the time specified by the I2C TIMEOUT register.
SCLTIMEOUT
SCL Time-out Interrupt flag. Indicates when SCL has remained low
longer than the time specific by the TIMEOUT register. The flag is
cleared by writing a 1 to this bit.
0
No time-out. SCL low time has not caused a time-out.
1
Time-out. SCL low time has caused a time-out.
31:26 -
Reserved. Read value is undefined, only zero should be written.
Table 377. Master function state codes (MSTSTATE)
MSTSTATE
Description
0x0
Idle. The Master function is available to be used for Send a Start or disable MSTPENDING
a new transaction.
interrupt if the Master function is not
needed currently.
No
0x1
Received data is available (Master Receiver
Read data and either continue, send a
mode). Address plus Read was previously sent and Stop, or send a Repeated Start.
Acknowledged by slave.
Yes
0x2
Data can be transmitted (Master Transmitter
Send data and continue, or send a Stop Yes
mode). Address plus Write was previously sent and or Repeated Start.
Acknowledged by slave.
0x3
Slave NACKed address.
Send a Stop or Repeated Start.
No
0x4
Slave NACKed transmitted data.
Send a Stop or Repeated Start.
No
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Table 378. Slave function state codes (SLVSTATE)
SLVSTATE
Description
Actions
DMA
access
allowed
0
SLVST_ADDR
Address plus R/W
received. At least one of
the 4 slave addresses has
been matched by
hardware.
No
Software can further check the address if needed, for
instance if a subset of addresses qualified by SLVQUAL0 is
to be used. Software can ACK or NACK the address by
writing 1 to either SLVCONTINUE or SLVNACK. Also see
Section 26.7.3 regarding 10-bit addressing.
1
SLVST_RX
Received data is
Read data reply with an ACK or a NACK.
available (Slave Receiver
mode).
Yes
2
SLVST_TX
Data can be transmitted
Send data.
(Slave Transmitter mode).
Yes
3
-
Reserved.
-
-
26.6.3 Interrupt Enable Set and read register
The INTENSET register controls which I2C status flags generate interrupts. Writing a 1 to
a bit position in this register enables an interrupt in the corresponding position in the STAT
register, if an interrupt is supported there. Reading INTENSET indicates which interrupts
are currently enabled.
Table 379. Interrupt Enable Set and read register (INTENSET, address 0x4005 0008) bit
description
Bit
Symbol
Value Description
0
MSTPENDINGEN
Master Pending interrupt Enable.
0
The MstPending interrupt is disabled.
1
The MstPending interrupt is enabled.
-
Reserved. Read value is undefined, only zero
should be written.
NA
4
MSTARBLOSSEN
Master Arbitration Loss interrupt Enable.
0
0
The MstArbLoss interrupt is disabled.
1
The MstArbLoss interrupt is enabled.
5
-
Reserved. Read value is undefined, only zero
should be written.
NA
6
MSTSTSTPERREN
Master Start/Stop Error interrupt Enable.
0
1
The MstStStpErr interrupt is disabled.
The MstStStpErr interrupt is enabled.
7
-
Reserved. Read value is undefined, only zero
should be written.
NA
8
SLVPENDINGEN
Slave Pending interrupt Enable.
0
10:9
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0
3:1
0
UM10736
Reset
value
-
0
The SlvPending interrupt is disabled.
1
The SlvPending interrupt is enabled.
Reserved. Read value is undefined, only zero
should be written.
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Table 379. Interrupt Enable Set and read register (INTENSET, address 0x4005 0008) bit
description
Bit
Symbol
Value Description
11
SLVNOTSTREN
Reset
value
Slave Not Stretching interrupt Enable.
0
The SlvNotStr interrupt is disabled.
1
The SlvNotStr interrupt is enabled.
0
14:12 -
Reserved. Read value is undefined, only zero
should be written.
NA
15
Slave Deselect interrupt Enable.
0
16
17
SLVDESELEN
0
The SlvDeSel interrupt is disabled.
1
The SlvDeSel interrupt is enabled.
MONRDYEN
Monitor data Ready interrupt Enable.
0
The MonRdy interrupt is disabled.
1
The MonRdy interrupt is enabled.
MONOVEN
18
-
19
MONIDLEEN
0
Monitor Overrun interrupt Enable.
0
The MonOv interrupt is disabled.
1
The MonOv interrupt is enabled.
0
Reserved. Read value is undefined, only zero
should be written.
NA
Monitor Idle interrupt Enable.
0
0
The MonIdle interrupt is disabled.
1
The MonIdle interrupt is enabled.
23:20 -
Reserved. Read value is undefined, only zero
should be written.
NA
24
Event time-out interrupt Enable.
0
25
EVENTTIMEOUTEN
0
The Event time-out interrupt is disabled.
1
The Event time-out interrupt is enabled.
SCLTIMEOUTEN
31:26 -
SCL time-out interrupt Enable.
0
The SCL time-out interrupt is disabled.
1
The SCL time-out interrupt is enabled.
0
Reserved. Read value is undefined, only zero
should be written.
NA
26.6.4 Interrupt Enable Clear register
Writing a 1 to a bit position in INTENCLR clears the corresponding position in the
INTENSET register, disabling that interrupt. INTENCLR is a write-only register.
Bits that do not correspond to defined bits in INTENSET are reserved and only zeroes
should be written to them.
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Table 380. Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit
description
Bit
Symbol
Description
Reset
value
0
MSTPENDINGCLR
Master Pending interrupt clear. Writing 1 to this bit clears
the corresponding bit in the INTENSET register if
implemented.
0
3:1
-
Reserved. Read value is undefined, only zero should be
written.
NA
4
MSTARBLOSSCLR
Master Arbitration Loss interrupt clear.
0
5
-
Reserved. Read value is undefined, only zero should be
written.
NA
6
MSTSTSTPERRCLR
Master Start/Stop Error interrupt clear.
0
7
-
Reserved. Read value is undefined, only zero should be
written.
NA
8
SLVPENDINGCLR
Slave Pending interrupt clear.
0
10:9
-
Reserved. Read value is undefined, only zero should be
written.
NA
11
SLVNOTSTRCLR
Slave Not Stretching interrupt clear.
0
14:12 -
Reserved. Read value is undefined, only zero should be
written.
NA
15
SLVDESELCLR
Slave Deselect interrupt clear.
0
16
MONRDYCLR
Monitor data Ready interrupt clear.
0
17
MONOVCLR
Monitor Overrun interrupt clear.
0
18
-
Reserved. Read value is undefined, only zero should be
written.
NA
19
MONIDLECLR
Monitor Idle interrupt clear.
0
Reserved. Read value is undefined, only zero should be
written.
NA
23:20 24
EVENTTIMEOUTCLR Event time-out interrupt clear.
0
25
SCLTIMEOUTCLR
SCL time-out interrupt clear.
0
Reserved. Read value is undefined, only zero should be
written.
NA
31:26 -
26.6.5 Time-out value register
The TIMEOUT register allows setting an upper limit to certain I2C bus times, informing by
status flag and/or interrupt when those times are exceeded.
Two time-outs are generated, and software can elect to use either of them.
1. EVENTTIMEOUT checks the time between bus events while the bus is not idle: Start,
SCL rising, SCL falling, and Stop. The EVENTTIMEOUT status flag in the STAT
register is set if the time between any two events becomes longer than the time
configured in the TIMEOUT register. The EVENTTIMEOUT status flag can cause an
interrupt if enabled to do so by the EVENTTIMEOUTEN bit in the INTENSET register.
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2. SCLTIMEOUT checks only the time that the SCL signal remains low while the bus is
not idle. The SCLTIMEOUT status flag in the STAT register is set if SCL remains low
longer than the time configured in the TIMEOUT register. The SCLTIMEOUT status
flag can cause an interrupt if enabled to do so by the SCLTIMEOUTEN bit in the
INTENSET register. The SCLTIMEOUT can be used with the SMBus.
Also see Section 26.7.2 “Time-out”.
Table 381. Time-out value register (TIMEOUT, address 0x4005 0010) bit description
Bit
Symbol
Description
Reset
value
3:0
TOMIN
Time-out time value, bottom four bits. These are hard-wired to 0xF.
This gives a minimum time-out of 16 I2C function clocks and also a
time-out resolution of 16 I2C function clocks.
0xF
15:4
TO
Time-out time value. Specifies the time-out interval value in increments 0xFFF
of 16 I2C function clocks, as defined by the CLKDIV register. To change
this value while I2C is in operation, disable all time-outs, write a new
value to TIMEOUT, then re-enable time-outs.
0x000 = A time-out will occur after 16 counts of the I2C function clock.
0x001 = A time-out will occur after 32 counts of the I2C function clock.
...
0xFFF = A time-out will occur after 65,536 counts of the I2C function
clock.
31:16 -
Reserved. Read value is undefined, only zero should be written.
NA
26.6.6 Clock Divider register
The CLKDIV register divides down the Peripheral Clock (PCLK) to produce the I2C
function clock that is used to time various aspects of the I2C interface. The I2C function
clock is used for some internal operations in the I2C block and to generate the timing
required by the I2C bus specification, some of which are user configured in the MSTTIME
register for Master operation and the SLVTIME register for Slave operation.
See Section 26.7.1.1 “Rate calculations” for details on bus rate setup.
Table 382. I2C Clock Divider register (CLKDIV, address 0x4005 0014) bit description
Bit
Symbol Description
15:0
DIVVAL
Reset
value
This field controls how the clock (PCLK) is used by the I2C functions
that need an internal clock in order to operate.
0
0x0000 = PCLK is used directly by the I2C function.
0x0001 = PCLK is divided by 2 before use by the I2C function.
0x0002 = PCLK is divided by 3 before use by the I2C function.
...
0xFFFF = PCLK is divided by 65,536 before use by the I2C function.
31:16 -
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26.6.7 Interrupt Status register
The INTSTAT register provides register provides a view of those interrupt flags that are
currently enabled. This can simplify software handling of interrupts. See Table 376 for
detailed descriptions of the interrupt flags.
Table 383. I2C Interrupt Status register (INTSTAT, address 0x4005 0018) bit description
Bit
Symbol
Description
Reset
value
0
MSTPENDING
Master Pending.
1
3:1
-
Reserved.
4
MSTARBLOSS
Master Arbitration Loss flag.
0
5
-
Reserved. Read value is undefined, only zero should be
written.
NA
6
MSTSTSTPERR
Master Start/Stop Error flag.
0
7
-
Reserved. Read value is undefined, only zero should be
written.
NA
8
SLVPENDING
Slave Pending.
0
10:9
-
Reserved. Read value is undefined, only zero should be
written.
NA
11
SLVNOTSTR
Slave Not Stretching status.
1
14:12 -
Reserved. Read value is undefined, only zero should be
written.
NA
15
SLVDESEL
Slave Deselected flag.
0
16
MONRDY
Monitor Ready.
0
17
MONOV
Monitor Overflow flag.
0
18
-
Reserved. Read value is undefined, only zero should be
written.
NA
19
MONIDLE
Monitor Idle flag.
0
23:20 -
Reserved. Read value is undefined, only zero should be
written.
NA
24
EVENTTIMEOUT
Event time-out Interrupt flag.
0
25
SCLTIMEOUT
SCL time-out Interrupt flag.
0
Reserved. Read value is undefined, only zero should be
written.
NA
31:26 -
26.6.8 Master Control register
The MSTCTL register contains bits that control various functions of the I2C Master
interface. Only write to this register when the master is pending (MSTPENDING = 1 in the
STAT register, Table 376).
Software should always write a complete value to MSTCTL, and not OR new control bits
into the register as is possible in other registers such as CFG. This is due to the fact that
MSTSTART and MSTSTOP are not self-clearing flags. ORing in new data following a
Start or Stop may cause undesirable side effects.
After an initial I2C Start, MSTCTL should generally only be written when the
MSTPENDING flag in the STAT register is set, after the last bus operation has completed.
An exception is when DMA is being used and a transfer completes. In this case there is no
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MSTPENDING flag, and the MSTDMA control bit would be cleared by software potentially
at the same time as setting either the MSTSTOP or MSTSTART control bit.
Remark: When in the idle or slave NACKed states (see Table 377), set the MSTDMA bit
either with or after the MSTCONTINUE bit. MSTDMA can be cleared at any time.
Table 384. Master Control register (MSTCTL, address 0x4005 0020) bit description
Bit Symbol
0
1
2
3
Value Description
MSTCONTINUE
Reset
value
Master Continue. This bit is write-only.
0
0
No effect.
1
Continue. Informs the Master function to continue to the
next operation. This must done after writing transmit data,
reading received data, or any other housekeeping related
to the next bus operation.
MSTSTART
Master Start control. This bit is write-only.
0
0
No effect.
1
Start. A Start will be generated on the I2C bus at the next
allowed time.
MSTSTOP
Master Stop control. This bit is write-only.
0
0
No effect.
1
Stop. A Stop will be generated on the I2C bus at the next
allowed time, preceded by a NACK to the slave if the
master is receiving data from the slave (Master Receiver
mode).
MSTDMA
Master DMA enable. Data operations of the I2C can be
performed with DMA. Protocol type operations such as
Start, address, Stop, and address match must always be
done with software, typically via an interrupt. When a
DMA data transfer is complete, MSTDMA must be
cleared prior to beginning the next operation, typically a
Start or Stop.This bit is read/write.
31: 4
0
Disable. No DMA requests are generated for master
operation.
1
Enable. A DMA request is generated for I2C master data
operations. When this I2C master is generating
Acknowledge bits in Master Receiver mode, the
acknowledge is generated automatically.
Reserved. Read value is undefined, only zero should be
written.
0
NA
26.6.9 Master Time
The MSTTIME register allows programming of certain times that may be controlled by the
Master function. These include the clock (SCL) high and low times, repeated Start setup
time, and transmitted data setup time.
The I2C clock pre-divider is described in Table 382.
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Table 385. Master Time register (MSTTIME, address 0x4005 0024) bit description
Bit
Symbol
2:0
MSTSCLLOW
3
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Value Description
Reset
value
Master SCL Low time. Specifies the minimum low time
0
that will be asserted by this master on SCL. Other devices
on the bus (masters or slaves) could lengthen this time.
This corresponds to the parameter tLOW in the I2C bus
specification. I2C bus specification parameters tBUF and
tSU;STA have the same values and are also controlled by
MSTSCLLOW.
0x0
2 clocks. Minimum SCL low time is 2 clocks of the I2C
clock pre-divider.
0x1
3 clocks. Minimum SCL low time is 3 clocks of the I2C
clock pre-divider.
0x2
4 clocks. Minimum SCL low time is 4 clocks of the I2C
clock pre-divider.
0x3
5 clocks. Minimum SCL low time is 5 clocks of the I2C
clock pre-divider.
0x4
6 clocks. Minimum SCL low time is 6 clocks of the I2C
clock pre-divider.
0x5
7 clocks. Minimum SCL low time is 7 clocks of the I2C
clock pre-divider.
0x6
8 clocks. Minimum SCL low time is 8 clocks of the I2C
clock pre-divider.
0x7
9 clocks. Minimum SCL low time is 9 clocks of the I2C
clock pre-divider.
Reserved.
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Table 385. Master Time register (MSTTIME, address 0x4005 0024) bit description …continued
Bit
Symbol
6:4
MSTSCLHIGH
31:7
Value Description
Reset
value
Master SCL High time. Specifies the minimum high time 0
that will be asserted by this master on SCL. Other
masters in a multi-master system could shorten this time.
This corresponds to the parameter tHIGH in the I2C bus
specification. I2C bus specification parameters tSU;STO
and tHD;STA have the same values and are also controlled
by MSTSCLHIGH.
0x0
2 clocks. Minimum SCL high time is 2 clock of the I2C
clock pre-divider.
0x1
3 clocks. Minimum SCL high time is 3 clocks of the I2C
clock pre-divider .
0x2
4 clocks. Minimum SCL high time is 4 clock of the I2C
clock pre-divider.
0x3
5 clocks. Minimum SCL high time is 5 clock of the I2C
clock pre-divider.
0x4
6 clocks. Minimum SCL high time is 6 clock of the I2C
clock pre-divider.
0x5
7 clocks. Minimum SCL high time is 7 clock of the I2C
clock pre-divider.
0x6
8 clocks. Minimum SCL high time is 8 clock of the I2C
clock pre-divider.
0x7
9 clocks. Minimum SCL high time is 9 clocks of the I2C
clock pre-divider.
-
Reserved. Read value is undefined, only zero should be
written.
NA
26.6.10 Master Data register
The MSTDAT register provides the means to read the most recently received data for the
Master function, and to transmit data using the Master function.
Table 386. Master Data register (MSTDAT, address 0x4005 0028) bit description
Bit
Symbol
Description
7:0
DATA
Master function data register.
Reset
value
0
Read: read the most recently received data for the Master function.
Write: transmit data using the Master function.
31:8
-
Reserved. Read value is undefined, only zero should be written.
NA
26.6.11 Slave Control register
The SLVCTL register contains bits that control various functions of the I2C Slave interface.
Only write to this register when the slave is pending (SLVPENDING = 1 in the STAT
register, Table 376).
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Remark: When in the slave address state (slave state 0, see Table 378), set the SLVDMA
bit either with or after the SLVCONTINUE bit. SLVDMA can be cleared at any time.
Table 387. Slave Control register (SLVCTL, address 0x4005 0040) bit description
Bit
Symbol
0
SLVCONTINUE
1
3
31:4
Value Description
Reset
Value
Slave Continue.
0
0
No effect.
1
Continue. Informs the Slave function to continue to the
next operation. This must done after writing transmit
data, reading received data, or any other housekeeping
related to the next bus operation.
SLVNACK
Slave NACK.
0
0
No effect.
1
NACK. Causes the Slave function to NACK the master
when the slave is receiving data from the master (Slave
Receiver mode).
SLVDMA
Slave DMA enable.
0
0
Disabled. No DMA requests are issued for Slave mode
operation.
1
Enabled. DMA requests are issued for I2C slave data
transmission and reception.
-
Reserved. Read value is undefined, only zero should be
written.
NA
26.6.12 Slave Data register
The SLVDAT register provides the means to read the most recently received data for the
Slave function and to transmit data using the Slave function.
Table 388. Slave Data register (SLVDAT, address 0x4005 0044) bit description
Bit
Symbol
Description
7:0
DATA
Slave function data register.
Reset
Value
0
Read: read the most recently received data for the Slave function.
Write: transmit data using the Slave function.
31:8
-
Reserved. Read value is undefined, only zero should be written.
NA
26.6.13 Slave Address registers
The SLVADR[0:3] registers allow enabling and defining one of the addresses that can be
automatically recognized by the I2C slave hardware. The value in the SLVADR0 register is
qualified by the setting of the SLVQUAL0 register.
When the slave address is compared to the receive address, the compare can be affected by the
setting of the SLVQUAL0 register (see Section 26.6.14).
The I2C slave function has 4 address comparators. The additional 3 address comparators
do not include the address qualifier feature. For handling of the general call address, one
of the 4 address registers can be programmed to respond to address 0.
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Table 389. Slave Address registers (SLVADR[0:3], address 0x4005 0048 (SLVADR0) to
0x4005 0054 (SLVADR3)) bit description
Bit
Symbol
Value Description
0
SADISABLE
Reset
value
Slave Address n Disable.
1
0
Enabled. Slave Address n is enabled and will be
recognized with any changes specified by the SLVQUAL0
register.
1
Ignored Slave Address n is ignored.
7:1
SLVADR
Seven bit slave address that is compared to received
addresses if enabled.
0
31:8
-
Reserved. Read value is undefined, only zero should be
written.
NA
26.6.14 Slave address Qualifier 0 register
The SLVQUAL0 register can alter how Slave Address 0 is interpreted.
Table 390. Slave address Qualifier 0 register (SLVQUAL0, address 0x4005 0058) bit
description
Bit
Symbol
0
QUALMODE0
7:1
Value Description
Reset
Value
Reserved. Read value is undefined, only zero should be
written.
0
The SLVQUAL0 field is used as a logical mask for
matching address 0.
1
The SLVQUAL0 field is used to extend address 0
matching in a range of addresses.
SLVQUAL0
0
Slave address Qualifier for address 0. A value of 0 causes 0
the address in SLVADR0 to be used as-is, assuming that
it is enabled.
If QUALMODE0 = 0, any bit in this field which is set to 1
will cause an automatic match of the corresponding bit of
the received address when it is compared to the
SLVADR0 register.
If QUALMODE0 = 1, an address range is matched for
address 0. This range extends from the value defined by
SLVADR0 to the address defined by SLVQUAL0 (address
matches when SLVADR0[7:1] <= received address <=
SLVQUAL0[7:1]).
31:8
-
Reserved. Read value is undefined, only zero should be
written.
NA
26.6.15 Monitor data register
The read-only MONRXDAT register provides information about events on the I2C bus,
primarily to facilitate debugging of the I2C during application development. All data
addresses and data passing on the bus and whether these were acknowledged, as well
as Start and Stop events, are reported.
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The Monitor function must be enabled by the MONEN bit in the CFG register. Monitor
mode can be configured to stretch the I2C clock if data is not read from the MONRXDAT
register in time to prevent it, via the MONCLKSTR bit in the CFG register. This can help
ensure that nothing is missed but can cause the monitor function to be somewhat intrusive
(by potentially adding clock delays, depending on software or DMA response time). In
order to improve the chance of collecting all Monitor information if clock stretching is not
enabled, Monitor data is buffered such that it is available until the end of the next piece of
information from the I2C bus.
Table 391. Monitor data register (MONRXDAT, address 0x4005 0080) bit description
Bit
Symbol
7:0
MONRXDAT
Monitor function Receiver Data. This reflects every data
byte that passes on the I2C pins, and adds indication of
Start, Repeated Start, and data NACK.
0
8
MONSTART
Monitor Received Start.
0
9
10
Value Description
0
No detect. The monitor function has not detected a Start
event on the I2C bus.
1
Start detect. The monitor function has detected a Start
event on the I2C bus.
MONRESTART
Monitor Received Repeated Start.
0
0
No start detect. The monitor function has not detected a
Repeated Start event on the I2C bus.
1
Repeated start detect. The monitor function has
detected a Repeated Start event on the I2C bus.
MONNACK
31:11 -
Reset
value
Monitor Received NACK.
0
0
Acknowledged. The data currently being provided by the
monitor function was acknowledged by at least one
master or slave receiver.
1
Not acknowledged. The data currently being provided by
the monitor function was not acknowledged by any
receiver.
Reserved. Read value is undefined, only zero should be NA
written.
26.7 Functional description
26.7.1 Bus rates and timing considerations
Due to the nature of the I2C bus, it is generally not possible to guarantee a specific clock
rate on the SCL pin. On the I2C-bus, the The clock can be stretched by any slave device,
extended by software overhead time, etc. In a multi-master system, the master that
provides the shortest SCL high time will cause that time to appear on SCL as long as that
master is participating in I2C traffic (i.e. when it is the only master on the bus, or during
arbitration between masters).
Rate calculations give a base frequency that represents the fastest that the I2C bus could
operate if nothing slows it down.
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26.7.1.1 Rate calculations
SCL high time (in I2C function clocks) = (CLKDIV + 1) * (MSTSCLHIGH + 2)
SCL low time (in I2C function clocks) = (CLKDIV + 1) * (MSTSCLLOW + 2)
Nominal SCL rate = I2C function clock rate / (SCL high time + SCL low time)
26.7.2 Time-out
A time-out feature on an I2C interface can be used to detect a “stuck” bus and potentially
do something to alleviate the condition. Two different types of time-out are supported.
Both types apply whenever the I2C block and the time-out function are both enabled,
Master, Slave, or Monitor functions do not need to be enabled.
In the first type of time-out, reflected by the EVENTTIMEOUT flag in the STAT register, the
time between bus events governs the time-out check. These events include Start, Stop,
and all changes on the I2C clock (SCL). This time-out is asserted when the time between
any of these events is longer than the time configured in the TIMEOUT register. This
time-out could be useful in monitoring an I2C bus within a system as part of a method to
keep the bus running of problems occur.
The second type of I2C time-out is reflected by the SCLTIMEOUT flag in the STAT
register. This time-out is asserted when the SCL signal remains low longer than the time
configured in the TIMEOUT register. This corresponds to SMBus time-out parameter
TTIMEOUT. In this situation, a slave could reset its own I2C interface in case it is the
offending device. If all listening slaves (including masters that can be addressed as
slaves) do this, then the bus will be released unless it is a current master causing the
problem. Refer to the SMBus specification for more details.
Both types of time-out are generated when the I2C bus is considered busy.
26.7.3 Ten-bit addressing
Ten-bit addressing is accomplished by the I2C master sending a second address byte to
extend a particular range of standard 7-bit addresses. In the case of the master writing to
the slave, the I2C frame simply continues with data after the 2 address bytes. For the
master to read from a slave, it needs to reverse the data direction after the second
address byte. This is done by sending a Repeated Start, followed by a repeat of the same
standard 7-bit address, with a Read bit. The slave must remember that it had been
addressed by the previous write operation and stay selected for the subsequent read with
the correct partial I2C address.
For the Master function, the I2C is simply instructed to perform the 2-byte addressing as a
normal write operation, followed either by more write data, or by a Repeated Start with a
repeat of the first part of the 10-bit slave address and then reading in the normal fashion.
For the Slave function, the first part of the address is automatically matched in the same
fashion as 7-bit addressing. The Slave address qualifier feature (see Section 26.6.14) can
be used to intercept all potential 10-bit addresses (first address byte values F0 through
F6), or just one. In the case of Slave Receiver mode, data is received in the normal
fashion after software matches the first data byte to the remaining portion of the 10-bit
address. The Slave function should record the fact that it has been addressed, in case
there is a follow-up read operation.
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For Slave Transmitter mode, the slave function responds to the initial address in the same
fashion as for Slave Receiver mode, and checks that it has previously been addressed
with a full 10-bit address. If the address matched is address 0, and address qualification is
enabled, software must check that the first part of the 10-bit address is a complete match
to the previous address before acknowledging the address.
26.7.4 Clocking and power considerations
The Master function of the I2C always requires a peripheral clock to be running in order to
operate. The Slave function can operate without any internal clocking when the slave is
not currently addressed. This means that reduced power modes up to Power-down mode
can be entered, and the device will wake up when the I2C Slave function recognizes an
address. Monitor mode can similarly wake up the device from a reduced power mode
when information becomes available.
26.7.5 lnterrupt handling
The I2C provides a single interrupt output that handles all interrupts for Master, Slave, and
Monitor functions.
26.7.6 DMA
Generally, data transfers can be handled by DMA for Master mode after an address is
sent and acknowledged by a slave, and for Slave mode after software has acknowledged
an address. In either mode, software is always involved in the address portion of a
message. In master and slave modes, data receive and transmit data can be transferred
by the DMA. The DMA supports three DMA requests: data transfer in master mode, slave
mode, and monitor mode.
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27.1 How to read this chapter
The C_CAN controller is available on all parts.
27.2 Features
•
•
•
•
•
•
•
Conforms to protocol version 2.0 parts A and B.
Supports bit rate of up to 1 Mbit/s.
Supports 32 Message Objects.
Each Message Object has its own identifier mask.
Provides programmable FIFO mode (concatenation of Message Objects).
Provides maskable interrupts.
Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
• Provides programmable loop-back mode for self-test operation.
27.3 Basic configuration
The C_CAN0 is configured using the following registers:
1. Power: In the SYSAHBCLKCTRL1 register, set bit 7 (Table 51).
2. Clocking: For an accurate peripheral clock to the C_CAN0 block, select the system
oscillator as clock source for the system clock. Do not select the IRC if C_CAN0 baud
rates above 100 kbit/s are required.
3. Use the PRESETCTRL1 register (Table 36) reset the C_CAN0 block.
4. Enable/disable the C_CAN0 interrupt in interrupt slot #27 in the NVIC.
The peripheral clock PCLK to the C_CAN0 (the C_CAN system clock) and to the
programmable C_CAN0 clock divider (see Table 423) is provided by the system clock
(see Table 49). This clock can be disabled through bit 7 in the SYSAHBCLKCTRL1
register for power savings.
Remark: If C_CAN0 baudrates above 100 kbit/s are required, the system oscillator must
be selected as the clock source for the system clock. For lower baudrates, the IRC may
also be used as clock source.
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Chapter 27: LPC15xx Controller Area Network C_CAN0
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Fig 76. C_CAN clocking
27.4 General description
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a very high level of security.
The CAN controller consists of a CAN core, message RAM, a message handler, control
registers, and the APB interface.
For communication on a CAN network, individual Message Objects are configured. The
Message Objects and Identifier Masks for acceptance filtering of received messages are
stored in the Message RAM.
All functions concerning the handling of messages are implemented in the Message
Handler. Those functions are the acceptance filtering, the transfer of messages between
the CAN Core and the Message RAM, and the handling of transmission requests as well
as the generation of the module interrupt.
The register set of the CAN controller can be accessed directly by an external CPU via the
APB bus. These registers are used to control/configure the CAN Core and the Message
Handler and to access the Message RAM.
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Fig 77. C_CAN block diagram
27.5 Pin description
The C_CAN pins are movable functions and are assigned to pins through the switch
matrix.
See Section 8.3.1 “Connect an internal signal to a package pin” to assign the C_CAN pins
to any pin on the package.
Table 392. C_CAN pin description
Function
Direction Type
Connect
to
Use register
Reference Description
CAN_TD1_
O
O
external
to pin
any
PINASSIGN6
Table 113
Transmit
external
to pin
any
PINASSIGN6
Table 113
Receive
CAN_RD1_I I
27.6 Register description
The C_CAN registers are organized as 32-bit wide registers.
The two sets of interface registers (IF1 and IF2) control the CPU access to the Message
RAM. They buffer the data to be transferred to and from the RAM, avoiding conflicts
between CPU accesses and message reception/transmission.
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Table 393. Register overview: CCAN (base address 0x400F 0000)
Name
Access
Address
offset
Description
Reset
value
Reference
CNTL
R/W
0x000
CAN control
0x0001
Table 394
STAT
R/W
0x004
Status register
0x0000
Table 395
EC
RO
0x008
Error counter
0x0000
Table 396
BT
R/W
0x00C
Bit timing register
0x2301
Table 397
INT
RO
0x010
Interrupt register
0x0000
Table 398
TEST
R/W
0x014
Test register
-
Table 399
BRPE
R/W
0x018
Baud rate prescaler extension register
0x0000
Table 400
-
-
0x01C
Reserved
-
IF1_CMDREQ
R/W
0x020
Message interface 1 command request
0x0001
Table 403
IF1_CMDMSK_W
R/W
0x024
Message interface 1 command mask (write
direction)
0x0000
Table 404
IF1_CMDMSK_R
R/W
0x024
Message interface 1 command mask (read
direction)
0x0000
Table 405
IF1_MSK1
R/W
0x028
Message interface 1 mask 1
0xFFFF
Table 406
IF1_MSK2
R/W
0x02C
Message interface 1 mask 2
0xFFFF
Table 407
IF1_ARB1
R/W
0x030
Message interface 1 arbitration 1
0x0000
Table 408
IF1_ARB2
R/W
0x034
Message interface 1 arbitration 2
0x0000
Table 409
IF1_MCTRL
R/W
0x038
Message interface 1 message control
0x0000
Table 410
IF1_DA1
R/W
0x03C
Message interface 1 data A1
0x0000
Table 411
IF1_DA2
R/W
0x040
Message interface 1 data A2
0x0000
Table 412
IF1_DB1
R/W
0x044
Message interface 1 data B1
0x0000
Table 413
IF1_DB2
R/W
0x048
Message interface 1 data B2
0x0000
Table 414
-
-
0x04C 0x07C
Reserved
-
IF2_CMDREQ
R/W
0x080
Message interface 2 command request
0x0001
Table 403
IF2_CMDMSK_W
R/W
0x084
Message interface 2 command mask (write
direction)
0x0000
Table 404
IF2_CMDMSK_R
R/W
0x084
Message interface 2 command mask (read
direction)
0x0000
Table 405
IF2_MSK1
R/W
0x088
Message interface 2 mask 1
0xFFFF
Table 406
IF2_MSK2
R/W
0x08C
Message interface 2 mask 2
0xFFFF
Table 407
IF2_ARB1
R/W
0x090
Message interface 2 arbitration 1
0x0000
Table 408
IF2_ARB2
R/W
0x094
Message interface 2 arbitration 2
0x0000
Table 409
IF2_MCTRL
R/W
0x098
Message interface 2 message control
0x0000
Table 410
IF2_DA1
R/W
0x09C
Message interface 2 data A1
0x0000
Table 411
IF2_DA2
R/W
0x0A0
Message interface 2 data A2
0x0000
Table 412
IF2_DB1
R/W
0x0A4
Message interface 2 data B1
0x0000
Table 413
IF2_DB2
R/W
0x0A8
Message interface 2 data B2
0x0000
Table 414
-
-
0x0AC 0x0FC
Reserved
-
TXREQ1
RO
0x100
Transmission request 1
0x0000
Table 415
TXREQ2
RO
0x104
Transmission request 2
0x0000
Table 416
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Table 393. Register overview: CCAN (base address 0x400F 0000)
Name
Access
Address
offset
Description
Reset
value
Reference
-
-
0x108 0x11C
Reserved
-
ND1
RO
0x120
New data 1
0x0000
Table 417
ND2
RO
0x124
New data 2
0x0000
Table 418
-
-
0x128 0x13C
Reserved
-
IR1
RO
0x140
Interrupt pending 1
0x0000
Table 419
IR2
RO
0x144
Interrupt pending 2
0x0000
Table 420
-
-
0x148 0x15C
Reserved
-
MSGV1
RO
0x160
Message valid 1
0x0000
Table 421
MSGV2
RO
0x164
Message valid 2
0x0000
Table 422
-
-
0x168 0x17C
Reserved
-
CLKDIV
R/W
0x180
Can clock divider register
0x0001
Table 423
27.6.1 CAN protocol registers
27.6.1.1 CAN control register
The reset value 0x0001 of the CANCTL register enables initialization by software (INIT =
1). The C_CAN does not influence the CAN bus until the CPU resets the INIT bit to 0.
Table 394. CAN control registers (CNTL, address 0x400F 0000) bit description
Bit
Symbol Value
Description
Reset
value
Access
0
INIT
Initialization
1
R/W
0
R/W
0
R/W
1
2
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0
Normal operation.
1
Started. Initialization is started. On reset,
software needs to initialize the CAN controller.
IE
Module interrupt enable
0
Disable CAN interrupts. The interrupt line is
always HIGH.
1
Enable CAN interrupts. The interrupt line is set
to LOW and remains LOW until all pending
interrupts are cleared.
0
Disable status change interrupts. No status
change interrupt will be generated.
1
Enable status change interrupts. A status
change interrupt will be generated when a
message transfer is successfully completed or
a CAN bus error is detected.
SIE
Status change interrupt enable
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Table 394. CAN control registers (CNTL, address 0x400F 0000) bit description
…continued
Bit
Symbol Value
3
EIE
4
-
5
DAR
6
7
31:8
Description
Reset
value
Access
Error interrupt enable
0
R/W
0
Disable error interrupt. No error status interrupt
will be generated.
1
Enable error interrupt. A change in the bits
BOFF or EWARN in the CANSTAT registers
will generate an interrupt.
-
reserved
0
-
Disable automatic retransmission
0
R/W
0
R/W
0
R/W
-
-
0
Enabled. Automatic retransmission of
disturbed messages enabled.
1
Disabled. Automatic retransmission disabled.
CCE
Configuration change enable
0
No write access. The CPU has no write access
to the bit timing register.
1
Write access. The CPU has write access to the
CANBT register while the INIT bit is one.
TEST
Test mode enable
0
Normal operation.
1
Test mode.
-
reserved
Remark: The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be
shortened by setting or resetting the INIT bit. If the device goes into busoff state, it will set
INIT, stopping all bus activities. Once INIT has been cleared by the CPU, the device will
then wait for 129 occurrences of Bus Idle (129  11 consecutive HIGH/recessive bits)
before resuming normal operations. At the end of the busoff recovery sequence, the Error
Management Counters will be reset.
During the waiting time after the resetting of INIT, each time a sequence of 11
HIGH/recessive bits has been monitored, a Bit0Error code is written to the Status Register
CANSTAT, enabling the CPU to monitor the proceeding of the busoff recovery sequence
and to determine whether the CAN bus is stuck at LOW/dominant or continuously
disturbed.
27.6.1.2 CAN status register
A status interrupt is generated by bits BOFF, EWARN, RXOK, TXOK, or LEC. BOFF and
EWARN generate an error interrupt, and RXOK, TXOK, and LEC generate a status
change interrupt if EIE and SIE respectively are set to enabled in the CANCTRL register.
A change of bit EPASS and a write to RXOK, TXOK, or LEC will never create a status
interrupt.
Reading the STAT register will clear the Status Interrupt value (0x8000) in the INT register.
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Table 395. CAN status register (STAT, address 0x400F 0004) bit description
Bit
Symbol
2:0
LEC
Value
Description
Reset
value
Access
Last error code
000
R/W
0
R/W
0
R/W
Type of the last error to occur on the CAN bus.The LEC field holds a
code which indicates the type of the last error to occur on the CAN bus.
This field will be cleared to ‘0’ when a message has been transferred
(reception or transmission) without error. The unused code ‘111’ may be
written by the CPU to check for updates.
3
0x0
No error.
0x1
Stuff error. More than 5 equal bits in a sequence have occurred in a
part of a received message where this is not allowed.
0x2
Form error. A fixed format part of a received frame has the wrong
format.
0x3
AckError. The message this CAN core transmitted was not
acknowledged.
0x4
Bit1Error. During the transmission of a message (with the exception of
the arbitration field), the device wanted to send a HIGH/recessive level
(bit of logical value ‘1’), but the monitored bus value was
LOW/dominant.
0x5
Bit0Error. During the transmission of a message (or acknowledge bit,
or active error flag, or overload flag), the device wanted to send a
LOW/dominant level (data or identifier bit logical value ‘0’), but the
monitored Bus value was HIGH/recessive. During busoff recovery this
status is set each time a sequence of 11 HIGH/recessive bits has been
monitored. This enables the CPU to monitor the proceeding of the
busoff recovery sequence (indicating the bus is not stuck at
LOW/dominant or continuously disturbed).
0x6
CRCError. The CRC checksum was incorrect in the message received.
0x7
Unused. No CAN bus event was detected (written by the CPU).
TXOK
Transmitted a message successfully
This bit must be reset by the CPU. It is never reset by the CAN
controller.
4
0
No transmit. Since this bit was last reset by the CPU, no message has
been successfully transmitted.
1
Successful transmit. Since this bit was last reset by the CPU, a
message has been successfully transmitted (error free and
acknowledged by at least one other node).
RXOK
Received a message successfully
This bit must be reset by the CPU. It is never reset by the CAN
controller.
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0
No receive. Since this bit was last reset by the CPU, no message has
been successfully received.
1
Successful receive.Since this bit was last set to zero by the CPU, a
message has been successfully received independent of the result of
acceptance filtering.
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Table 395. CAN status register (STAT, address 0x400F 0004) bit description
…continued
Bit
Symbol
5
EPASS
6
7
31:8
Value
Reset
value
Access
Error passive
0
RO
0
RO
0
RO
0
Active. The CAN controller is in the error active state.
1
Passive. The CAN controller is in the error passive state as defined in
the CAN 2.0 specification.
EWARN
Warning status
0
Below limit. Both error counters are below the error warning limit of 96.
1
At limit. At least one of the error counters in the EC has reached the
error warning limit of 96.
0
The CAN module is not in busoff.
1
The CAN controller is in busoff state.
-
reserved
BOFF
-
Description
Busoff status
27.6.1.3 CAN error counter
Table 396. CAN error counter (EC, address 0x400F 0008) bit description
Bit
Symbol
7:0
TEC7_0
Value Description
Transmit error counter
Reset
value
Access
0
RO
-
RO
-
RO
-
-
Current value of the transmit error counter
(maximum value 255)
14:8
REC6_0
Receive error counter
Current value of the receive error counter
(maximum value 127).
15
RP
31:16 -
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Receive error passive
0
Below error level. The receive counter is below
the error passive level.
1
At error level. The receive counter has reached
the error passive level as defined in the CAN2.0
specification.
-
Reserved
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27.6.1.4 CAN bit timing register
Hardware interprets the value programmed into the bits in this register as the bit value + 1.
Table 397. CAN bit timing register (BT, address 0x400F 000C) bit description
Bit
Symbol
Description
Reset
value
Access
5:0
BRP
Baud rate prescaler
000001
R/W
00
R/W
0011
R/W
010
R/W
-
-
The value by which the oscillator frequency is divided for
generating the bit time quanta. The bit time is built up from
a multiple of this quanta. Valid values for the Baud Rate
Prescaler are 0 to 63.
7:6
SJW
(Re)synchronization jump width
11:8
TSEG1
Time segment before the sample point
Valid programmed values are 0 to 3.
Valid values are 1 to 15.
14:12
TSEG2
Time segment after the sample point
Valid values are 0 to 7.
31:15
-
Reserved
For example, with a system clock set to of 8 MHz, the reset value of 0x2301 configures
the C_CAN for a bit rate of 500 kBit/s.
The registers are only writable if a configuration change is enabled in CANCTRL and the
controller is initialized by software (bits CCE and INIT in the CAN Control Register are
set).
For details on bit timing, see Section 27.7.5 and the Bosch C_CAN user’s manual,
revision 1.2.
Baud rate prescaler
The bit time quanta tq are determined by the BRP value:
tq = BRP / fsys
(fsys is the system clock to the C_CAN block).
Time segments 1 and 2
Time segments TSEG1 and TSEG2 determine the number of time quanta per bit time
and the location of the sample point:
tTSEG1/2 = tq  (TSEG1/2 + 1)
Synchronization jump width
To compensate for phase shifts between clock oscillators of different bus controllers, any
bus controller must re-synchronize on any relevant signal edge of the current
transmission. The synchronization jump width tSJW defines the maximum number of clock
cycles a certain bit period may be shortened or lengthened by one re-synchronization:
tSJW = tq  (SJW + 1)
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27.6.1.5 CAN interrupt register
Table 398. CAN interrupt register (INT, address 0x400F 0010) bit description
Bit
Symbol
Description
Reset
value
15:0
INTID
0x0000 = No interrupt is pending.
0
0x0001 - 0x0020 = Number of message object which
caused the interrupt.
0x0021 - 0x7FFF = Unused
0x8000 = Status interrupt
0x8001 - 0xFFFF = Unused
R
31:16
-
Reserved
-
-
Access
If several interrupts are pending, the CAN Interrupt Register will point to the pending
interrupt with the highest priority, disregarding their chronological order. An interrupt
remains pending until the CPU has cleared it. If INTID is different from 0x0000 and IE is
set, the interrupt line to the CPU is active. The interrupt line remains active until INTID is
back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
The Status Interrupt has the highest priority. Among the message interrupts, the Message
Object’ s interrupt priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object’s INTPND bit. The
StatusInterrupt is cleared by reading the Status Register.
27.6.1.6 CAN test register
Write access to the Test Register is enabled by setting bit Test in the CAN Control
Register.
The different test functions may be combined, but when TX[1:0]  “00” is selected, the
message transfer is disturbed.
Table 399. CAN test register (TEST, address 0x400F 0014) bit description
Bit
Symbol
Value
Description
1:0
-
-
Reserved
2
BASIC
3
4
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0
Disabled. Basic mode disabled.
1
Enabled. IF1 registers used as TX buffer, IF2
registers used as RX buffer.
0
Normal operation.
1
Silent mode. The module is in silent mode.
SILENT
Silent mode
LBACK
Loop back mode
0
Disabled. Loop back mode is disabled.
1
Enabled. Loop back mode is enabled.
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Reset
value
Access
-
0
R/W
0
R/W
0
R/W
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Table 399. CAN test register (TEST, address 0x400F 0014) bit description
Bit
Symbol
6:5
TX
7
31:8
Value
Reset
value
Access
Control of CAN_TXD pins
00
R/W
0
R
0x0
Controller. Level at the CAN_TXD pin is
controlled by the CAN controller. This is the
value at reset.
0x1
Sample point. The sample point can be
monitored at the CAN_TXD pin.
0x2
Low. CAN_TXD pin is driven LOW/dominant.
0x3
High. CAN_TXD pin is driven
HIGH/recessive.
RX
-
Description
Monitors the actual value of the CAN_RXD
pin.
0
Recessive. The CAN bus is recessive
(CAN_RXD = 1).
1
Dominant. The CAN bus is dominant
(CAN_RXD = 0).
R/W
-
27.6.1.7 CAN baud rate prescaler extension register
Table 400. CAN baud rate prescaler extension register (BRPE, address 0x400F 0018) bit
description
Bit
Symbol
Description
Reset
value
Access
3:0
BRPE
Baud rate prescaler extension
0x0000 R/W
By programming BRPE the Baud Rate Prescaler can be
extended to values up to 1023. Hardware interprets the
value as the value of BRPE (MSBs) and BRP (LSBs) plus
one. Allowed values are 0 to 15.
31:4
-
Reserved
-
-
27.6.2 Message interface registers
There are two sets of interface registers which are used to control the CPU access to the
Message RAM. The interface registers avoid conflicts between CPU access to the
Message RAM and CAN message reception and transmission by buffering the data to be
transferred. A complete Message Object (see Section 27.6.2.1) or parts of the Message
Object may be transferred between the Message RAM and the IFx Message Buffer
registers in one single transfer.
The function of the two interface register sets is identical (except for test mode Basic).
One set of registers may be used for data transfer to the Message RAM while the other
set of registers may be used for the data transfer from the Message RAM, allowing both
processes to be interrupted by each other.
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Each set of interface registers consists of message buffer registers controlled by their own
command registers. The command mask register specifies the direction of the data
transfer and which parts of a message object will be transferred. The command request
register is used to select a message object in the message RAM as target or source for
the transfer and to start the action specified in the command mask register.
Table 401. Message interface registers
IF1 register names
IF1 register set
IF2 register names
IF2 register set
IF1_CMDREQ
IF1 command request
IF2_CMDREQ
IF2 command request
IF1_CMDMASK
IF1 command mask
IF2_CMDMASK
IF2 command mask
IF1_MASK1
IF1 mask 1
IF2_MSK1
IF2 mask 1
IF1_MASK2
IF1 mask 2
IF2_MSK2
IF2 mask 2
IF1_ARB1
IF1 arbitration 1
IF2_ARB1
IF2 arbitration 1
IF1_ARB2
IF1 arbitration 2
IF2_ARB2
IF2 arbitration 2
IF1_MCTRL
IF1 message control
IF2_MCTRL
IF2 message control
IF1_DA1
IF1 data A1
IF2_DA1
IF2 data A1
IF1_DA2
IF1 data A2
IF2_DA2
IF2 data A2
IF1_DB1
IF1 data B1
IF2_DB1
IF2 data B1
IF1_DB2
IF1 data B2
IF2_DB2
IF2 data B2
There are 32 Message Objects in the Message RAM. To avoid conflicts between CPU
access to the Message RAM and CAN message reception and transmission, the CPU
cannot directly access the Message Objects. The message objects are accessed through
the IFx Interface Registers.
For details of message handling, see Section 27.7.3.
27.6.2.1 Message objects
A message object contains the information from the various bits in the message interface
registers. Table 402 below shows a schematic representation of the structure of the
message object. The bits of a message object and the respective interface register where
this bit is set or cleared are shown. For bit functions see the corresponding interface
register.
Table 402. Structure of a message object in the message RAM
UMASK
MSK[28:0]
IF1/2_MCTRL
RMTEN
TXRQST
MXTD
IF1/2_DA1
DATA1
EOB
NEWDAT
MSGLST
IF1/2_MSK1/2
MSGVAL
IF1/2_MCTRL
DATA0
MDIR
RXIE
INTPND
IF1/2_MCTRL
ID[28:0]
XTD
DIR
DLC3
DLC2
IF1/2_ARB1/2
DATA2
TXIE
DATA3
IF1/2_DA2
DATA4
DLC1
DLC0
IF1/2_MCTRL
DATA5
DATA6
IF1/2_DB1
DATA7
IF1/2_DB2
27.6.2.2 CAN message interface command request registers
A message transfer is started as soon as the CPU has written the message number to the
Command Request Register. With this write operation the BUSY bit is automatically set to
‘1’ and the signal CAN_WAIT_B is pulled LOW to notify the CPU that a transfer is in
progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer between the Interface
Register and the Message RAM has completed. The BUSY bit is set back to zero and the
signal CAN_WAIT_B is set back.
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Table 403. CAN message interface command request registers (IF1_CMDREQ, address
0x400F 0020 and IF2_CMDREQ, address 0x400F 0080) bit description
Bit
Symbol Value
Description
Reset
Value
Access
5:0
MN
Message number
0x01 - 0x20 = Valid message numbers. The
message object in the message RAM is selected
for data transfer.
0x00 = Not a valid message number. This value is
interpreted as 0x20.[1]
0x21 - 0x3F = Not a valid message number. This
value is interpreted as 0x01 - 0x1F.[1]
0x00
R/W
14:6
-
reserved
-
-
15
BUSY
BUSY flag
0
RO
-
-
31:16
[1]
-
0
Done. Set to zero by hardware when read/write
action to this Command request register has
finished.
1
Busy. Set to one by hardware when writing to this
Command request register.
-
Reserved
When a message number that is not valid is written into the Command request registers, the message
number will be transformed into a valid value and that message object will be transferred.
27.6.2.3 CAN message interface command mask registers
The control bits of the IFx Command Mask Register specify the transfer direction and
select which of the IFx Message Buffer Registers are source or target of the data
transfer.The functions of the register bits depend on the transfer direction (read or write)
which is selected in the WR_RD bit (bit 7) of this Command mask register.
Select the WR_RD to
one for the Write transfer direction (write to message RAM)
zero for the Read transfer direction (read from message RAM)
Table 404. CAN message interface command mask registers (IF1_CMDMSK_W, address
0x400F 0024 and IF2_CMDMSK_W, address 0x400F 0084) bit description for write
direction
Bit
Symbol
0
DATA_B
1
UM10736
User manual
Value Description
Access data bytes 4-7
0
Unchanged. Data bytes 4-7 unchanged.
1
Transfer. Transfer data bytes 4-7 to message
object.
DATA_A
Access data bytes 0-3
0
Unchanged. Data bytes 0-3 unchanged.
1
Transfer. Transfer data bytes 0-3 to message
object.
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Reset
value
Access
0
R/W
0
R/W
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Chapter 27: LPC15xx Controller Area Network C_CAN0
Table 404. CAN message interface command mask registers (IF1_CMDMSK_W, address
0x400F 0024 and IF2_CMDMSK_W, address 0x400F 0084) bit description for write
direction …continued
Bit
Symbol
2
TXRQST
Value Description
Access transmission request bit
0
Reset
value
Access
0
R/W
No transmission request. TXRQST bit
unchanged in IF1/2_MCTRL.
Remark: If a transmission is requested by
programming this bit, the TXRQST bit in the
CANIFn_MCTRL register is ignored.
3
CLRINTPND
4
CTRL
5
6
7
1
Request a transmission. Set the TXRQST bit
IF1/2_MCTRL.
-
This bit is ignored in the write direction.
0
R/W
Access control bits
0
R/W
0
R/W
0
R/W
0
R/W
0
-
0
Unchanged. Control bits unchanged.
1
Transfer. Transfer control bits to message
object
ARB
Access arbitration bits
0
Unchanged. Arbitration bits unchanged.
1
Transfer. Transfer Identifier, DIR, XTD, and
MSGVAL bits to message object.
MASK
Access mask bits
WR_RD
0
Unchanged. Mask bits unchanged.
1
Transfer. Transfer Identifier MSK + MDIR +
MXTD to message object.
1
Write transfer
Transfer data from the selected message
buffer registers to the message object
addressed by the command request register
CANIFn_CMDREQ.
31:8
-
-
reserved
Table 405. CAN message interface command mask registers (IF1_CMDMSK_R, address
0x400F 0024 and IF2_CMDMSK_R, address 0x400F 0084) bit description for read
direction
Bit
Symbol
0
DATA_B
1
UM10736
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Value Description
Access data bytes 4-7
0
Unchanged. Data bytes 4-7 unchanged.
1
Transfer. Transfer data bytes 4-7 to IFx
message buffer register.
DATA_A
Access data bytes 0-3
0
Unchanged. Data bytes 0-3 unchanged.
1
Transfer. Transfer data bytes 0-3 to IFx
message buffer.
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Reset
value
Access
0
R/W
0
R/W
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Chapter 27: LPC15xx Controller Area Network C_CAN0
Table 405. CAN message interface command mask registers (IF1_CMDMSK_R, address
0x400F 0024 and IF2_CMDMSK_R, address 0x400F 0084) bit description for read
direction …continued
Bit
Symbol
2
NEWDAT
Value Description
Access new data bit
0
Reset
value
Access
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
-
Unchanged. NEWDAT bit remains
unchanged.
Remark: A read access to a message object
can be combined with the reset of the control
bits INTPND and NEWDAT in IF1/2_MCTRL.
The values of these bits transferred to the IFx
Message Control Register always reflect the
status before resetting these bits.
1
3
4
5
6
7
CLRINTPND
Clear. Clear NEWDAT bit in the message
object.
Clear interrupt pending bit.
0
Unchanged. INTPND bit remains unchanged.
1
Clear. Clear INTPND bit in the message
object.
CTRL
Access control bits
0
Unchanged. Control bits unchanged.
1
Transfer. Transfer control bits to IFx message
buffer.
ARB
Access arbitration bits
0
Unchanged. Arbitration bits unchanged.
1
Transfer. Transfer Identifier, DIR, XTD, and
MSGVAL bits to IFx message buffer register.
MASK
Access mask bits
WR_RD
0
Unchanged. Mask bits unchanged.
1
Transfer. Transfer Identifier MSK + MDIR +
MXTD to IFx message buffer register.
0
Read transfer
Transfer data from the message object
addressed by the command request register
to the selected message buffer registers
CANIFn_CMDREQ.
31:8
-
-
reserved
27.6.2.4 IF1 and IF2 message buffer registers
The bits of the Message Buffer registers mirror the Message Objects in the Message
RAM.
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Chapter 27: LPC15xx Controller Area Network C_CAN0
27.6.2.4.1
CAN message interface mask 1 registers
Table 406. CAN message interface mask 1 registers (IF1_MSK1, address 0x400F 0028 and
IF2_MASK1, address 0x400F 0088) bit description
Bit
Symbol
15:0
MSK15_0
31:16
27.6.2.4.2
Value
-
Description
Reset
value
Access
Identifier mask [15:0]
0xFFFF
R/W
0
-
0
Match. The corresponding bit in the identifier of
the message cannot inhibit the match in the
acceptance filtering.
1
Mask. The corresponding identifier bit is used
for acceptance filtering.
-
Reserved
CAN message interface mask 2 registers
Table 407. CAN message interface mask 2 registers (IF1_MSK2, address 0x400F 002C and
IF2_MASK2, address 0x400F 008C) bit description
Bit
Symbol
12:0
MSK28_16
0
Match. The corresponding bit in the identifier of
the message cannot inhibit the match in the
acceptance filtering.
1
Mask. The corresponding identifier bit is used for
acceptance filtering.
Access
0xFFF
R/W
-
Reserved
1
-
14
MDIR
Mask message direction
1
R/W
1
R/W
0
-
31:16
User manual
Identifier mask [28:16]
Reset
value
13
15
UM10736
Value Description
0
Without DIR bit. The message direction bit (DIR)
has no effect on acceptance filtering.
1
With DIR bit. The message direction bit (DIR) is
used for acceptance filtering.
MXTD
-
Mask extend identifier
0
Without XTD. The extended identifier bit (XTD)
has no effect on acceptance filtering.
1
With XTD. The extended identifier bit (XTD) is
used for acceptance filtering.
-
Reserved
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27.6.2.4.3
CAN message interface arbitration 1 registers
Table 408. CAN message interface arbitration 1 registers (IF1_ARB1, address 0x400F 0030
and IF2_ARB1, address 0x400F 0090) bit description
Bit
Symbol
15:0
ID15_0
Description
Reset
value
Access
Message identifier [15:0]
0x00
R/W
0
-
29-bit identifier (extended frame)
11-bit identifier (standard frame). These bits are not used
for 11-bit identifiers.
31:16
-
Reserved
[1]
27.6.2.4.4
CAN message interface arbitration 2 registers
Table 409. CAN message interface arbitration 2 registers (IF1_ARB2, address 0x400F 0034 and IF2_ARB2, address
0x400F 0094) bit description
Bit
Symbol
Value Description
12:0
ID28_16
Message identifier
ID28_18
29-bit identifier (extended frame)
Reset
value
Access
0x00
R/W
0x00
R/W
0x00
R/W
0
R/W
0
-
11-bit identifier (standard frame). ID[17:16] are not used for 11-bit
identifiers.
13
DIR
Message direction
0
Receive.
On TXRQST, a Remote Frame with the identifier of this Message Object is
transmitted. On reception of a Data Frame with matching identifier, that
message is stored in this Message Object.
1
Transmit.
On TXRQST, the respective Message Object is transmitted as a Data
Frame. On reception of a Remote Frame with matching identifier, the
TXRQST bit of this Message Object is set (if RMTEN = one).
14
15
XTD
Extend identifier
0
Standard. The 11-bit standard identifier will be used for this message
object.
1
Extended. The 29-bit extended identifier will be used for this message
object.
MSGVAL
Message valid
Remark: The CPU must reset the MSGVAL bit of all unused Messages
Objects during the initialization before it resets bit INIT in the CAN Control
Register. This bit must also be reset before the identifier ID28:0, the control
bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the
Messages Object is no longer required.
31:16
-
0
Invalid. The message object is ignored by the message handler.
1
Valid. The message object is configured and should be considered by the
message handler.
-
Reserved
[1]
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27.6.2.4.5
CAN message interface message control registers
Table 410. CAN message interface message control registers (IF1_MCTRL, address 0x400F 0038 and IF2_MCTRL,
address 0x400F 0098) bit description
Bit
Symbol
3:0
DLC3_0
Value
Description
Reset
value
Access
Data length code 3:0
0000
R/W
Reserved
-
-
End of buffer
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Remark: The Data Length Code of a Message Object must be defined the
same as in all the corresponding objects with the same identifier at other
nodes. When the Message Handler stores a data frame, it will write the
DLC to the value given by the received message.
0000 - 1000 = Data frame has 0 - 8 data bytes.
1001 - 1111 = Data frame has 8 data bytes.
6:4
-
7
EOB
8
9
0
Not end of buffer. Message object belongs to a FIFO buffer and is not the
last message object of that FIFO buffer.
1
End of buffer. Single message object or last message object of a FIFO
buffer.
TXRQST
Transmit request
0
Not waiting. This message object is not waiting for transmission.
1
Waiting. The transmission of this message object is requested and is not
yet done
RMTEN
Remote enable
0
1
10
11
12
RXIE
TXRQST unchanged. At the reception of a remote frame, TXRQST is left
unchanged.
TXRQST set. At the reception of a remote frame, TXRQST is set.
Receive interrupt enable
0
INTPND unchanged. INTPND will be left unchanged after successful
reception of a frame.
1
INTPND set. INTPND will be set after successful reception of a frame.
TXIE
Transmit interrupt enable
0
INTPND unchanged. The INTPND bit will be left unchanged after a
successful transmission of a frame.
1
INTPND set. INTPND will be set after a successful transmission of a
frame.
UMASK
Use acceptance mask
Remark: If UMASK is set to 1, the message object’s mask bits have to be
programmed during initialization of the message object before MAGVAL is
set to 1.
13
0
Ignore. Mask ignored.
1
Use. Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering.
INTPND
UM10736
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Interrupt pending
0
Not pending. This message object is not the source of an interrupt.
1
Pending. This message object is the source of an interrupt. The Interrupt
Identifier in the Interrupt Register will point to this message object if there
is no other interrupt source with higher priority.
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Chapter 27: LPC15xx Controller Area Network C_CAN0
Table 410. CAN message interface message control registers (IF1_MCTRL, address 0x400F 0038 and IF2_MCTRL,
address 0x400F 0098) bit description …continued
Bit
Symbol
14
MSGLST
15
Value
Reset
value
Access
Message lost (only valid for message objects in the direction receive).
0
R/W
0
R/W
0
-
0
Not lost. No message lost since this bit was reset last by the CPU.
1
Lost. The Message Handler stored a new message into this object when
NEWDAT was still set, the CPU has lost a message.
0
No new data. No new data has been written into the data portion of this
message object by the message handler since this flag was cleared last by
the CPU.
1
New data. The message handler or the CPU has written new data into the
data portion of this message object.
-
Reserved
NEWDAT
31:16 -
Description
New data
27.6.2.4.6
CAN message interface data A1 registers
In a CAN Data Frame, DATA0 is the first, DATA7 (in CAN_IF1B2 AND CAN_IF2B2) is the
last byte to be transmitted or received. In CAN’s serial bit stream, the MSB of each byte
will be transmitted first.
Remark: Byte DATA0 is the first data byte shifted into the shift register of the CAN Core
during a reception, byte DATA7 is the last. When the Message Handler stores a Data
Frame, it will write all the eight data bytes into a Message Object. If the Data Length Code
is less than 8, the remaining bytes of the Message Object will be overwritten by non
specified values.
Table 411. CAN message interface data A1 registers (IF1_DA1, address 0x400F 003C and
IF2_DA1, address 0x400F 009C) bit description
27.6.2.4.7
Bit
Symbol Description
Reset value Access
7:0
DATA0
Data byte 0
0x00
R/W
15:8
DATA1
Data byte 1
0x00
R/W
31:16
-
Reserved
-
-
CAN message interface data A2 registers
Table 412. CAN message interface data A2 registers (IF1_DA2, address 0x400F 0040 and
IF2_DA2, address 0x400F 00A0) bit description
UM10736
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Bit
Symbol Description
Reset value Access
7:0
DATA2
Data byte 2
0x00
R/W
15:8
DATA3
Data byte 3
0x00
R/W
31:16
-
Reserved
-
-
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27.6.2.4.8
CAN message interface data B1 registers
Table 413. CAN message interface data B1 registers (IF1_DB1, address 0x400F 0044 and
IF2_DB1, address 0x400F 00A4) bit description
27.6.2.4.9
Bit
Symbol Description
Reset value Access
7:0
DATA4
Data byte 4
0x00
R/W
15:8
DATA5
Data byte 5
0x00
R/W
31:16
-
Reserved
-
-
CAN message interface data B2 registers
Table 414. CAN message interface data B2 registers (IF1_DB2, address 0x400F 0048 and
IF2_DB2, address 0x400F 00A8) bit description
Bit
Symbol Description
Reset value Access
7:0
DATA6
Data byte 6
0x00
R/W
15:8
DATA7
Data byte 7
0x00
R/W
31:16
-
Reserved
-
-
27.6.3 Message handler registers
All Message Handler registers are read-only. Their contents (TXRQST, NEWDAT,
INTPND, and MSGVAL bits of each Message Object and the Interrupt Identifier) is status
information provided by the Message Handler FSM.
27.6.3.1 CAN transmission request 1 register
This register contains the TXRQST bits of message objects 1 to 16. By reading out the
TXRQST bits, the CPU can check for which Message Object a Transmission Request is
pending. The TXRQST bit of a specific Message Object can be set/reset by the CPU via
the IFx Message Interface Registers or by the Message Handler after reception of a
Remote Frame or after a successful transmission.
Table 415. CAN transmission request 1 register (TXREQ1, address 0x400F 0100) bit
description
Bit
Symbol
Description
15:0
TXRQST16_1
Transmission request bit of message objects 16 to 1. 0x00
0 = This message object is not waiting for
transmission.
1 = The transmission of this message object is
requested and not yet done.
R
Reserved
-
31:16 -
Reset
value
-
Access
27.6.3.2 CAN transmission request 2 register
This register contains the TXRQST bits of message objects 32 to 17. By reading out the
TXRQST bits, the CPU can check for which Message Object a Transmission Request is
pending. The TXRQST bit of a specific Message Object can be set/reset by the CPU via
the IFx Message Interface Registers or by the Message Handler after reception of a
Remote Frame or after a successful transmission.
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Table 416. CAN transmission request 2 register (TXREQ2, address 0x400F 0104) bit
description
Bit
Symbol
Description
15:0
TXRQST32_17
Transmission request bit of message objects 32 to 17. 0x00
0 = This message object is not waiting for
transmission.
1 = The transmission of this message object is
requested and not yet done.
R
Reserved
-
31:16 -
Reset Access
value
-
27.6.3.3 CAN new data 1 register
This register contains the NEWDAT bits of message objects 16 to 1. By reading out the
NEWDAT bits, the CPU can check for which Message Object the data portion was
updated. The NEWDAT bit of a specific Message Object can be set/reset by the CPU via
the IFx Message Interface Registers or by the Message Handler after reception of a Data
Frame or after a successful transmission.
Table 417. CAN new data 1 register (ND1, address 0x400F 0120) bit description
Bit
Symbol
Description
Reset Access
value
15:0
NEWDAT16_1
New data bits of message objects 16 to 1.
0x00
0 = No new data has been written into the data portion
of this Message Object by the Message Handler since
last time this flag was cleared by the CPU.
1 = The Message Handler or the CPU has written new
data into the data portion of this Message Object.
R
31:16
-
Reserved
-
-
27.6.3.4 CAN new data 2 register
This register contains the NEWDAT bits of message objects 32 to 17. By reading out the
NEWDAT bits, the CPU can check for which Message Object the data portion was
updated. The NEWDAT bit of a specific Message Object can be set/reset by the CPU via
the IFx Message Interface Registers or by the Message Handler after reception of a Data
Frame or after a successful transmission.
Table 418. CAN new data 2 register (ND2, address 0x400F 0124) bit description
UM10736
User manual
Bit
Symbol
Description
Reset Access
value
15:0
NEWDAT32_17
New data bits of message objects 32 to 17.
0 = No new data has been written into the data
portion of this Message Object by the Message
Handler since last time this flag was cleared by the
CPU.
1 = The Message Handler or the CPU has written
new data into the data portion of this Message
Object.
0x00
R
31:16
-
Reserved
-
-
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27.6.3.5 CAN interrupt pending 1 register
This register contains the INTPND bits of message objects 16 to 1. By reading out the
INTPND bits, the CPU can check for which Message Object an interrupt is pending. The
INTPND bit of a specific Message Object can be set/reset by the CPU via the IFx
Message Interface Registers or by the Message Handler after reception or after a
successful transmission of a frame. This will also affect the value of INTPND in the
Interrupt Register.
Table 419. CAN interrupt pending 1 register (IR1, address 0x400F 0140) bit description
Bit
Symbol
Description
Reset
value
Access
15:0
INTPND16_1
Interrupt pending bits of message objects 16 to 1.
0 = This message object is ignored by the message
handler.
1 = This message object is the source of an interrupt.
0x00
R
Reserved
-
-
31:16 -
27.6.3.6 CAN interrupt pending 2 register
This register contains the INTPND bits of message objects 32 to 17. By reading out the
INTPND bits, the CPU can check for which Message Object an interrupt is pending. The
INTPND bit of a specific Message Object can be set/reset by the CPU via the IFx
Message Interface Registers or by the Message Handler after reception or after a
successful transmission of a frame. This will also affect the value of INTPND in the
Interrupt Register.
Table 420. CAN interrupt pending 2 register (IR2, addresses 0x400F 0144) bit description
Bit
Symbol
Description
15:0
INTPND32_17
Interrupt pending bits of message objects 32 to 17.
0x00
0 = This message object is ignored by the message
handler.
1 = This message object is the source of an interrupt.
R
Reserved
-
31:16 -
Reset
value
-
Access
27.6.3.7 CAN message valid 1 register
This register contains the MSGVAL bits of message objects 16 to 1. By reading out the
MSGVAL bits, the CPU can check which Message Object is valid. The MSGVAL bit of a
specific Message Object can be set/reset by the CPU via the IFx Message Interface
Registers.
Table 421. CAN message valid 1 register (MSGV1, addresses 0x400F 0160) bit description
Bit
Symbol
Description
15:0
MSGVAL16_1
Message valid bits of message objects 16 to 1.
0x00
0 = This message object is ignored by the message
handler.
1 = This message object is configured and should be
considered by the message handler.
R
Reserved
-
31:16 -
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value
-
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27.6.3.8 CAN message valid 2 register
This register contains the MSGVAL bits of message objects 32 to 17. By reading out the
MSGVAL bits, the CPU can check which Message Object is valid. The MSGVAL bit of a
specific Message Object can be set/reset by the CPU via the IFx Message Interface
Registers.
Table 422. CAN message valid 2 register (MSGV2, address 0x400F 0164) bit description
Bit
Symbol
Description
15:0
MSGVAL32_17 Message valid bits of message objects 32 to 17.
R
0 = This message object is ignored by the message
handler.
1 = This message object is configured and should
be considered by the message handler.
31:16 -
Reserved
Access
-
Reset
value
0x00
-
27.6.4 CAN timing register
27.6.4.1 CAN clock divider register
This register determines the CAN clock signal. The CAN_CLK is derived from the
peripheral clock PCLK divided by the values in this register. Also see Section 27.3 for
details on how the C_CAN clock is connected.
Table 423. CAN clock divider register (CLKDIV, address 0x400F 0180) bit description
Bit
Symbol
Description
3:0
CLKDIVVAL Clock divider value. CAN_CLK =
PCLK/(CLKDIVVAL +1)
Reset
value
Access
1
R/W
-
-
0000: CAN_CLK = PCLK divided by 1.
0001: CAN_CLK = PCLK divided by 2.
0010: CAN_CLK = PCLK divided by 3
0011: CAN_CLK = PCLK divided by 4.
...
1111: CAN_CLK = PCLK divided by 16.
31:4
-
reserved
27.7 Functional description
27.7.1 C_CAN controller state after reset
After a hardware reset, the registers hold the values described in Table 393. Additionally,
the busoff state is reset and the output CAN_TXD is set to recessive (HIGH). The value
0x0001 (INIT = ‘1’) in the CAN Control Register enables the software initialization. The
CAN controller does not communicate with the CAN bus until the CPU resets INIT to ‘0’.
The data stored in the message RAM is not affected by a hardware reset. After power-on,
the contents of the message RAM is undefined.
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27.7.2 C_CAN operating modes
27.7.2.1 Software initialization
The software initialization is started by setting the bit INIT in the CAN Control Register,
either by software or by a hardware reset, or by entering the busoff state.
During software initialization (INIT bit is set), the following conditions are present:
•
•
•
•
•
All message transfer from and to the CAN bus is stopped.
The status of the CAN output CAN_TXD is recessive (HIGH).
The EC counters are unchanged.
The configuration registers are unchanged.
Access to the bit timing register and the BRP extension register is enabled if the CCE
bit in the CAN control register is also set.
To initialize the CAN controller, software has to set up the bit timing register and each
message object. If a message object is not needed, it is sufficient to set its MSGVAL bit to
not valid. Otherwise, the whole message object has to be initialized.
Resetting the INIT bit finishes the software initialization. Afterwards the Bit Stream
Processor BSP synchronizes itself to the data transfer on the CAN bus by waiting for the
occurrence of a sequence of 11 consecutive recessive bits (Bus Idle) before it can take
part in bus activities and starts the message transfer.
Remark: The initialization of the Message Objects is independent of INIT and also can be
done on the fly, but the Message Objects should all be configured to particular identifiers
or set to not valid during software initialization before the BSP starts the message transfer.
To change the configuration of a Message Object during normal operation, the CPU has to
start by setting the MSGVAL bit to not valid. When the configuration is completed,
MSAGVALis set to valid again.
27.7.2.2 CAN message transfer
Once the CAN controller is initialized and INIT is reset to zero, the CAN core synchronizes
itself to the CAN bus and starts the message transfer.
Received messages are stored into their appropriate Message Objects if they pass the
Message Handler’s acceptance filtering. The whole message including all arbitration bits,
DLC and eight data bytes is stored into the Message Object. If the Identifier Mask is used,
the arbitration bits which are masked to “don’t care” may be overwritten in the Message
Object.
The CPU may read or write each message any time via the Interface Registers. The
Message Handler guarantees data consistency in case of concurrent accesses.
Messages to be transmitted are updated by the CPU. If a permanent Message Object
(arbitration and control bits set up during configuration) exists for the message, only the
data bytes are updated and then TXRQUT bit with NEWDAT bit are set to start the
transmission. If several transmit messages are assigned to the same Message Object
(when the number of Message Objects is not sufficient), the whole Message Object has to
be configured before the transmission of this message is requested.
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The transmission of any number of Message Objects may be requested at the same time,
and they are transmitted subsequently according to their internal priority. Messages may
be updated or set to not valid any time, even when their requested transmission is still
pending. The old data will be discarded when a message is updated before its pending
transmission has started.
Depending on the configuration of the Message Object, the transmission of a message
may be requested autonomously by the reception of a remote frame with a matching
identifier.
27.7.2.3 Disabled Automatic Retransmission (DAR)
According to the CAN Specification (ISO11898, 6.3.3 Recovery Management), the CAN
controller provides means for automatic retransmission of frames that have lost arbitration
or that have been disturbed by errors during transmission. The frame transmission service
will not be confirmed to the user before the transmission is successfully completed. By
default, the automatic retransmission on lost arbitration or error is enabled. It can be
disabled to enable the CAN controller to work within a Time Triggered CAN (TTCAN, see
ISO11898-1) environment.
The Disable Automatic Retransmission mode is enabled by programming bit DAR in the
CAN Control Register to one. In this operation mode the programmer has to consider the
different behavior of bits TXRQST and NEWDAT in the Control Registers of the Message
Buffers:
• When a transmission starts, bit TXRQST of the respective Message Buffer is reset
while bit NEWDAT remains set.
• When the transmission completed successfully, bit NEWDAT is reset.
• When a transmission failed (lost arbitration or error), bit NEWDAT remains set. To
restart the transmission, the CPU has to set TXRQST back to one.
27.7.2.4 Test modes
The Test mode is entered by setting bit TEST in the CAN Control Register to one. In Test
mode the bits TX1, TX0, LBACK, SILENT, and BASIC in the Test Register are writable. Bit
RX monitors the state of pins RD0,1 and therefore is only readable. All Test register
functions are disabled when bit TEST is reset to zero.
27.7.2.4.1
Silent mode
The CAN core can be set in Silent mode by programming the Test register bit SILENT to
one.
In Silent Mode, the CAN controller is able to receive valid data frames and valid remote
frames, but it sends only recessive bits on the CAN bus, and it cannot start a
transmission. If the CAN Core is required to send a dominant bit (ACK bit, overload flag,
active error flag), the bit is rerouted internally so that the CAN Core monitors this dominant
bit, although the CAN bus may remain in recessive state. The Silent mode can be used to
analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits
(Acknowledge Bits, Error Frames).
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Chapter 27: LPC15xx Controller Area Network C_CAN0
&$1B7;' &$1B5;'
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Fig 78. CAN core in Silent mode
27.7.2.4.2
Loop-back mode
The CAN Core can be set in Loop-back mode by programming the Test Register bit
LBACK to one. In Loop-back Mode, the CAN Core treats its own transmitted messages as
received messages and stores them (if they pass acceptance filtering) into a Receive
Buffer.
This mode is provided for self-test functions. To be independent from external stimulation,
the CAN Core ignores acknowledge errors (recessive bit sampled in the acknowledge slot
of a data/remote frame) in Loop-back mode. In this mode the CAN core performs an
internal feedback from its CAN_TXD output to its CAN_RXD input. The actual value of the
CAN_RXD input pin is disregarded by the CAN Core. The transmitted messages can be
monitored at the CAN_TXD pin.
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Fig 79. CAN core in Loop-back mode
27.7.2.4.3
Loop-back mode combined with Silent mode
It is also possible to combine Loop-back mode and Silent mode by programming bits
LBACK and SILENT to one at the same time. This mode can be used for a “Hot Selftest”,
meaning the C_CAN can be tested without affecting a running CAN system connected to
the pins CAN_TXD and CAN_RXD. In this mode the CAN_RXD pin is disconnected from
the CAN Core and the CAN_TXD pin is held recessive.
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Chapter 27: LPC15xx Controller Area Network C_CAN0
&$1B7;' &$1B5;'
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Fig 80. CAN core in Loop-back mode combined with Silent mode
27.7.2.4.4
Basic mode
The CAN Core can be set in Basic mode by programming the Test Register bit BASIC to
one. In this mode the CAN controller runs without the Message RAM.
The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the
IF1 Registers is requested by writing the BUSY bit of the IF1 Command Request Register
to ‘1’. The IF1 Registers are locked while the BUSY bit is set. The BUSY bit indicates that
the transmission is pending.
As soon the CAN bus is idle, the IF1 Registers are loaded into the shift register of the CAN
Core and the transmission is started. When the transmission has completed, the BUSY bit
is reset and the locked IF1 Registers are released.
A pending transmission can be aborted at any time by resetting the BUSY bit in the IF1
Command Request Register while the IF1 Registers are locked. If the CPU has reset the
BUSY bit, a possible retransmission in case of lost arbitration or in case of an error is
disabled.
The IF2 Registers are used as Receive Buffer. After the reception of a message the
contents of the shift register is stored into the IF2 Registers, without any acceptance
filtering.
Additionally, the actual contents of the shift register can be monitored during the message
transfer. Each time a read Message Object is initiated by writing the BUSY bit of the IF2
Command Request Register to ‘1’, the contents of the shift register is stored into the IF2
Registers.
In Basic mode the evaluation of all Message Object related control and status bits and of
the control bits of the IFx Command Mask Registers is turned off. The message number of
the Command request registers is not evaluated. The NEWDAT and MSGLST bits of the
IF2 Message Control Register retain their function, DLC3-0 will show the received DLC,
the other control bits will be read as ‘0’.
In Basic mode the ready output CAN_WAIT_B is disabled (always ‘1’)
27.7.2.4.5
Software control of pin CAN_TXD
Four output functions are available for the CAN transmit pin CAN_TXD:
1. serial data output (default).
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2. drives CAN sample point signal to monitor the CAN controller’s timing.
3. drives recessive constant value.
4. drives dominant constant value.
The last two functions, combined with the readable CAN receive pin CAN_RXD, can be
used to check the CAN bus’ physical layer.
The output mode of pin CAN_TXD is selected by programming the Test Register bits TX1
and TX0 as described Section 27.6.1.6.
Remark: The three test functions for pin CAN_TXD interfere with all CAN protocol
functions. The CAN_TXD pin must be left in its default function when CAN message
transfer or any of the test modes Loo-back mode, Silent mode, or Basic mode are
selected.
27.7.3 CAN message handler
The Message handler controls the data transfer between the Rx/Tx Shift Register of the
CAN Core, the Message RAM and the IFx Registers, see Figure 81.
The message handler controls the following functions:
•
•
•
•
•
•
•
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Data Transfer between IFx Registers and the Message RAM
Data Transfer from Shift Register to the Message RAM
Data Transfer from Message RAM to Shift Register
Data Transfer from Shift Register to the Acceptance Filtering unit
Scanning of Message RAM for a matching Message Object
Handling of TXRQST flags
Handling of interrupts
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Fig 81. Block diagram of a message object transfer
27.7.3.1 Management of message objects
The configuration of the Message Objects in the Message RAM will (with the exception of
the bits MSGVAL, NEWDAT, INTPND, and TXRQST) is not be affected by resetting the
chip. All the Message Objects must be initialized by the CPU or they must be set to not
valid (MSGVAL = ‘0’).The bit timing must be configured before the CPU clears the INIT bit
in the CAN Control Register.
The configuration of a Message Object is done by programming Mask, Arbitration, Control
and Data field of one of the two interface register sets to the desired values. By writing to
the corresponding IFx Command Request Register, the IFx Message Buffer Registers are
loaded into the addressed Message Object in the Message RAM.
When the INIT bit in the CAN Control Register is cleared, the CAN Protocol Controller
state machine of the CAN core and the Message Handler State Machine control the CAN
controller’s internal data flow. Received messages that pass the acceptance filtering are
stored into the Message RAM, and messages with pending transmission request are
loaded into the CAN core’s shift register and are transmitted via the CAN bus.
The CPU reads received messages and updates messages to be transmitted via the IFx
Interface Registers. Depending on the configuration, the CPU is interrupted on certain
CAN message and CAN error events.
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27.7.3.2 Data Transfer between IFx Registers and the Message RAM
When the CPU initiates a data transfer between the IFx Registers and Message RAM, the
Message Handler sets the BUSY bit in the respective Command Register to ‘1’. After the
transfer has completed, the BUSY bit is set back to ‘0’.
The Command Mask Register specifies whether a complete Message Object or only parts
of it will be transferred. Due to the structure of the Message RAM it is not possible to write
single bits/bytes of one Message Object. Software must always write a complete Message
Object into the Message RAM. Therefore the data transfer from the IFx Registers to the
Message RAM requires a read-modify-write cycle:
1. Read the parts of the message object that are not to be changed from the message
RAM using the command mask register.
– After the partial read of a Message Object, the Message Buffer Registers that are
not selected in the Command Mask Register will be left unchanged.
2. Write the complete contents of the message buffer registers into the message object.
– After the partial write of a Message Object, the Message Buffer Registers that are
not selected in the Command Mask Register will set to the actual contents of the
selected Message Object.
27.7.3.3 Transmission of messages between the shift registers in the CAN core and
the Message buffer
If the shift register of the CAN Core cell is ready for loading and if there is no data transfer
between the IFx Registers and Message RAM, the MSGVAL bits in the Message Valid
Register TXRQST bits in the Transmission Request Register are evaluated. The valid
Message Object with the highest priority pending transmission request is loaded into the
shift register by the Message Handler and the transmission is started. The Message
Object’s NEWDAT bit is reset.
After a successful transmission and if no new data was written to the Message Object
(NEWDAT = ‘0’) since the start of the transmission, the TXRQST bit will be reset. If TXIE
is set, INTPND will be set after a successful transmission. If the CAN controller has lost
the arbitration or if an error occurred during the transmission, the message will be
retransmitted as soon as the CAN bus is free again. If meanwhile the transmission of a
message with higher priority has been requested, the messages will be transmitted in the
order of their priority.
27.7.3.4 Acceptance filtering of received messages
When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming
message is completely shifted into the Rx/Tx Shift Register of the CAN Core, the
Message Handler state machine starts the scanning of the Message RAM for a matching
valid Message Object.
To scan the Message RAM for a matching Message Object, the Acceptance Filtering unit
is loaded with the arbitration bits from the CAN Core shift register. Then the arbitration and
mask fields (including MSGVAL, UMASK, NEWDAT, and EOB) of Message Object 1 are
loaded into the Acceptance Filtering unit and compared with the arbitration field from the
shift register. This is repeated with each following Message Object until a matching
Message Object is found or until the end of the Message RAM is reached.
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If a match occurs, the scanning is stopped and the Message Handler state machine
proceeds depending on the type of frame (Data Frame or Remote Frame) received.
27.7.3.4.1
Reception of a data frame
The Message Handler state machine stores the message from the CAN Core shift register
into the respective Message Object in the Message RAM. The data bytes, all arbitration
bits, and the Data Length Code are stored into the corresponding Message Object. This is
implemented to keep the data bytes connected with the identifier even if arbitration mask
registers are used.
The NEWDAT bit is set to indicate that new data (not yet seen by the CPU) has been
received. The CPU/software should reset NEWDAT when it reads the Message Object. If
at the time of the reception the NEWDAT bit was already set, MSGLST is set to indicate
that the previous data (supposedly not seen by the CPU) is lost. If the RxIE bit is set, the
INTPND bit is also set, causing the Interrupt Register to point to this Message Object.
The TXRQST bit of this Message Object is reset to prevent the transmission of a Remote
Frame, while the requested Data Frame has just been received.
27.7.3.4.2
Reception of a remote frame
When a Remote Frame is received, three different configurations of the matching
Message Object have to be considered:
1. DIR = ‘1’ (direction = transmit), RMTEN = ‘1’, UMASK = ‘1’ or’0’
On the reception of a matching Remote Frame, the TXRQST bit of this Message
Object is set. The rest of the Message Object remains unchanged.
2. DIR = ‘1’ (direction = transmit), RMTEN = ‘0’, UMASK = ’0’
On the reception of a matching Remote Frame, the TXRQST bit of this Message
Object remains unchanged; the Remote Frame is ignored.
3. DIR = ‘1’ (direction = transmit), RMTEN = ‘0’, UMASK = ’1’
On the reception of a matching Remote Frame, the TXRQST bit of this Message
Object is reset. The arbitration and control field (Identifier + IDE + RTR + DLC) from
the shift register is stored into the Message Object in the Message RAM, and the
NEWDAT bit of this Message Object is set. The data field of the Message Object
remains unchanged; the Remote Frame is treated similar to a received Data Frame.
27.7.3.5 Receive/transmit priority
The receive/transmit priority for the Message Objects is attached to the message number.
Message Object 1 has the highest priority, while Message Object 32 has the lowest
priority. If more than one transmission request is pending, they are serviced due to the
priority of the corresponding Message Object.
27.7.3.6 Configuration of a transmit object
Table 424 shows how a transmit object should be initialized by software (see also
Table 402):
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Table 424. Initialization of a transmit object
MSGVAL
1
MSGLST
0
Arbitration
bits
Data bits
Mask bits
EOB
DIR
NEWDAT
application
dependent
application
dependent
application
dependent
1
1
0
RXIE
TXIE
INTPND
RMTEN
TXRQST
0
application
dependent
0
application
dependent
0
The Arbitration Registers (ID28:0 and XTD bit) are given by the application. They define
the identifier and the type of the outgoing message. If an 11-bit Identifier (“Standard
Frame”) is used, it is programmed to ID28. In this case ID18, ID17 to ID0 can be
disregarded.
If the TXIE bit is set, the INTPND bit will be set after a successful transmission of the
Message Object.
If the RMTEN bit is set, a matching received Remote Frame will cause the TXRQST bit to
be set, and the Remote Frame will autonomously be answered by a Data Frame.
The Data Registers (DLC3:0, Data0:7) are given by the application. TXRQST and RMTEN
may not be set before the data is valid.
The Mask Registers (Msk28-0, UMASK, MXTD, and MDIR bits) may be used
(UMASK=’1’) to allow groups of Remote Frames with similar identifiers to set the TXRQST
bit. For details see Section 27.7.3.4.2. The DIR bit should not be masked.
27.7.3.7 Updating a transmit object
The CPU may update the data bytes of a Transmit Object any time via the IFx Interface
registers. Neither MSGVAL nor TXRQST have to be reset before the update.
Even if only a part of the data bytes are to be updated, all four bytes of the corresponding
IFx Data A Register or IFx Data B Register have to be valid before the content of that
register is transferred to the Message Object. Either the CPU has to write all four bytes
into the IFx Data Register or the Message Object is transferred to the IFx Data Register
before the CPU writes the new data bytes.
When only the (eight) data bytes are updated, first 0x0087 is written to the Command
Mask Register. Then the number of the Message Object is written to the Command
Request Register, concurrently updating the data bytes and setting TXRQST.
To prevent the reset of TXRQST at the end of a transmission that may already be in
progress while the data is updated, NEWDAT has to be set together with TXRQST. For
details see Section 27.7.3.3.
When NEWDAT is set together with TXRQST, NEWDAT will be reset as soon as the new
transmission has started.
27.7.3.8 Configuration of a receive object
Table 425 shows how a receive object should be initialized by software (see also
Table 402)
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Table 425. Initialization of a receive object
MSGVAL
1
MSGLST
0
Arbitration
bits
Data bits
Mask bits
EOB
DIR
NEWDAT
application
dependent
application
dependent
application
dependent
1
0
0
RXIE
TXIE
INTPND
RMTEN
TXRQST
application
dependent
0
0
0
0
The Arbitration Registers (ID28-0 and XTD bit) are given by the application. They define
the identifier and type of accepted received messages. If an 11-bit Identifier (“Standard
Frame”) is used, it is programmed to ID28 to ID18. ID17 to ID0 can then be disregarded.
When a Data Frame with an 11-bit Identifier is received, ID17 to ID0 will be set to ‘0’.
If the RxIE bit is set, the INTPND bit will be set when a received Data Frame is accepted
and stored in the Message Object.
The Data Length Code (DLC[3:0] is given by the application. When the Message Handler
stores a Data Frame in the Message Object, it will store the received Data Length Code
and eight data bytes. If the Data Length Code is less than 8, the remaining bytes of the
Message Object will be overwritten by non specified values.
The Mask Registers (Msk[28:0], UMASK, MXTD, and MDIR bits) may be used
(UMASK=’1’) to allow groups of Data Frames with similar identifiers to be accepted. For
details see section Section 27.7.3.4.1. The DIR bit should not be masked in typical
applications.
27.7.3.9 Handling of received messages
The CPU may read a received message any time via the IFx Interface registers. The data
consistency is guaranteed by the Message Handler state machine.
To transfer the entire received message from message RAM into the message buffer,
software must write first 0x007F to the Command Mask Register and then the number of
the Message Object to the Command Request Register. Additionally, the bits NEWDAT
and INTPND are cleared in the Message RAM (not in the Message Buffer).
If the Message Object uses masks for acceptance filtering, the arbitration bits show which
of the matching messages has been received.
The actual value of NEWDAT shows whether a new message has been received since
last time this Message Object was read. The actual value of MSGLST shows whether
more than one message has been received since last time this Message Object was read.
MSGLST will not be automatically reset.
Using a Remote Frame, the CPU may request another CAN node to provide new data for
a receive object. Setting the TXRQST bit of a receive object will cause the transmission of
a Remote Frame with the receive object’s identifier. This Remote Frame triggers the other
CAN node to start the transmission of the matching Data Frame. If the matching Data
Frame is received before the Remote Frame could be transmitted, the TXRQST bit is
automatically reset.
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27.7.3.10 Configuration of a FIFO buffer
With the exception of the EOB bit, the configuration of Receive Objects belonging to a
FIFO Buffer is the same as the configuration of a (single) Receive Object, see section
Section 27.7.3.8.
To concatenate two or more Message Objects into a FIFO Buffer, the identifiers and
masks (if used) of these Message Objects have to be programmed to matching values.
Due to the implicit priority of the Message Objects, the Message Object with the lowest
number will be the first Message Object of the FIFO Buffer. The EOB bit of all Message
Objects of a FIFO Buffer except the last have to be programmed to zero. The EOB bits of
the last Message Object of a FIFO Buffer is set to one, configuring it as the End of the
Block.
27.7.3.10.1
Reception of messages with FIFO buffers
Received messages with identifiers matching to a FIFO Buffer are stored into a Message
Object of this FIFO Buffer starting with the Message Object with the lowest message
number.
When a message is stored into a Message Object of a FIFO Buffer the NEWDAT bit of this
Message Object is set. By setting NEWDAT while EOB is zero the Message Object is
locked for further write accesses by the Message Handler until the CPU has written the
NEWDAT bit back to zero.
Messages are stored into a FIFO Buffer until the last Message Object of this FIFO Buffer
is reached. If none of the preceding Message Objects is released by writing NEWDAT to
zero, all further messages for this FIFO Buffer will be written into the last Message Object
of the FIFO Buffer and therefore overwrite previous messages.
27.7.3.10.2
Reading from a FIFO buffer
When the CPU transfers the contents of Message Object to the IFx Message Buffer
registers by writing its number to the IFx Command Request Register, bits NEWDAT and
INTPND in the corresponding Command Mask Register should be reset to zero
(TXRQST/NEWDAT = ‘1’ and ClrINTPND = ‘1’). The values of these bits in the Message
Control Register always reflect the status before resetting the bits.
To assure the correct function of a FIFO Buffer, the CPU should read out the Message
Objects starting at the FIFO Object with the lowest message number.
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Fig 82. Reading a message from the FIFO buffer to the message buffer
27.7.4 Interrupt handling
If several interrupts are pending, the CAN Interrupt Register will point to the pending
interrupt with the highest priority, disregarding their chronological order. An interrupt
remains pending until the CPU has cleared it.
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Chapter 27: LPC15xx Controller Area Network C_CAN0
The Status Interrupt has the highest priority. Among the message interrupts, the Message
Object’s interrupt priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object’s INTPND bit. The Status
Interrupt is cleared by reading the Status Register.
The interrupt identifier INTID in the Interrupt Register indicates the cause of the interrupt.
When no interrupt is pending, the register will hold the value zero. If the value of the
Interrupt Register is different from zero, then there is an interrupt pending and, if IE is set,
the interrupt line to the CPU, IRQ_B, is active. The interrupt line remains active until the
Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is
reset.
The value 0x8000 indicates that an interrupt is pending because the CAN Core has
updated (not necessarily changed) the Status Register (Error Interrupt or Status Interrupt).
This interrupt has the highest priority. The CPU can update (reset) the status bits RXOK,
TXOK and LEC, but a write access of the CPU to the Status Register can never generate
or reset an interrupt.
All other values indicate that the source of the interrupt is one of the Message Objects
where INTID points to the pending message interrupt with the highest interrupt priority.
The CPU controls whether a change of the Status Register may cause an interrupt (bits
EIE and SIE in the CAN Control Register) and whether the interrupt line becomes active
when the Interrupt Register is different from zero (bit IE in the CAN Control Register). The
Interrupt Register will be updated even when IE is reset.
The CPU has two possibilities to follow the source of a message interrupt:
• Software can follow the INTID in the Interrupt Register.
• Software can poll the interrupt pending register, see Section 27.6.3.5.
An interrupt service routine reading the message that is the source of the interrupt may
read the message and reset the Message Object’s INTPND at the same time (bit
ClrINTPND in the Command Mask Register). When INTPND is cleared, the Interrupt
Register will point to the next Message Object with a pending interrupt.
27.7.5 Bit timing
Even if minor errors in the configuration of the CAN bit timing do not result in immediate
failure, the performance of a CAN network can be reduced significantly. In many cases,
the CAN bit synchronization will amend a faulty configuration of the CAN bit timing to such
a degree that only occasionally an error frame is generated. In the case of arbitration
however, when two or more CAN nodes simultaneously try to transmit a frame, a
misplaced sample point may cause one of the transmitters to become error passive.
The analysis of such sporadic errors requires a detailed knowledge of the CAN bit
synchronization inside a CAN node and of the CAN nodes’ interaction on the CAN bus.
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Chapter 27: LPC15xx Controller Area Network C_CAN0
27.7.5.1 Bit time and bit rate
CAN supports bit rates in the range of lower than 1 kBit/s up to 1000 kBit/s. Each member
of the CAN network has its own clock generator, usually a quartz oscillator. The timing
parameter of the bit time (i.e. the reciprocal of the bit rate) can be configured individually
for each CAN node, creating a common bit rate even though the CAN nodes’ oscillator
periods (fosc) may be different.
The frequencies of these oscillators are not absolutely stable, as small variations are
caused by changes in temperature or voltage and by deteriorating components. As long
as the variations remain inside a specific oscillator tolerance range (df), the CAN nodes
are able to compensate for the different bit rates by re-synchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments (Figure 83).
The Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific,
programmable number of time quanta (see Table 426). The length of the time quantum
(tq), which is the basic time unit of the bit time, is defined by the CAN controller’s system
clock f and the Baud Rate Prescaler (BRP): tq = BRP / fsys. The C_CAN’s system clock fsys
is the frequency of the system clock (see Section 27.3).
The Synchronization Segment Sync_Seg is the part of the bit time where edges of the
CAN bus level are expected to occur; the distance between an edge that occurs outside of
Sync_Seg and the Sync_Seg is called the phase error of that edge. The Propagation
Time Segment Prop_Seg is intended to compensate for the physical delay times within
the CAN network. The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 surround
the Sample Point. The (Re-)Synchronization Jump Width (SJW) defines how far a
re-synchronization may move the Sample Point inside the limits defined by the Phase
Buffer Segments to compensate for edge phase errors.
Table 426 describes the minimum programmable ranges required by the CAN protocol.
Bit time parameters are programmed through the CANBT register, Table 397. For details
on bit timing and examples, see the C_CAN user’s manual, revision 1.2.
Table 426. Parameters of the C_CAN bit time
UM10736
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Parameter
Range
Function
BRP
(1...32)
Defines the length of the time quantum tq.
SYNC_SEG
1tq
Synchronization segment. Fixed length. Synchronization
of bus input to system clock.
PROP_SEG
(1...8)  tq
Propagation time segment. Compensates for physical
delay times. This parameter is determined by the system
delay times in the C_CAN network.
TSEG1
(1...8)  tq
Phase buffer segment 1. May be lengthened temporarily
by synchronization.
TSEG2
(1...8)  tq
Phase buffer segment 2. May be shortened temporarily by
synchronization.
SJW
(1...4)  tq
(Re-) synchronization jump width. May not be longer than
either phase buffer segment.
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Chapter 27: LPC15xx Controller Area Network C_CAN0
Fig 83. Bit timing
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Chapter 28: LPC15xx 12-bit ADC controller ADC0/1
Rev. 1.1 — 3 March 2014
User manual
28.1 How to read this chapter
The ADC controller is available on all parts. For API support, see Chapter 39. The number
of ADC channels available is dependent on the package size.
Table 427. ADC available analog inputs
Package
ADC0
LQFP48
ADC0_0 to ADC0_7; ADC1_1 to ADC1_3; ADC1_6 to
ADC0_10
ADC1_9
ADC1
9/7
Channels ADC0/ADC1
LQFP64
ADC0_0 to ADC0_11 ADC1_0 to ADC1_11
12/12
LQFP100
ADC0_0 to ADC0_11 ADC1_0 to ADC1_11
12/12
28.2 Features
•
•
•
•
•
•
•
•
•
12-bit successive approximation analog to digital converter.
Input multiplexing among 12 pins and 4 internal sources.
Two configurable conversion sequences with independent triggers.
Optional automatic high/low threshold comparison and “zero crossing” detection.
Power-down mode and low-power operating mode.
Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage level).
12-bit conversion rate of 2 MHz.
Burst conversion mode for single or multiple inputs.
Synchronous or asynchronous operation. Asynchronous operation maximizes
flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger
latency and can eliminate uncertainty and jitter in response to a trigger.
28.3 Basic configuration
Configure the ADC as follows:
• Use the SYSAHBCLKCTRL0 register (Table 50) to enable the clock to the ADC0/1
register interface and the ADC0/1 clock.
• Clear the ADC0/1 peripheral reset using the PRESETCTRL0 register (Table 35).
• Each ADC block creates four interrupts which are connected to slot #31/35
(ADC0/1_SEQA), slot #32/36 (ADC0/1_SEQB), slot #33/37 (ADC0/1_THCMP), and
slot #34/38 (ADC0/1_OVR) in the NVIC. The interrupts can also be configured as
DMA triggers through the INPUT MUX (see Table 132) for each DMA channel and as
inputs to the SCTs (Figure 31 “SCT to ADC connections”).
• Use the switch matrix to enable the ADC analog inputs.
• The power to the ADC0/1 blocks is controlled by the PDRUNCFG register in the
SYSCON block. See Table 75.
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Chapter 28: LPC15xx 12-bit ADC controller ADC0/1
• Calibration is required after every power-up or wake-up from Deep power-down
mode. See Section 28.3.4 “Hardware self-calibration”.
• See Figure 31 “SCT to ADC connections” for connections between the ADC and the
large SCTs.
• You can select from two options in the ADC CTRL register to clock ADC conversions:
– Use the system clock to clock the ADC in synchronous mode. This option allows
exact timing of triggers but requires a system clock of 50 MHz or higher to obtain
the full ADC conversion speed.
– Use the asynchronous ADC clock derived from the output of any of the three PLLs
or the IRC. This option provides a clock which is independent of the system clock
for ADC conversions. Some extra time might be needed to synchronize the ADC
trigger inputs.
• Configure the ADC for the appropriate analog supply voltage using the TRM register
(Table 447).
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Chapter 28: LPC15xx 12-bit ADC controller ADC0/1
28.3.1 Perform a single ADC conversion triggered by software
Remark: When A/D conversions are triggered by software only and hardware triggers are
not used in the conversion sequence, follow these steps to avoid spurious conversions:
1. Before changing the trigger set-up, disable the conversion sequence by setting the
SEQ_ENA bit to 0 in the SEQA_CTRL register.
2. Set the trigger source to 0x0 using the TRIGGER bits in the SEQA_CTRL register.
This is the default.
3. Disconnect the ADC0_PINTRIG0 from any pin by writing 0xFF to the PINASSIGN10 register
bits ADC0_PIN_TRIG0_I. (For ADC1, write 0xFF to PINASSIGN11 register bits
(ADC1_PIN_TRIG0_I). This is the default.
4. Set the TRIGPOL bit to 1 in the in the SEQA_CTRL register.
Once the sequence is enabled again, the ADC converts a sample whenever the START
bit is written to. The TRIGPOL bit can be set in the same write that sets the SEQ_ENA
and the START bits. Be careful not to modify the TRIGGER, TRIGPOL, and SEQ_ENA
bits on subsequent writes to the START bit. See also Section 28.7.2.1 “Avoiding spurious
hardware triggers”.
The ADC converts an analog input signal VIN on the ADC0_[11:0] and ADC1_[11:0] pins.
The VREFP and VREFN pins provide a positive and negative reference voltage input. The
result of the conversion is (4095 x VIN)/(VREFP - VREFN). The result of an input voltage
below VREFN is 0, and the result of an input voltage above VREFP is 4095 (0xFFF).
To perform a single ADC conversion for ADC0 channel 1 using the analog signal on pin
ADC0_1, follow these steps:
1. Enable the analog function on pin ADC0_1 through the switch matrix register
PINENABLE0 on PIO0_7. See Table 123.
2. Configure the system clock to be 50 MHz and select a CLKDIV value of 0 for a
sampling rate of 2 Msamples/s using the ADC CTRL register.
3. Select the synchronous mode in the CTRL register.
4. Select ADC channel 1 to perform the conversion by setting the CHANNELS bits to
0x2 in the SEQA_CTL register.
5. Set the TRIGPOL bit to 1 and the SEQA_ENA bit to 1 in the SEQA_CTRL register.
6. Set the START bit to 1 in the SEQA_CTRL register.
7. Read the RESULT bits in the DAT1 register for the conversion result.
28.3.2 Perform a sequence of conversions triggered by an external pin
The ADC can perform conversions on a sequence of selected channels. Each individual
conversion of the sequence (single-step) or the entire sequence can be triggered by
hardware. Hardware triggers are either a signal from an external pin or an internal signal.
See Section 28.3.3.
To perform a single-step conversion on the first four channels of ADC0 triggered by rising
edges on pin PIO1_0, follow these steps:
1. Enable the analog function on pin ADC0_0 to ADC0_3 through the switch matrix
register PINENABLE0 on PIO0_8, PIO0_7, PIO0_6, and PIO0_5. See Table 123.
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Chapter 28: LPC15xx 12-bit ADC controller ADC0/1
2. Connect the ADC0_PINTRIG1 function to pin PIO1_0 through the PINASSIGN11
register in the switch matrix. See Table 118.
3. Configure the system clock to be 50 MHz and select a CLKDIV value of 0 for a
sampling rate of 2 Msamples/s using the ADC CTRL register.
4. Select the synchronous mode in the CTRL register.
5. Select ADC channels 0 to 3 to perform the conversion by setting the CHANNELS bits
to 0xF in the SEQA_CTRL register.
6. Select ADC0_PINTRG1 by writing 0x1 the TRIGGER bits in the SEQA_CTRL
register.
7. To generate one interrupt at the end of the entire sequence, set the MODE bit to 1 in
the SEQA_CTRL register.
8. Select single-step mode by setting the SINGLESTEP bit in the SEQA_CTRL register
to 1.
9. Enable the Sequence A by setting the SEQA_ENA bit.
A conversion on ADC0 channel 0 will be triggered whenever the pin PIO1_0 goes
from LOW to HIGH. The conversion on the next channel (channel 1) is triggered on
the next rising edge of pin PIO1_0. The ADC0 interrupt is generated when the
sequence has finished after four rising edges on pin PIO1_0.
10. Read the RESULT bits in the DAT0 to DAT3 registers for the conversion result.
28.3.3 ADC hardware trigger inputs
An analog-to-digital conversion can be initiated by a hardware trigger. You can select the
trigger independently for each of the two conversion sequences in the ADC SEQA_CTRL
or SEQB_CTRL registers by programming the hardware trigger input # into the TRIGGER
bits.
Related registers:
• Table 435 “A/D Conversion Sequence A Control Register (SEQA_CTRL, addresses
0x4000 0008 (ADC0) and 0x4008 0008 (ADC1)) bit description”
• Table 436 “A/D Conversion Sequence B Control Register (SEQB_CTRL, 0x4000
000C (ADC0) and 0x4008 000C (ADC1)) bit description”
Table 428. ADC0 hardware trigger inputs
UM10736
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Input #
Source
Description
0
ADC0_PINTRIG0
Use the switch matrix to select a pin.
1
ADC0_PINTRIG1
Use the switch matrix to select a pin.
2
SCT0_OUT7
Internal; SCT output
3
SCT0_OUT9
Internal; SCT output
4
SCT1_OUT7
Internal; SCT output
5
SCT1_OUT9
Internal; SCT output
6
SCT2_OUT3
Internal; SCT output
7
SCT2_OUT4
Internal; SCT output
8
SCT3_OUT3
Internal; SCT output
9
SCT3_OUT4
Internal; SCT output
10
ACMP0_O
Internal; comparator output
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Chapter 28: LPC15xx 12-bit ADC controller ADC0/1
Table 428. ADC0 hardware trigger inputs
Input #
Source
Description
11
ACMP1_O
Internal; comparator output
12
ACMP2_O
Internal; comparator output
13
ACMP3_O
Internal; comparator output
14
Reserved
-
15
ARM_TXEV
-
Table 429. ADC1 hardware trigger inputs
Input #
Source
Description
0
ADC1_PINTRIG0
Use the switch matrix to select a pin.
1
ADC1_PINTRIG1
Use the switch matrix to select a pin.
2
SCT0_OUT6
Internal; SCT output
3
SCT0_OUT9
Internal; SCT output
4
SCT1_OUT8
Internal; SCT output
5
SCT1_OUT9
Internal; SCT output
6
SCT2_OUT2
Internal; SCT output
7
SCT2_OUT5
Internal; SCT output
8
SCT3_OUT2
Internal; SCT output
9
SCT3_OUT5
Internal; SCT output
10
ACMP0_O
Internal; comparator output
11
ACMP1_O
Internal; comparator output
12
ACMP2_O
Internal; comparator output
13
ACMP3_O
Internal; comparator output
14
Reserved
-
15
ARM_TXEV
-
28.3.4 Hardware self-calibration
The A/D converter includes a built-in, hardware self-calibration mode. In order to achieve
the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum,
following every chip reset before initiating normal ADC operation.
The calibration voltage level is VREFP - VREFN.
To calibrate the ADC use the ADC calibration API (see Table 563 “ADC API calls”) or
follow these steps:
1. Save the current contents of the ADC CTRL register if different from default.
2. In a single write to the ADC CTRL register, do the following to start the calibration:
– Set the calibration mode bit CALMODE.
– Clear the ASYNC bit.
– Write a divider value to the CLKDIV bit field that divides the system clock to yield
an ADC clock of about 500 kHz.
– Clear the LPWR bit.
3. Poll the CALMODE bit until it is cleared.
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Before launching a new A/D conversion, restore the contents of the CTRL register or use
the default values.
Remark: The API calibration routine saves any existing Control Register settings, then
modifies those settings as required and sets the CAL_MODE bit to launch calibration.
When the calibration completes, the API routine will restore the original user settings to
the Control Register.
A calibration cycle requires approximately 290 μs to complete. Normal ADC conversions
cannot be launched, and the ADC Control Register must not be written to while calibration
is in progress. The calibration procedure does not use the CPU or memory, so other
processes can be executed during calibration.
28.4 Pin description
The ADC can measure the voltage on any of the input signals on the analog input
channel. Digital signals are disconnected from the ADC input pins when the ADC function
is selected on that pin in the PINENABLE register.
The ADC analog inputs are connected to pins through the switch matrix which enables or
disabled the analog function on a specific pin on the package.
Remark: If the ADC is used, signal levels on analog input pins must not be above the
level of VDDA at any time. Otherwise, ADC readings will be invalid. If the ADC is not used
in an application, then the pins associated with ADC inputs can be configured as digital
I/O pins and are 5 V tolerant.
The ADC pin triggers are movable (digital) functions. If you want to use external pin
triggers for ADC conversions, assign the pin triggers to any pin on the package through
the pin assign registers in the switch matrix. In addition to assigning the pin triggers to a
pin, you must also select them in the conversion sequence registers for each ADC
conversion sequence defined.
.The VREFP_ADC and VREFN pins provide a positive and negative reference voltage
input. The result of the conversion is (4095 x input voltage VIN)/(VREFP_ADC - VREFN).
The result of an input voltage below VREFN is 0, and the result of an input voltage above
VREFP is 4095 (0xFFF). VREFP_ADC should be tied to VDD and VREFN should be tied
to VSS if the ADC and DAC are not used.
Analog Power and Ground should typically be the same voltages as VDD and VSS, but
should be isolated to minimize noise and error. VDDA should be tied to VDD and VSSA
should be tied to VSS if the ADC and DAC are not used.
Table 430. ADC common supply and reference pins
Pin
Description
VDDA
Analog supply voltage. VREFP_ADC must not exceed the voltage level on
VDDA.
Remark: The supply voltage VDD must be equal or lower than VDDA.
UM10736
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VSSA
Analog ground.
VREFP_ADC
Positive reference voltage. VREFP must > 2.4 V. For best performance, select
VREFP = VDDA and VREFN = VSSA.
VREFN
Negative reference voltage.
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Chapter 28: LPC15xx 12-bit ADC controller ADC0/1
Table 431. ADC0/1 pin description
Function
Direction Type
Connect to
Use register
Reference Description
ADC0
ADC0_0
AI
external to pin PIO0_8 or temp
or internal
sensor, band gap
voltage, power
PINENABLE0, Table 123, Analog input channel 0.
Table 434
INSEL
ADC0_1
AI
external to pin PIO0_7
PINENABLE0
Table 123
Analog input channel 1.
ADC0_2
AI
external to pin PIO0_6
PINENABLE0
Table 123
Analog input channel 2.
ADC0_3
AI
external to pin PIO0_5
PINENABLE0
Table 123
Analog input channel 3.
ADC0_4
AI
external to pin PIO0_4
PINENABLE0
Table 123
Analog input channel 4.
ADC0_5
AI
external to pin PIO0_3
PINENABLE0
Table 123
Analog input channel 5.
ADC0_6
AI
external to pin PIO0_2
PINENABLE0
Table 123
Analog input channel 6.
ADC0_7
AI
external to pin PIO0_1
PINENABLE0
Table 123
Analog input channel 7.
ADC0_8
AI
external to pin PIO1_0
PINENABLE0
Table 123
Analog input channel 8.
ADC0_9
AI
external to pin PIO0_31
PINENABLE0
Table 123
Analog input channel 9.
ADC0_10
AI
external to pin PIO0_0
PINENABLE0
Table 123
Analog input channel
10.
ADC0_11
AI
external to pin PIO0_30
PINENABLE0
Table 123
Analog input channel
11.
ADC0_PINTRIG0
I
external to pin any pin
PINASSIGN10 Table 117
ADC0 pin trigger input
0. Also select in ADC
CTRL register as
trigger.
ADC0_PINTRIG1
I
external to pin any pin
PINASSIGN11 Table 118
ADC0 pin trigger input
1. Also select in ADC
CTRL registers as
trigger.
ADC1_0
AI
external to pin PIO1_1 or temp
or internal
sensor, band gap
voltage, power
PINENABLE0, Table 123, Analog input channel 0.
Table 434
INSEL
ADC1_1
AI
external to pin PIO0_9
PINENABLE0
Table 123
Analog input channel 1.
ADC1_2
AI
external to pin PIO0_10
PINENABLE0
Table 123
Analog input channel 2.
ADC1_3
AI
external to pin PIO0_11
PINENABLE0
Table 123
Analog input channel 3.
ADC1_4
AI
external to pin PIO1_2
PINENABLE0
Table 123
Analog input channel 4.
ADC1_5
AI
external to pin PIO1_3
PINENABLE0
Table 123
Analog input channel 5.
ADC1_6
AI
external to pin PIO0_13
PINENABLE0
Table 123
Analog input channel 6.
ADC1_7
AI
external to pin PIO0_14
PINENABLE0
Table 123
Analog input channel 7.
ADC1_8
AI
external to pin PIO0_15
PINENABLE0
Table 123
Analog input channel 8.
ADC1_9
AI
external to pin PIO0_16
PINENABLE0
Table 123
Analog input channel 9.
ADC1_10
AI
external to pin PIO1_4
PINENABLE0
Table 123
Analog input channel
10.
ADC1
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Chapter 28: LPC15xx 12-bit ADC controller ADC0/1
Table 431. ADC0/1 pin description
Function
Direction Type
ADC1_11
AI
ADC1_PINTRIG0
ADC1_PINTRIG1
Connect to
Use register
Reference Description
external to pin PIO1_5
PINENABLE0
Table 123
I
external to pin any pin
PINASSIGN11 Table 118
ADC1 pin trigger input
0. Also select in ADC
CTRL register as
trigger.
I
external to pin any pin
PINASSIGN11 Table 118
ADC1 pin trigger input
1. Also select in ADC
CTRL registers as
trigger.
Analog input channel
11.
28.5 General description
ADCn
switch matrix
ADCn_PINTRIG1:0
1:0
SCT0_OUTm
SCT1_OUTm
3:2
5:4
SCT2_OUTm
7:6
SCT3_OUTm
ACMP[0:3]_OUT
9:8
13:10
reserved
ARM_TXEV
14
15
INSEL
CONVERSION
TRIGGER
sequence A/B
complete IRQ
start
conversion
2
data overrun IRQ
CHANNEL
and
SEQUENCE
CONTROL
channel
select
ANALOG-toDIGITAL
CONVERTER
ADC
result
NVIC
NVIC
DATA
REGISTERS
switch matrix ADCn_0
core voltage regulator output
channel 0
internal voltage reference
temperature sensor output
THRESHOLD
COMPARE
VDDA/2
switch matrix
ADCn_[1:11]
AD0SEL
11
channel 1:11
ADCn_THCMP_IRQ
NVIC
SCT0_INMUX
SCT1_INMUX
SCT2_INMUX
SCT3_INMUX
Fig 86. ADC block diagram
The ADC controller provides a great deal of flexibility in launching and controlling
sequences of A/D conversions using the associated 12-bit, successive approximation A/D
converter. A/D conversion sequences can be initiated under software control or in
response to a selected hardware trigger. Each ADC supports 16 possible hardware
triggers.
Once the triggers are set up (software and hardware triggers can be mixed), the ADC runs
through the pre-defined conversion sequence, converting a sample whenever a trigger
signal arrives, until the sequence is disabled.
UM10736
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 3 March 2014
© NXP B.V. 2014. All rights reserved.
486 of 759
UM10736
NXP Semiconductors
Chapter 28: LPC15xx 12-bit ADC controller ADC0/1
The ADC controller uses the system clock as a bus clock. The system clock or the
asynchronous ADC clock (see Figure 84) can be used to create the ADC clock which
drives the successive approximation process:
• In the synchronous operating mode, this ADC clock is derived from the system clock.
In this mode, a programmable divider is included to scale the system clock to the
maximum ADC clock rate of 50 MHz (72 MHz in 10-bit mode).
• In the asynchronous mode, an independent clock source is used as the ADC clock
source without any further divider in the ADC. The maximum ADC clock rate is
50 MHz (72 MHz in 10-bit mode) as well. In this mode, the ADC clock frequency
must not exceed ten times the system clock.
A fully accurate conversion requires 25 ADC clocks.
28.6 Register description
The reset value reflects the data stored in used bits only. It does not include reserved bits
content.
Table 432. Register overview : ADC (base address 0x4000 0000 (ADC0) and 0x4008 0000 (ADC1))
Name
Access
Address
offset
Description
Reset
value
Reference
CTRL
R/W
0x000
A/D Control Register. Contains the clock divide value,
enable bits for each sequence and the A/D power-down
bit.
0x0
Table 433
INSEL
R/W
0x004
A/D Input Select Register: Selects between external pin
and internal source for channel 0 input.
0x0
Table 434
SEQA_CTRL
R/W
0x008
A/D Conversion Sequence-A control Register: Controls
triggering and channel selection for conversion
sequence-A. Also specifies interrupt mode for
sequence-A.
0x0
Table 435
SEQB_CTRL
R/W
0x00C
A/D Conversion Sequence-B Control Register: Controls
triggering and channel selection for conversion
sequence-B. Also specifies interrupt mode for
sequence-B.
0x0
Table 436
SEQA_GDAT
R/W
0x010
A/D Sequence-A Global Data Register. This register
contains the result of the most recent A/D conversion
performed under sequence-A
NA
Table 437
SEQB_GDAT
R/W
0x014
A/D Sequence-B Global Data Register. This register
contains the result of the most recent A/D conversion
performed under sequence-B
NA
Table 438
DAT0
RO
0x020
A/D Channel 0 Data Register. This register contains the
NA
result of the most recent conversion completed on channel
0.
Table 439
DAT1
RO
0x024
A/D Channel 1 Data Register. This register contains the
NA
result of the most recent conversion completed on channel
1.
Table 439
DAT2
RO
0x028
A/D Channel 2 Data Register. This register contains the
NA
result of the most recent conversion completed on channel
2.
Table 439
UM10736
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 3 March 2014
© NXP B.V. 2014. All rights reserved.
487 of 759
UM10736
NXP Semiconductors
Chapter 28: LPC15xx 12-bit ADC controller ADC0/1
Table 432. Register overview : ADC (base address 0x4000 0000 (ADC0) and 0x4008 0000 (ADC1))
Name
Access
Address
offset
Description
DAT3
RO
0x02C
A/D Channel 3 Data Register. This register contains the
NA
result of the most recent conversion completed on channel
3.
Table 439
DAT4
RO
0x030
A/D Channel 4 Data Register. This register contains the
NA
result of the most recent conversion completed on channel
4.
Table 439
DAT5
RO
0x034
A/D Channel 5 Data Register. This register contains the
NA
result of the most recent conversion completed on channel
5.
Table 439
DAT6
RO
0x038
A/D Channel 6 Data Register. This register contains the
NA
result of the most recent conversion completed on channel
6.
Table 439
DAT7
RO
0x03C
A/D Channel 7 Data Register. This register contains the
NA
result of the most recent conversion completed on channel
7.
Table 439
DAT8
RO
0x040
A/D Channel 8 Data Register. This register contains the
NA
result of the most recent conversion completed on channel
7.
Table 439
DAT9
RO
0x044
A/D Channel 9 Data Register. This register contains the
NA
result of the most recent conversion completed on channel
7.
Table 439
DAT10
RO
0x048
A/D Channel 10 Data Register. This register contains the NA
result of the most recent conversion comp