HD74LS195A 4-bit Parallel-Access Shift Register REJ03D0457–0300 Rev.3.00 Jul.15.2005 This 4-bit register features parallel inputs, parallel outputs, J-K serial inputs, shift / load control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. The registers have two modes of operation: • Parallel (broadside) load • Shift (in the direction QA toward QD) Parallel loading is accomplished by applying the four bits of data and taking the shift / load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished synchronously when the shift / load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D-, or Ttype flip-flop as shown in the function table. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS195AFPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) Pin Arrangement Clear 1 16 VCC Clear J 2 J QA 15 QA K 3 K QB 14 QB A 4 A QC 13 QC B 5 B QD 12 QD C 6 C QD 11 QD D 7 D CK Shift/Load 10 Clock GND 8 9 Shift/Load Serial Inputs Parallel Inputs (Top view) Rev.3.00, Jul.15.2005, page 1 of 7 Outputs HD74LS195A Function Table Clear Shift / Load Clock L H H H H H H X L H H H H H X ↑ L ↑ ↑ ↑ ↑ Inputs Serial J K X X X X X X L H L L H H H L Outputs Parallel B C X X b c X X X X X X X X X X A X a X X X X X D X d X X X X X QA QB QC QD QD L a QA0 QA0 L H QAn L b QB0 QA0 QAn QAn QAn L c QC0 QBn QBn QBn QBn L d QD0 QCn QCn QCn QCn H d QD0 QCn QCn QCn QCn Notes: 1. 2. 3. 4. H; high level, L; low level, X; irrelevant ↑; transition from low to high level a to d; the level of steady-state input at inputs A, B, C, or D, respectively QA0 to QD0; the level of QA, QB, QC, or QD, respectively before the indicated steady-state input conditions were established. 5. QAn to QCn; the level of QA, QB, QC, respectively before the most-recent ↑ transition of the clock. Block Diagram Serial Inputs J K Parallel Inputs A B C D Shift/Load Control Clock Clear Clear Clear Clear Clear R QA CK R R CK CK R QD CK S QA S QB S QC S QD QA QB QC QD QD parallel Outputs Absolute Maximum Ratings Symbol Ratings Unit Supply voltage Item VCC 7 V Input voltage VIN 7 V Power dissipation PT 400 mW Tstg –65 to +150 °C Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Rev.3.00, Jul.15.2005, page 2 of 7 HD74LS195A Recommended Operating Conditions Item Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Operating temperature Topr –20 25 75 °C Clock frequency ƒclock 0 — 30 MHz Clock pulse width tw (CK) 16 — — ns Clear pulse width tsu (CLR) 12 — — ns 25 — — ns 15 — — ns 25 — — ns trelease — — 5 ns th 0 — — ns Supply voltage Output current Shift / load Setup time Serial and parallel data tsu Clear inactive-state Release time Hold time Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V — — — — — — — — — — 0.4 0.5 20 –0.4 0.1 Output voltage VOL Input current IIH IIL II V µA mA mA Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V Short-circuit output IOS –20 — –100 mA VCC = 5.25 V current Supply current** ICC — 14 21 mA VCC = 5.25 V Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** With all outputs open, shift / load grounded, and 4.5 V applied to the J, K, and data inputs, ICC is measured by applying a momentary ground, followed by 4.5 V, to clear and then applying a momentary ground, followed by 4.5 V, to clock. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol ƒmax tPHL tPLH tPHL Rev.3.00, Jul.15.2005, page 3 of 7 Inputs Clock Clear Outputs QA to QD QA to QD Clock QA to QD QD min. 30 — — — typ. 39 19 14 17 max. — 30 22 26 Unit MHz ns ns ns Condition CL = 15 pF, RL = 2 kΩ HD74LS195A Count Sequence Clock Clear Serial Inputs J K Shift Load A Parallel Data Inputs H L B H L C D QA QB Outputs QC QD Serial Shift Clear Rev.3.00, Jul.15.2005, page 4 of 7 Serial Shift Load HD74LS195A Testing Method Test Circuit VCC Output 4.5V RL Load circuit 1 QA See Testing Table P.G. Zout = 50Ω Input P.G. Zout = 50Ω Output J K QB Same as Load Circuit 1. Output A QC B Same as Load Circuit 1. Output C QD D Same as Load Circuit 1. Output CLR Notes: CL CK Shift/Load Input QD Same as Load Circuit 1. 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Testing Table Inputs Item From input to output ƒmax tPLH tPHL Item Clear→ QA to QD Clock→ QA to QD, QD J K CK A B C D 4.5V IN 4.5V Shift / Load 4.5V GND 4.5V 4.5V 4.5V 4.5V GND 4.5V GND IN IN IN 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V GND 4.5V 4.5V IN IN IN IN IN CLR From input to output ƒmax tPLH tPHL Clear→ QA to QD Clock→ QA to QD, QD Rev.3.00, Jul.15.2005, page 5 of 7 Outputs QA QB QC QD QD OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT — OUT OUT OUT OUT OUT OUT HD74LS195A Waveform tw (CLR) tTHL tTLH 90% 1.3V Clear 10% tTLH Clock 10% 0V tn+1 1.3V 10% tn 3V 1.3V 1.3V th th 0V tw (CK) tsu Data tn+1 tn tTHL 90% 90% 1.3V 3V 90% 1.3V 10% tsu 1.3V tsu 1.3V 1.3V 3V 1.3V 0V tsu tsu trelease Shift/Load 1.3V 1.3V trelease 1.3V 3V 1.3V 0V tPHL tPLH tPHL VOH Outputs Q 1.3V 1.3V 1.3V VOL Notes: 1. Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50% 2. A clear pulse is applied prior to each test. 3. Propagation delay times (tPLH and tPHL) are measured at tn + 1. Proper shifting of data is verified at tn + 4 with a functional test. 4. J and K inputs are tested the same as data A, B, C, and D inputs except that shift / load input remains high. 5. tn; bit time beroer clocking transition. 6. tn + 1; bit time after one clocking transition. 7. tn + 4; bit time after four clocking transition. Rev.3.00, Jul.15.2005, page 6 of 7 HD74LS195A Package Dimensions JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 0.20 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.3.00, Jul.15.2005, page 7 of 7 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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