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1
HMP8117
July 29, 2009
FN4643.4
NTSC/PAL Video Decoder
Features
The HMP8117 is a high quality NTSC and PAL video
decoder with internal A/D converters. It is compatible with
NTSC M, PAL B, D, G, H, I, M, N, and combination N (NC)
video standards.
• (M) NTSC and (B, D, G, H, I, M, N, NC) PAL Operation
- Optional Auto Detect of Video Standard
- ITU-R BT.601 (CCIR601) and Square Pixel Operation
Both composite and S-video (Y/C) input formats are
supported. A 2-line comb filter plus a user-selectable
chrominance trap filter provide high quality Y/C separation.
User adjustments include brightness, contrast, saturation,
hue, and sharpness.
Vertical blanking interval (VBI) data, such as Closed
Captioning, Wide Screen Signalling and Teletext, may be
captured and output as BT.656 ancillary data. Closed
Captioning and Wide Screen Signalling information may also
be read out via the I2C interface.
The Videolyzer™ feature provides approved Macrovision™
copy-protection bypass and detection.
Ordering Information
PART NUMBER
TEMP
RANGE
(°C)
PART
MARKING
• Videolyzer Feature
- Macrovision™ Bypass and Detection
• Digital Anti-Alias Filter
• Power Down Mode
• Digital Output Formats
- VMI Compatible
- 8-bit, 16-bit 4:2:2 YCbCr
- 15-bit (5, 5, 5), 16-bit (5, 6, 5) RGB
- Linear or Gamma-Corrected
- 8-bit BT.656
• Analog Input Formats
- Three Analog Composite Inputs
- Analog Y/C (S-video) Input
• “Raw” (Oversampled) VBI Data Capture
PACKAGE
PKG
DWG. #
HMP8117CN
HMP8117CN
0 to +70 80 Ld PQFP Q80.14x20
(Note 2)
HMP8117CNZ
(Note 1)
HMP8117CNZ 0 to +70 80 Ld PQFP Q80.14x20
(Note 2)
(Pb-free)
HMPVIDEVAL/ISA Evaluation Board: ISA Frame Grabber (Note 3)
• “Sliced” VBI Data Capture Capabilities
- Closed Captioning
- Widescreen Signalling (WSS)
- BT.653 System B, C and D Teletext
- North American Broadcast Teletext (NABTS)
- World System Teletext (WST)
• 2-Line (1H) Comb Filter Y/C Separator
• Fast I2C Interface
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. PQFP is also known as QFP and MQFP.
3. Evaluation Board descriptions are in the Applications section.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Multimedia PCs
• Video Conferencing
• Video Compression Systems
• Video Security Systems
• LCD Projectors and Overhead Panels
• Related Products
- NTSC/PAL Encoders: HMP8156, HMP8170
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2003, 2006, 2007, 2009, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
SEE ANALOG FRONT END BLOCK DIAGRAM
SEE DIGITAL PROCESSING BLOCK DIAGRAM
EXTERNAL
ANTI-ALIAS
FILTER
MACROVISION
DETECT
VBI
DETECTION &
DECODING LOGIC
2
YOUT
COMPOSITE/LUMA
CVBS1
CVBS2
CVBS3(Y)
INPUT CLAMP,
MUX,
COARSE AGC,
DC-RESTORE
YIN
YIN[7:0]
ADC
P[15:0]
HSYNC
INPUT
SAMPLE
RATE
CONVERTER
Y/C
SEPARATION
AND
USER
ADJUSTS
OUTPUT
SAMPLE
RATE
CONVERTER
OUTPUT VSYNC
TIMING
BLANK
AND
DATA
FIELD
FIFO
DVALID
CHROMA
EXTERNAL
ANTI-ALIAS
FILTER
C
COARSE AGC
DC-RESTORE
VBIVALID
CIN[7:0]
ADC
CCAP
SYNC-TIP, BACKPORCH TIMING
MICROPROCESSOR
INTERFACE AND
CONTROL
RESET INTREQ
SA
SCL
SCL
HMP8117
FINE AGC,
DC-RESTORE
CONTROL
LCAP
FN4643.4
July 29, 2009
Analog Front End Block Diagram
(EXTERNAL)
INPUT
VIDEO
nmos
1.0μF
75
1.0μF
VID1
(INTERNAL CLAMP)
VAA
1.75V
TO
MUX
+
-
13
#
PIN
50μA
CVBS1
3
7
CLAMP
6
CLAMP
BACKPORCH
ENABLE
GAIN
CORRECTION
LOGIC
LOW-PASS
FILTER
(REMOVE Fsc)
4
4 TO 13
DECODER
CHROMA
ATTEN
(BELOW)
GAIN CONTROL
SET POINT
11
CHROMA MULT.
(BELOW)
FINE ADJUST MULT. FACTOR
1.0μF
CVBS2
1.0μF
Y_IN
5
CLAMP
M
U
X
13-STEP
VARIABLE
ATTENUATOR
2X
9
EXTERNAL
ANTI-ALIAS
FILTER
YIN
8
BUF
75
1.75V
DISABLE
CHARGE PUMP
MUX
SELECT
100μA
DISCHARGE
76
CHARGE
0.1μF
LUMA
DC-RESTORE
LOGIC
100μA
CHROMA
ATTEN
SYNC-TIP ENABLE
CHROMA
MULT.
CHROMA INPUT
C_IN
C
19
(SIGNAL BIAS ~ 2.0V)
13-STEP
VARIABLE
ATTENUATOR
2X
17
BUF
10-BIT 10
ADC
DIGITAL
ANTIALIAS
FILTER
1.5V
2.0V
DISABLE
CHARGE PUMP
100μA
CCAP
STORAGE
CAP
DISCHARGE
29
CHARGE
(OFFSET CHROMA SIGNAL TO ADC MID-SCALE ~= 2.0V)
0.1μF
CORRECTION
MULTIPLIER
75
EXTERNAL
ANTI-ALIAS
FILTER
A/D_TEST
8-BIT
TRUNCATE
2.5V
1.0μF
Y[7:0]
C[7:0]
CHROMA
DC-RESTORE
LOGIC
100μA
POWERDOWN
SYNC-TIP ENABLE
#
PIN # NOMINAL (NTSC) OPERATING CONDITION
FN4643.4
July 29, 2009
6
7
CVBSX. SIZE = INPUT. SYNC TIP CLAMPED AT ~= 1.75 VDC.
76
LCAP. DC-SIGNAL OFFSET ~= 2.4 VDC.
9
8
YOUT /YIN . SIZE = ~1.0 VP-P, SYNC TIP OFFSET ~= 1.5 VDC.
29
CCAP. DC-SIGNAL OFFSET ~= 2.4 VDC.
19
C. SIZE = INPUT SIZE. PORCH OFFSET ~= 2.0 VDC.
28
RSET. DC-SIGNAL OFFSET ~= 1.2 VDC.
17
A/D_TEST. SIZE ~= F(LUMA AGC), PORCH OFFSET ~= 2.0VDC.
78
REF_CAP. DC-SIGNAL OFFSET ~= 2.5 VDC.
BIAS/
INTERNAL
REFERENCE
28
78
RSET
REF_CAP
1.0μF
12.1k
NOMINAL (NTSC) OPERATING CONDITION
PIN #
5
DECODER PIN #
HMP8117
(OFFSET LUMA SIGNAL TO LOWER ADC REF ~= 1.5V)
STORAGE
CAP
DIGITAL
ANTIALIAS
FILTER
1.5V
1.75V
REF
LCAP
10-BIT 10
ADC
CORRECTION
MULTIPLIER
75 75
CVBS3(Y)
2.5V
YOUT
8-BIT
TRUNCATE
VID2
Digital Processing Block Diagram
CLK2 FREQ SELECT
(24.54, 27.0 or 29.5MHz)
HUE
ADJUST
CHROMA
PLL LOOP
FILTER
4
CHROMA
PLL NCO
CHROMA
PHASE
DETECTOR
CLK2 TO
4FSC RATIO
4FSC
CLOCK
CHROMA
AGC AND
SATURATION
ADJUST
CHROMA DATA
C[7:0]
M
U
X
C, CVBS
CHROMA
U, V
DEMOD
LINE LOCKED
NCO
VSYNC
DETECT
U/V TO CbCr
COLOR SPACE
CONVERTER,
COLOR KILLER
FIELD AND
VSYNC
TO FIFO
CHROMA
LP FILTER
ENABLE
RATE
OUTPUT
SAMPLE
CHROMA
TRAP
CONVERTER
RATE
CONVERTER
Y[7:0]
Y
LUMA DATA
M
U
X
SHARPNESS
ADJUST
VBI STATUS
VBI DETECTION
AND DECODING LOGIC
MACROVISION
DETECT
HORIZONTAL
AND VERTICAL
SHARPNESS
ADJUST
MV STATUS
NORMAL
LP FILTER
P[15:0]
CbCr
INPUT
SAMPLE
LINE LOCKED
PLL LOOP
FILTER
M
U
X
FILTER
SELECT
Y
STANDARD
SELECT
SYNC
STRIPPER,
BRIGHTNESS DATA OUTPUT
TIMING
AND
AND
CONTRAST
TIMING
DATA
ADJUST,
FIFO
RGB
CONVERSION
HSYNC
VSYNC
BLANK
FIELD
DVALID
VBIVALID
HMP8117
LINE
DELAY
COMB
FILTER
LOCK
STATUS
FN4643.4
July 29, 2009
HMP8117
Introduction
Digitization of Video
The HMP8117 is designed to decode baseband composite
or S-video NTSC and PAL signals, and convert them to
either digital YCbCr or RGB data. In addition to performing
the basic decoding operations, these devices include
hardware to decode different types of VBI data and to
generate full-screen blue, black and color bar patterns.
Prior to A/D conversion, the input signal is offset and scaled to
known video levels. After digitization, sample rate converters
and a comb filter are used to perform color separation and
demodulation.
Digital PLLs are used to synchronize to all NTSC and PAL
standards. A chroma PLL is used to maintain color lock for
chroma demodulation while a line-locked PLL is used to
maintain vertical spatial alignment. The PLLs are designed
to maintain lock in the presence of VCR head switches, VCR
trick-mode and multi-path noise.
The HMP8117 provides the Videolyzer feature for
Macrovision (MV) copy-protection bypass and detection.
A/D Conversion
Each CVBSX video input channel has a video clamp circuit
that is independent of PLL timing. The input clamp provides
a coarse signal offset to position the sync tip within the A/D
converter sampling range so that the AGC and DCRESTORE logic can operate.
A/D Conversion
Video data is sampled at the CLK2 frequency then processed
by the input sample rate converter. The output levels of the
ADC after AGC and DC restoration processing are:
External Video Processing
Before a video signal can be digitized the decoder has some
external processing considerations that need to be
addressed. This section discusses those external aspects of
the HMP8117.
Analog Video Inputs
The HMP8117 supports either three composite or two
composite and one S-video input.
Three analog video inputs (CVBS 1-3) are used to select
which one of three composite video sources are to be
decoded. To support S-video applications, the Y channel
drives the CVBS3(Y) analog input, and the C channel drives
the C analog input.
The analog inputs must be AC-coupled to the video signals,
as shown in the Applications section.
Anti-alias Filters
Although a 23 tap digital halfband anti-alias filter is provided
for each A/D channel, an external passive filter is
recommended for optimum performance. The digital filter
has a flat response out to 5.4MHz with an approximate -3dB
bandwidth of 6.3MHz using a 27MHz input CLK2 sample
rate. For the CVBSx inputs, the filter is connected between
the YOUT and YIN pins. For the C (chroma) input, the antialias filter should be connected before the C input.
Recommended filter configurations are shown on the
reference schematic in Figure 20. These filters have flat
response out to 4.2MHz with an approximate -3dB
bandwidth of 8MHz. If upgrading from the HMP8115 or
HMP8112A, the previous filter configurations may be used
but with slightly degraded bandwidth. Alternative higher or
lower performance filters configurations may substituted.
(M) NTSC
(M, N) PAL
(B, D, G, H, I, NC)
PAL
white
196
196
black
66
59
blank
56
59
sync
0
0
AGC and DC Restoration
The AGC amplifier attenuates or amplifies the analog video
signal to ensure that the blank level generates code 56 or 59
depending on the video standard. The difference from the
ideal blank level of 56 or 59 is used to control the amount of
attenuation or gain of the analog video signal. To obtain a
stable DC reference for the AGC, a digital low-pass filter
removes the chroma burst from the input signal’s backporch.
DC restoration positions the video signal so that the sync tip
generates a code 0. The internal timing windows for AGC
and DC restoration are show in Figure 3. The appropriate
windows are automatically determined by the decoder when
the input signal is auto-detected or manually selected.
VIDEO INPUT
AGC
DC RESTORE
FIGURE 1. AGC AND DC RESTORE INTERNAL TIMING
5
FN4643.4
July 29, 2009
HMP8117
Input Signal Detection
Comb Filter
If no input video signal is detected for 16 consecutive line
periods, nominal video timing is generated for the previously
detected or programmed video standard. A maskable
interrupt is provided for the condition of “Input Signal Loss”
allowing the host to enable blue field output if desired.
A 2-line comb filter, using a single line delay, is used to
perform part of the Y/C separation process. During S-video
operation, the Y signal bypasses the comb filter; the C signal
is processed by the comb filter since it is an integral part of
the chroma demodulator. During PAL operation, the chroma
trap filter should also be enabled for improved performance.
Vertical Sync and Field Detection
The vertical sync and field detect circuit uses a low time
counter to detect the vertical sync sequence in the video
data stream. The low time counter accumulates the low time
encountered during any sync pulse, including serration and
equalization pulses. When the low time count exceeds the
vertical sync detect threshold, VSYNC is asserted
immediately. FIELD is asserted at the same time that
VSYNC is asserted. FIELD is asserted low for odd fields and
high for even fields. Field is determined from the location in
the video line where VSYNC is detected. If VSYNC is
detected in the first half of the line, the field is odd. If VSYNC
is detected in the second half of a line, the field is even.
In the case of lost vertical sync or excessive noise that would
prevent the detection of vertical sync, the FIELD output will
continue to toggle. Lost vertical sync is declared if after 337
lines, a vertical sync period was not detected for 1 or 3
(selectable) successive fields as specified by bit 2 of the
GENLOCK CONTROL register 04H. When this occurs, the
PLLs are initialized to the acquisition state.
Y/C Separation
A composite video signal has the luma (Y) and chroma (C)
information mixed in the same video signal. The Y/C
separation process is responsible for separating the
composite video signal into these two components. The
HMP8117 utilizes a comb filter to minimize the artifacts that
are associated with the Y/C separation process.
Input Sample Rate Converter
The input sample rate converter is used to convert video data
sampled at the CLK2 rate to a virtual 4xfSC sample rate for
comb filtering and color demodulation. An interpolating filter is
used to generate the 4xfSC samples as illustrated in Figure 2.
Since a single line store is used, the chroma will normally
have a half-line vertical offset from the luma data. This may
be eliminated, vertically aligning the chroma and luma
samples, at the expense of vertical resolution of the luma. Bit
0 of the OUTPUT FORMAT register 02H controls this option.
Chroma Demodulation
The output of the comb filter is further processed using a
patented frequency domain transform to complete the Y/C
separation and demodulate the chrominance.
Demodulation is done at a virtual 4xfSC sample rate using
the interpolated data samples to generate U and V data. The
demodulation process decimates by 2 the U/V sample rate.
Output Sample Rate Converter
The output sample rate converter converts the Y, U and V data
from a virtual 4xfSC sample rate to the desired output sample
rate (i.e., 13.5MHz). It also vertically aligns the samples based
on the horizontal sync information embedded in the digital video
data stream. The output sample rate is determined by the input
video standard and the selected rectangular/square pixel
mode. The output pixel rate is 1/2 of the CLK2 input clock
frequency. The output format is 4:2:2 for all modes except the
RGB modes which use a 4:4:4 output format.
CLK2 Input
The decoder requires a stable clock source for the CLK2
input. For best performance, use termination resistor(s) to
minimize pulse overshoot and reflections on the CLK2 input.
Since chroma demodulation uses the virtual 4xfSC , any jitter
on CLK2 will be transferred as chrominance error on the
output pixels. The CLK2 clock frequency must be one of the
valid selections from Table 1 below based on the video
standard and desired pixel mode.
TABLE 1. VIDEO STANDARD CLOCK RATE SELECTION
SUMMARY
INCOMING VIDEO SAMPLES
VALID CLK2
FREQUENCIES (MHz)
TIME
RESAMPLED VIDEO
VIDEO FORMAT
RECTANGULAR
PIXEL MODE
SQUARE
PIXEL MODE
(M) NTSC, (M) PAL
27.00
24.54
(B, D, G, H, I, N, NC) PAL
27.00
29.50
TIME
4xfSC
FIGURE 2. SAMPLE RATE CONVERSION
6
The CLK2 should be derived from a stable clock source,
such as a crystal. CLK2 must have at least a ±50ppm
accuracy and at least a 60/40% duty cycle to ensure proper
FN4643.4
July 29, 2009
HMP8117
operation. Use of a PLL to generate a “Line Locked” CLK2
input based on the input video is not recommend. (See the
following section.)
Cycle Slipping and Real-Time Pixel Jitter
The decoder’s digital PLL allows it to maintain lock and
provide high quality Y/C separation even on the poorest
quality input video signals. However, this architecture does
not provide a “Line Lock Clock” output and should not be
used as a timing master for direct interface to another video
encoder in a system.
Since the decoder uses a fixed CLK2 input frequency, the
output pixel rate must be periodically adjusted to
compensate for any frequency error between CLK2 and the
input video signal. This output pixel rate adjustment is
referred to as cycle slipping. Since the decoder has an
output data FIFO, all cycle slipping can be deferred until the
next horizontal blanking interval. This guarantees a
consistent number of pixels during the active video region.
Due to cycle slipping, the output timing and data will exhibit a
nominal real-time (line-to-line) pixel jitter of one CLK2 period.
Although the sample rate converter maintains a 1/8 pixel
vertical sample alignment, the output data must be routed to
a frame buffer or video compression chip in order remove
the effects of cycle slipping. (The frame buffer or
compression chip serves as a time base corrector.)
By directly interfacing the decoder to a video encoder, the
output video signal will directly reflect the real-time pixel jitter
effects of the decoder output timing. The jitter effects can be
visualized on a CRT monitor using a static image containing
patterns with sharp vertical edges. The edges will appear
more “ragged” when compared to the input video signal. The
severity of this visual effect relates directly to the frequency
error between CLK2 and the input video signal. It is nearly
impossible to completely match CLK2 with the input video
signal. Therefore, a direct decoder to encoder interface is
not recommended.
The use of an external PLL to generate a “Line Locked”
CLK2 input derived from the input video signal is also not
recommended, since this will defeat the internal digital PLL
and result in pixel decoding errors.
Digital Processing of Video
Once the luma and chroma have been separated the
HMP8117 then performs programmable modifications (i.e.
contrast, coring, color space conversions, color AGC, etc.) to
the decoded video signal.
UV to CbCr Conversion
The baseband U and V signals are scaled and offset to
generate a nominal range of 16-240 for both the Cb and Cr
data.
7
Digital Color Gain Control
There are four types of color gain control modes available:
no gain control, automatic gain control, fixed gain control,
and freeze automatic gain control.
If “no gain control” is selected, the amplitude of the color
difference signals (CbCr) is not modified, regardless of
variations in the color burst amplitude. Thus, a gain of 1x is
always used for Cb and Cr.
If “automatic gain control” is selected, the amplitude of the
color difference signals (CbCr) is compensated for variations
in the color burst amplitude. The burst amplitude is averaged
with the two previous lines having a color burst to limit lineto-line variations. A gain of 0.5x to 4x is used for Cb and Cr.
If “fixed gain control” is selected, the amplitude of the color
difference signals (CbCr) is multiplied by a constant,
regardless of variations in the color burst amplitude. The
constant gain value is specified by the COLOR GAIN
register 1CH . A gain of 0.5x to 4x is used for Cb and Cr.
Limiting the gain to 4x limits the amount of amplified noise.
If “freeze automatic gain control” is selected, the amplitude of
the color difference signals (CbCr) is multiplied by a constant.
This constant is the value the AGC circuitry generated when the
“freeze automatic gain” command was selected.
Color Killer
If “enable color killer” is selected, the color output is turned
off when the running average of the color burst amplitude is
below approximately 25% of nominal for four consecutive
fields. When the running average of the color burst
amplitude is above approximately 25% of nominal for four
consecutive fields, the color output is turned on. The color
output is also turned off when excessive phase error of the
chroma PLL is present.
If “force color off” is selected, color information is never
present on the outputs.
If “force color on” is selected, color information is present on
the outputs regardless of the color burst amplitude or
chroma PLL phase error.
Y Processing
The black level is subtracted from the luminance data to
remove sync and any blanking pedestal information.
Negative values of Y are supported at this point to allow
proper decoding of “below black” luminance levels.
Scaling is done to position black at 8-bit code 0 and white at
8-bit code 219.
A chroma trap filter may be used to remove any residual color
subcarrier from the luminance data. The center frequency of
the chroma trap is automatically determined from the video
standard being decoded. The chroma trap should be disabled
during S-video operation to maintain maximum luminance
bandwidth. Alternately, a 3MHz low-pass filter may be used to
FN4643.4
July 29, 2009
HMP8117
remove high-frequency Y data. This may make a noisy image
more pleasing to the user, although softer.
RGB Output Format Processing
Coring of the high-frequency Y data may be done to reduce
low-level high frequency noise.
The 4:2:2 YCbCr data is converted to 4:4:4 YCbCr data and
then converted to either 15-bit or 16-bit gamma-corrected
RGB (R′G′B′) data. While BLANK is asserted, RGB data is
forced to a value of 0.
Coring of the Y data may also be done to reduce low-level
noise around black. This forces Y data with the following
values to a value of 0:
15-Bit R′G′B′
coring = 1: ± 1
coring = 2: ± 1, ± 2
coring = 3: ± 1, ± 2. ± 3
High-frequency components of the luminance signal may be
“peaked” to control the sharpness of the image. Maximum
gain may be selected to occur at either 2.6MHz or the color
subcarrier frequency. This may be used to make the
displayed image more pleasing to the user. It should not be
used if the output video will be compressed, as the circuit
introduces high-frequency components that will reduce the
compression ratio.
The brightness control adds or subtracts a user-specified DC
offset to the Y data. The contrast control multiplies the Y
data by a user-specified amount. These may be used to
make the displayed image more pleasing to the user.
Finally, a value of 16 is added to generate a nominal range
of 16 (black) to 235 (white).
CbCr Processing
The CbCr data is low-pass filtered to either 0.85MHz or
1.5MHz.
Coring of the CbCr data may be done to reduce low-level
noise around zero. This forces CbCr data with the following
values to a value of 128.
coring = 1: 127, 129
coring = 2: 126, 127, 129, 130
coring = 3: 125, 126, 127, 129, 130, 131
The saturation control multiplies the CbCr data by a userspecified amount. This may be used to make the displayed
image more pleasing to the user. The CbCr data may also be
optionally multiplied by the contrast value to avoid color
shifts when changing contrast.
The hue control provides a user-specified phase offset to the
color subcarrier during decoding. This may be used to
correct slight hue errors due to transmission.
YCbCr Output Format Processing
Y has a nominal range of 16 to 235. Cb and Cr have a
nominal range of 16 to 240, with 128 corresponding to zero.
Values less than 1 are made 1 and values greater than 254
are made 254.
While BLANK is asserted, Y is forced to have a value of 16,
with Cb and Cr forced to have a value of 128, unless VBI
data is present.
8
The following YCbCr to R′G′B′ equations are used to
maintain the proper black and white levels:
R′ = 0.142(Y - 16) + 0.194(Cr - 128)
G′ = 0.142(Y - 16) - 0.099(Cr - 128) - 0.048(Cb - 128)
B′ = 0.142(Y - 16) + 0.245(Cb - 128)
The resulting 15-bit R′G′B′ data has a range of 0 to 31.
Values less than 0 are made 0 and values greater than 31
are made 31.
The 15-bit R′G′B′ data may be converted to 15-bit linear
RGB, using the following equations. Although the PAL
specifications specify a gamma of 2.8, a gamma of 2.2 is
normally used. The HMP8117 allows the selection of the
gamma to be either 2.2 or 2.8, independent of the video
standard.
for gamma = 2.2:
for R′G′B′ < 0.0812*31
R = (31)((R′/31)/4.5)
G = (31)((G′/31)/4.5)
B = (31)((B′/31)/4.5)
for R′G′B′ >= 0.0812*31
R = (31)(((R′/31) + 0.099)/1.099)2.2
G = (31)(((G′/31) + 0.099)/1.099)2.2
B = (31)(((B′/31) + 0.099)/1.099)2.2
for gamma = 2.8:
R = (31)(R′/31)2.8
G = (31)(G′/31)2.8
B = (31)(B′/31)2.8
16-Bit R′G′B′
The following YCbCr to R′G′B′ equations are used to
maintain the proper black and white levels:
R′ = 0.142(Y - 16) + 0.194(Cr - 128)
G′ = 0.288(Y - 16) - 0.201(Cr - 128) - 0.097(Cb - 128)
B′ = 0.142(Y - 16) + 0.245(Cb - 128)
The resulting 16-bit R′G′B′ data has a range of 0 to 31 for R′
and B′, and a range of 0 to 63 for G′. Values less than 0 are
made 0; R′ and B′ values greater than 31 are made 31, G′
values greater than 63 are made 63.
The 16-bit R′G′B′ data may be converted to 16-bit linear RGB,
using the following equations. Although the PAL specifications
specify a gamma of 2.8, a gamma of 2.2 is normally used. The
HMP8117 allows the selection of the gamma to be either 2.2
or 2.8, independent of the video standard.
FN4643.4
July 29, 2009
HMP8117
for gamma = 2.2:
Pixel Port Timing
for R′B′ < 0.0812*31, G′ < 0.0812*63
R = (31)((R′/31)/4.5)
G = (63)((G′/63)/4.5)
B = (31)((B′/31)/4.5)
The the timing and format of the output data and control
signals is presented in the following sections. Refer to the
section “CYCLE SLIPPING AND REAL-TIME PIXEL
JITTER” for PLL and interface considerations.
for R′B′ >= 0.0812*31, G′ >= 0.0812*63
R = (31)(((R′/31) + 0.099)/1.099)2.2
G = (63)(((G′/63) + 0.099)/1.099)2.2
B = (31)(((B′/31) + 0.099)/1.099)2.2
HSYNC and VSYNC Timing
The HSYNC and VSYNC output timing is VMI v1.4 compatible.
Figures 3-6 illustrate the video timing. The leading edge of
HSYNC is synchronous to the video input signal and has a
fixed latency due to internal pipeline processing. The pulse
width of the HSYNC is defined by the END HSYNC register
36H , where the trailing edge of HSYNC has a programmable
delay of 0-510 CLK2 cycles from the leading edge.
for gamma = 2.8:
R = (31)(R′/31)2.8
G = (63)(G′/63)2.8
B = (31)(B′/31)2.8
The leading edge of VSYNC is asserted approximately half way
through the first serration pulse of each field. An accumulator is
used to detect a low-time period within the serration pulse.
Since the leading edge of VSYNC is detected, it should not be
used for timing with respect to HSYNC or BLANK.
Built-in Video Generation
The decoder can be configured to output a full-screen of built-in
blue, black or 75% color bar patterns. The type of pattern
generated is determined by bits 2-1 of the OUTPUT FORMAT
register 02H . When built-in video generation is not desired, the
bits need to be set for normal operation to pass decoded video.
The trailing edge of VSYNC implements the VMI handshake
with HSYNC in order to determine field information without
using the FIELD pin. For an odd field, the trailing edge of
VSYNC is 5 ±1 CLK2 cycles after the trailing edge of the
HSYNC that follows the last equalization pulse. Refer to
Figures 3 and 5. For an even field, the trailing edge of VSYNC
is 5 ±1 CLK2 cycles after the leading edge of the HSYNC that
follows the last equalization pulse. Refer to Figures 4 and 6.
If the decoder is currently locked to a video source on the
input, the output data timing will be based on the input video
source. If an input video source is not detected, internallygenerated output data timing will be used. The following
table lists the data codes output for each built-in video
pattern in YCbCr format.
Field Timing
TABLE 2. BUILT-IN VIDEO PATTERN DATA CODES
PATTERN: COLOR
Y
Cb
Cr
75% Color Bar: White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
B4H
A2H
83H
70H
54H
41H
23H
10H
80H
2CH
9CH
48H
B8H
64H
D4H
80H
80H
8EH
2CH
3AH
C6H
D4H
72H
80H
Blue Screen: Blue
4BH
D9H
88H
Black Screen: Black
10H
80H
80H
When field information can be determined from the input
video source, the FIELD output pin reflects the video source
field state. When field information cannot be determined
from the input video source, the FIELD output pin alternates
its state at the beginning of each field. FIELD changes state
5±1 CLK2 cycles before the leading edge of VSYNC.
NTSC(M) LINE#
524
525
1
2
3
4
5
6
7
8
9
10
PAL(M) LINE#
521
522
523
524
525
1
2
3
4
5
6
7
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘EVEN’ FIELD
‘ODD’ FIELD
FIGURE 3. NTSC(M) AND PAL(M) ODD FIELD TIMING
9
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July 29, 2009
HMP8117
NTSC(M) LINE#
262
263
264
265
266
267
268
269
270
271
272
273
PAL(M) LINE#
259
260
261
262
263
264
265
266
267
268
269
270
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
FIGURE 4. NTSC(M) AND PAL(M) EVEN FIELD TIMING
LINE #
621
622
623
624
625
1
2
3
4
5
6
7
317
318
319
320
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
FIGURE 5. PAL(B, D, G, H, I, N, NC) ODD FIELD TIMING
LINE #
309
310
311
312
313
314
315
316
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
FIGURE 6. PAL(B, D, G, H, I, N, NC) EVEN FIELD TIMING
BLANK and DVALID Timing
DVALID is asserted when P15-P0 contain valid data. The
behavior of the DVALID output is determined by bit 4
(DVLD_LTC) and bit 5 (DLVD_DCYC) of the GENLOCK
CONTROL register 04H for each video output mode.
The BLANK output pin is used to distinguish the blanking
interval period from active video data. The blanking intervals
are programmable in both horizontal and vertical
dimensions. Reference Figure 7 for active video timing and
use Table 3 for typical blanking programming values.
During active scan lines, BLANK is asserted when the
horizontal pixel count matches the value in the START
H_BLANK register 31H/30H . The pixel counter is 000H at the
10
leading edge of the sync tip after a fixed pipeline delay.
Since blanking normally occurs on the front porch, (prior to
count 000H) the START H_BLANK count must be
programmed with a large value from the previous line. Refer
to the Last Pixel Count from Table 3. BLANK is negated
when the horizontal pixel count matches the value in the
END H_BLANK register 32H. Note that horizontally, BLANK
is programmable with two pixel resolution.
START V_BLANK register 34H/33H and END V_BLANK
register 35H determine which scan lines are blanked for each
field. During inactive scan lines, BLANK is asserted during the
entire scan line. Half-line blanking of the output video cannot
be done.
FN4643.4
July 29, 2009
HMP8117
NTSC M
PAL B, D, G, H, I, N, NC
LINES 1 - 22 NOT ACTIVE
LINES 1 - 22 NOT ACTIVE
ODD FIELD
SYNC AND
BACK
PORCH
240 ACTIVE LINES
PER FIELD
(LINES 23-262)
288 ACTIVE LINES
PER FIELD
(LINES 23 - 310)
VERTICAL
BLANKING
480 ACTIVE
LINES/FRAME
(NTSC, PAL M)
EVEN FIELD
LINES 263 - 284 NOT ACTIVE
LINES 311 - 335 NOT ACTIVE
FRONT
PORCH
240 ACTIVE LINES
PER FIELD
(LINES 285 - 524)
LINE 525
NOT ACTIVE
TOTAL PIXELS
858 (780)
ACTIVE PIXELS
288 ACTIVE LINES
PER FIELD
(LINES 336 - 623)
NUMBER OF PIXELS
RECTANGULAR (SQUARE)
NTSC
720 (640)
576 ACTIVE
LINES/FRAME
(PAL)
LINES 624-625
NOT ACTIVE
PAL
864 (944)
TOTAL PIXELS
720 (768)
ACTIVE PIXELS
NOTE:
4. The line numbering for PAL (M) is the NTSC (M) line count minus 3 per the video standards.
FIGURE 7. TYPICAL ACTIVE VIDEO REGIONS
TABLE 3. TYPICAL VALUES FOR H_BLANK AND V_BLANK REGISTERS
VIDEO STANDARD
(MSB/LSB)
ACTIVE
PIXELS/
LINE
TOTAL
PIXELS/
LINE
LAST
PIXEL
COUNT
START
H_BLANK
(31H/30H)
END
H_BLANK
(32H)
START
V_BLANK
(34H/33H)
END
V_BLANK
(35H)
720
720
858
864
857 (0359H)
863 (035FH)
842 (034AH)
852 (0354H)
122 (7AH)
132 (84H)
259 (0103H)
310 (0136H)
19 (13H)
22 (16H)
640
768
780
944
779 (030BH)
943 (03AFH)
758 (02F6H)
922 (039AH)
118 (76H)
154 (9AH)
259 (0103H)
310 (0136H)
19 (13H)
22 (16H)
RECTANGULAR PIXELS
NTSC (M), PAL (M)
PAL (B, D, G, H, I, N, NC)
SQUARE PIXELS
NTSC (M), PAL (M)
PAL (B, D, G, H, I, N, NC)
TABLE 4. PIXEL OUTPUT FORMATS
PIN NAME
8-BIT, 4:2:2, YCbCr
16-BIT, 4:2:2, YCbCr
15-BIT, RGB, (5,5,5)
16-BIT, RGB, (5,6,5)
BT.656
P0
P1
P2
P3
P4
P5
P6
P7
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
Cb0, Cr0 [D0n+1]
Cb1, Cr1 [D1n+1]
Cb2, Cr2 [D2n+1]
Cb3, Cr3 [D3n+1]
Cb4, Cr4 [D4n+1]
Cb5, Cr5 [D5n+1]
Cb6, Cr6 [D6n+1]
Cb7, Cr7 [D7n+1]
B0 [D0n+1]
B1 [D1n+1]
B2 [D2n+1]
B3 [D3n+1]
B4 [D4n+1]
G0 [D5n+1]
G1 [D6n+1]
G2 [D7n+1]
B0 [D0n+1]
B1 [D1n+1]
B2 [D2n+1]
B3 [D3n+1]
B4 [D4n+1]
G0 [D5n+1]
G1 [D6n+1]
G2 [D7n+1]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
P8
P9
P10
P11
P12
P13
P14
P15
Y0, Cb0, Cr0 [D0]
Y1, Cb1, Cr1 [D1]
Y2, Cb2, Cr2 [D2]
Y3, Cb3, Cr3 [D3]
Y4, Cb4, Cr4 [D4]
Y5, Cb5, Cr5 [D5]
Y6, Cb6, Cr6 [D6]
Y7, Cb7, Cr7 [D7]
Y0 [D0n]
Y1 [D1n]
Y2 [D2n]
Y3 [D3n]
Y4 [D4n]
Y5 [D5n]
Y6 [D6n]
Y7 [D7n]
G3 [D0n]
G4 [D1n]
R0 [D2n]
R1 [D3n]
R2 [D4n]
R3 [D5n]
R4 [D6n]
0 [D7n]
G3 [D0n]
G4 [D1n]
G5 [D2n]
R0 [D3n]
R1 [D4n]
R2 [D5n]
R3 [D6n]
R4 [D7n]
YCbCr Data,
Ancillary Data,
SAV and EAV
Sequences
[D0-D7, where P8
corresponds to
D0]
NOTE:
5. Definitions in brackets are port definitions during raw VBI data transfers. Refer to the section on teletext for more information on raw VBI.
11
FN4643.4
July 29, 2009
HMP8117
Pixel Output Port
Cr Y′...], with the first active data each scan line containing
Cb data. The pixel output timing is shown in Figures 8 and 9.
Pixel data is output via the P0-P15 pins. Refer to Table 4 for
the output pin definition as a function of the output mode.
Refer to the section “CYCLE SLIPPING AND REAL-TIME
PIXEL JITTER” for PLL and interface considerations.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr. The behavior
of the DVALID output is determined by bit 4 (DVLD_LTC) of
the GENLOCK CONTROL register 04H .
8-Bit YCbCr Output
Each YCbCr data byte is output following each rising edge of
CLK2. The YCbCr data is multiplexed as [Cb Y Cr Y′ Cb Y
CLK
DVALID
BLANK
P[15-8]
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
tDVLD
NOTE:
6. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate every
cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values are forced to blanking levels.
FIGURE 8. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 0)
16-Bit YCbCr, 15-Bit RGB, or 16-RGB Output
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr; the RGB
outputs have a value of 0.
For 16-bit YCbCr, 15-bit RGB data, or 16-bit RGB output
modes, the data is output following the rising edge of CLK2
with DVALID asserted. Either linear or gamma-corrected
RGB data may be output. The pixel output timing is shown in
Figures 10 to 13.
The behavior of the DVALID output is determined by bit 4
(DVLD_LTC) and bit 5 (DLVD_DCYC) of the GENLOCK
CONTROL register 04H.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
CLK
DVALID
BLANK
P[15-8]
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
tDVLD
NOTES:
7. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate every
cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values are forced to blanking levels.
8. When DVLD_LTC is set to 1, the polarity of DVALID needs to be set to active low, otherwise DVALID will stay low during active video and be
gated with the clock only during the blanking interval.
FIGURE 9. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 1)
12
FN4643.4
July 29, 2009
HMP8117
CLK
DVALID
BLANK
P15-P8
Y0
Y1
Y2
Y3
Y4
P7-P0
Cb0
Cr0
Cb2
Cr2
Cb4
tDVLD
NOTES:
9. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate every
cycle due to the 4:2:2 subsampling.
10. BLANK is asserted per Figure 7.
FIGURE 10. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 0)
CLK
DVALID
P15-P11
[P14-P10]
R0
R1
R2
R3
R4
P10-P5
[P9-P5]
G0
G1
G2
G3
G4
P4-P0
B0
B1
B2
B3
B4
tDVLD
NOTE:
11. BLANK is asserted per Figure 7.
FIGURE 11. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0)
13
FN4643.4
July 29, 2009
HMP8117
CLK
DVALID
P15-P8
P7-P0
Y0
Y1
Y2
Y3
Y4
Cb0
Cr0
Cb2
Cr2
Cb4
tDVLD
NOTES:
12. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle due
to the 4:2:2 subsampling.
13. BLANK is asserted per Figure 7.
14. DVALID is asserted for every valid pixel during both active and blanking regions.
FIGURE 12. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
CLK
DVALID
BLANK
P15-P11
[P14-P10]
R0
R1
R2
R3
R4
P10-P5
[P9-P5]
G0
G0
G2
G2
G4
P4-P0
B0
B1
B2
B3
B4
tDVLD
NOTES:
15. BLANK is asserted per Figure 7.
16. DAVLID is asserted for every valid pixel during both active and blanking regions. DVALID is not a 50% duty cycle synchronous output and will
appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
FIGURE 13. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
8-Bit BT.656 Output
For the BT.656 output mode, data is output following each
rising edge of CLK2. The BT.656 EAV and SAV formats are
shown in Table 5 and the pixel output timing is shown in
Figure 14. The EAV and SAV timing is determined by the
programmed horizontal and vertical blank timing.
During the blanking intervals, the YCbCr outputs have a
value of 16 for Y and 128 for Cb and Cr, unless ancillary data
is present.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2.
14
FN4643.4
July 29, 2009
HMP8117
.
CLK
DVALID
BLANK
P[15-8]
FF
00
00
Status
Cb0
Y0
Cr0
Y1
Cb2
Y2
tDVLD
NOTES:
17. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate
every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period.
18. Notice that DVALID is not asserted during the preamble and that BLANK is still asserted.
19. See table 5 for Status bit definitions.
FIGURE 14. OUTPUT TIMING FOR 8-BIT BT.656 MODE
TABLE 5. BT.656 EAV AND SAV SEQUENCES
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
F
V
H
P3
P2
P1
P0
Status Word
NOTES:
20. P3 = V xor H; P2 = F xor H; P1 = F xor V; P0 = F xor V xor H
21. F: “0” = field 1; “1” = field 2
22. V: “1” during vertical blanking
23. H: “0” at SAV (start of active video); “1” at EAV (end of active video)
Advanced Features
In addition to digitizing an analog video signal the HMP8117
has hardware to process different types of Vertical Blanking
Interval (VBI) data as described in the following sections.
“Sliced” VBI Data Capture
The HMP8117 implements “sliced” data capture of select
types of VBI data. The VBI decoders incorporate detection
hysteresis to prevent them from rapidly turning on and off
due to noise and transmission errors. In order to handle realworld signals, the VBI decoders also compensate for DC
offsets and amplitude variations.
Closed Captioning
During closed captioning capture, the scan lines containing
captioning information are monitored. If closed captioning is
enabled and captioning data is present, the caption data is
loaded into the caption data registers.
DETECTION OF CLOSED CAPTIONING
The closed caption decoder monitors the appropriate scan
lines looking for the clock run-in and start bits used by
captioning. If found, it locks to the clock run-in, the caption
15
data is sampled and loaded into shift registers, and the data
is then transferred to the caption data registers.
If the clock run-in and start bits are not found, it is assumed
the scan line contains video data unless other VBI
information is detected, such as teletext.
Once the clock run-in and start bits are found on the
appropriate scan line for four consecutive odd fields, the
Closed Captioning odd field Detect status bit is set to “1”. It is
reset to “0” when the clock run-in and start bits are not found
on the appropriate scan lines for four consecutive odd fields.
Once the clock run-in and start bits are found on the
appropriate scan line for four consecutive even fields, the
Closed Captioning even field Detect status bit is set to “1”. It
is reset to “0” when the clock run-in and start bits are not
found on the appropriate scan lines for four consecutive
even fields.
READING THE CAPTION DATA
The caption data registers may be accessed in two ways: via
the I2C interface or as BT.656 ancillary data.
FN4643.4
July 29, 2009
HMP8117
CAPTIONING DISABLED ON BOTH LINES
DETECTION OF WSS
In this case, any caption data present is ignored.
The WSS decoder monitors the appropriate scan lines
looking for the run-in and start codes used by WSS. If found,
it locks to the run-in code, the WSS data is sampled and
loaded into shift registers, and the data is then transferred to
the WSS data registers.
The Caption odd field Read status bit and the Caption even
field Read status bit are always a “0”.
ODD FIELD CAPTIONING
In this case, any caption data present on line 284 (or line 281
or 335 in the PAL modes) is ignored. Caption data present
on line 21 (or line 18 or 22 in the PAL modes) is captured
into a shift register then transferred to CLOSED
CAPTION_ODD_A register 20H and CLOSED
CAPTION_ODD_B register 21H.
The Caption even field Read status bit is always a “0”. The
Caption odd field Read status bit is set to “1” after data has
been transferred from the shift register to the CLOSED
CAPTION_ODD_A and CLOSED CAPTION_ODD_B
registers. It is set to “0” after the data has been read out.
EVEN FIELD CAPTIONING
In this case, any caption data present on line 21 (or line 18 or
22 in the PAL modes) is ignored. Caption data present on
line 284 (or line 281 or 335 in the PAL modes) is captured
into a shift register then transferred to CLOSED
CAPTION_EVEN_A register 22H and CLOSED
CAPTION_EVEN_B register 23H.
If the run-in and start codes are not found, it is assumed the
scan line contains video data unless other VBI information is
detected, such as teletext.
Once the run-in and start codes are found on the appropriate
scan line for four consecutive odd fields, the WSS Line 20
Detect status bit is set to “1”. It is reset to “0” when the run-in
and start codes are not found on the appropriate scan lines
for four consecutive odd fields.
Once the run-in and start codes are found on the appropriate
scan line for four consecutive even fields, the WSS Line 283
Detect status bit is set to “1”. It is reset to “0” when the clock
run-in and start bits are not found on the appropriate scan
lines for four consecutive even fields.
READING THE WSS DATA
The WSS data registers may be accessed in two ways: via
the I2C interface or as BT.656 ancillary data.
WSS DISABLED ON BOTH LINES
The Caption odd field Read status bit is always a “0”. The
Caption even field Read status bit is set to “1” after data has
been transferred from the shift register to the CLOSED
CAPTION_EVEN_A and CLOSED CAPTION_EVEN_B
registers. It is set to “0” after the data has been read out.
In this case, any WSS data present is ignored.
ODD AND EVEN FIELD CAPTIONING
In this case, any WSS data present on line 283 (or line 280
or 336 in the PAL modes) is ignored. WSS data present on
line 20 (or line 17 or 23 in the PAL modes) is captured into a
shift register then transferred to the WSS_ODD_A and
WSS_ODD_B data registers.
Caption data present on line 21 (or line 18 or 22 in the PAL
modes) is captured into a shift register then transferred to
the CLOSED CAPTION_ODD_A and CLOSED
CAPTION_ODD_B registers. Caption data present on line
284 (or line 281 or 335 in the PAL modes) is captured into a
shift register then transferred to the CLOSED
CAPTION_EVEN_A and CLOSED CAPTION_EVEN_B
registers.
The Caption odd field Read status bit is set to “1” after data
has been transferred from the shift register to the CLOSED
CAPTION_ODD_A and CLOSED CAPTION_ODD_B
registers. It is set to “0” after the data has been read out.
The Caption even field Read status bit is set to “1” after data
has been transferred from the shift register to the CLOSED
CAPTION_EVEN_A and CLOSED CAPTION_EVEN_B
registers. It is set to “0” after the data has been read out.
Widescreen Signalling (WSS)
During WSS capture (ITU-R BT.1119 and EIAJ CPX-1204),
the scan lines containing WSS information are monitored. If
WSS is enabled and WSS data is present, the WSS data is
loaded into the WSS data registers.
16
The WSS odd field Read status bit and the WSS even field
Read status bit are always a “0”.
ODD FIELD WSS
The WSS even field Read status bit is always a “0”. The
WSS odd field Read status bit is set to “1” after data has
been transferred from the shift register to the WSS_ODD_A
and WSS_ODD_B registers. It is set to “0” after the data has
been read out.
EVEN FIELD WSS
In this case, any WSS data present on line 20 (or line 17 or
23 in the PAL modes) is ignored. WSS data present on line
283 (or line 280 or 336 in the PAL modes) is captured into a
shift register then transferred to the WSS_EVEN_A and
WSS_EVEN_B data registers.
The WSS odd field Read status bit is always a “0”. The WSS
even field Read status bit is set to “1” after data has been
transferred from the shift register to the WSS_EVEN_A and
WSS_EVEN_B registers. It is set to “0” after the data has
been read out.
FN4643.4
July 29, 2009
HMP8117
ODD AND EVEN WSS
Real-Time Control Interface (RTCI) information. Teletext and
RTCI data is only available as BT.656 ancillary data.
WSS data present on line 20 (or line 17 or 23 in the PAL
modes) is captured into a shift register then transferred to
the WSS_ODD_A and WSS_ODD_B registers. WSS data
present on line 283 (or line 280 or 336 in the PAL modes) is
captured into a shift register then transferred to the
WSS_EVEN_A and WSS_EVEN_B registers.
VBIVALID Output Timing
The VBIVALID output is asserted when outputting Closed
Captioning, Wide Screen Signalling, Teletext or RTCI data
as BT.656 ancillary data. It is asserted during the entire
BT.656 ancillary data packet time, including the preamble.
The WSS odd field Read status bit is set to “1” after data has
been transferred from the shift register to the WSS_ODD_A
and WSS_ODD_B registers. It is set to “0” after the data has
been read out.
BT.656 Closed Captioning and Wide Screen
Signalling
Table 6 illustrates the format when outputting the caption
data registers as BT.656 ancillary data. The ancillary data is
present during the horizontal blanking interval after the line
containing the captioning information.
The WSS even field Read status bit is set to “1” after data
has been transferred from the shift register to the
WSS_EVEN_A and WSS_EVEN_B registers. It is set to “0”
after the data has been read out.
Table 7 illustrates the format when outputting the WSS data
registers as BT.656 ancillary data. The ancillary data is
present during the horizontal blanking interval after the line
containing the WSS information.
BT.656 Ancillary Data
Through the BT.656 interface the HMP8117 can generate
non-active video data which contains CC, WSS, teletext or
CLK
VBIVALID
P[15-8]
00
FF
FF
DATA ID
BLK #
# BYTES/4 BYTE #1
BYTE #2
BYTE #3
BYTE #4
tDVLD
NOTES:
24. BT.656 VBI ancillary starts with a 00H, FFH and FFH sequence which is opposite to the SAV/EAV sequence of FFH, 00H and 00H.
25. During active VBI data intervals, DVALID is deasserted and BLANK is asserted.
FIGURE 15. OUTPUT TIMING FOR BT.656 VBI DATA TRANSFERS (CC, WSS, TELETEXT, RTCI)
TABLE 6. READING THE CLOSED CAPTION DATA AS BT.656 ANCILLARY DATA
PIXEL OUTPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Data ID
P14
ep
1
1
0
0
0
0 = odd field data
1 = even field data
Data Block Number
P14
ep
0
0
0
0
0
1
Data Word Count
P14
ep
0
0
0
0
0
1
Caption Data
P14
ep
0
0
bit 15
bit 14
bit 13
bit 12
P14
ep
0
0
bit 11
bit 10
bit 9
bit 8
P14
ep
0
0
bit 7
bit 6
bit 5
bit 4
P14
ep
0
0
bit 3
bit 2
bit 1
bit 0
P14
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CRC
NOTES:
26. ep = even parity for P8-P13.
27. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored.
17
FN4643.4
July 29, 2009
HMP8117
TABLE 7. OUTPUTTING THE SLICED WSS DATA AS BT.656 ANCILLARY DATA
PIXEL OUTPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Data ID
P14
ep
1
1
0
0
1
0 = odd field data
1 = even field data
Data Block Number
P14
ep
0
0
0
0
0
1
Data Word Count
P14
ep
0
0
0
0
1
0
WSS Data
P14
ep
0
0
0
0
bit 13
bit 12
P14
ep
0
0
bit 11
bit 10
bit 9
bit 8
P14
ep
0
0
bit 7
bit 6
bit 5
bit 4
P14
ep
0
0
bit 3
bit 2
bit 1
bit 0
P14
ep
0
0
0
0
bit 5
bit 4
P14
ep
0
0
bit 3
bit 2
bit 1
bit 0
P14
ep
0
0
0
0
0
0
P14
ep
0
0
0
0
0
0
P14
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
WSS CRC
Data
CRC
NOTES:
28. ep = even parity for P8-P13.
29. WSS CRC data = “00 0000” during PAL operation.
30. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored.
Teletext
ACCESSING THE TELETEXT DATA
The HMP8117 supports ITU-R BT.653 625-line and 525-line
teletext system B, C and D capture. NABTS (North American
Broadcast Teletext Specification) is the same as BT.653
525-line system C, which is also used to transmit Intel
Intercast™ information. WST (World System Teletext) is the
same as BT.653 system B. Figure 16 shows the basic
structure of a video signal that contains teletext data.
The teletext data must be output as BT.656 ancillary data.
The I2C interface does not have the bandwidth to output
teletext information when needed.
The scan lines containing teletext information are monitored.
If teletext is enabled and teletext data is present, the teletext
data is output as BT.656 ancillary data.
DETECTION OF TELETEXT
Table 8 illustrates the teletext BT.656 ancillary data format
and Figure 15 depicts the portion of the incoming teletext
signal which is sliced and output as part of the ancillary data
stream. The teletext data is present during the horizontal
blanking interval after the line containing the teletext
information. The actual BT.656 bytes that contain teletext
data only contain 4 bits of the actual data packet. Note that
only the data packet of Figure 16 is sent as ancillary data;
the clock run-in is not included in the data stream.
The teletext decoder monitors the scan lines, looking for the
16-bit clock run-in (sometimes referred to as the clock
synchronization code) used by teletext. If found, it locks to
the clock run-in, the teletext data is sampled and loaded into
shift registers, and the data is then transferred to internal
holding registers.
If the clock run-in is not found, it is assumed the scan line
contains video data unless other VBI information is detected,
such as WSS.
If a teletext clock run-in is found before line 23 or line 289 for
NTSC and (M) PAL, or line 336 for (B, D, G, H, I, N, NC) PAL,
the VBI Teletext Detect status bit is immediately set to “1”. If not
found by these lines, the status bit is immediately reset to “0”.
18
FN4643.4
July 29, 2009
HMP8117
CLOCK
RUN-IN
DATA PACKET
Bit 0
MSB
NOTES:
31. The MSB is bit number: 271 for system C, 279 for system B 525-line and 343 for system B 625-line.
32. The clock run-in is 16 bits wide for both systems and is not included in the BT.656 ancillary data stream.
33. The bit rate is 5.727272 Mbits/s for system B and C on 525/60 systems and 6.9375 and 5.734375 Mbits/second respectively for 625/50 systems.
34. Teletext VBI Video Signal
FIGURE 16. TELETEXT VBI VIDEO SIGNAL
TABLE 8. OUTPUTTING THE SLICED TELETEXT DATA AS BT.656 ANCILLARY DATA
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Data ID
P14
ep
1
1
0
1
0
0
Data Block Number
P14
ep
0
0
0
0
0
1
Data Word Count
P14
ep
0
1
0
1
1
0
Teletext Data
(B, 625-line = 43 bytes)
(B, 525-line = 35 bytes)
(C = 34 bytes)
P14
ep
0 = 525-line
1 = 625-line
0 = system B
1 = system C
bit 343
bit 342
bit 341
bit 340
P14
ep
0
0
bit 339
bit 338
bit 337
bit 336
:
Reserved
CRC
P14
ep
0
0
bit 7
bit 6
bit 5
bit 4
P14
ep
0
0
bit 3
bit 2
bit 1
bit 0
P14
ep
0
0
0
0
0
0
P14
ep
0
0
0
0
0
0
P14
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
NOTES:
35. ep = even parity for P8-P13.
36. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored.
37. For 525-line system B, bits 280-343 are “0”.
38. For system C, bits 272-343 are “0”.
“RAW” VBI DATA CAPTURE
“Raw” data capture of VBI data during blanked scan lines
may be optionally implemented. In this instance, the active
line time of blanked scan lines are sampled at the CLK2 rate,
and output onto the pixel outputs. This permits software
decoding of the VBI data to be done.
The line mask registers specify on which scan lines to
generate “raw” VBI data. If the RAW VBI All bit is enabled, all
the video lines are treated as raw VBI data, excluding the
equalization and serration lines.
The start and end timing of capturing “raw” VBI data on a
scan line is determined by the Start and End Raw VBI
19
Registers. This allows the proper capture of “raw” VBI data
regardless of the BLANK# output timing for active video.
The blanking level is subtracted from the “raw” VBI data
samples, and the result is output onto the pixel outputs.
Note both “sliced” and “raw” VBI data may be available on
the same line.
During NTSC operation, the first possible line of VBI data is
lines 10 and 272, and the last possible lines are the last
blanked scan lines. Lines 1-9 and 264-271 are always
blanked.
FN4643.4
July 29, 2009
HMP8117
During PAL (B, D, G, H, I, N, NC) operation, the first possible
line of VBI data are lines 6 and 318, and the last possible
lines are the last blanked scan lines. Lines 623-5 and 311317 are always blanked.
TABLE 9. OUTPUTTING RTCI AS BT.656 ANCILLARY DATA
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Data ID
P14
ep
1
1
0
1
0
1
Data Block Number
P14
ep
0
0
0
0
0
1
Data Word Count
P14
ep
0
0
0
0
1
1
HPLL
Increment
P14
ep
0
0
0
0
0
0
P14
ep
0
0
0
0
0
0
P14
ep
0
0
0
0
0
0
P14
ep
0
0
0
0
0
0
P14
ep
PSW
0
bit 31
bit 30
bit 29
bit 28
P14
ep
F2 = 0
F1 = 0
bit 27
bit 26
bit 25
bit 24
FSCPLL
Increment
:
CRC
P14
ep
0
0
bit 7
bit 6
bit 5
bit 4
P14
ep
0
0
bit 3
bit 2
bit 1
bit 0
P14
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
NOTES:
39. ep = even parity for P8-P13.
40. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored.
During PAL (M) operation, the first possible line of VBI data
is lines 7 and 269, and the last possible lines are the last
blanked scan lines. Lines 523-6 and 261-268 are always
blanked.
Real Time Control Interface
The Real Time Control Interface (RTCI) outputs timing
information for a NTSC/PAL encoder as BT.656 ancillary
data. This allows the encoder to generate “clean” output
video.
RTCI information via BT.656 ancillary data is shown in Table
9. If enabled, this transfer occurs once per line and is
completed before the start of the SAV sequence.
The PSW bit is always a “0” for NTSC encoding. During PAL
encoding, it indicates the sign of V (“0” = negative;
“1” = positive) for that scan line.
Host Interface
All internal registers may be written to or read by the host
processor at any time, except for those bits identified as
read-only. The bit descriptions for the control registers are
listed beginning with Table 10.
The HMP8117 supports the fast-mode (up to 400kbps) I2C
interface consisting of the SDA and SCL pins. The device
20
acts as a slave for receiving and transmitting data over the
serial interface. When the interface is not active, SCL and
SDA must be pulled high using external 4kΩ pull-up
resistors. The SA input pin determines the slave address for
the HMP8117. If the SA pin is pulled low, the address is
1000100xB . If the SA pin is pulled high through a 10kΩ pullup resistor, the address is 1000101xB . (This ‘x’ bit in the
address is the I2C read flag.)
Data is placed on the SDA line when the SCL line is low and
held stable when the SCL line is pulled high. Changing the
state of the SDA line while SCL is high will be interpreted as
either an I2C bus START or STOP condition as indicated by
Figure 18.
During I2C write cycles, the first data byte after the slave
address is treated as the control register sub address and is
written into the internal address register. Any remaining data
bytes sent during an I2C write cycle are written to the control
registers, beginning with the register specified by the
address register as given in the first byte. The address
register is then auto-incremented after each additional data
byte sent on the I2C bus during a write cycle. Writes to
reserved bits within registers or reserved registers are
ignored.
FN4643.4
July 29, 2009
HMP8117
In order to perform a read from a specific control register
within the HMP8117, an I2C bus write must first be
performed to properly setup the address register. Then an
I2C bus read can be performed to read from the desired
control register(s). As a result of needing the write cycle for a
read cycle there are actually two START conditions as
shown in Figure 19. The address register is then
auto-incremented after each byte read during the I2C read
cycle. Reserved registers return a value of 00H .
tSU:DATA
tBUF
SDA
tHD:DATA
SCL
tLOW
tHIGH
tR
tF
tSU:STOP
FIGURE 17. I2C TIMING DIAGRAM
SDA
SCL
1-7
S
START
CONDITION
8
ADDRESS
9
R/W
1-7
ACK
8
DATA
9
P
ACK
STOP
CONDITION
FIGURE 18. I2C SERIAL DATA FLOW
DATA WRITE
1000 1000
S
CHIP ADDR
FROM MASTER
A
SUB ADDR
A
0x88
DATA READ
S
DATA
A
REGISTER
POINTED
TO BY
SUB ADDR
DATA
A
P
FROM HMP8117
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
1000 1000 (R/W)
CHIP ADDR
A
SUB ADDR
A
S
CHIP ADDR
0x89
0x88
A
DATA
REGISTER
POINTED
TO BY
SUB ADDR
A
DATA
NA
P
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
FIGURE 19. REGISTER WRITE/READ FLOW
21
FN4643.4
July 29, 2009
HMP8117
Control Registers
R
TABLE 10. CONTROL REGISTER SUMMARY
SUBADDRESS
CONTROL REGISTER
RESET/
DEFAULT
VALUE
USE
VALUE
COMMENTS
00H
Product ID
01H
Input Format
19H
Defaults to auto-detect of input video standard.
02H
Output Format
00H
Defaults to 16-bit YCbCr data format.
03H
Output Control
00H
04H
Genlock Control
09H
Defaults to 27MHz CLK2, Rectangular Pixel Mode
05H
Analog Input Control
10H
Defaults to input signal select = CVBS1.
06H
Color Processing
52H
08H
Luma Processing
04H
0AH
Sliced VBI Data Enable
00H
0BH
Sliced VBI Data Output
00H
0CH
VBI Data Status
00H
0EH
Video Status
00H
0FH
Interrupt Mask
00H
10H
Interrupt Status
00H
11H
Raw VBI Control
00H
12H
Raw VBI Start Count
7AH
14H/13H
16H or 17H
Raw VBI Stop Count MSB/LSB
Raw VBI Line Mask_7_0
FEH
16H
Raw VBI Line Mask_15_8
1FH
17H
Raw VBI Line Mask_18_16
00H
18H
Brightness
00H
19H
Contrast
80H
1AH
Hue
00H
1BH
Saturation
80H
1CH
Color Gain Adjust
40H
1DH
Video Gain Adjust
80H
1EH
Sharpness
10H
1FH
Host Control
00H
20H-23H
Closed Caption Data Registers
80H
24H-29H
WSS Data & CRC Registers
31H/30H
Start H_BLANK MSB/LSB
34H/33H
End H_BLANK
Start V_BLANK MSB/LSB
C0H
Set Bits 7-6 to enable data and timing outputs.
03H/4AH
15H
32H
Returns last two digits of part number in hex format.
Set bit 7 for Soft Reset. Set bit 6 for Power Down.
00H
03H/4AH
Table 3
BLANK programming changes for each video standard.
7AH
Table 3
(same as above)
01H/02H
Table 3
(same as above)
35H
End V_BLANK
12H
Table 3
(same as above)
36H
End HSYNC
30H
Table 3
(same as above)
90H
A wider window tolerates poorly timed video sources.
37H
HSYNC Detect Window
20H
41H
MV Control
26H
42H
Reserved
00H
30H
Set bits 5-4 to 11B for optimum performance.
50H
Programmable Fractional Gain
0CH
21H
A slower PFG improves AGC stability.
51H
MV Stripe Gate
14H
52H
Reserved
02H
22H
Set bit 5 to “1” for optimum performance.
53H
AGC Hysteresis
00H
F0H
Larger hysteresis improves AGC stability.
7FH
Device Revision
01H
Production baseline revision is 01H.
Sub-Addresses: 40H, 43H-4FH are reserved. Reads from these registers may return non-zero values.
Sub-Addresses: 07H, 09H, 0DH, 2AH-2FH, 38H-3FH and 54H-7EH are unused. Reads from these registers return 00H. Writes are ignored.
22
FN4643.4
July 29, 2009
HMP8117
TABLE 11. PRODUCT ID REGISTER
SUB ADDRESS = 00H
BIT
NUMBER
7-0
FUNCTION
DESCRIPTION
Product ID
This 8-bit register specifies the last two digits of the product number. Data written to this readonly register is ignored.
RESET
STATE
17H
TABLE 12. INPUT FORMAT REGISTER
SUB ADDRESS = 01H
BIT
NUMBER
7
6-5
FUNCTION
DESCRIPTION
Reserved
RESET
STATE
0B
Video Timing
Standard
These bits are read only unless bit 4 = “0”.
00 = (M) NTSC
01 = (B, D, G, H, I, N) PAL
10 = (M) PAL
11 = Combination (N) PAL; also called (NC) PAL
00B
4
Auto Detect
Video Standard
0 = Manual selection of video timing standard
1 = Auto detect of video timing standard
1B
3
Setup Select
Typically, this bit should be a “1” during (M) NTSC and (M, N) PAL operation. Otherwise, it should
be a “0”.
0 = Video source has a 0 IRE blanking pedestal
1 = Video source has a 7.5 IRE blanking pedestal
1B
2-1
0
Reserved
00B
Adaptive Sync Slice This bit specifies whether to use fixed or adaptive sync slicing. Adaptive sync slicing
Enable
automatically determines the midpoint of the sync amplitude to determine timing.
0 = Fixed sync slicing
1 = Adaptive sync slicing
1B
TABLE 13. OUTPUT FORMAT REGISTER
SUB ADDRESS = 02H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-5
Output Color
Format
000 = 16-bit 4:2:2 YCbCr100 = 16-bit RGB
001 = 8-bit 4:2:2 YCbCr101 = reserved
010 = 8-bit parallel BT.656110 = reserved
011 = 15-bit RGB111 = reserved
000B
4-3
RGB Gamma
Select
These bits are ignored except during RGB output modes.
00 = Linear RGB (gamma of input source = 2.2)
01 = Linear RGB (gamma of input source = 2.8)
10 = Gamma-corrected RGB (gamma = gamma of input source)
11 = reserved
00B
2-1
Output Color
Select
00 = Normal operation10 = Output black field
01 = Output blue field11 = Output 75% color bars
00B
Reserved
Set to “0” for proper operation. Vertical Pixel Siting control is not supported.
0B
0
23
FN4643.4
July 29, 2009
HMP8117
TABLE 14. OUTPUT CONTROL REGISTER
SUB ADDRESS = 03H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7
Video Data
Output Enable
This bit is used to enable the P0-P15 outputs.
0 = Outputs 3-stated. 1 = Outputs enabled
0B
6
Video Timing
Output Enable
This bit is used to enable the HSYNC, VSYNC, BLANK, FIELD, VBIVALID, DVALID, and
INTREQ outputs. 0 = Outputs 3-stated. 1 = Outputs enabled
0B
5
FIELD Polarity
0 = Active low (low during odd fields). 1 = Active high (high during odd fields)
0B
4
BLANK Polarity
0 = Active low (low during blanking). 1 = Active high (high during blanking)
0B
3
HSYNC Polarity
0 = Active low (low during horizontal sync). 1 = Active high (high during horizontal sync)
0B
2
VSYNC Polarity
0 = Active low (low during vertical sync). 1 = Active high (high during vertical sync)
0B
1
DVALID Polarity
0 = Active low (low during valid pixel data). 1 = Active high (high during valid pixel data)
0B
0
VBIVALID Polarity
0 = Active low (low during VBI data). 1 = Active high (high during VBI data)
0B
TABLE 15. GENLOCK CONTROL REGISTER
SUB ADDRESS = 04H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Aspect Ratio
Mode
0 = Rectangular (BT.601) pixels
1 = Square pixels
0B
6
Freeze Output
Timing Enable
Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit to a “0”
resumes normal operation at the start of the next field.
0 = Normal operation
1 = Freeze output timing
0B
5
DVALID Duty Cycle
Control
(DVLD_DCYC)
This bit is ignored during the 8-bit YCbCr and BT.656 output modes.
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID has 50/50 duty cycle at the pixel output data rate
1 = DVALID goes active based on line-lock. This will cause DVALID to not have a 50/50 duty
cycle. This bit is intended to be used in maintaining backward compatibility with the HMP8112A
DVALID output timing.
0B
4
DVALID Line Timing During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID present only during active video time on active scan lines
Control
(DVLD_LTC)
1 = DVALID present the entire scan line time on all scan lines
During the 8-bit YCbCr and BT.656 output modes, this bit defines the DVALID output as:
0 = Normal timing
1 = DVALID signal ANDed with CLK2
0B
3
Missing HSYNC
Detect Select
This bit specifies the number of missing horizontal sync pulses before entering horizontal lock
acquisition mode.
0 = 12 pulses
1 = 1 pulse
1B
2
Missing VSYNC
Detect Select
This bit specifies the number of missing vertical sync pulses before entering vertical lock
acquisition mode.
0 = 3 pulses
1 = 1 pulse
0B
1-0
CLK2 Frequency
This bit indicates the frequency of the CLK2 input clock.
00 = 24.54MHz10 = 29.5MHz
01 = 27.0MHz11 = Reserved
01B
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TABLE 16. ANALOG INPUT CONTROL REGISTER
SUB ADDRESS = 05H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Lock Loss
Video Gain
Select
If bits 5-4 do not equal “01”, these bits indicate what mode the AGC circuitry will be after loss of
sync. If bits 5-4 equal “01”, these bits are ignored.
00 = Automatic gain control: bits 5-4 will be reset to “01”
01 = Maintain fixed gain: bits 5-4 will not be changed
10 = Normal AGC switching to fixed gain after lock achieved: bits 5-4 will not be reset to “01”
unless they indicated “freeze automatic gain control”
11 = reserved
00B
5-4
Video Gain
Control Select
00 = Fixed 1x gain
01 = Automatic gain control
10 = Fixed gain control. (Use gain factor from Video Gain Adjust register 1DH.)
11 = Freeze automatic gain control
01B
Digital Anti-Alias
Filter Control
0 = Internal digital anti-alias filter is active.
1 = Internal digital anti- alias filter is bypassed. (Not Recommended)
0B
Video Signal
Input Select
000 = CVBS1
001 = CVBS2
010 = CVBS3
011 = S-video
1XX = reserved
3
2-0
000B
TABLE 17. COLOR PROCESSING REGISTER
SUB ADDRESS = 06H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Digital Color Gain
Control Select
00 = No gain control (gain = 1x)
01 = Automatic gain control
10 = Fixed gain control. (Use gain factor from Color Gain Adjust register 1CH.)
11 = Freeze automatic gain control
01B
5-4
Color Killer
Select
00 = Force color on
01 = Enable color killer
10 = reserved
11 = Force color off
01B
3-2
Color Coring
Select
Coring may be used to reduce low-level noise in the CbCr signals.
00 = No coring
01 = 1 code coring
10 = 2 code coring
11 = 3 code coring
00B
1
Contrast Control
Select
This bit specifies whether the contrast control affects just the Y data (“0”) or both the Y and CbCr
data (“1”). To avoid color shifts when changing contrast, this bit should be a “1”.
0 = Contrast controls only Y data
1 = Contrast controls Y and CbCr data
1B
0
Color Low-Pass
Filter Select
This bit selects the bandwidth of the CbCr data.
0 = 850kHz
1 = 1.5MHz
0B
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TABLE 18. LUMA PROCESSING REGISTER
SUB ADDRESS = 08H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Y Filtering
Select
The chroma trap filter may be used to remove any residual color subcarrier information from the
Y channel. During S-video operation, it should be disabled. During PAL operation, it should be
enabled. The 3MHz low-pass filter may be used to remove high-frequency noise.
00 = No filtering
01 = Enable chroma trap filter
10 = Enable 3.0MHz low-pass filter
11 = reserved
00B
5-4
Black Level Y
Coring Select
Coring may be used to reduce low-level noise around black in the Y signal.
00 = No coring
01 = 1 code coring
10 = 2 code coring
11 = 3 code coring
00B
3-2
High Frequency Y
Coring Select
Coring may be used to reduce high-frequency low-level noise in the Y signal.
00 = No coring
01 = 1 code coring
10 = 2 code coring
11 = 3 code coring
01B
1-0
Sharpness
Frequency Select
Specifies the amount of sharpness to be applied per the Sharpness Adjust register 1EH.
00 = Bypass sharpness control10 = Maximum gain at color FSC
01 = Maximum gain at 2.6MHz11 = reserved
00B
TABLE 19. SLICED VBI DATA ENABLE REGISTER
SUB ADDRESS = 0AH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Sliced
Closed Captioning
Enable
00 = Closed caption disabled
01 = Closed caption enabled for odd fields: line 21 for NTSC, line 18 for (M) PAL, or line 22 for
(B, D, G, H, I, N, NC) PAL
10 = Closed caption enabled for even fields: line 284 for NTSC, line 281 for (M) PAL, or line 335
for (B, D, G, H, I, N, NC) PAL
11 = Closed caption enabled for both odd and even fields
00B
5-4
Sliced
WSS Enable
00 = WSS disabled
01 = WSS enabled for odd fields: line 20 for NTSC; line 17 for (M) PAL, or line 23 for (B, D, G, H,
I, N, NC) PAL
10 = WSS enabled for even fields: line 283 for NTSC, line 280 for (M) PAL, or line 336 for (B, D,
G, H, I, N, NC) PAL
11 = WSS enabled for both odd and even fields
00B
3-2
Sliced Teletext
Enable
00 = Teletext disabled10 = Teletext system C enabled
01 = Teletext system B enabled11 = Teletext system D enabled
00B
1-0
Reserved
00B
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TABLE 20. SLICED VBI DATA OUTPUT REGISTER
SUB ADDRESS = 0BH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Sliced Closed
Caption BT.656
Output
Enable
If set to “1”, this bit enables output of sliced closed captioning via BT.656 ancillary data.
Closed captioning must be enabled by the Sliced VBI Data Enable register 0AH.
Access via the I2C interface is always available.
0B
6
Sliced WSS
BT.656 Output
Enable
If set to “1”, this bit enables output of sliced WSS via BT.656 ancillary data.
WSS must be enabled by the Sliced VBI Data Enable register 0AH.
Access via the I2C interface is always available.
0B
5
Sliced Teletext
BT.656 Output
Enable
If set to “1”, this bit enables output of sliced teletext via BT.656 ancillary data.
Teletext data is not available via the I2C interface.
0B
4-1
0
Reserved
0000B
RTCI BT.656
Output Enable
If set to “1”, this bit enables output of RTCI data as BT.656 ancillary data.
0B
TABLE 21. VBI DATA STATUS REGISTER
SUB ADDRESS = 0CH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
CC Odd Field
Detect Status
This bit is read-only. Data written to this bit is ignored.
If set to “1”, Closed Captioning (CC) data is detected on the odd field.
0B
6
CC Even Field
Detect Status
This bit is read-only. Data written to this bit is ignored.
If set to “1”, Closed Captioning (CC) data is detected on the even field.
0B
5
WSS Odd Field
Detect Status
This bit is read-only. Data written to this bit is ignored.
If set to “1”, Wide Screen Signalling (WSS) data is detected on the odd field.
0B
4
WSS Even Field
Detect Status
This bit is read-only. Data written to this bit is ignored.
If set to “1”, Wide Screen Signalling (WSS) data is detected on the even field.
0B
3
VBI Teletext
Detect Status
This bit is read-only. Data written to this bit is ignored.
If set to “1”, Teletext data is detected during the vertical blanking interval.
0B
2-0
Reserved
000B
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TABLE 22. VIDEO STATUS REGISTER
SUB ADDRESS = 0EH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Vertical Lock
Status
This bit is read-only. Data written to this bit is ignored.
If set to “1”, the decoder is vertically locked to the input signal.
0B
6
Horizontal Lock
Status
This bit is read-only. Data written to this bit is ignored.
If set to “1”, the decoder is horizontally locked to the input signal.
0B
5
Color Lock
Status
This bit is read-only. Data written to this bit is ignored.
If set to “1”, the decoder is chroma locked to the input signal.
0B
4
Input Video
Detect Status
This bit is read-only. Data written to this bit is ignored.
If set to “1”, video is detected on the input signal.
0B
3-1
0
MV Detection Status These bits are read-only. Data written to this bit is ignored.
000B = No MV present
001B = PSP present, No Stripes
010B = PSP present, 2-Line Stripes
011B = PSP present, 4-line Stripes
100B = reserved
101B = reserved
110B = No PSP present, 2-line Stripes (invalid MV scheme, may indicate false detection)
111B = No PSP present, 4-line Stripes (invalid MV scheme, may indicate false detection)
This bit is read-only. Data written to this bit is ignored.
If set to “1”, the decoder determined the video standard on the input signal.
This bit is enabled by the Input Format Register 01H bit 4.
Auto Detect
Video Standard
Status
000B
0B
TABLE 23. INTERRUPT MASK REGISTER
SUB ADDRESS = 0FH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Genlock Loss
Interrupt Mask
If set to “1”, an interrupt is enabled for the loss of genlock.
0B
6
Input Signal Loss
Interrupt Mask
If set to “1”, an interrupt is enabled for the loss of input video signal.
0B
5
Closed Caption
Interrupt Mask
If set to “1”, an interrupt is enabled for new data in the closed caption data registers.
0B
4
WSS
Interrupt Mask
If set to “1”, an interrupt is enabled for new data in the WSS data registers.
0B
3
Teletext
Interrupt Mask
If set to “1”, an interrupt is enabled for the detection of teletext data in the current field.
0B
2
MV Interrupt Mask
If set to “1”, an interrupt is enabled for a change in the MV Detection Status Register 0EH.
0B
1
Auto Detect
Video Standard
Interrupt Mask
If set to “1”, an interrupt is enabled for the successful auto detection of a video standard.
0B
0
Vertical Sync
Interrupt Mask
If set to “1”, an interrupt is enabled for the start of a new field.
0B
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TABLE 24. INTERRUPT STATUS REGISTER
SUB ADDRESS = 10H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Genlock Loss
Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to a loss of genlock.
To clear the interrupt request, a “1” must be written to this bit.
0B
6
Input Signal Loss
Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to a loss of input video signal.
To clear the interrupt request, a “1” must be written to this bit.
0B
5
Closed Caption
Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to new data in the closed caption data
registers. To clear the interrupt request, a “1” must be written to this bit.
0B
4
WSS Interrupt
Status
If set to “1”, this bit indicates the interrupt request was due to new data available in the WSS data
registers. To clear the interrupt request, a “1” must be written to this bit.
0B
3
Teletext Interrupt
Status
If set to “1”, this bit indicates the interrupt request was due to the detection of teletext data in the
current field. To clear the interrupt request, a “1” must be written to this bit.
0B
2
MV Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to a change in the MV Detection Status
of register 0EH. To clear the interrupt request, a “1” must be written to this bit.
0B
1
Auto Detect
Video Standard
Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to the successful auto detection of a
video standard. To clear the interrupt request, a “1” must be written to this bit.
0B
0
Vertical Sync
Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to the start of a new field.
To clear the interrupt request, a “1” must be written to this bit.
0B
TABLE 25. RAW VBI CONTROL REGISTER
SUB ADDRESS = 11H
BIT
NO.
7-4
FUNCTION
DESCRIPTION
Reserved
RESET
STATE
0000B
3
RAW Preamble
Enable
If set to “1”, enables a four byte preamble in the RAW VBI data stream.
The preamble format is FFH, CNT1, CNT2 and 00H, where:
CNT1:
Bit 7 = even parity bar,
Bit 6 = even parity[5-0],
Bit 5 = 0,
Bit 4 = Field (0=Odd, 1=Even),
Bits 3 -0 =Linecount[8-4].
CNT2:
Bit 7 = even parity bar,
Bit 6 = even parity [5-0],
Bits 5-4 = 00
Bits 3-0 = Linecount[3-0].
0B
2
RAW VBI
All
If set to “1”, all the video lines (full field) are converted to RAW VBI data.
If set to “0”, only the lines enabled by the RAW VBI LINE MASK registers are converted to RAW
VBI data.
0B
1
RAW VBI
Even Field
If set to “1”, even field lines are converted to RAW VBI data as specified by the RAW VBI All bit
and the RAW VBI LINE MASK registers.
If set to “0”, the even field lines are excluded from the RAW VBI data stream.
0B
0
RAW VBI
Odd Field
If set to “1”, odd field lines are converted to RAW VBI data as specified by the RAW VBI All bit
and the RAW VBI LINE MASK registers.
If set to “0”, the odd field lines are excluded from the RAW VBI data stream.
0B
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TABLE 26. RAW VBI START COUNT REGISTER
SUB ADDRESS = 12H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Raw VBI Start Count Specifies the start of the raw VBI data sampling window in two CLK2 period steps from the
leading edge of HSYNC.
RESET
STATE
7AH
TABLE 27. RAW VBI STOP COUNT LSB REGISTER
SUB ADDRESS = 13H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Raw VBI Stop Count This 8-bit register is cascaded with Raw VBI Stop Count MSB (below) to form a 10-bit stop count
LSB
value. The stop count specifies the end of the raw VBI data sampling window in two CLK2 period
steps from the leading edge of HSYNC.
RESET
STATE
4AH
TABLE 28. RAW VBI STOP COUNT MSB REGISTER
SUB ADDRESS = 14H
BIT
NO.
FUNCTION
DESCRIPTION
7-2
Reserved
1-0
Raw VBI Stop Count This 2-bit register is cascaded with Raw VBI Stop Count LSB (above) to form a 10-bit stop count
MSB
value. The stop count specifies the end of the raw VBI data sampling window in two CLK2 period
steps from the leading edge of HSYNC.
RESET
STATE
000000B
11B
TABLE 29. RAW VBI LINE MASK_7_0 REGISTER
SUB ADDRESS = 15H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Raw VBI Line
Mask_7_0
A “1” in each bit position enables raw VBI capture for a corresponding input video line. Refer to
Table 32 below.
RESET
STATE
FEH
TABLE 30. RAW VBI LINE MASK_15_8 REGISTER
SUB ADDRESS = 16H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Raw VBI Line
Mask_15_8
A “1” in each bit position enables raw VBI capture for a corresponding input video line. Refer to
Table 32 below.
RESET
STATE
1FH
TABLE 31. RAW VBI LINE MASK_18_16 REGISTER
SUB ADDRESS = 17H
BIT
NO.
FUNCTION
7-3
Reserved
2-0
Raw VBI Line
Mask_18_16
DESCRIPTION
RESET
STATE
00000B
A “1” in each bit position enables raw VBI capture for a corresponding input video line. Refer to
Table 32 below.
30
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TABLE 32. RAW VBI MASK DEFINITIONS
MASK
(Register = Default)
MASK_18_16
(Reg. 17H)
MASK_15_8
(Register 16H)
MASK_7_0
(Register 15H)
REGISTER BIT
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Mask Bit
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NTSC (Odd) Line#
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
NTSC (Even) Line#
290
289
288
287
286
285
284
283
282
281
280
279
278
277
276
275
274
273
272
PAL (Odd) Line#
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
PAL (Even) Line#
336
335
334
333
332
331
330
329
328
327
326
325
324
323
322
321
320
319
318
TABLE 33. BRIGHTNESS REGISTER
SUB ADDRESS = 18H
BIT
NO.
FUNCTION
7
Reserved
6-0
Brightness
Adjust
DESCRIPTION
RESET
STATE
0B
These bits control the brightness. They may have a value of +63 (“011 1111”) to -64 (“100 0000”),
with positive values increasing brightness. A value of 0 (“000 0000”) has no effect on the data.
0000000B
TABLE 34. CONTRAST REGISTER
SUB ADDRESS = 19H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Contrast
Adjust
These bits control the contrast. They may have a value of 0x (“0000 0000”) to 1.992x (“1111
1111”). A value of 1x (“1000 0000”) has no effect on the data.
RESET
STATE
80H
TABLE 35. HUE REGISTER
SUB ADDRESS = 1AH
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Hue
Adjust
These bits control the color hue. They may have a value of +30 degrees (“0111 1111”) to -30
degrees (“1111 1111”). A value of 0 degrees (“0000 0000”) has no effect on the color data.
RESET
STATE
00H
TABLE 36. SATURATION REGISTER
SUB ADDRESS = 1BH
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Saturation
Adjust
These bits control the color saturation. They may have a value of 0x (“0000 0000”) to 1.992x
(“1111 1111”). A value of 1x (“1000 0000”) has no effect on the color data. A value of 0x (“0000
0000”) disables the color information.
RESET
STATE
80H
TABLE 37. COLOR GAIN ADJUST REGISTER
SUB ADDRESS = 1CH
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Color Gain Adjust
These bits control the amount of digital gain applied to the color difference (CbCr) signals. They
may have a value of 0.5x (“0010 0000”) to 3.98x (“1111 1111”). A value of 1x (“0100 0000”) has
no effect on the data. This register enabled by the selection of “fixed gain control” mode in the
Color Processing register 06H.
31
RESET
STATE
40H
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TABLE 38. VIDEO GAIN ADJUST REGISTER
SUB ADDRESS = 1DH
BIT
NO.
7-0
FUNCTION
RESET
STATE
DESCRIPTION
Video Gain Adjust
This register is enabled by the selection of “fixed gain control” mode in the Analog Input Control
register 05H bits 7-4. The value of this register selects a combined analog attenuation and a
digital gain factor which is applied to both Luma and Chroma input channels. The gain factor is
selected from nonlinear lookup table and may range in value from 0.5x (CEH) to 1.99x (33H).
Refer to Table 39 below. The Register Values in italics below mark the approximate analog
attenuation ladder switching points.
80H
TABLE 39. VIDEO GAIN REGISTER LOOKUP TABLE
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
0.50
0.51
0.52
0.53
0.54
0.55
206/CEH
202/CAH
197/C5H
193/C1H
191/BFH
187/BBH
0.67
0.68
0.69
0.70
0.71
0.72
153/99H
151/97H
150/96H
147/93H
145/91H
143/8FH
0.84
0.85
0.86
0.87
0.88
0.89
123/7BH
121/79H
119/77H
118/76H
117/75H
115/73H
1.03
1.04
1.05
1.06
1.07
1.08
100/64H
99/63H
98/62H
97/61H
96/60H
95/5FH
1.23
1.25
1.27
1.28
1.30
1.31
83/53H
82/52H
81/51H
80/50H
79/4FH
78/4EH
1.55
1.57
1.59
1.63
1.65
1.67
66/42H
65/41H
64/40H
63/3FH
62/3EH
61/3DH
0.56
0.57
0.58
0.59
0.60
0.61
183/B7H
180/B4H
178/B2H
174/AEH
171/ABH
169/A9H
0.73
0.74
0.75
0.76
0.77
0.78
141/8DH
139/8BH
137/89H
136/88H
134/86H
132/84H
0.90
0.91
0.92
0.94
0.95
0.96
114/72H
113/71H
111/6FH
110/6EH
109/6DH
107/6BH
1.09
1.10
1.12
1.13
1.14
1.15
94/5EH
93/5DH
92/5CH
91/5BH
90/5AH
89/59H
1.33
1.34
1.37
1.38
1.40
1.42
77/4DH
76/4CH
75/4BH
74/4AH
73/49H
72/48H
1.70
1.73
1.76
1.79
1.82
1.86
60/3CH
59/3BH
58/3AH
57/39H
56/38H
55/37H
0.62
0.63
0.64
0.65
0.66
167/A7H
164/A4H
161/A1H
159/9FH
156/9CH
0.79
0.80
0.81
0.82
0.83
130/82H
128/80H
126/7EH
125/7DH
124/7CH
0.97
0.98
1.00
1.01
1.02
106/6AH
104/68H
103/67H
102/66H
101/65H
1.16
1.18
1.20
1.21
1.22
88/58H
87/57H
86/56H
85/55H
84/54H
1.44
1.46
1.48
1.51
1.52
71/47H
70/46H
69/45H
68/44H
67/43H
1.89
1.93
1.97
1.99
54/36H
53/35H
52/34H
51/33H
TABLE 40. SHARPNESS ADJUST REGISTER
SUB ADDRESS = 1EH
BIT
NO.
FUNCTION
7-6
Reserved
5-0
Sharpness
Adjust
DESCRIPTION
RESET
STATE
00B
Specifies the amount of high frequency gain control for luminance signals (either 2.6MHz or
FSC), as determined by the Luma Processing register 08H. The gain ranges from +12dB (11
1111B) to -12dB (00 0100B). A value of 0dB (“01 0000”) has no effect on the data.
32
010000B
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TABLE 41. HOST CONTROL REGISTER
SUB ADDRESS = 1FH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Software Reset
When this bit is set to 1, the entire device except the I2C bus is reset to a known state exactly
like the RESET input going active. The software reset will initialize all register bits to their reset
state. Once set this bit is self clearing. This bit is cleared on power-up by the external RESET pin.
0B
6
Power Down
When this bit is set to a 1, the entire device is shut down except the I2C bus by gating off the
clock. For normal decoding operations this bit should be set to a 0.
0B
5
Closed Caption
Odd Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption data
has been read out via the I2C interface or as BT.656 ancillary data.
0 = No new caption data
1 = Caption_ODD_A and Caption_ODD_B data registers contain new data.
0B
4
Closed Caption
Even Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption data
has been read out via the I2C interface or as BT.656 ancillary data.
0 = No new caption data
1 = Caption_EVEN_A and Caption_EVEN_B data registers contain new data.
0B
3
WSS
Odd Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS data has
been read out via the I2C interface or as BT.656 ancillary data.
0 = No new WSS data
1 = WSS_ODD_A and WSS_ODD_B data registers contain new data.
0B
2
WSS
Even Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS data has
been read out via the I2C interface or as BT.656 ancillary data.
0 = No new WSS data
1 = WSS_EVEN_A and WSS_EVEN_B data registers contain new data.
0B
1-0
Reserved
00B
TABLE 42. CLOSED CAPTION_ODD_A DATA REGISTER
SUB ADDRESS = 20H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Odd Field
Caption Data
If odd field captioning is enabled and present, this register is loaded with the first eight bits of
caption data on line 18, 21, or 22. Bit 0 corresponds to the first bit of caption information. Data
written to this register is ignored.
RESET
STATE
80H
TABLE 43. CLOSED CAPTION_ODD_B DATA REGISTER
SUB ADDRESS = 21H
BIT
NO.
15-8
FUNCTION
DESCRIPTION
Odd Field
Caption Data
If odd field captioning is enabled and present, this register is loaded with the second eight bits of
caption data on line 18, 21, or 22. Data written to this register is ignored.
RESET
STATE
80H
TABLE 44. CLOSED CAPTION_EVEN_A DATA REGISTER
SUB ADDRESS = 22H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Even Field
Caption Data
If even field captioning is enabled and present, this register is loaded with the first eight bits of
caption data on line 281, 284, or 335. Bit 0 corresponds to the first bit of caption information. Data
written to this register is ignored.
33
RESET
STATE
80H
FN4643.4
July 29, 2009
HMP8117
TABLE 45. CLOSED CAPTION_EVEN_B DATA REGISTER
SUB ADDRESS = 23H
BIT
NO.
15-8
FUNCTION
DESCRIPTION
Even Field
Caption Data
If even field captioning is enabled and present, this register is loaded with the second eight bits
of caption data on line 281, 284, or 335. Data written to this register is ignored.
RESET
STATE
80H
TABLE 46. WSS_ODD_A DATA REGISTER
SUB ADDRESS = 24H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Odd Field
WSS Data
If odd field WSS is enabled and present, this register is loaded with the first eight bits of WSS
information on line 17, 20, or 23. Bit 0 corresponds to the first bit of WSS information. Data written
to this register is ignored.
RESET
STATE
00H
TABLE 47. WSS_ODD_B DATA REGISTER
SUB ADDRESS = 25H
BIT
NO.
FUNCTION
15-14
Reserved
13-8
Odd Field
WSS Data
DESCRIPTION
RESET
STATE
00B
If odd field WSS is enabled and present, this register is loaded with the second six bits of WSS
information on line 17, 20, or 23. Data written to this register is ignored.
000000B
TABLE 48. WSS_CRC_ODD DATA REGISTER
SUB ADDRESS = 26H
BIT
NO.
FUNCTION
7-6
Reserved
5-0
Odd Field
WSS CRC Data
DESCRIPTION
RESET
STATE
00B
If odd field WSS is enabled and present during NTSC operation, this register is loaded with the
six bits of CRC information on line 20. It is always a “000000” during PAL operation. Data written
to this register is ignored.
000000B
TABLE 49. WSS_EVEN_A DATA REGISTER
SUB ADDRESS = 27H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Even Field
WSS Data
If even field WSS is enabled and present, this register is loaded with the first eight bits of WSS
information on line 280, 283, or 336. Bit 0 corresponds to the first bit of WSS information. Data
written to this register is ignored.
RESET
STATE
00H
TABLE 50. WSS_EVEN_B DATA REGISTER
SUB ADDRESS = 28H
BIT
NO.
FUNCTION
15-14
Reserved
13-8
Even Field
WSS Data
DESCRIPTION
RESET
STATE
00B
If even field WSS is enabled and present, this register is loaded with the second six bits of WSS
information on line 280, 283, or 336. Data written to this register is ignored.
34
000000B
FN4643.4
July 29, 2009
HMP8117
TABLE 51. WSS_CRC_EVEN DATA REGISTER
SUB ADDRESS = 29H
BIT
NO.
FUNCTION
7-6
Reserved
5-0
Even Field
WSS CRC Data
DESCRIPTION
RESET
STATE
00B
If even field WSS is enabled and present during NTSC operation, this register is loaded with the
six bits of CRC information on line 283. It is always a “000000” during PAL operation. Data written
to this register is ignored.
000000B
TABLE 52. START H_BLANK LSB REGISTER
SUB ADDRESS = 30H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Assert BLANK
Output Signal
This 8-bit register is cascaded with Start H_BLANK High Register to form a 10-bit start horizontal
blank REGISTER. It specifies the horizontal count (in 1x clock cycles) at which to assert BLANK
each scan line. Bit 0 is always a “0”, so the start of horizontal blanking may only be done with two
pixel resolution. The leading edge of HSYNC is count 000H.
RESET
STATE
4AH
TABLE 53. START H_BLANK MSB REGISTER
SUB ADDRESS = 31H
BIT
NO.
15-10
9-8
FUNCTION
DESCRIPTION
Reserved
RESET
STATE
000000B
Assert BLANK
Output Signal
This 2-bit register is cascaded with Start H_BLANK Low Register to form a 10-bit start horizontal
blank register. It specifies the horizontal count (in 1x clock cycles) at which to assert BLANK each
scan line. The leading edge of HSYNC is count 000H.
11B
TABLE 54. END H_BLANK REGISTER
SUB ADDRESS = 32H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Negate BLANK
Output Signal
This 8-bit register specifies the horizontal count (in 1x clock cycles) to negate BLANK each scan
line. For proper operation, bit 0 must always be set to “0”; therefore, the end of horizontal
blanking may only set with two pixel resolution. If bit 0 is set to “1”, the chroma/luma output data
may be swapped. The leading edge of HSYNC is count 000H.
RESET
STATE
7AH
TABLE 55. START V_BLANK LSB REGISTER
SUB ADDRESS = 33H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Assert BLANK
Output Signal
This 8-bit register is cascaded with Start V_BLANK High Register to form a 9-bit start vertical
blank register. It specifies the line number to assert BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. For
PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields.
RESET
STATE
02H
TABLE 56. START V_BLANK MSB REGISTER
SUB ADDRESS = 34H
BIT
NO.
15-9
8
FUNCTION
DESCRIPTION
Reserved
RESET
STATE
0000000B
Assert BLANK
Output Signal
This 1-bit register is cascaded with Start V_BLANK Low Register to form a 9-bit start vertical
blank register.
35
1B
FN4643.4
July 29, 2009
HMP8117
TABLE 57. END V_BLANK REGISTER
SUB ADDRESS = 35H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Negate BLANK
Output Signal
This 8-bit register specifies the line number to negate BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. For
PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields.
RESET
STATE
12H
TABLE 58. END HSYNC REGISTER
SUB ADDRESS = 36H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Negate HSYNC
Output Signal
This 8-bit register specifies the horizontal count at which to negate HSYNC each scan line.
Values may range from 0 (0000 0000) to 510 (1111 1111) CLK2 cycles. The leading edge of
HSYNC is count 00H.
RESET
STATE
30H
TABLE 59. HSYNC DETECT WINDOW REGISTER
SUB ADDRESS = 37H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Horizontal Sync
Detect Window
This 8-bit register specifies the width of the timing window (in 1x clock samples) for the digital
PLL to accept horizontal sync pulses in each line. The window is centered about where the
horizontal sync pulse should be located.
If the horizontal sync pulse falls inside the window, the digital PLL maintains normal lock timing.
If the horizontal sync pulse falls outside this window, the digital PLL will to enter the horizontal
lock acquisition mode based on the current setting for bits 3-2 of register 04H. Recommend
changing this register to 90H following reset in order to widen the window for poorly timed input
video sources.
RESET
STATE
20H
(Use 90H)
TABLE 60. MV CONTROL
SUB ADDRESS = 41H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
MV Stripe Detection Set to “1” to enable the detection and bypass of the MV Color Striping component. If this bit is
and Bypass Enable not enabled and the MV Color Striping component exists on the input signal, artifacts will be
clearly visible as horizontal streaks in the output data. This bit must be enabled for the MV
Detection Status of register 0EH to be updated.
0B
6
MV PSP Detection
Enable
Set to “1” to enable detection of the MV Pseudo Sync Pulse (PSP)
component. If the MV PSP component exists on the input signal, this bit must be enabled for the
MV Detection Status of register 0EH to be updated.
0B
5-3
MV PSP Detection
Count
Defines the number of extra sync pulses required before declaring the Pseudo Sync Pulse (PSP)
component in the MV Detection Status of register 0EH. The PSP component must also be
present for the number of fields defined in bits 2-0 below.
100B
2-0
MV Detection
Field Count
Defines the minimum number of fields that an MV component must be present for in order to
change the MV Detection Status of register 0EH. Add 2 to bits 2-0 to obtain the minimum field
count. Ex: The default of 110B is actually 6 + 2 = 8 fields.
110B
TABLE 61. RESERVED
SUB ADDRESS = 42H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Reserved
Set bits 5-4 to 11B for optimum performance.
36
RESET
STATE
00H
(Use 30H)
FN4643.4
July 29, 2009
HMP8117
TABLE 62. PROGRAMMABLE FRACTIONAL GAIN
SUB ADDRESS = 50H
BIT
NO.
7-6
5
4-0
FUNCTION
DESCRIPTION
Reserved
Set to 00B for proper operation.
Select PFG Enable
Set to “1” to enable the recommended PFG value in bits 4-0 below.
PFG
Programmable Fractional Gain (PFG). When enabled by bit 5, changes the loop gain (response
time) of the AGC logic. Slower values provide some noise immunity to input signals with poor
sync/back-porch characteristics. Recommend using the slowest PFG value of 00001B for
optimum performance. (Thus the recommended 8-bit register value = 21H).
RESET
STATE
00B
0B
(Use 1B)
01100B
(Use 01H)
The 5-bit PFG value has a fractional representation as: 20. 2-1 2-2 2-3 2-4
Sample PFG values:
00000B: Gain = 0.0000 (freezes AGC at current value)
00001B: Gain = 0.0625 (slowest AGC response time -- recommended PFG)
01100B: Gain = 0.7500 (default)
10000B: Gain = 1.0000
11111B: Gain = 1.9375 (fastest AGC response time -- not recommended)
TABLE 63. MV STRIPE GATE
SUB ADDRESS = 51H
BIT
NO.
FUNCTION
DESCRIPTION
7-6
Reserved
Set to 00B for proper operation.
5-0
MV Stripe Gate
Defines the start of the gate for MV Color Stripe detection in 4xFSC counts. The gate should start
prior to the chroma burst. Default value of 010100B (14H) is valid for NTSC. Recommend
100000B (20H) for PAL.
RESET
STATE
00B
010100B
TABLE 64. RESERVED
SUB ADDRESS = 52H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Reserved
Set bit 5 to “1” for optimum performance.
RESET
STATE
02H
(Use 22H)
TABLE 65. AGC HYSTERESIS
SUB ADDRESS = 53H
BIT
NO.
FUNCTION
DESCRIPTION
7-4
3-0
Defines the amount of hysteresis in the AGC logic. Larger hysteresis values stabilize the AGC
with poor quality input signals. For example:
0000B = No Hysteresis
1000B = Default Hysteresis
1111B = Maximum Hysteresis (Recommended hysteresis value)
Reserved
Set to 0000B for proper operation.
RESET
STATE
1000B
(Use F0H)
0000B
TABLE 66. DEVICE REVISION
SUB ADDRESS = 7FH
BIT
NO.
FUNCTION
7-0
Device Revision
DESCRIPTION
This 8-bit register specifies the device revision number. Data written to this read-only register is
ignored. The production baseline revision number is 01H.
37
RESET
STATE
01H
FN4643.4
July 29, 2009
HMP8117
Pinout
GND
VCC
REF_CAP
NC
LCAP
VCC
NC
NC
GND
HSYNC
VSYNC
GND
VCC
FIELD
DVALID
BLANK
80 LEAD PQFP
TOP VIEW
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AGND
VAA
AGND
NC
CVBS3(Y)
CVBS2
CVBS1
YIN
YOUT
AGND
AGND
VAA
NC
VAA
AGND
AGND
A/D_TEST
NC
C
NC
AGND
AGND
AGND
AGND
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P15
P14
GND
VBIVALID
P13
VCC
P12
P11
P10
P9
P8
GND
VCC
P7
P6
P5
P4
P3
GND
P2
INTREQ
P1
P0
SCL
GND
VCC
SA
RSET
CCAP
NC
VCC
NC
GND
RESET
GND
GND
VCC
CLK2
GND
SDA
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pin Descriptions
PIN
NAME
PIN
NUMBER
CVBS1,
CVBS2,
CVBS3(Y)
7, 6, 5
YOUT
9
I/O
I
O
YIN
8
C
19
A/D TEST
17
RSET
28
REF_CAP
78
PASSIVE
DESCRIPTION
Composite Video Inputs. CVBS3(Y) is the Luminance (Y) signal in S-Video mode. These
inputs must each be terminated by a 75Ω resistor to AGND and AC-coupled by a 1.0µF
75Ω Term,
capacitor as shown in the Reference Schematic. These components should be as close to
1μF AC-coupled
this pin as possible for best performance. If not used, this pin should be connected to AGND
through a 0.1μF capacitor.
External AntiAlias Filter
I
Analog output of the video multiplexer. A external low-pass anti-alias filter between the
YOUT and YIN pins, as shown in the Reference Schematic. The filter components should
be as close as possible to the YOUT and YIN pins for best performance.
Analog input to the ADC. See YOUT description above.
Chrominance (C) S-Video input. This input must each be terminated by a 75Ω resistor to
AGND and AC-coupled by a 1.0μF capacitor as shown in the Reference Schematic. These
components, and the corresponding anti-alias low-pass filter, should be as close to this pin
as possible for best performance. If not used, this pin should be connected to AGND
through a 0.1μF capacitor.
I
75Ω Term,
1μF AC-coupled
and
External AntiAlias Filter
O
none
O
12.1kΩ
to AGND
A 12.1kΩ resistor must be connected between this pin and AGND. This resistor should be as
close to this pin as possible for best performance. The function of this pin has changed from
the HMP8112A/15 GAIN_CNTRL input. Do not use capacitor decoupling for this output pin.
O
1.0µF
to AGND
Voltage reference capacitor. A 1µF ceramic capacitor must be connected between this pin
and AGND. This capacitor should be as close to this pin as possible for best performance.
38
Chroma signal A/D test pin. This pin must be left floating for proper operation.
FN4643.4
July 29, 2009
HMP8117
Pin Descriptions
PIN
NAME
PIN
NUMBER
LCAP
76
CCAP
P0-P15
HSYNC
VSYNC
42, 43, 45,
47-51, 54-58,
60, 63, 64
PASSIVE
DESCRIPTION
I
0.1µF
to AGND
Storage capacitor for Luminance signal DC restoration. The LCAP voltage offsets the sync
tip to the lower reference of the A/D. A 0.1μF capacitor should be connected between this
pin and AGND. This capacitor should be as close to this pin as possible for best
performance.
I
0.1µF
to AGND
Storage capacitor for Chrominance signal DC restoration. The CCAP voltage offsets the
chroma signal to mid-range of the A/D. A 0.1μF capacitor should be connected between
this pin and AGND. This capacitor should be as close to this pin as possible for best
performance.
O
N/A
O
10kΩ Pullup
Horizontal sync output. HSYNC is asserted during the horizontal sync intervals. The
polarity of HSYNC is programmable. This pin is three-stated after a RESET or software
reset and should be pulled high through a 10kΩ resistor.
O
10kΩ Pullup
Vertical sync output. VSYNC is asserted during the vertical sync intervals. The polarity of
VSYNC is programmable. This pin is three-stated after a RESET or software reset and
should be pulled high through a 10kΩ resistor.
O
10kΩ Pullup
FIELD output. The polarity of FIELD is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10kΩ resistor.
O
10kΩ Pullup
Data valid output. DVALID is asserted during CLK2 cycles that contain valid pixel data. This
pin is three-stated after a RESET or software reset and should be pulled high through a
10kΩ resistor.
O
10kΩ Pullup
Composite blanking output. BLANK is asserted during the horizontal and vertical blanking
intervals. The polarity of BLANK is programmable. This pin is three-stated after a RESET
or software reset and should be pulled high through a 10kΩ resistor.
O
10kΩ Pullup
Vertical Blanking Interval Valid output. VBIVALID is asserted during CLK2 cycles that
contain valid VBI (Vertical Blanking Interval) data such as Closed Captioning, Teletext, and
WSS data. The polarity of VBIVALID is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10k resistor.
O
10kΩ Pullup
Interrupt Request Output. This is an open-drain output and requires an external 10kΩ pullup resistor to VCC.
Pixel output pins. See Table 3. These pins are three-stated after a RESET or software reset.
71
70
67
DVALID
66
VBIVALID
I/O
29
FIELD
BLANK
(Continued)
65
61
INTREQ
44
CLK2
38
RESET
34
SA
27
I
2x pixel clock input. This clock must be a continuous, free-running clock. Refer to Table 1
for allowable CLK2 frequencies for each video standard and aspect ratio. For best
performance, use termination resistor(s) to minimize pulse overshoot and reflections.
I
Reset control input. A logical zero for a minimum of four CLK2 cycles resets the device.
RESET must be a logical one for normal operation.
I
10kΩ Pullup
or
0Ω Pulldown
I2C slave address select input. This was formerly the WPE pin on HMP8112/15 decoders.
If the SA pin is pulled low, the I2C address is 1000100xB or 88H. If the SA pin is pulled high,
the address is 1000101xB or 8AH. (The ‘x’ bit is the address is the I2C read flag.)
SDA
40
I/O
4kΩ Pullup
I2C data input/output. This pin should be pulled high through a 4kΩ resistor.
SCL
41
I
4kΩ Pullup
I2C clock input. This pin should be pulled high through a 4kΩ resistor.
VAA
2, 12, 14
0.1µF
to AGND
Analog power supply pins. All VAA pins must be connected together.
I
1, 3, 10, 11,
15,16, 21, 22,
23, 24
I
none
VCC
26, 31,37, 52,
59, 68, 75, 79
I
GND
25, 33, 35, 36,
39, 46, 53, 62,
69, 72, 80
I
AGND
NC
Analog ground pins. All AGND pins must be connected together. Refer to Applications
section for recommended grounding scheme.
Digital power supply pins. All VCC pins must be connected together.
Digital ground pins. All GND pins must be connected together.
No Connect pins. These pins may be left floating or tied to GND.
4, 13, 18,
20, 30, 32,
73, 74, 77
39
FN4643.4
July 29, 2009
HMP8117
Applications Information
Direct Interface to Video Encoders
Direct interface to a video encoder will induce pixel jitter in
the output video and is therefore not recommended as a
primary data interface. The jitter will occur with all decoder
output formats, including BT.656. However, pixel jitter may
be acceptable for some applications; such as a “preview
mode” prior to image capture or compression. For more
detail, reference“Cycle Slipping and Real-Time Pixel Jitter”
on page 7.
Decoder Upgrades
The following table describe the impacts to pins for
upgrading from the HMP8112/A or HMP8115 to the
HMP8117.
TABLE 67. UPGRADING FROM HMP8112/A OR HMP8115
Pin #
HMP8112/15 Pin
HMP8117 Impact
28
GAIN_CNTL
(Now RSET)
Use single 12.1k resistor to AGND.
Remove any decoupling caps.
78
DEC_T
(Now REF_CAP)
Change to single 1.0uF capacitor
(1206-size XR7-type) to AGND.
29
CCLAMP_CAP
(Now CCAP)
Change to 0.1uF capacitor.
76
LCLAMP_CAP
(Now LCAP)
Change to 0.1uF capacitor.
9,8,19
L_OUT,
L_ADIN, and C
Recommend use of new anti-alias
filter from Reference Schematic.
27
WPE
(Now SA)
Pull low for I2C address compatibility
with HMP8112/A.
44
DVCC/NC
(Now INTREQ)
Pin actually NC on HMP8112/A.
Float or use 10K pullup to VCC.
61
DGND/NC
(Now VBIVALID)
Pin actually NC on HMP8112/A.
Float or use 10K pullup to VCC.
13
CLK2
(Now NC)
Trace may be deleted to reduce
reflections on CLK2 at pin 38.
30, 32, DEC_L, DGND,
Pins no longer used (NC). Capacitors
73, 77 DGND, AGC_CAP used at these pins may be removed.
Typical Programming Sequence
The following pseudo code provides a typical programming
sequence to initialize the HMP8117 using the default 16-bit
YCbCr output data format.
SetReg 0x1F = 0x80 // Soft Reset
SetReg 0x37 = 0x90 // Wider HSYNC Detect Window
SetReg 0x42 = 0x30 // Recommended Value
SetReg 0x50 = 0x21 // Slower PFG
SetReg 0x52 = 0x22 // Recommended Value
SetReg 0x53 = 0xF0 // Large AGC Hysteresis
SetReg 0x03 = 0xC0 // Enable Data/Timing Outputs
PCB Layout Considerations
A PCB board with a minimum of 4 layers is recommended,
with layers 1 and 4 (top and bottom) for signals and layers
2 and 3 for power and ground. The PCB layout should
40
implement the lowest possible noise on the power and
ground planes by providing excellent decoupling. The
optimum layout places the HMP8117 as close as possible
to the power supply connector and the video input
connector. Place external components as close as possible
to the appropriate pin using short, wide traces.
ANALOG POWER PLANE
The analog power plane (VAA) is recommended to be
separate from the common board digital power plane (VCC)
with a gap between the two planes of at least 1/8 inch. The
VAA plane should be connected to the VCC plane at a single
point though a low-resistance ferrite bead, such as a
Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK
BF45-4001. The ferrite bead provides resistance to
switching currents, improving the performance of HMP8117.
If a separate linear regulator is used to provide power to the
analog power plane, the power-up sequence should be
designed to ensure latch up will not occur. A separate linear
regulator is recommended if the power supply noise on the VAA
pins exceeds 200mV.
ANALOG GROUND PLANE
A separate analog ground (AGND) plane is recommended
with a single point connection to the digital ground (GND)
plane using a ferrite bead as mentioned above.
POWER SUPPLY DECOUPLING
Decouple each VAA and VCC pin to the appropriate ground
plane using a 0.1μF ceramic chip capacitor. Bulk decouple
the power planes using a 1.0μF ceramic chip capacitor
located at each corner of the device. (One capacitor placed
at the top left corner for VAA and three capacitors placed at
the other corners for VCC.) A single 47μF decoupling
capacitor for the analog power plane may also be used to
control excessive low-frequency power supply ripple. See
Figure 20, HMP8117 Reference Schematics.
ANALOG SIGNALS
Traces containing digital signals should not be routed over,
under, or adjacent to the analog output traces to minimize
cross-talk. If this is not possible, coupling can be minimized
by routing the digital signals at a 90 degree angle to the
analog signals. The analog traces should also not overlay
the VCC power plane to maximize high-frequency power
supply rejection.
Evaluation Board
HMPVIDEVAL/ISA
The HMPVIDEVAL/ISA board provides a complete video
frame-grabber platform to evaluate all modes of the video
decoder and encoder. The ISA style PC add-in board
supports a complete Windows 95 software application to
easily operate all features of the evaluation platform.
FN4643.4
July 29, 2009
HMP8117
Related Application Notes
Application Notes are also available on the Intersil
Multimedia web site at http://www.intersil.com/mmedia.
AN9644: Composite Video Separation Techniques
AN9716: Wide Screen Signalling
AN9717: YCbCr to RGB Considerations
AN9728: BT.656 Video Interface for ICs
AN9806: Advantages of the HMP8117 Videolyzer Operation
EXTERNAL 75Ω
VIDEO SOURCES
75
C1
1.0μF
7
VID1
VID2
C2
1.0μF
6
Y_IN
C3
1.0μF
5
75
75
R3
75
R2
75
CVBS1
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
CVBS2
CVBS3(Y)
R1
75
LUMA ANTI-ALIAS FILTER
9
L1
R4
8.2μH
324
YIN
HMP8117
L2
R7
C6
324
1.0μF
C7
22pF
19
8.2μH
R9
4K
HSYNC
C
VSYNC
C8
47pF
FIELD
DVALID
BLANK
76
C9
0.1μF
29
C10
0.1μF
LCAP
VBIVALID
28
RSET
VCC
SDA
SCL
JP1: ADDRESS
SELECT JUMPER
R11
38
BULK
DECOUPLING
RESET
CLK2
SERIES TERMINATION
NEAR CLK2 SOURCE
100
DIGITAL - VCC
DECOUPLING
C18
C19
C20
C21
C22
C23
C24
C25
C26
1.0μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
BOT LEFT
PIN 26
PIN 31
PIN 37
PIN 52
PIN 59
PIN 68
PIN 72
PIN 79
NEAR
FERRITE
BOT RIGHT
47μF
TOP LEFT
1.0μF
C27
1.0μF
PIN 14
GND
INTREQ
C17
C15
0.1μF
PIN 12
AGND
VBIVALID
TOP RIGHT
C14
0.1μF
PIN 1
FERRITE
BEAD
BLANK
61
1.0μF
C13
0.1μF
L4
DVALID
65
C16
C12
FERRITE
BEAD
FIELD
66
34
CLK2
L3
VSYNC
67
27
RESET
VAA
HSYNC
70
41
SA
REF_CAP
R8
12.1K
ANALOG - VAA
DECOUPLING
71
40
SCL
C11
1.0μF
R10
4K
INTREQ 44
CCAP
SDA
78
VCC
VCC
VCC RP1
10K
CHROMA ANTI-ALIAS FILTER
C_IN
R6
75
YOUT
R5
4.02K
C5
47pF
C4
22pF
FROM
75Ω
SOURCE
8
P[15:0]
64
63
60
58
57
56
55
54
51
50
49
48
47
45
43
42
FIGURE 20. HMP8117 REFERENCE SCHEMATICS
41
FN4643.4
July 29, 2009
HMP8117
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage (VCC to GND) . . . . . . . . . . . . . . . . . . . . 7.0V
Analog Supply Voltage (VAA to GND) . . . . . . . . . . . . . . . . . . . 7.0V
Digital Input Voltages . . . . . . . . . . . . . . . GND - 0.5V to VCC + 0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, See Note 41)
θJA (°C/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
Maximum Power Dissipation
HMP8117CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.78W
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperatures . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
Operating Temperature Range
HMP8117CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
41. θJA is measured with the component mounted on an evaluation PC board in free air. Dissipation rating assumes device is mounted with all leads
soldered to printed circuit board.
Electrical Specifications
VCC = VAA = 5.0V, TA = +25°C
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNITS
4.75
5
5.25
V
279
305
mA
POWER SUPPLY CHARACTERISTICS
Power Supply Voltage Range
VCC , VAA
Total Power Supply Current
ITOT
Digital Power Supply Current
ICC
Analog Power Supply Current
Total Power Dissipation
(Note 42)
CLK2 = 29.5MHz,
VCC = VAA = 5.25V
Outputs Not Loaded
132
mA
IAA
147
mA
PTOT
1.46
1.60
W
DC CHARACTERISTICS: DIGITAL I/O (EXCEPT CLK2 and I2C INTERFACE)
Input Logic High Voltage
VIH
VCC = Max
Input Logic Low Voltage
VIL
VCC = Min
Output Logic High Voltage
VOH
IOH = -4mA, VCC = Max
Output Logic Low Voltage
VOL
IOL = 4mA, VCC = Min
Input Leakage Current
IIH, IIL
Input/Output Capacitance
CIN , COUT
Three-State Output Current
Leakage
VCC = Max,
Input = 0V or 5V
2.0
0.8
2.4
V
V
-
0.4
V
-10
± 10
μA
-
pF
10
μA
8
f = 1MHz (Note 42)
All Measurements Referenced to
Ground, TA = +25°C
IOZ
V
-10
DC CHARACTERISTICS: CLK2 DIGITAL INPUT
Input Logic High Voltage
VIH
VCC = Max
Input Logic Low Voltage
VIL
VCC = Min
Input Leakage Current
IIH
VCC = Max
Input = 0V or VCC
IIL
Input Capacitance
CIN
CLK2 = 1MHz (Note 42)
All Measurements Referenced to
Ground, TA = +25°C
Input Logic High Voltage
VIH
VCC = Max
Input Logic Low Voltage
VIL
VCC = Min
0.7xVCC
V
-10
0.3xVCC
V
10
μA
μA
-450
-
8
-
pF
DC CHARACTERISTICS: I2C INTERFACE
Output Logic High Voltage
VOH
IOH = -1mA, VCC = Max
Output Logic Low Voltage
VOL
IOL = 3mA, VCC = Min
42
0.7xVCC
V
0.3xVCC
3.0
0
V
V
0.4
V
FN4643.4
July 29, 2009
HMP8117
Electrical Specifications
VCC = VAA = 5.0V, TA = +25°C (Continued)
PARAMETER
SYMBOL
Input Leakage Current
IIH, IIL
Input/Output Capacitance
CIN, COUT
TEST CONDITION
MIN
TYP
VCC = Max, Input = 0V or 5V
MAX
UNITS
10
μA
8
SCL = 400kHz, (Note 42) All
Measurements Referenced to GND,
TA = +25°C
pF
AC CHARACTERISTICS: DIGITAL I/O (EXCEPT I2C INTERFACE)
CLK2 Frequency
CLK2 Waveform Symmetry
(Note 42)
24.54
29.5
MHz
40
60
%
CLK2 Pulse Width High
tPWH
13
ns
CLK2 Pulse Width Low
tPWL
13
ns
10
ns
ns
Data and Control Setup Time
tSU
Data and Control Hold Time
tHD
0
tDVLD
0
23
ns
1
12
ns
400
kHz
CLK2 to Output Delay
Data and Control Rise/Fall Time
tr , tf
(Note 43)
(Note 42)
AC CHARACTERISTICS: I2C INTERFACE
SCL Clock Frequency
fSCL
0
SCL Pulse Width Low
tLOW
1.3
μs
SCL Pulse Width High
tHIGH
0.6
μs
Data Hold Time
tHD:DATA
0
ns
Data Setup Time
tSU:DATA
100
ns
SDA, SCL Rise Time
tR
SDA, SCL Fall Time
tF
(Note 42)
300
ns
300
ns
ANALOG INPUT PERFORMANCE
Composite Video Input Amplitude
(Sync Tip to White Level)
Input Termination of 75Ω and 1.0μF
AC-Coupled
0.5
1.0
2.0
VP-P
Luminance (Y) Video Input
Amplitude (Sync Tip to White Level)
Input Termination of 75Ω and 1.0μF
AC-Coupled
0.5
1.0
2.0
VP-P
Chrominance (C) Video Input
Amplitude (Burst Amplitude)
Input Termination of 75Ω and 1.0μF
AC-Coupled, (Note 42)
0.143
0.286
0.6
VP-P
Video Input Impedance
RAIN
Video Input Bandwidth
BW
ADC Input Range
(Note 42)
1VP-P Sine Wave Input to
-3dBc Reduction, (Note 42)
200
kΩ
5
MHz
AIN FULL SCALE
1
VP-P
AIN OFFSET
1.5
V
±2
LSB
± 0.35
LSB
2
%
1
Deg.
2
Deg.
2
%
NTC-7 Composite (Note 42)
2
%
Pedestal Input (Note 42)
50
dB
ADC Integral Nonlinearity
INL
ADC Differential Nonlinearity
DNL
Best Fit Linearity
VIDEO PERFORMANCE
Differential Gain
DG
Differential Phase
DP
Hue Accuracy
Modulated Ramp (Note 42)
75% Color Bars (Note 42)
Color Saturation Accuracy
Luminance Nonlinearity
SNR
SNRL WEIGHTED
43
FN4643.4
July 29, 2009
HMP8117
Electrical Specifications
VCC = VAA = 5.0V, TA = +25°C (Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
2
3
MAX
UNITS
GENLOCK PERFORMANCE
Horizontal Locking Time
tLOCK
Long-Term horizontal Sync
Lock Range
Time from Initial Lock
Acquisition to an Error of
1 Pixel. (Note 42)
Range over specified pixel jitter is
maintained. Assumes line time changes
by amount indicated slowly between
over one field. (Note 42)
Number of Missing Horizontal Syncs
Before Lost Lock Declared
HSYNC LOST
Number of Missing Vertical Syncs
Before Lost Lock Declared
VSYNC LOST
Programmable via register 04H
(Note 42)
Long-Term Color Subcarrier
Lock Range
Range over color subcarrier locking
time and accuracy specifications are
maintained. Subcarrier frequency
changes by amount indicated slowly
over 24 hours. (Note 42)
Vertical Sample Alignment
(Notes 42, 44)
±-
Fields
5
%
1 or 12
1 or 12
1 or 12
HSYNCs
1 or 3
1 or 3
1 or 3
VSYNCs
±200
±400
Hz
1/8
Pixel
10
ns
NOTES:
42. Guaranteed by design or characterization.
43. Test performed with CL = 40pF, IOL = 4mA, IOH = -4mA. Input reference level is 1.5V for all inputs. VIH = 3.0V, VIL = 0V.
44. Since the HMP8117 does not generate the sample clock, any clock jitter present on the CLK2 input will directly translate to pixel jitter on the
output data. The Vertical Sample Alignment parameter specifies the spatial pixel alignment from one scan line to the next using a stable CLK2
source.
44
FN4643.4
July 29, 2009
HMP8117
Metric Plastic Quad Flatpack Packages (MQFP)
D
Q80.14x20 (JEDEC MS-022GB-1 ISSUE B)
80 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
INCHES
SYMBOL
-A-
-B-
E E1
e
PIN 1
SEATING
A PLANE
-H-
0.076
0.003
-C-
12o-16o
0.40
0.016 MIN
0.20
M
0.008
C A-B S
0o MIN
D S
b
L
b1
MIN
MAX
NOTES
A
-
A1
0.010
0.134
-
3.40
-
-
0.25
-
-
A2
0.098
0.114
2.50
2.90
-
b
0.012
0.018
0.30
0.45
6
b1
0.012
0.016
0.30
0.40
-
D
0.908
0.918
23.08
23.32
3
D1
0.782
0.792
19.88
20.12
4, 5
E
0.673
0.681
17.10
17.30
3
E1
0.547
0.555
13.90
14.10
4, 5
L
0.029
0.040
0.73
1.03
-
N
80
80
7
e
0.032 BSC
0.80 BSC
-
ND
24
24
-
NE
16
16
Rev. 1 4/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
BASE METAL
WITH PLATING
3. Dimensions D and E to be determined at seating plane -C- .
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
0.13/0.17
0.005/0.007
12o-16o
MAX
2. All dimensions and tolerances per ANSI Y14.5M-1982.
A2 A1
0o-7o
MILLIMETERS
MIN
0.13/0.23
0.005/0.009
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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45
FN4643.4
July 29, 2009
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