AN-669: Effectively Applying the AD628 Precision Gain Block (Rev. 0)

AN-669
APPLICATION NOTE
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EFFECTIVELY APPLYING THE AD628 PRECISION GAIN BLOCK
By Moshe Gerstenhaber and Charles Kitchin
Introduction
The AD628 can be operated as either a differential/
scaling amplifier or as a pin-strapped precision gain
block. Specifically designed for use ahead of an analogto-digital converter, the AD628 is extremely useful as an
input scaling and buffering amplifier. As a differential
amplifier, it can extract small differential voltages riding
on large common-mode voltages up to ±120 V. As a
prepackaged precision gain block, the pins of the AD628
can be strapped to provide a wide range of precision
gains, allowing for high accuracy data acquisition with
very little gain or offset drift.
The AD628 uses an absolute minimum of external components. Its tiny MSOP provides these functions in the
smallest size package available in the market. Besides
high gain accuracy and low drift, the AD628 provides a
very high common-mode rejection, typically more than
90 dB at 1 kHz while still maintaining a 60 dB CMRR at
100 kHz.
The AD628 includes a VREF pin to allow a dc (midscale)
offset for driving single-supply ADCs. In this case, the
VREF pin may simply be tied to the ADC’s reference pin,
which also allows easy ratio-metric operation.
Why Use a Gain Block IC?
Real - world measurement requires extracting weak
signals from noisy sources. Even when a differential
measurement is made, high common-mode voltages
are often present. The usual solution is to use an op amp
or, better still, an in amp, and then perform some type of
low-pass filtering to reduce the background noise level.
The problem with this traditional approach is that a
discrete op amp circuit will have poor common-mode
rejection and its input voltage range will always be less
than the power supply voltage. When used with a differential signal source, an in amp circuit using a monolithic
REV. 0
IC will improve common-mode rejection. However, signal
sources greater than the power supply voltage or signals
riding on high common-mode voltages can't handle standard in amps. In addition, in amps using a single external
gain resistor suffer from gain drift. Finally, low-pass filtering usually requires the addition of a separate op amp,
along with several external components. This drains valuable board space.
The AD628 eliminates these common problems by functioning as a scaling amplifier between the sensor, the
shunt resistor, or other point of data acquisition, as well
as the ADC. Its 120 V max input range permits the direct
measurement of large signals, or small signals riding on
large common-mode voltages.
Standard Differential Input ADC Buffer Circuit with
Single-Pole LP Filter
Figure 1 shows the AD628 connected to accept a differential input signal riding on a very high common-mode
voltage. The AD628 gain block has two internal amplifiers: A1 and A2. Pin 3 is grounded, thus operating
amplifier A1 at a gain of 0.1. The 100 k input resistors
and other aspects of its design allow the AD628 to
process small input signals riding on common-mode
voltages up to ±120 V.
The output of A1 connects to the plus input of amplifier
A2 through a 10 k resistor. Pin 4 allows connecting an
external capacitor to this point, providing single-pole
low-pass filtering.
Changing the Output Scale Factor
Figure 1 reveals that the output scale factor of the AD628
may be set by changing the gain of amplifier A2. This
uncommitted op amp may be operated at any convenient
gain higher than unity. When configured, the AD628 may
be set to provide circuit gains between 0.1 and 1000.
AN-669
C1
+15V
0.1F
CFILTER
4
+VS
10k
DIFFERENTIAL
INPUT SIGNAL
100k
8
AD628
– IN
10k
A1
VIN
100k
1
A2
+ IN
–VS
VOUT
TO ADC
+ IN
VREF
2
5
– IN
10k
VCM
7
RG
3
6
0.1F
RF
RG
–15V
Figure 1. Basic Differential Input Connection with Single Pole LP Filter
Since the gain of A1 is 0.1, the combined gain of A1 and
A2 equals:
(
the circuit may be operated from ±2.25 V to ±18 V dual
supplies. This VREF pin may also be used to allow singlesupply operation; VREF may simply be biased at VS /2.
)
VOUT
= G = 0.1 1 + (R F / RG )
VIN
Using an External Resistor to Operate the AD628 at
Gains Below 0.1
The AD628 gain block may be modified to provide any
desired gain from 0.01 to 0.1, as shown in Figure 2.
Therefore:
(10G – 1) =
RF
RG
This connection is the same as the basic wide input
range circuit of Figure 1, but with Pins 5 and 6 strapped,
and with an external resistor RG connection between
Pin 4 and ground. The pin strapping operates amplifier
A2 at unity gain. Acting with the on-chip 10 k resistor
at the output of A1, RGAIN forms a voltage divider that
attenuates the signal between the output of A1 and the
input of A2. The gain for this connection equals 0.1 VIN
((10 k + RG)/RG).
For ADC buffering applications, the gain of A2 should
be chosen so the voltage driving the ADC is close to its
full-scale input range. The use of external resistors RF
and RG to set the output scale factor (i.e., gain of A2) will
degrade gain accuracy and drift essentially to the resistors themselves.
A separate VREF pin is available for offsetting the AD628
output signal, so it is centered in the middle of the
ADC’s input range. Although Figure 1 indicates ±15 V,
RG
+15V
0.1F
7
4
CFILTER
+VS
10k
DIFFERENTIAL
INPUT SIGNAL
8
100k
AD628
– IN
10k
A1
VIN
1
100k
+ IN
A2
–VS
2
5
– IN
10k
VCM
VOUT
TO ADC
+ IN
VREF
RG
3
6
0.1F
–15V
Figure 2. AD628 Connection for Gains Less Than 0.1
–2–
REV. 0
AN-669
+15V
C1
0.1F
CFILTER
0.1F
7
4
+VS
10k
DIFFERENTIAL
INPUT SIGNAL
8
AD628
100k
–
IN
10k
A1
VIN
100k
+
1
– IN
–VS
RG
VREF
2
5
A2
IN
10k
VCM
VOUT
TO ADC
+ IN
3
6
C2
0.1F
RG
–15V
RF
Figure 3. Differential Input Circuit with Two-Pole Low-Pass Filtering
Figure 4 shows the filter’s output versus frequency using
components chosen to provide a 200 Hz –3 dB corner
frequency. There is a sharp roll-off between the corner
frequency and approximately 10 the corner frequency.
Above this point, the second pole starts to become less
effective and the rate of attenuation is close to that of a
single-pole response.
Differential Input Circuit with Two-Pole Low-Pass Filtering
The circuit in Figure 3 is a modification of the basic ADC
interface circuit. Here, two-pole low-pass filtering is
added for the price of one additional capacitor (C2).
As before, the first pole of the low-pass filter is set by
the internal 10 k resistor at the output of A1 and the
external capacitor C1. The second pole is created by an
external RC time constant, in the feedback path of A2,
consisting of capacitor C2 across resistor RF. Note that
this second pole provides a more rapid roll-off of frequencies above its RC “corner” frequency (1/(2RC))
than a single - pole LP filter. However, as the input
frequency is increased, the gain of amplifier A2 eventually drops to unity and will not be further reduced. So,
amplifier A2 will have a voltage gain set by the ratio of
RF /RG at frequencies below its –3 dB corner and have
unity gain at higher frequencies.
TABLE I
Two-Pole LP Filter
Input Range: 10 V p-p F.S. for a 5 V p-p Output
RF = 49.9 k, RG = 12.4 k
–3 dB Corner Frequency
Capacitor C2
Capacitor C1
1 kHz
5 kHz
10 kHz
0.01 F
0.047 F
0.002 F
0.01 F
390 pF
0.002 F
220 pF
0.001 F
TABLE II
Two-Pole LP Filter
Input Range: 20 V p-p F.S. for a 5 V p-p Output
RF = 24.3 k, RG = 16.2 k
����
������������������������
���������������������������
����������������������
200 Hz
���
–3 dB Corner Frequency
Capacitor C2
Capacitor C1
����
����
��
���
��
��������������
���
1 kHz
5 kHz
10 kHz
0.02 F
0.047 F
0.0039 F
0.01 F
820 pF
0.002 F
390 pF
0.001 F
Tables I and II provide typical filter component values for
various –3 dB corner frequencies and two different fullscale input ranges. Values have been rounded off to
match standard resistor and capacitor values. Capacitors
C1 and C2 need to be high Q, low drift devices; low
grade disc ceramics should be avoided. High quality
NPO ceramic, Mylar, or polyester film capacitors are
recommended for the lowest drift and best settling time.
����
Figure 4. Frequency Response of the Two-Pole LP Filter
REV. 0
200 Hz
–3–
AN-669
The input signal is applied between the VREF pin (Pin 3)
and ground. With the input tied to Pin 3, the voltage at
the positive input of A1 equals VIN (100 k/110 k) which
is VIN (10/11). With Pin 6 grounded, the minus input of
A2 equals 0 V. Therefore, the positive input of A2 will be
forced by feedback from the output of A2 to be 0 V as
well. The output of A1 must then also be at 0 V. Since the
negative input of A1 must be equal to the positive input
of A1, both will equal VIN (10/11).
Using the AD628 to Create Precision Gain Blocks
Real-world data acquisition systems require amplifying
weak signals enough to apply them to an ADC. Unfortunately, when configured as gain blocks, most common
amplifiers have both gain errors and offset drift.
In op amp circuits, the usual two resistor gain setting
arrangement has accuracy and drift limitations. Using
standard 1% resistors, amplifier gain can be off by 2%.
The gain will also vary with temperature because each
resistor will drift differently. Monolithic resistor networks
can be used for precise gain setting, but these components increase cost, complexity, and board space.
This means that the output voltage of A2 (VOUT) will equal
VOUT = VIN (10 / 11) (1 + 100 k / 10 k ) =
VIN (10 / 11) 11 = 10 VIN
The gain block circuits of Figures 5 to 9 overcome all of
these performance limitations, are very inexpensive, and
offer a single MSOP solution. The AD628 provides this
complete function using the smallest IC package available. Since all resistors are internal to the AD628 gain
block, both accuracy and drift are excellent.
The companion circuit in Figure 6 provides a gain of –10.
This time, the input is applied between the negative
input of A2 (Pin 6) and ground. Operation is exactly the
same but now the input signal is inverted 180° by A2.
With Pin 3 grounded, the positive input of A1 is at 0 V,
so feedback will force the negative input of A1 to zero as
well. Since A1 operates at a gain of 1/10 (0.1), the output
of A2 that is needed to force the negative input of A1
to zero is minus 10 VIN.
All of these pin-strapped circuits (using no external
components) have a gain accuracy better than 0.2%,
with a gain TC better than 50 ppm/°C.
Operating the AD628 as a +10 or –10 Precision Gain Block
Figure 5 shows an AD628 precision gain block IC connected to provide a voltage gain of +10. The gain block
may be configured to provide different gains by strapping or grounding the appropriate pin. The gain block
itself consists of two internal amplifiers: a gain of 0.1
difference amplifier (A1) followed by an uncommitted
buffer amplifier (A2).
The two connections will have different input impedances.
When driving Pin 3 (Figure 5), the input impedance to
ground is 110 k, while it is approximately 50 G when
driving Pin 6 (Figure 6). The –3 dB bandwidth for both
circuits is approximately 110 kHz for 10 mV and 95 kHz
for 100 mV input signals.
+15V
0.1F
CFILTER
4
+VS
10k
100k
8
100k
1
–
+
AD628
IN
A1
10k
+ IN
A2
IN
– IN
10k
–VS
2
7
3
5
VOUT
RG
VREF
6
0.1F
–15V
VIN
Figure 5. Circuit with a Gain of +10 Using No External Components
–4–
REV. 0
AN-669
+15V
0.1F
7
4
CFILTER
+VS
10k
100k
8
100k
1
AD628
– IN
10k
A1
+
+ IN
IN
A2
5
VOUT
– IN
10k
–VS
2
3
RG
VREF
6
0.1F
–15V
VIN
Figure 6. Companion Circuit Providing a Gain of –10
input through approximately a 9 k resistor. Note that
this series resistance is negligible compared to the very
high input impedance of amplifier A1. The gain from
Pin 8 to the output of A1 is 0.1. Therefore, feedback will
force the output of A2 to equal 10 VIN. The –3 dB bandwidth of this circuit is approximately 105 kHz for 10 mV
and 95 kHz for 100 mV input signals.
Operating the AD628 at a Precision Gain of +11
The gain of +11 circuit (Figure 7) is almost identical to the
gain of +10 connection, except that Pin 1 is strapped to
Pin 3, rather than being grounded. This connects the two
internal resistors (100 k and 10 k) that are tied to the
plus input of A1 in parallel. So, this now removes the
10 k/110 k voltage divider between VIN and the positive input of A1. Thus modified, V IN drives the positive
7
4
CFILTER
+VS
10k
8
100k
AD628
– IN
10k
A1
1
100k
+
+ IN
IN
A2
– IN
10k
–VS
2
3
RG
VREF
6
VIN
Figure 7. A Gain of +11 Circuit
REV. 0
–5–
5
VOUT
AN-669
Operating the AD628 at a Precision Gain of +1
Figure 8 shows the AD628 connected to provide a precision gain of +1. As before, this connection uses the gain
block’s internal resistor networks for high gain accuracy
and stability.
Increased BW Gain Block of –9.91 Using Feed Forward
The circuit of Figure 6 can be modified slightly by applying a small amount of positive feedback to increase its
bandwidth, as shown in Figure 9. The output of amplifier
A1 feeds back its positive input by connecting Pins 4 and
1 together. Now, Gain = –(10 – 1/11)= –9.91
The input signal is applied between the VREF pin and
ground. As Pins 1 and 8 are grounded, the input signal
runs through a 100 k /110 k input attenuator to the
plus input of A1. The voltage equals VIN (10/11) = 0.909 VIN.
The gain from this point to the output of A1 will equal
1 + (10 k /100 k) = 1.10. Therefore, the voltage at the
output of A1 will equal VIN (1.10) (0.909) = 1.00. Amplifier
A2 is operated as a unity gain buffer (as Pins 5 and 6 tied
together), providing an overall circuit gain of +1.
The resulting circuit is still stable because of the large
amount of negative feedback applied around the entire
circuit (from the output of A2 back to the negative input
of A1). This connection actually results in a small signal
–3 dB bandwidth of approximately 140 kHz. This is a 27%
increase in bandwidth over the unmodified circuit in
Figure 6. However, gain accuracy is reduced to ±2%.
+15V
0.1F
CFILTER
7
4
+VS
10k
100k
8
AD628
– IN
10k
+ IN
A1
100k
1
+
IN
–
10k
–VS
2
5
RG
VREF
3
VOUT
A2
IN
6
0.1F
–15V
VIN
Figure 8. AD628 Precision Gain of +1
7
4
CFILTER
+VS
10k
8
100k
–
AD628
IN
10k
A1
1
100k
+
+ IN
IN
A2
– IN
10k
–VS
2
VREF
3
5
VOUT
RG
6
VIN
Figure 9. Precision –10 Gain Block with Feed Forward
–6–
REV. 0
–7–
E04332–0–7/03(0)
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–8–
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