R8A66173SP REJ03F0264-0100 Rev.1.00 Jan.24.2008 4-CH 12-BIT PWM GENERATOR DESCRIPTION R8A66173 has four 12-bit PWM (Pulse Width Modulation) circuits which are built by using the CMOS process. This IC controls PWM waveform by adjusting the “H” width according to serial data sent from MCU (Micro Controller Unit) or other device. Each channel can be independently controlled. High-resolution digital-analog (D-A) converter can be formed easily by connecting a low-pass filter (LPF) circuit to the output pins of this circuit. R8A66173 is the succession product of M66242. FEATURES ● Built-in four 12-bit high-resolution PWM circuits ● Easy D-A conversion – Quick output waveform smoothing Control by 1.22mV possible per step (VCC=5V range) ● Serial data input ●“H” level width setting type ● 4 channels controlled independently ● All 4 channels reset by reset input (R), High-impedance status after reset ● All 4 channels controlled by output control input (OC) ● Settings take effect after ongoing cycle is completed ● Output : CMOS 3-state output Output current Io=±4mA (Vcc=5.0V range), Io=±2mA (Vcc=3.3V range) ● Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V, single power supply) ● Wide operating temperature range: Ta=-40oC~+85 oC APPLICATION ● Analog signal control in televisions and audio systems ● Control of lamps, heaters and motors ● For software servo in home appliances and industrial machinery PIN CONFIGURATION (TOP VIEW) CHIP SELECT CS 1 14 Vcc RESET R 2 13 PWM1 WRITE CONTROL WR 3 12 PWM2 SERIAL DATA INPUT SIN 4 11 PWM3 WRITE CLOCK Sc LK 5 10 PWM4 OUTPUT CONTROL OC 6 9 XOUT CLOCK OUTPUT GND 7 8 XIN CLOCK INPUT OUTPUT REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 1 of 12 R8A66173SP BLOCK DIAGRAM (EACH CHANNEL) Upper byte register SIN 4 SCLK 5 1 WR 3 R 2 OC 6 Vcc 13 PWM1 12 PWM2 11 PWM3 10 PWM4 8-bit PWM circuit Input register PWM register 12-bit PWM circuit 4-bit-rate multiplier Low er byte register CS 14 Control circuit 1/2 divider To other channels Oscillation circuit 8 XIN 9 XOUT 7 GND FUNCTION The PWM output waveform of each channel is controlled by taking in PWM data from MCU or other device via serial data input SIN. 12-bit PWM data is input being divided between upper 8-bits (upper byte) and lower 4-bits. The lower 4-bit data is combined with command data such as channel designation and input as 8-bit data (lower byte). The lower byte should be written first, and then the upper byte. Even if only the upper byte is to be changed, rewrite from the lower byte. The PWM waveform changes according to the new setting from the next cycle. One cycle of PWM waveform (=4096 divisions; 12-bit resolution) are divided into 16 (24) subsections t. Each subsection consists of 256 (=28; 8-bit resolution) minimum bits τ(=2/fXIN**). One subsection t consists of an 8-bit PWM waveform (basic waveform). The “H” width of this waveform is determined according to the upper 8-bits of PWM data. One cycle has 16 subsections t, each of which has this basic waveform. Among them, those which are designated by the 4-bit-rate multiplier are conditioned to have a “H” width that is longer by τ. The lower 4-bits of PWM data are used to specify those subsections (tm). The waveform of other subsections remains unchanged. The PWM waveform (12-bit resolution) is a combination of two types of waveforms which are different in “H” width, as described above. When output control input OC is “H”, the output of every 4-channel turns high-impedance from the next cycle. When reset input R is “L”, the output of every channel turns high-impedance as soon as the ongoing cycle is completed, and PWM data of all channels is reset. If R input is changed from “L” to “H”, the next cycle starts, however, the output of the channels remains high-impedance. To enable output, rewrite input data for each channel. **)fXIN: Clock XIN repeat frequency REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 2 of 12 R8A66173SP PIN DESCRIPTIONS R Pin Name Reset input Input/Output Functions Input "L" : All 4-channels put in high-impedance state. CS Chip select input Input "L" : Communication with MCU becomes possible. WR, SIN and SCLK put in enable state. WR Write control input Input "L": Serial data written. "L"-to-"H" edge: Written data stored in upper or lower byte register. SIN SCLK Serial data input Input Inputs 8-bit serial data from MCU synchronously with SCLK clock. Write clock input Input Inputs sync clock pulses for 8-bit serial data writing. Input "H": All 4-channels put in high-impedance state. Output Outputs PWM waveform. (CMOS 3-state output) OC Output control input PWM1∼ PWM4 PWM outputs 1∼4 XIN Clock input XOUT Clock output Input Output Input/output signals generated by clock signal generation circuit. Oscillation frequency is determined by connecting ceramic or quartz resonator between XIN and XOUT. The frequency of internal clock (PWM timing clock) signals is the 1/2 divider of the frequency input from clock input XIN. When external clock signals are used, connect clock generator to XIN pin and leave XOUT open. (1) Upper byte register b7 b6 b5 b4 b3 b2 b1 b0 PWM output "H" w idth setting bits (Upper 8 bits ： b11∼b4) (2) Lower byte register b7 b6 b5 b4 b3 b2 b1 b0 Write data designation bit 0 : Low er byte only 1 : Both low er and upper bytes PWM output select bits 00 : PWM1 01 : PWM2 10 : PWM3 11 : PWM4 Output control select bit 0 : Output disable (b7∼b4 and b0 are ignored.) 1 : Output enable PWM output "H" w idth setting bits (Low er 4 bits ： b3∼b0) Fig. 1 Upper and Lower Byte Register Makeup Table 1 Mode Selection Input serial data Mode PWM data setting (output enable) Lower 4-bit data setting 12-bit data setting Output disable REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 3 of 12 b7 b7 X b6 b6 X Lower byte data b5 b4 1 b2 b5 b4 1 b2 X X 0 b2 Upper byte data b1 b1 b1 0 1 X − b7 b6 b5 b4 b3 − b2 b1 b0 R8A66173SP Table 2 Patterns of Lower 4-bits and Subsections whose "H" Width is increased PWM register b3∼b0 0000 0001 0010 0100 1000 1111 Subsection tm whose H width is increased by τ ( m = 0∼15) Nothing m=8 m = 4, 12 m = 2, 6, 10, 14 m = 1, 3, 5, 7, 9, 11, 13, 15 m = 1∼15 (m≠0) Number of Subsections 0 1 2 4 8 15 Upper byte register Low er byte register b7 0 1 0 0 1 0 1 b0 b7 0 0 b0 1 1 0 ? ? ? ? PWM register b11 4A616 0 1 0 0 1 0 1 b4 b3 0 0 Determines "H" w idth of basic w aveform (In this case, "H" w idth is 4A 16=74) Basic w aveform b0 1 1 0 Determines subsections tm w hose "H" w idth is increased by the minimum bit w idth of τ (Refer to Table 2.) (In this case, m=2, 4, 6, 10, 12 and 14.) τ ×74 τ τ ×74 2 τ= f XIN (Exp. When f XIN is 4MHz. τ =0.5µs) One subsection t=τ ×256 (8-bit resolution) Designated subsection tm (In this case, m=2, 4, 6, 10, 12 and 14.) Output w aveform τ τ ×74 τ ×74 t0 ∼ t4 t5 Subsection τ ×75 t6 t7 t8 t9 t10 t11 t12 t13 ∼ t15 One cycle Fig.2 PWM Waveform Output Example (Input data:4A616) OPERATION Serial Data Input When chip select CS is “L” and write control input WR is ”L”, data input to SIN at the edge where write clock input SCLK status shifts from “L” to “H” is written.(See Fig.3.) At the edge where WR rises from “L” to “H”, the latest 8-bit data writing is completed, and input data is stored in lower (or upper) byte register .When writing on the lower byte or writing on both upper and lower bytes is completed, data on the lower byte register or, in the latter case, data on both lower and upper byte registers is written on the PWM register of the channel designated by lower bytes b2 and b1. All setting process ends with this writing, and PWM waveform changes according to the setting from the next cycle. REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 4 of 12 R8A66173SP PWM Waveform Output (1)12-bit PWM output One PWM waveform cycle is divided into 16(=24) subsections t, and each subsection is further divided into 256(=28) minimum resolution bits τ(=2/fXIN). The “H” width of subsection t basic waveform is determined by the upper 8-bits of PWM data. (In Fig.2 above, ”H” width is 4A16=74×τ) Among these 16 subsections t, subsections tm designated by the lower 4-bits of PWM data have “H” width that is longer by τ. (In Fig.2 above, the “H” width of designated 6 subsections (m =2, 4, 6, 10, 12 and 14) is 4B16=75×τ.) The “H” width of undesignated subsections remains unchanged. As explained above, one cycle of waveform is a combination of two waveforms different in the “H” width. (In Fig. 2 above, one cycle consists of 10 subsections whose “H” width is 74×τ and 6 subsections whose “H” width is 75×τ) Note: It is impossible to set one whole cycle to “H” level. (2)8-bit PWM output As can be seen from the 12-bit PWM waveform output process as described above, 8-bit resolution PWM waveform can be output by fixing the lower 4-bits of PWM data to 00002. All subsections from t0 to t15 have the “H” width as determined by the upper 8-bits of PWM data. Note: It is impossible to set one whole cycle to “H” level. Output Control (1)Serial data input By using data on lower byte register b3 (output control selection bit), output of each channel can be controlled independently. The state of the selected PWM output changes after the completion of the ongoing cycle. When b3 is set 0, lower byte register b0 (write data designation bit) is reset. Do not write on upper byte in this case. (2)Output control input The status of all 4-channel outputs during a cycle is determined depending on the status of output control input OC at the start of the cycle. (See Fig. 6.) Even when output is in a high-impedance state, data on each PWM register is retained, and data can be rewritten. (3)Reset When reset input R turns “L”, all operation is reset as soon as the ongoing cycle is completed. The outputs of all 4-channels turn high-impedance. The PWM register of each channel is reset. When R is shifted from “L” to “H”, a next cycle starts, and data writing becomes possible. However, outputs stay in the high-impedance state. (See Fig. 6) To resume output, write input data for each channel. Initial State After power-on, outputs and PWM register data are unstable. (1)Reset Reset input R is kept on “L” level for more than one cycle (2.048ms when fXIN is 4 MHz) or more, this integrated circuit is put in a reset state. If stabilization needs more time, e.g. when a quartz resonator is used, keep R on “L” level for an adequate period of time. (2)Serial data input When starting using this integrated circuit without resetting, input false lower byte data (b0=0) to stabilize lower byte register b0 data, and then input normal data. REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 5 of 12 R8A66173SP WR SIN b0 b1 b2 b3 b4 b5 b6 b7 SCLK PWM output Ongoing cycle Next cycle Fig.3 Serial Data Write Timing PWM Setting Data 000 16 τ 001 16 τ τ 002 16 τ τ τ 003 16 τ 00E 16 00F 16 τ 010 16 τ 011 16 τ 012 16 τ 013 16 τ τ×150 τ×150 963 16 τ×255 FFD 16 τ FFE 16 τ FFF 16 τ t0 ∼ t4 t5 t6 t7 t8 t9 t10 t11 1 cycle T= 2 ×212 fXIN Fig.4 12-bit PWM Waveform Output Example REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 6 of 12 t12 t13 ∼ t15 R8A66173SP PWM Setting Data 00016 τ τ τ τ τ τ τ τ×2 τ×2 τ×2 τ×2 τ×2 τ×2 τ×2 01016 02016 τ×254 τ×254 τ×254 τ×254 τ×254 τ×254 τ×254 τ×255 τ×255 τ×255 τ×255 τ×255 τ×255 τ×255 t13 t14 t15 FE016 FF016 t0 t1 t2 t3 1 cycle Fig.5 8-bit PWM Waveform Output Example R OC CS WR SIN DATA internal signal "Φ" (cycle start signal) PWM output High-impedance 1 cycle Fig.6 Output Control Timing Chart REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 7 of 12 High-impedance R8A66173SP Start Reset R="L" WR="L" Set low er byte 1 WR="L" b0=? Set upper byte A 0 NO Setting complete? YES OC="L", or low er byte b3=1 Output enable PWM output Change setting? YES Repeat A NO Stop Fig.7 PWM Setting Flow Chart REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 8 of 12 R8A66173SP o o ABSOLUTE MAXIMUM RATINGS (Ta= -40 C~85 C unless otherwise noted) Symbol Parameter Conditions Ratings Unit -0.5 ~ +7.0 V V Vcc Supply voltage VI Input voltage -0.5 ~ Vcc+0.5 VO Output voltage -0.5 ~ Vcc+0.5 V IO Output current ±15 mA Icc Supply/GND current ±40 mA Pd Power dissipation 150 mW Tstg Storage temperature Vcc, GND o C -65 ~ 150 o o RECOMMENDED OPERATING CONDITIONS (Ta=-40 C ~ 85 C unless otherwise noted) Symbol Limits Parameter Min. Typ. Max. 5.0V support 4.5 5.0 5.5 3.3V support 3.0 3.3 3.6 Unit V Vcc Supply voltage GND Supply voltage VI Input voltage 0 Vcc V VO Output voltage 0 Vcc V Topr Operating temperature range -40 85 0 V V o C ELECTRICAL CHARACTERISTICS ■5.0V version support specifications (Ta=-40 Symbol Parameter o C ~ 85 oC, Vcc=4.5V ~ 5.5V, unless otherwise noted) Limits Test conditions Min. VIH VIL “H” input voltage “L” input voltage XIN 0.8Vcc Other input 0.75Vcc Typ. Unit Max. V V XIN 0.2Vcc V Other input 0.25Vcc V VOH “H” output voltage PWM1~4 IOH=-4mA VOL “L” output voltage PWM1~4 IOL=4mA IIH “H” input current Vcc-0.5 V VI=Vcc 0.5 1.0 V µA IIL “L” input current VI=GND -1.0 µA IOZH Off-state “H” output current VO=Vcc 5.0 µA IOZL Off-state “L” output current VO=GND -5.0 µA ICC Quiescent supply current VI=Vcc, GND, Output open 40 µA ■3.3V version support specifications (Ta=-40 Symbol Parameter o C ~ 85 oC, Vcc=3.0V ~ 3.6V, unless otherwise noted) Limits Test conditions Min. VIH VIL “H” input voltage “L” input voltage XIN 0.8Vcc Other input 0.75Vcc Typ. Unit Max. V V XIN 0.2Vcc V Other input 0.25Vcc V VOH “H” output voltage PWM1~4 IOH=-2mA VOL “L” output voltage PWM1~4 IOL=2mA IIH “H” input current Vcc-0.5 V VI=Vcc 0.5 1.0 V µA IIL “L” input current VI=GND -1.0 µA IOZH Off-state “H” output current VO=Vcc 5.0 µA IOZL Off-state “L” output current VO=GND -5.0 µA ICC Quiescent supply current VI=Vcc, GND, Output open 40 µA REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 9 of 12 R8A66173SP SWITCHING CHARACTERISTICS (Ta=-40 oC ~ 85 oC, Vcc=5.0V±0.5V or 3.3V±0.3V, unless otherwise noted) Symbol Parameter 5.0V specification Test conditions Min. fmax tPLH tPHL Maximum clock frequency XIN Output "L-H", "H-L" propagation time XIN-PWM1~4 Typ. Max. 3.3V specification Min. Typ. 16 CL=50pF (Note 1) o Unit Max. 12.5 MHz 100 100 ns 100 100 ns o TIMING REQUIREMENTS (Ta=-40 C ~ 85 C, Vcc=5.0V±0.5V or 3.3V±0.3V, unless otherwise noted) Symbol Parameter Test conditions 5.0V specification Max. Min. 80 Typ. Unit XIN cycle time tw(XH) XIN “H” pulse width 32.5 40 ns tw(XL) XIN “L” pulse width 30 40 ns tw(S) SCLK pulse width WR “H” hold time 30 40 ns twRH 6tc(x) 6tc(x) ns tsu(CS) CS "L" setup time before WR 30 40 ns tsu(WR) WR "L" setup time before SCLK 30 40 ns tsu(S) SIN setup time before SCLK 50 60 ns th(CS) CS "L" hold time after WR 30 40 ns th(WR) WR "L" hold time after SCLK 10 20 ns th(S) SIN hold time after SCLK 10 20 ns th(SCLK) SCLK hold time after WR 30 tr Input rise time 25 25 ns tf Input fall time 25 25 ns tc(X) Typ. 3.3V specification Min. 62.5 Vcc OUTPUT DUT P.G. 50Ω GND CL (1) The pulse generator (PG) has the following characteristics. : tr=3ns, tf=3ns (2) The capacitance CL includes stray wiring capacitance and the probe input capacitance. REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 10 of 12 ns 40 Note 1. Test Circuit INPUT Max. ns R8A66173SP TIMING CHARTS tsu(CS) th(CS) 50% CS Vcc 50% 0V tWRH Vcc WR 50% 50% 50% 0V tsu(WR) tw (S) th(WR) tw (S) th(SCLK) Vcc SCLK 50% 50% 50% 50% 50% 0V tsu(S) th(S) Vcc SIN 50% 50% 0V tc(X) tw (XH) tw (XL) Vcc 50% XIN 50% 50% 0V Φ (internal clock) tPLH tPHL V OH 50% PWM1~4 50% V OL Note 2. (1)Shaded portions indicate that switching is possible during those periods. (2)PWM outputs 1 to 4 change synchronously with internal clock signals Φ. The frequency of these signals is the 1/2 divider of the frequency input from XIN. APPLICATION EXAMPLE (Combination with electronic control for amplifier system) Electronic control Pow er amplifier CD FM DAT AV Graphic equalizer Buffer/Low -pass filter Control microcomputer PWM MCU R8A66173SP REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 11 of 12 Speaker R8A66173SP PACKAGE OUTLINE Package 14pin SOP RENESAS Code PRSP0014DG-A Previous Code 14P2X-B All trademarks and registered trademarks are the property of their respective owners. REJ03F0264-0100 Rev.1.00 Jan.24.2008 Page 12 of 12