AP3440

A Product Line of
Diodes Incorporated
AP3440
4A, 2MHZ HIGH PERFORMANCE SYNCHRONOUS BUCK CONVERTER
Pin Assignments
Under voltage lockout is internally set at 2.6V, but can be increased
by programming the threshold with a resistor network on the enable
pin. The output voltage startup ramp is controlled by the soft-start pin.
An open drain power good signal indicates the output is within 93% to
107% of its nominal voltage.
The AP3440 is available in U-QFN3030-16 package.
VIN
1
VIN
2
GND
3
GND
4
PGD
BOOT
16
15
14
13
EP
5
6
7
8
RT/CLK
The switching frequency of AP3440 can be programmable from
200kHz to 2MHz, which allows small-sized components, such as
capacitors and inductors. A standard series of inductors from several
different manufacturers are available. This feature greatly simplifies
the design of switch-mode power supplies.
COMP
Pin 1 Mark
FB
The device integrates two N-channel power MOSFETs with low onresistance. Current mode control provides fast transient response and
cycle-by-cycle current limit.
EN
(Top View)
VIN
NEW PRODUCT
The AP3440 is a current mode, PWM synchronous buck (step-down)
DC-DC converter, capable of driving a 4A load with high efficiency,
excellent line and load regulation.
AGND
Description
12
SW
11
SW
10
SW
9
SS
U-QFN3030-16
Features
Applications



Low-voltage, High-density Power Systems
Point of Load Regulation for High Performance DSPs, FPGAs,
ASICs and Microprocessors
Broadband,
Networking
and
Optical
Communications
Infrastructure
Notes:


















Input Voltage Range: 2.95V to 5.5V
0.8V Reference Voltage with ±3% Precision
Two 30m(Typical) MOSFETs for High Efficiency at 4A Load
High Efficiency: Up to 94%
Output Current: 4A
Programmable Frequency:200kHz to 2MHz
Current Mode Control
Synchronizes to External Clock
Adjustable Soft-start
Soft Start-up into Pre-biased Output
UV and OV Power Good Output
Built-in Over Current Protection
Built-in Thermal Shutdown Function
Programmable UVLO Function
Built-in Over Voltage Protection
Thermally Enhanced 3mm×3mm 16-pin U-QFN3030-16
Totally Lead-free & Fully RoHS Compliant (Note1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
AP3440
Document number: DS36691 Rev. 3 - 2
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AP3440
Typical Applications Circuit
U1
VIN=5V
16
1
C2
C3
C1
NEW PRODUCT
10mF 0.1mF
R4
R1 100kΩ
2
14
15
7
8
R2
9
L1 1.5mH
VIN
SW
VIN
SW
VIN
SW
BOOT
PGD
EN
AP3440
COMP
GND
RT/CLK
SS
FB
GND
AGND
10
R8 2.2Ω
(Optional)
11
12
13
VOUT=1.8V
C6
0.1mF
C10 2.2nF
(Optional)
6
R6 12.5kΩ
3
4
R7
10kΩ
C8
22mF
C9
22mF
5
R3
7.5kΩ
C5
Optional
C4
2.7nF
R5
180kΩ
C7
0.01mF
Pin Description
Pin Number
Pin Name
Function
1,2,16
VIN
Supply input pin. A capacitor should be connected between the VIN and GND pin to keep the
DC input voltage constant
3,4
GND
Power ground. This pin should be electrically connected to the power pad under the IC
5
AGND
6
FB
7
COMP
Compensation pin. This pin is the output of the transconductance error amplifier and the input
to the current comparator. Connect external compensation elements to this pin to stabilize the
control loop
8
RT/CLK
Resistor timing or external clock input pin
9
SS
Soft-start pin. An external capacitor connected to this pin sets the output voltage rise time. This
pin can also be used for tracking
10,11,12
SW
Internal power switch output pin. This pin is connected to the inductor and bootstrap capacitor
13
BOOT
14
PGD
15
EN
EP
Exposed Thermal Pad
AP3440
Document number: DS36691 Rev. 3 - 2
Analog ground. This pin should be electrically connected to GND close to the device
Feedback pin. Inverting node of the transconductance error amplifier
Bootstrap pin. A bootstrap capacitor is connected between the BOOT pin and SW pin. The
voltage across the bootstrap capacitor drives the internal high-side power MOSFET
Power good indicator output. Asserts low if output voltage is low due to thermal shutdown,
over-current, over/under-voltage or EN shut down
Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Can be
used to set the on/off threshold (adjust UVLO) with two additional resistors
Exposed Pad can be connected to GND, for best thermal performance thermal vias are
recommended under the package
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AP3440
NEW PRODUCT
Functional Block Diagram
AP3440
Document number: DS36691 Rev. 3 - 2
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AP3440
Absolute Maximum Ratings (Note 4)
NEW PRODUCT
Symbol
Rating
Unit
VIN
VIN Pin Voltage
-0.3 to 6.5
V
VEN
EN Pin Voltage
-0.3 to 6.5
V
VSW
SW Pin Voltage
-0.3 to VIN+0.3
V
VFB
FB Pin Voltage
-0.3 to 6.5
V
COMP Pin Voltage
-0.3 to 6.5
V
PGD Pin Voltage
-0.3 to 6.5
V
RT/CLK Pin Voltage
-0.3 to 6.5
V
VSS
SS Pin Voltage
-0.3 to 6.5
V
JA
Thermal Resistance
70
ºC/W
TJ
Operating Junction Temperature
-40 to +125
ºC
TSTG
Storage Temperature
-65 to +150
ºC
TLEAD
Lead Temperature (Soldering, 10sec)
+260
ºC
—
ESD(Machine Model)
200
V
—
ESD(Human Body Model)
2000
V
VCOMP
VPGD
VRT/CLK
Parameter
Note 4: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied.
Exposure to “Absolute Maximum Ratings” for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol
VIN
IOUT(MAX)
TA
Parameter
Input Voltage
Maximum Output Current
Operating Ambient Temperature
Min
Max
Unit
2.95
5.5
V
4
—
A
-40
+85
ºC
Electrical Characteristics
(@VIN=2.95 to 5.5V, TA=+25ºC, unless otherwise specified. Specifications with boldface type apply
over full operating temperature range from -40 to +85ºC.)
Symbol
Parameters
Conditions
Min
Typ
Max
Unit
2.95
—
5.5
V
SUPPLY VOLTAGE (VIN PIN)
VIN
Input Voltage
—
IQ
Quiescent Current
VFB=0.9V, VIN=5V,
TA=+25ºC, RT=400k
—
360
575
μA
Shutdown Supply Current
VEN=0V,TA=+25C,
2.95V≤VIN≤5.5V
—
2
5
μA
Rising
1.16
1.25
1.37
V
Falling
—
1.18
—
V
—
—
2.6
2.8
V
—
—
150
—
mV
ISHDN
ENABLE AND UVLO (EN PIN)
VEN_H
Enable Threshold
VEN_L
VUVLO
VHYS
Internal
Under
Voltage
Lockout Threshold
Internal
Under
Voltage
Hysteresis
AP3440
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AP3440
Electrical Characteristics
(Cont.) (@VIN=2.95 to 5.5V, TA=+25ºC, unless otherwise specified. Specifications with boldface type
apply over full operating temperature range from -40 to +85ºC.)
Symbol
Parameters
Conditions
Min
Typ
Max
Unit
0.779
0.803
0.827
V
VBOOT-SW=5V
—
30
60
m
VBOOT-SW=2.95V
—
44
70
m
VIN=5V
—
30
60
m
VIN=2.95V
—
44
70
mΩ
—
4.8
7.0
—
A
Thermal Shutdown
—
—
+140
—
C
Hysteresis
—
—
+20
—
C
VOLTAGE REFERENCE (FB PIN)
VREF
2.95V≤VIN≤5.5V
Voltage Reference
NEW PRODUCT
MOSFET
RON_H
RON_L
High Side
resistance
Switch
Low
Side
resistance
Switch
On-
On-
CURRENT LIMIT
ILIMIT
Current Limit Threshold
THERMAL SHUTDOWN
TTSD
—
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching Frequency Range
(RT Mode)
Switching Frequency Range
(CLK Mode)
—
200
—
2000
kHz
—
300
—
2000
kHz
fS
Switching Frequency
RT=400k
400
500
600
kHz
—
Minimum CLK Pulse Width
—
75
—
—
ns
—
RT/CLK Voltage
RT=400k
—
0.5
—
V
—
RT/CLK High Threshold
—
—
1.6
2.2
V
—
RT/CLK Low Threshold
—
0.4
0.6
—
V
BOOT Charge Resistor
VIN=5V
—
16
—

BOOT-SW UVLO
VIN=2.95V
—
2.2
—
V
—
—
BOOT (BOOT PIN)
RBOOT
—
SOFT START (SS PIN)
ISS
Charge Current
VSS=0.4V
—
2
—
mA
VSS
SS to Reference Crossover
98% Nominal
—
1.1
—
V
VFB Falling (Fault)
—
91
—
VFB Rising (Good)
—
93
—
VFB Rising (Fault)
—
107
—
VFB Falling (Good)
—
105
—
POWER GOOD (PGD PIN)
VFB_TH
Feedback Threshold
AP3440
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AP3440
Performance Characteristics
Supply Current vs. Input Voltage
Supply Current vs. Temperature
435
460
430
455
425
450
420
445
Supply Current (mA)
Supply Current (mA)
440
410
405
400
395
390
385
380
435
430
425
420
415
410
375
405
370
400
365
395
360
390
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
5.7
-50
-25
0
Input Voltage (V)
25
50
75
100
125
150
o
Temperature ( C)
UVLO Threshold vs. Temperature
EN Threshold vs. Temperature
1.28
2.60
1.27
2.55
1.25
2.45
1.24
EN Threshold (V)
UVLO Threshold (V)
1.26
2.50
2.40
2.35
2.30
2.25
2.20
1.23
1.22
VIN=5V
1.21
Rising
Falling
1.20
1.19
1.18
1.17
Start Switching
Stop Switching
2.15
1.16
1.15
1.14
2.10
-50
-25
0
25
50
75
100
125
150
-50
-25
0
o
25
50
75
100
125
150
o
Temperature ( C)
Temperature ( C)
Efficiency vs. Output Current
Switching Frequency vs. Temperature
100
1020
95
1010
90
85
75
70
65
60
55
VOUT=1.8V
50
45
VIN=3.3V
40
VIN=5V
Switching Frequency (kHz)
1000
80
Efficiency (%)
NEW PRODUCT
415
990
980
970
960
950
RT=180k
940
930
35
920
30
0
-50
300 600 900 1200 1500 1800 2100 2400 2700 3000 3300 3600 3900 4200
AP3440
Document number: DS36691 Rev. 3 - 2
-25
0
25
50
75
100
125
150
o
Output Current (mA)
Temperature ( C)
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AP3440
Performance Characteristics (Cont.)
NEW PRODUCT
Start Up from VIN (VIN=5V, VOUT=1.8V, IOUT=4A)
Disable IC (VIN=5V, VOUT=1.8V, IOUT=4A)
VEN
2V/div
VIN
2V/div
VOUT
1V/div
VOUT
1V/div
VSS
2V/div
IL
2A/div
VSS
2V/div
IL
2A/div
Time 4ms/div
Time 20ms/div
Load Transient Response (VIN=5V, VOUT=1.8V, IOUT=0 to 4A)
Synchronizing to External Clock (fCLOCK=2MHz)
VOUT(AC)
200mV/div
VCLOCK
2V/div
IOUT
2A/div
VSW
2V/div
Time 200ms/div
Time 400ns/div
Short Circuit Protection (VIN=5V, VOUT=1.8V, IOUT=4A)
VOUT
1V/div
Short Circuit Recovery (VIN=5V, VOUT=1.8V, IOUT=4A)
VOUT
1V/div
VSS
2V/div
VCOMP
0.5V/div
VSS
2V/div
VCOMP
0.5V/div
IL
2A/div
IL
2A/div
Time 4ms/div
AP3440
Document number: DS36691 Rev. 3 - 2
Time 4ms/div
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AP3440
Application Note
Theory of Operation
The AP3440 consists of a reference voltage module, slope compensation circuit, error amplifier, PWM comparator, current limit circuit, two Nchannel MOSFETs etc. (Refer to the Functional Block Diagram on page 3 for detailed information)
NEW PRODUCT
Soft-start
The AP3440 integrates an internal soft start circuit to minimize inrush currents or provide power supply sequencing during power up. A capacitor
connected between SS pin and ground implements the soft-start time. The AP3440 has an internal pull-up current source of 2μA, which charges
the external slow start capacitor. Equation 1 calculates the required slow start capacitor, I SS is the internal slow start charging current of 2μA, and
VREF is the internal voltage reference of 0.803V.
C SS (nF ) 
t SS (ms )  I SS ( mA)
VREF (V )
………………….(1)
During normal operation, if the VIN goes below the UVLO, or the EN pin is pulled below 1.2V, or a thermal shutdown occurs, the AP3440 will stop
switching and the SS pin will be discharged to 40mV before reinitiating a powering up sequence.
Enable and Adjusting UVLO
The AP3440 are disabled when the VIN falls below 2.6V. If an application requires a higher under-voltage lockout (UVLO), use the EN pin as
shown in Figure 1 to adjust the input voltage UVLO by using two external resistors. The EN pin has an internal pull-up current source that provides
the default condition of the AP3440 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25V, an additional 2.55μA of hysteresis
is added. When the EN pin is pulled below 1.18V, the 2.55μA hysteresis is removed. This additional current facilitates input voltage hysteresis.
For AP3440, the divider resistor R1 and R2 on the EN pin can be calculated according to equation 2 and 3.
R1 
R2 
0.944  VSTART  VSTOP
2.59 10 6
VSTOP
…………………...(2)
1.18  R1
 1.18  R1 3.2  10 6
………………(3)
AP3440
VIN
0.6μA
2.55μA
R1
EN
R2
Figure 1. Adjustable Under Voltage Lock Out
Adjusting Output Voltage
The output voltage is set with a resistor divider from the FB pin. It is recommended to use divider resistors with 1% tolerance or better. Start with a
10kΩ R2 resistor and use the equation 4 to calculate R1. To improve efficiency at very light loads consider using larger value resistors. If the
values are too high, the regulator is more susceptible to noise and voltage errors from the FB input current are noticeable.
AP3440
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AP3440
Application Note (Cont.)
Resistor R1 can be calculated according to equation 4.
VOUT
AP3440
R1
NEW PRODUCT
FB
R2
V

R1  R 2   OUT  1
0
.
803


0.803V
SS
……………………….. (4)
Figure 2. Voltage Divider Circuit
Synchronize Using the RT/CLK Pin
The RT/CLK pin of AP3440 is used to synchronize the converter with an external system clock referring to Figure 3. To implement the
synchronization feature in a system, connect a square wave to the RT/CLK pin with an on-time of at least 75ns. When the clock is detected on the
RT/CLK pin, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled. If clocking edges stop, the
internal amplifier is re-enabled and the mode returns to the frequency set by the resistor. The low level of the square wave must be lower than
0.6V and the high level higher than 1.6V typically. The synchronization frequency range is from 300kHz to 2000kHz. The rising edge of the SW is
synchronized to the falling edge of RT/CLK pin. Figure 4 shows a typical synchronizing waveform, the clock frequency is 2MHz.
AP3440
RT/CLK
Clock
Source
RT
Figure 3. Synchronizing to a System Clock
Figure 4. Synchronizing Waveform
Constant Switching Frequency and Timing Resistor
The switching frequency of the AP3440 is adjustable over a wide range from 200kHz to 2000kHz by placing a resistor with maximum value of
1000kΩ and minimum of 85kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this pin at a fixed voltage when connecting an external
resistor to ground to set the switching frequency. The VRT/CLK is typically 0.5V. To determine the timing resistance for a given switching frequency,
use the equation 5.
RT (k) 
311890
f SW (kHz)1.0793
f SW (kHz) 
133870
RT (k) 0.9393
……………………….(5)
………………………..(6)
To reduce the solution size one should typically set the switching frequency as high as possible, but tradeoffs of the efficiency, maximum input
voltage and minimum controllable on time should be considered.
AP3440
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AP3440
Application Note (Cont.)
NEW PRODUCT
Over Current Protection
The AP3440 implements a cycle-by-cycle current limit. The high side switch current is detected during each cycle. During SCP conditions, V OUT is
pulled down and VCOMP is drived to high, increasing the switch current. When the increased high side switch current is continuously detected to
trigger the current limit of high side switch 6 times, the high side and low side switches are turned off for about 2.5ms. Then both switches start
switching and they will not be turned off until the next 6 OCPs are triggered. The IC works with a hiccup mode during SCP conditions.
Power Good
The PGD pin output is an open drain MOSFET. The output is pulled low when the FB voltage enters the fault condition by falling below 91% or
rising above 107% of the nominal internal reference voltage. There is a 2% hysteresis on the threshold voltage, so when the FB voltage rises to
the good condition above 93% or falls below 105% of the internal voltage reference the PGD output MOSFET is turned off. It is recommended to
use a pull-up resistor between the values of 1kΩ
Ω to a voltage source that is 5V or less. The PGD is in a valid state once the VIN input
voltage is greater than 1.2V.
Thermal Shutdown
The AP3440 implement an internal thermal shutdown to protect itself if the junction temperature exceeds +140°C. Switching is stopped when the
junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below +120°C, the device reinitiates the soft start
operation. The thermal shutdown hysteresis is +20°C.
Component Selection
Typical application circuit of AP3440 is shown in Figure 5. For the major component selection please refer to the following section.
U1
VIN=5V
16
1
C1
Optional
C2
C3
10mF 0.1mF
R4
R1 100kΩ
2
14
15
7
8
R2
9
L1 1.5mH
VIN
SW
VIN
SW
VIN
SW
BOOT
PGD
EN
AP3440
COMP
RT/CLK
SS
FB
GND
GND
AGND
10
R8 2.2Ω
(Optional)
11
12
13
VOUT=1.8V
C6
0.1mF
C10 2.2nF
(Optional)
6
R6 12.5kΩ
3
4
R7
10kΩ
C8
22mF
C9
22mF
5
R3
7.5kΩ
C5
Optional
C4
2.7nF
R5
180kΩ
C7
0.01mF
Figure 5. Typical Application of AP3440
Input Capacitor
The AP3440 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7μF effective capacitance and in some
applications a bulk capacitor. The effective capacitance includes any DC bias effects. To ensure a stable operation, the input capacitor should be
placed as close to the VIN pin as possible, and its value varies according to different load and different characteristic of input impedance.
There are two important parameters of the input capacitor: the voltage rating and RMS current rating. The voltage rating of the input capacitor
should be at least 1.25 times larger than the maximum input voltage. The capacitor must also have a RMS current rating greater than the
maximum input current ripple of the AP3440. The RMS current of input capacitor can be expressed as:
I CIN_RMS  I OUT(MAX) 
VOUT  VOUT  ………..(7)

 1 
VIN 
VIN 
AP3440
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AP3440
Application Note (Cont.)
Output Capacitor
The output capacitor is the most critical component of a switching regulator. It is used for filtering output and keeping the loop stable. The typical
value is 44μF.
NEW PRODUCT
The primary parameters for output capacitor are the voltage rating and the equivalent series resistance (ESR). A low ESR capacitor is preferred to
keep the output voltage ripple low. The output ripple is calculated as the following:
VOUT  I L  ( RESR 
1
) ……………..(8)
8  f  COUT
Where f is the switching frequency, COUT is the output capacitance and △IL is the ripple current in the inductor.
Inductor
The inductor is used to supply smooth current to output when it is driven by a switching voltage. The higher the inductance, the lower the peak-topeak ripple current, as the higher inductance usually means the larger inductor size, so some trade-offs should be made when select an inductor.
The AP3440 is a synchronous buck converter. It always works on continuous current mode (CCM), and the inductor value can be selected as the
following:
L  VOUT  (
VIN  VOUT
) …………………. ….(9)
f  VIN  I OUT  k
Where VOUT is the output voltage, VIN is the input voltage, IOUT is the output current, k is the coefficient of ripple current, and its typical value is 20%
to 40%. Another important parameter for the inductor is the current rating. Exceeding an inductor's maximum current rating may cause the
inductor to saturate and overheat. If inductor value has been selected, the peak inductor current can be calculated as the following:
I PEAK  I OUT  VOUT  (
VIN  VOUT …………..(10)
)
2  f  VIN  L
It should be ensured that the current rating of the selected inductor is 1.5 times of the I PEAK.
Slow Start Capacitor
The slow start capacitor determines the output voltage soft start time during power up.
The slow start capacitor value can be calculated using equation 11.
C SS (nF ) 
t SS (ms )  I SS ( mA) ……………………… (11)
VREF (V )
In AP3440, ISS is 2μA and VREF is 0.803V.
Bootstrap Capacitor
A 0.1μF ceramic capacitor must be connected between the BOOT pin and the SW pin for normal operation. It is recommended to use a ceramic
capacitor with X5R or better grade dielectric.
Feedback Resistors
It is recommended to use divider resistors with 1% tolerance or better. Start with a 10kΩ for the R7 resistor and use the equation 12 to calculate
R6.
V

R 6  R 7   OUT  1 …………………………………(12)
0
.
803


AP3440
Document number: DS36691 Rev. 3 - 2
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Application Note (Cont.)
Compensation
NEW PRODUCT
The output capacitor and the load resistance largely determine where the error amplifier poles and zeros need to be placed for optimum transient
response and loop stability. The corner frequency of the pole and zero generated by output capacitor are:
f P1 
1
2  RLOAD  COUT
f Z1 
1
2  RESR  COUT
………………………..(13)
………………………. .. (14)
Where RLOAD is the load resistance, COUT is the output capacitance and RESR is the capacitor ESR.
The error amplifier provides most of the loop gain. After selecting the output capacitor, the control loop is compensated by tailoring the frequency
response of the error amplifier. The low frequency pole of the error amplifier is the dominant pole and is determined primarily by CCOMP and the
output resistance of the error amplifier as shown by:
f P2 
1
2  ROUT _ EA  CCOMP
…………………..(15)
Resistor RCOMP adds a zero to the frequency response to control gain in the mid frequency range. This zero frequency is:
fZ2 
1
2  RCOMP  CCOMP
……………………..(16)
Where RCOMP and CCOMP are compensation resistor and capacitor connected to COMP pin, ROUT_EA is the output impedance of the error amplifier.
A 7.5kΩ resistor and 2.7nF capacitor are used in typical application.
Layout Consideration
PCB layout is very important to the performance of AP3440. The loop which switching current flows through should be kept as short as possible.
The external components (especially CIN) should be placed as close to the IC as possible.
The feedback trace should be routed far away from the inductor and noisy power traces, and it needs to be routed as direct as possible. Locate
the feedback divider resistor network near the feedback pin with short leads.
Since the SW connection is the switching node, the output inductor should be located very close to the SW pins, and the area of the PCB
conductor is minimized to prevent excessive capacitive coupling.
The boot capacitor must also be located close to the device. The sensitive analog ground connections for the feedback voltage divider,
compensation components, slow start capacitor and frequency set resistor should be connected to a separate analog ground trace.
The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace.
Figure 6. Top View of PCB Layout
AP3440
Document number: DS36691 Rev. 3 - 2
Figure 7. Bottom View of PCB Layout
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Ordering Information
AP3440 XX XX - XX
NEW PRODUCT
Product Name
Package
Packing
RoHS/Green
FN : U-QFN3030-16
TR : Tape & Reel
G1 : Green
Diodes IC’s Pb-free products with "G1" suffix in the part number, are RoHS compliant and green.
Package
Temperature Range
U-QFN3030-16
-40 to +85ºC
Part Number
AP3440FNTR-G1
Marking ID
B2D
Packing
5000/Tape & Reel
Marking Information
B2D
YWW
MXX
AP3440
Document number: DS36691 Rev. 3 - 2
: AAC Logo
B2D: Marking ID (Per Datasheet)
YWW: Year and Work Week of Mold Operation
M: Assembly Site Code
th
th
XX: The 7 & 8 Digits of Batch No.
· Pin 1 Mark
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Package Outline Dimensions
(1)
Package Type: U-QFN3030-16
A1
NEW PRODUCT
A
A3
Dim
A
A1
A3
b
Side View
D
D
e
E
2.95
3.05
Typ
0.60
0.02
0.15
0.23
3.00
D2
1.40 1.60 1.50
E
2.95 3.05 3.00
E2
1.40 1.60 1.50
e
0.50


L
0.35 0.45 0.40
Z

 0.625
All Dimensions in mm
(Pin #1 ID)
0.450
00
R0.2
U-QFN3030-16
Type B
Min Max
0.55 0.65
0
0.05


0.18 0.28
E2
D2
L (16x)
Z (8x)
b (16x)
Bottom View
Suggested Pad Layout
(1)
Package Type: U-QFN3030-16
C
G
G1
Dimensions
C
G
G1
X
X1
Y
Y1
Y1
X1
Value
(in mm)
0.500
0.150
0.150
0.350
1.800
0.600
1.800
Y (16x)
X (16x)
AP3440
Document number: DS36691 Rev. 3 - 2
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IMPORTANT NOTICE
NEW PRODUCT
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
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final and determinative format released by Diodes Incorporated.
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written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
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representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2014, Diodes Incorporated
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AP3440
Document number: DS36691 Rev. 3 - 2
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