AN-501 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Aperture Uncertainty and ADC System Performance by Brad Brannon and Allen Barlow APERTURE UNCERTAINTY Aperture uncertainty is a key ADC concern when performing IF sampling. The terms aperture jitter and aperture uncertainty are synonymous and are frequently interchanged in the literature. Aperture uncertainty is the sample-to-sample variation in the encoding process. It has three distinct effects on system performance. First, it can increase system noise. Second, it can contribute to the uncertainty in the actual phase of the sampled signal itself giving rise to increases in error vector magnitude. Third, it can heighten intersymbol interference (ISI). However, in typical communications applications, an aperture uncertainty that is sufficiently small to meet system noise constraints results in negligible impact on phase uncertainty and ISI. For example, consider the case of sampling an IF of 250 MHz. At that speed, even 1 ps of aperture jitter can limit any ADC’s SNR to only 56 dB, while for the same conditions, the phase uncertainty error is only 0.09 degrees rms based on a 4 ns period. This is quite acceptable even for a demanding specification such as GSM. The focus of this analysis is, therefore, on overall noise contribution due to aperture uncertainty. Figure 1 illustrates how an error in the sampling instant results in an error in the sampled voltage. Mathematically, the magnitude of the sampled voltage error is defined by the time derivative of the signal function. Consider a sine wave input signal v(t ) = A sin (2π ft ) (1) The derivative is dv (t ) = A 2πf cos (2πft ) dt (2) The maximum error occurs when the cosine function equals 1, that is, at t = 0. dv(0 ) = A2πf dt max (3) We see from Figure 1 that dv is the error in the sampled voltage corresponding to the jitter dt. For conceptual clarity, if we relabel dv as Verr and dt as ta (aperture error) and rearrange the factors, we get Verr = A2πft a (4) If ta is given as an rms value, the derived Verr is also rms. Although this is the error at maximum input slew and represents an upper bound rather than a nominal, this simple model proves surprisingly accurate and useful for estimating the degradation in SNR as a function of sample clock jitter. dv ENCODE dt Figure 1. RMS Jitter vs. RMS Noise 01399-001 ERROR VOLTAGE JITTER AND SNR As Equation 4 indicates, the error in the sampled voltage increases linearly with input frequency, so at high frequencies, for example, in IF sampled receiver applications, clock purity becomes extremely important. Sampling is a mixing operation: the input signal is multiplied by a local oscillator or in this case, a sampling clock. Because multiplication in time is convolution in the frequency domain, the spectrum of the sample clock is convolved with the spectrum of the input signal. Considering that aperture uncertainty is wideband noise on the clock, it shows up as wideband noise in the sampled spectrum, periodic and repeated around the sample rate. Rev. A | Page 1 of 4 AN-501 Next, an FFT is done at high (IF) frequency. The high frequency chosen should be as high as possible. Again, the SNR value without harmonics is measured. This time jitter is a contributor to noise and solving Equation 6 for ta yields Because ADC encode inputs have very high bandwidth, the effects of clock input noise can extend out many times the sample rate itself and alias back into the baseband of the converter. Therefore, this wideband noise degrades the noise floor performance of the ADC. Consider a sinusoidal input signal of amplitude A. Utilizing Equation 4, the SNR for an ADC limited by aperture uncertainty is (5) SNR = the high frequency SNR just measured ε = the value determined in the low frequency measurement. EXAMPLE: JITTER AND THE AD9246 The example shown here utilizes the AD9246 evaluation board, a 14-bit, 125 MSPS ADC. An external clock oscillator such as a Wenzel Sprinter or Ultra-Low Noise provides a suitable encode source. A mainstream RF synthesizer from Rohde & Schwarz or Agilent can be used for the analog source. Typically, these generators have insufficient phase noise performance for use as the encode source. For more information about configuring Analog Devices evaluation boards, please consult the individual product data sheet. WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz 3.3V SWITCHING POWER SUPPLY 1/ 2 (6) ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER where: f = analog input frequency. ta = aperture uncertainty (jitter). ε = “composite rms DNL” in LSBs, including thermal noise. N = number of bits. ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER CHB PARALLEL CMOS OUTPUTS EVALUATION BOARD BAND-PASS FILTER XFMR INPUT CLK CHA PARALLEL CMOS OUTPUTS SPI – + HSC-ADC-EVALB-DC FIFO DATA CAPTURE BOARD PC RUNNING ADC ANALYZER USB CONNECTION SPI SPI Figure 2. Aperture Uncertainty Measurement Setup with AD9246 Customer Evaluation Board This simple equation provides considerable insight into the noise performance of a data converter. MEASURING SUBPICOSECOND JITTER Aperture uncertainty is readily determined by examining SNR without harmonics as a function of analog input frequency. Two measurements are required for the calculation. The first measurement is done at a sufficiently low analog input frequency that the effects of aperture uncertainty are negligible. Since jitter is negligible, Equation 6 can be simplified and rearranged to solve for ε, the “composite DNL.” −SNR 20 − 1 6V DC 2A MAX 01399-002 Aperture jitter is not always the performance limiter. Equation 6 shows its effect in superposition with other noise sources. The first term in the brackets is the jitter from Equation 5. To that, we must add terms for quantization noise, DNL, and thermal noise. For other analytic purposes, each of these could be broken out separately, but for simplicity in isolating the effect of jitter, we combine them here in a single additional term. ε = 2N × 10 (8) where: Equation 5 illustrates why systems that require high dynamic range and high analog input frequencies also require a low jitter encode source. For an analog input of 200 MHz and only 300 femtoseconds rms clock jitter, SNR is limited to only 68.5 dB, well below the level commonly achieved at lower speeds by 12-bit converters. Note in Equation 5 that the jitter limit of SNR is independent of the converter resolution. (For the case just mentioned, a 14-bit converter would do no better.) 2 ⎡ ⎛1+ ε ⎞ ⎤ 2 SNR = −20 log⎢(2 πf t a ) + ⎜ N ⎟ ⎥ ⎝ 2 ⎠ ⎦⎥ ⎣⎢ 2 ⎞ ⎛1 + ε ⎞2 ⎟ −⎜ N ⎟ ⎟ ⎝ 2 ⎠ ⎠ 2πf VCC A = −20 log(2πft a ) Verr − SNR 20 GND SNR = 20 log ta = ⎛ ⎜10 ⎜ ⎝ Figure 3 is a 5 average, 64 K FFT of the AD9246 sampling a 2.3 MHz sine wave at 125 MSPS. Analog Devices’ ADC AnalyzerTM Software (www.analog.com/fifo) collects and processes the data to report SNR without harmonics. From the plots, the SNR is 72.05 dBFS. (7) Here, SNR is the low frequency value just measured. Rev. A | Page 2 of 4 AN-501 Figure 5 overlays plots of Equation 5 for various jitter values (the sloped lines) with ideal, quantization noise limited performance at various resolutions (the horizontal lines), and is a useful guide for quickly determining jitter limits based on analog input frequency and SNR requirements. 0 Device No.: 1 Avcc: 1.8 Volts –10 Dvcc: 1.8 Volts –20 Encode: 125. MSPS –30 Analog: 2.3 MHz SNR: 71.06 dB –40 SNRFS: 72.05 dBFS –50 UDSNR: 96.62 dB –60 NF: 30.69 dB SINAD: 70.87 dB 100 16 BITS –70 –80 2nd: –90.62 dBc 3rd: –86.59 dBc 2 3 –90 4th: –104.15 dBc –100 5th: –108.51 dBc 6th: –94.04 dBc 4 –110 WoSpur: –90.53 dBc + + 6 90 14 BITS 5 SNR (dB) Fund: –0.999 dBfs –120 THD: –84.55 dBc SFDR: 86.59 dBc 0 Samples: 65536 5 10 15 20 25 30 35 40 45 50 55 01399-003 –130 Noise Floor: –117.21 dBFS 60 FREQUENCY (MHz) Windowing: None 80 2p s 1p s 0.5 0.2 5 ps ps 0.1 25 ps 12 BITS 70 Figure 3. 2.3 MHz FFT Using this value for SNR in Equation 7 gives a “composite DNL (ε)” for this converter of 3.09 LSB. Next, the degradation in SNR as a function of analog input frequency is found. Figure 4 shows data from the same setup and clock, but using an analog input frequency of 201 MHz. Here, the noise floor has risen and the resulting SNR is 69.05 dBFS. Device: AD9246 –10 –20 Encode: 125. MSPS SNR: 67.98 dB –40 SNRFS: 69.05 dBFS –60 NF: 33.69 dB SINAD: 66.75 dB –70 Fund: –1.069 dBfs 3 2 –80 2nd: –78.21 dBc 3rd: –74.41 dBc + –90 4th: –103.12 dBc –100 5th: –104.29 dBc 6th: –93.26 dBc 6 5 4 –110 WoSpur: –90.65 dBc + –120 SFDR: 74.41 dBc Noise Floor: –114.2 dBFS –130 Samples: 65536 0 5 10 15 20 25 30 35 40 45 FREQUENCY (MHz) Windowing: None 50 55 60 01399-004 THD: –72.85 dBc Figure 4. 201 MHz FFT Using this SNR and the previous solution for ε, Equation 8 gives ta = ⎛ ⎜10 ⎜ ⎝ 2 ⎞ ⎛ 1 + 3.092 ⎞ 2 ⎟ −⎜ ⎟ ⎝ 214 ⎟⎠ ⎠ = 197 fs rms 2 π 201 × 10 6 − 69.05 20 1000 If the sample clock is generated as a sinewave, it can be distributed using power dividers and delivered to the ADC with a transformer as shown in Figure 6. This solution is simple and works well for many applications, especially in situations involving single-ended to differential conversion. –50 UDSNR: 93.4 dB 100 INPUT (MHz) System clocks commonly must be distributed to multiple converters, and additionally to the FPGAs, ASICs, and DSPs included in the signal chain. There are several ways to distribute clocks with the low jitter demanded by the converters. –30 Analog: 49.004 MHz 10 CLOCK DISTRIBUTION Device No.: 1 Dvcc: 1.8 Volts 50 Figure 5. Signal-to-Noise Ratio Due to Aperture Jitter 0 Avcc: 1.8 Volts 10 BITS 60 01399-005 Device: AD9246 (9) This value, 197 fs, is the combined aperture uncertainty for the AD9246 plus the clock oscillator. Since total noise squared is the sum of the squares of individual contributors, the jitter of the ADC itself is readily determined if the jitter of the source clock is known. Here a Wenzel ULN clock oscillator with about 50 fs jitter is used, giving a jitter for the ADC of about 190 fs. These simple measurements confirm that it is possible to measure very small aperture uncertainty numbers using readily available hardware and simple numeric calculations. However, more often than not the clock is a logic signal sourced directly from a PLL, VCO, or VCXO. In these cases, it is advantageous to use logic gates to fan out the signal and to drive the data converters. Table 1 summarizes the typical jitter that can be achieved with a variety of logic families. It should be noted that many of the older families, and even current FPGAs, cannot deliver acceptable performance. Some newer, high-speed devices do provide acceptable jitter and have the ability to translate singleended signals into differential signals as shown in Figure 7. Table 1. Gate Type FPGA 1 74LS00 74HCT00 74ACT00 MC100EL16 (PECL) AD9510 Clock Synthesis and Distribution NBSG16 (Reduced Swing ECL) 1 Jitter 33 to 50 ps 4.94 ps 2.20 ps 0.99 ps 0.70 ps 0.22 ps 0.20 ps Does not include the jitter introduced by input structure or internal routing gates, or the jitter associated with the use of internal DLL/PLL structures. Based on product data sheet peak-to-peak values ranging from ±100 ps to ±300 ps peak. Rev. A | Page 3 of 4 AN-501 ADT1–1WT CLOCK SOURCE In addition, the AD9510 includes many other features not available in discrete logic such as selectable output types (LVDS, PECL, and CMOS) and programmable fine delays. Figure 10 shows how the AD9510 can be used in a typical low jitter solution. CLK+ 0.1µF AD9444 01399-006 CLK– HSMS2812 DIODES Figure 6. Distribution and Differential Encode Options VS RSET GND CPRSET VCP VT DISTRIBUTION REF 0.1µF ENCODE 0.1µF N DIVIDER ENCODE FUNCTION 01399-007 VT R DIVIDER REFINB AD9444 PHASE FREQUENCY DETECTOR SYNCB, RESETB PDB PLL REF CHARGE PUMP PLL SETTINGS CLK1 Figure 7. Active Differential Drive Circuit CP STATUS CLK2 CLK1B CLK2B PROGRAMMABLE DIVIDERS AND PHASE ADJUST Clock trees employing cascaded gates are commonly used in digital circuits (see Figure 8), but jitter accumulates as the clock progresses down the tree. LVPECL OUT0 /1, /2, /3... /31, /32 OUT0B LVPECL OUT1 /1, /2, /3... /31, /32 OUT1B LVPECL ADC ENCODE INPUT OUT2 /1, /2, /3... /31, /32 ADC DATA LATCH SYSTEM CLOCK AD9510 OUT2B SCLK SDIO SDO LVPECL SERIAL CONTROL PORT OUT3 /1, /2, /3... /31, /32 OUT3B CSB LVDS/CMOS OUT4 /1, /2, /3... /31, /32 DAC CLOCK INPUT OUT4B LVDS/CMOS DAC DATA LATCH /1, /2, /3... /31, /32 OUT5 ΔT (A) OUT5B LVDS/CMOS /1, /2, /3... /31, /32 SYSTEM CLOCK (B) OUT6B LVDS/CMOS 01399-008 ADC ENCODE INPUT OUT6 ΔT OUT7 /1, /2, /3... /31, /32 Figure 8. Clock Distribution Chains OUT7B Figure 9. AD9510 Clock Synthesis and Distribution In a cascade of just three NBSG16 gates (one of the better performers), the cumulative rms jitter increases to 350 fs, which is a significant impact on system performance of an IF sampling system. It is better to avoid conventional clock trees altogether, and instead, approach clock generation and distribution as a system level function. Devices such as the AD9510 have optimized the clock paths to minimize total rms noise. By comparing Figure 8 and Figure 9, it is clear that the AD9510 offers the same function for clock distribution as that in Figure 8, but with an additive jitter of only 220 fs. In addition, this part includes an ultra low noise PLL similar to the ADF4106 that allows complete clock cleanup, synthesis, and distribution in a single package. 16 AD6633 AD9786 TX IF = ~190MHz 92.16MHz 491.52MHz MAIN TX LOOP FILTER DSP 32.768MHz REFERENCE AD9510 VCXO 92.16MHz 92.16MHz 14 AD6636 AD9246 RX IF = ~190MHz MAIN RX 92.16MHz 92.16MHz 14 AD9246 RX IF = ~190MHz DIVERSITY RX Figure 10. Typical Clock Distribution Application ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN01399-0-3/06(A) Rev. A | Page 4 of 4 01399-010 AD6636 01399-009 ECL/ PECL REFIN

- Similar pages