An Inside Look at High Speed AD Converter Accuracy Part 3

TECHNICAL ARTICLE
Rob Reeder
System Applications
Engineer,
Analog Devices, Inc.
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AN INSIDE LOOK AT
HIGH SPEED ADC
ACCURACY, PART 3
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Signal Chain Recap
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Signal chain accuracy analysis can be an overwhelming task to understand
in any design. In Part 2 of this series, many errors were discussed that accumulate throughout the signal chain and are eventually seen by the converter.
Remember, the converter is the bottleneck of the signal chain and ultimately
decides how accurately the signal can be represented. Therefore, choosing
the converter is key to setting the overall system requirements. In this
article, the focus will continue to build on this knowledge, analyzing the
types of dc errors that can accumulate throughout the given signal chain.
In Part 2 the goal was to design a simple data acquisition system that
could meet 0.1% accuracy (Figure 1). Meaning for every 1 V input, the
output would be either 0.99388 V or 1.00612 V. Therefore, the converter
was defined to have a capable dynamic range of 60 dB or 9.67 ENOB,
assuming a 10 V full scale. It has two stages of amplifiers, a multiplexer,
and an analog-to-digital converter (ADC). The sensor, cables, connector(s),
printed circuit board (PCB) parasitics, and any outside influences/errors
will be neglected in this analysis since this will depend heavily on the application or signal the designer is trying to measure.
To define references for each error, each stage of the analysis should be
broken down into individual sections. The first stage of the data acquisition signal chain is a simple difference amplifier (Figure 2). The amplifier
has a gain of 4× and input impedance of 500 Ω. The capacitors are in
place for optional filtering purposes.
Two types of errors can accumulate through a signal chain—dc and
ac. Errors that are dc or static, such as gain and offset, provide an
understanding of the signal chain’s accuracy or sensitivity. Errors of
the ac variety, otherwise known as noise and distortion, set the bounds
on performance and dynamic range of the system. Both are important
to understand because they both ultimately determine the resolution
of the system.
CFB
RF1
This article will specifically analyze dc errors, breaking down each inaccuracy as it relates to both passive and active devices. A matrix or spreadsheet will be developed to show how to add or accumulate error within
the signal through different methods.
For ac errors, refer to References 10 and 11. Here, a review of noise
basics, such as bandwidth summation and error accumulation from
an ac perspective, can determine the overall SNR of analog signal
chain design.
RI1
SensorX
Diff
RP1
CS
AV = 4
RS Input Z-500 Ω
Figure 2. A difference amplifier is the first stage of the data acquisition
signal chain.
CFB
RF1
RI1
SensorX
Diff
RP1
CS
RS
VCC
RO1
AV = 4
Input Z-500 Ω
RI2
RONX
8:1
Mux
RADC
Buf
AV = 1
RF2
CADC
FS Input = ±5 V p-p
DPU
ADC
DPD
VEE
Clock
Figure 1. This simple data acquisition signal chain system was developed to provide 0.1% accuracy.
Visit analog.com
12 Bits
2
An Inside Look at High Speed ADC Accuracy, Part 3
The amplifier’s output signal is then applied to one of the eight inputs of
the multiplexer (Figure 3). Each input is buffered with a damping resistor
(RO) to minimize charge kickback from the multiplexer’s channel switching. Each channel internally will have some parasitic or characterized RO
per the multiplexer’s data sheet specifications.
RO1
RON
8:1
Mux
Figure 3. This 8:1 multiplexer has eight buffered inputs.
The resulting channel signal is then applied to a unity-gain buffer stage
amplifier (Figure 4). The resistors are applied to minimize input bias
current imbalance.
RI2
AV = 1
RF2
Figure 4. A channel signal would be applied to this type of buffer amplifier.
After the signal is buffered, it’s applied to the 12-bit, 1 MSPS ADC where it
finally enters the digital domain (Figure 5). The series resistor is applied to
buffer or dampen the signal between the amplifier and converter, adding
source resistance between the two devices. This minimizes charge kickback from the converter to the amplifier, much like the multiplexer. This
also helps the amplifier output settle and prevents it from oscillating.
RADC
CADC
FS Input = ±5 Vp-p
DPU
ADC
12 Bits
DPD
VEE
All passive components have errors associated with them, especially
resistors. Resistors seem like simple devices, but they can cause errors
throughout any signal chain if not specified correctly for the design.
Choosing the right type of resistor and its composition isn’t covered here.
Keep in mind, though, that depending on the application, some resistor
types may be better suited than others.
Resistive dc errors result from nonideal resistor tolerances. Simply specifying the value tolerance isn’t enough. However, being overly critical about
resistor error tolerances can also yield diminishing returns and overcomplicate the analysis. At least four critical specifications need attention
when specifying a resistor type for a given signal chain:
1. Value tolerance, usually specified in %.
2. Temperature coefficient or drift, usually specified in ppm/°C.
3. Life drift or qualification, usually specified in % over a set amount of
hours (usually in 1000s).
4. Value tolerance ratio, value tolerance specified in % when two or more
resistors are present in a network or the same package and are matched
in value.
Buf
VCC
DC Passive Errors
Clock
Figure 5. Once a signal is buffered, it’s applied to a 12-bit, 1 MSPS ADC.
The capacitor provides a simple low-pass antialiasing filter (AAF) to
attenuate signals and noise outside the band of interest. The design of
the AAF depends greatly on the system’s design and application. Lastly,
the pull-up and pull-down diodes add input protection against any fault
conditions of extreme signal overload conditions that may be applied to
the converter’s input.
Now that all of the signal chain components have been defined, let’s start
looking at the errors associated with each stage. In the following sections,
both passive and active errors will be reviewed based on each of the
signal chain’s stages discussed here.
To give an example of how resistor errors can accumulate (Figure 6), let’s
look at the following: A 100 Ω resistor with a value tolerance of 1%, drift of
100 ppm/°C, and life tolerance of 5% will yield a resistance from 93.15 Ω
to 106.85 Ω over a 5000 hour life within an 85°C temperature range:
***
Tol Coef Life
Figure 6. This diagram illustrates a resistor error model.
Total Tolerance (RVALUE + RTOL + RCOEFF + RLIFE) = (RVALUE + ((RTOL/100) × RVALUE)
+ (((RCOEFF × 0.000001) × TempRange) × RVALUE) + ((RLIFE/100) × RVALUE))
= 94 Ω to 106 Ω.
Hard to find information side note: some components have a life specification of only 1000 hours. Yet the design may call for a much longer time—
say, 10,000 hours. To get around this, don’t multiply the 1000 hour figure
by 8.77 (8766 hours/year); it’s much too pessimistic. Long-term drift in
any precision analog circuit is going to have some amount of “random
walk” to it. It’s more correct to take the square root of this number or
√8.766 = ~3× the 1000 hour figure. Therefore, a 10,000 hour life number
is √10.000 = 3.16 × 1000 hour specification and so on.
It should be noted that capacitors and inductors have errors too. However,
these errors are usually negligible and add no substantial value for this
type of dc analysis. These devices are also reactive in nature and have the
greatest impact on filtering and bandwidth tolerances, which again isn’t
applied in this particular dc analysis.
Visit analog.com DC Active Errors
Table 2. Individual Multiplexor Errors
The signal chain described in Figure 1 has the most common building
blocks, which describes one approach to implementing a data acquisition system. It consists of two amplifiers, a multiplexer, and an ADC. Keep
in mind, however, that many types of active devices describe all sorts
of signal chains and different system topologies. All active devices will
have some sort of dc error(s) when implementing this type of analysis. It’s
important to decide which of these errors need to be taken into account to
understand the accuracy of the system under design.
Basically, two types/groups of errors are involved in dc accuracy. These
errors are individual and global to all active devices. Individual active
device errors will exhibit their known dc error relative to that device only.
Such errors can be found in their respective data sheets. For example,
input offset voltage of an amplifier would be considered an individual
error because this error is particular to this active device only.
Global errors are common to each of the active devices in the signal chain
or system by the same amount, but exhibit a different error based on the
active device’s individual performance (Figure 7). A global error example
would be line regulation of the bus’s supply and temperature. Now, let’s
break down each of these errors for the three active devices shown in the
signal chain.
It’s well-known that amplifiers are still far from ideal. They have many
errors that are commonly listed in the data sheet. Offset voltage and bias
current are two common errors, but it’s also important to include any drift
errors, long-term errors, and isolation errors such as power supply rejection ratio (PSRR). Table 1 shows a listing of the following errors that should
be considered when using amplifiers.
Table 1. Individual Amplifier Errors
Specification
Input Offset Voltage Drift (V/C)
Input Bias Current Drift (A/C)
Input Bias Current (A)
Long-Term Drift (1000 hrs) (V)
Input Offset Current (A)
Power Supply Rejection Ratio (PSRR) (dB)
Input Offset Voltage (V)
Common-Mode Rejection Ratio (CMRR) (dB)
Error
3.50 × 10 –6
200 × 10 –15
150 × 10 –9
3.75 × 10 –3
10 × 10 –9
–120
200 × 10 –6
–80
Specification
On Resistance (RON) (Ω)
Resistor Coefficient (ppm/°C)
Resistor Tolerance (%)
Channel Isolation (dB)
Error
400.00
200.00
20.00
–70.00
Converter errors were specifically reviewed in the first part of the series
(shown below). Offset, gain, and DNL are well-known and understood. It’s
important to include PSRR as well. The following list of converter errors
should be considered when using ADCs from Part 1:
XX
Relative accuracy, DNL, which was defined as ±0.5 LSBs.
XX
Relative accuracy tempco, DNL tempco, which is typically included in
the relative accuracy specification in the data sheet.
XX
Gain tempco error, which was ±2.5 LSBs (from the previous example).
XX
Offset tempco error, which was ±1.3 LBs (from the previous example).
XX
Power supply sensitivity, which is typically in the form of low frequency
PSRR within the first Nyquist zone; this can typically be expressed as
60 dB or ±2 LSBs for a 12-bit ADC.
To keep the article at a reasonable length, this discussion will not go
into the details on how each of these errors are derived within the active
device itself. All of these errors are well-defined and described in various
papers and texts. What’s important to note here is that all of the essential
errors have been considered so that the analysis is robust enough to meet
the system’s accuracy target specifications.
Individual active device errors have been suggested and defined. Now
global errors should be considered, which influence the signal chain
as a whole (Table 3). In this simple example, only temperature and line
regulation will be factored into the analysis as global errors. However, it is
important to add any other outside influences that may be inherent to the
particular application or design.
Table 3. Global Signal Chain
Specification
Temperature (°C)
Power-Supply Line Regulation (%/V)
Error
–45 to +85
50 × 10 –3
Multiplexers typically have fewer errors than an amplifier. The on resistance and channel isolation are the most influential multiplexer dc errors.
Table 2 lists the errors that should be considered when using multiplexers.
Global Signal Chain Errors
Temperature
Power Supply Line Regulation
CFB
RF1
RI1
SensorX
Diff
RP1
CS
RS
VCC
RO1
RI2
AV = 4
Input Z-500 Ω
RON
8:1
Mux
Amplifier Errors
Input Offset Voltage Drift
Input Bias Current Drift
Input Bias Current
Long-Term Drift (1000 hrs)
Input Offset Current
PSRR
Input Offset Voltage
CMRR
Multiplex Errors
On Resistence (RON)
Resistor Coefficient
Resistor Tolerance
Channel Isolation
RADC
Buf
AV = 1
FS Input = ±5 V p-p
DPU
CADC
RF2
Amplifier Errors
Input Offset Voltage Drift
Input Bias Current Drift
Input Bias Current
Long-Term Drift (1000 hrs)
Input Offset Current
PSRR
Input Offset Voltage
CMRR
ADC
12 Bits
DPD
VEE
Clock
Converter Errors
Differential Nonlinearity (DNL)
Offset Error
Gain Error
Offset Drift
Gain Drift
PSRR
Figure 7. Active devices suffer from two types of dc accuracy errors—individual and global.
3
4
An Inside Look at High Speed ADC Accuracy, Part 3
Putting It All Together
Total Accumulation
Now that all of the errors have been defined both actively and passively,
it’s time to put them into a spreadsheet to calculate dc accuracy of the
signal chain. Table 4 shows one such approach to accomplish this task.
Accuracy can be calculated in many ways and can take on many forms.
Depending on how this is viewed by the designer, it should be understood
and documented to avoid creating any misrepresented results. Remember
from Part 1, simply taking the root sum square (RSS) of all these error
sources might seem overly pessimistic. Yet, a statistical tolerance may be
overly optimistic (the total sum of errors divided by the number of errors).
Finding the actual tolerance of the entire signal chain error should be
somewhere between these two thoughts or methods.
Even though there are many ways to go about analyzing signal chain
accuracy, using the spreadsheet method offers the greatest flexibility. It
also provides a solid understanding on how to go about crushing all of
these error numbers down within the signal chain design. This method
allows the designer to make quick and effective trade-offs between many
suitable devices that may be considered for the design.
Take the time to produce a spreadsheet that has a good layout and is
orderly. At the top, global errors and signal chain specifications are defined
because these numbers affect the performance of the signal chain as a
whole. The amplifier specifications/errors were also placed at the top,
since there are many errors and two amplifier stages throughout the
signal chain.
Continuing down, on the left-hand side of the spreadsheet, all of the errors
are divided down into each circuit stage. The resistor errors were also
grouped with each stage to understand the trade-offs accordingly. The
right-hand side shows a continuous calculation and accumulation of error
as the signal flows to and from each stage.
In the calculations, all of the errors are put into a voltage format. This
makes it easier, since the converter is at the end of the signal chain and
has an input full scale described in voltage. RTO (refer to output) is used
to describe the continuous accumulation of errors from one stage to the
next. Each stage also produces a separate sum total and RSS (root sum
square) total to show how the errors are accumulating depending on the
method used.
Therefore, the end result in Table 4 shows a total accumulation of ±2.6%
summed error and a ±1.6% RSS error. This is for the entire signal chain
discussed throughout this article, given the data sheet specifications for
each part and the global conditions stated previously at 26°C.
Therefore, when adding (accumulating) accuracy errors in the entire signal
chain or any accuracy system analysis, the designer could use a weighted
error source approach (as shown in the ADC example in Part 1), then RSS
these error sources together. This will provide the best method in determining the entire signal chain’s overall error.
Conclusion
Many errors occur with both passive and active devices. Not all are
important, but keep in mind those that are important to the signal chain
application at hand. Not all errors may be valid for every application.
Deciding which errors are the most dominant or have the most influence
or weight is essential to any dc accuracy error analysis. A spreadsheet
was developed to show how the signal chain example in this article
meets the requirements of <±2.0% accuracy. For a copy of this spreadsheet, please contact Rob Reeder at [email protected] or the
Analog Devices EngineeringZone.®
Choosing the right passives can make just as much a difference in the
total accumulated error in the signal chain as well as the active devices.
Creating and partitioning a spreadsheet makes it simple and tidy to consider many different devices and trade-offs quickly. Finally, accumulation
of error can take on many forms, and the most common practice used is
the RSS accuracy method.
However, some may argue that a weighted summation approach of errors
is the right way to determine a true “worst-case dc error.” If not, this can
easily cause a signal chain to be overdesigned, leading to more parts to
compensate for the original set of errors. Not to mention the increase in
cost and the design’s size, weight, and power (SWaP).
Visit analog.com Table 4. Full Signal Chain Analysis Example
Signal Chain Specifications
Value
Input Signal (V)
1 × 10
Specification
Minimum
Unit
Maximum
Amplifier Specifications
1
ADC Number of Bits
1.2 × 101
Input offset voltage drift (V/C)
3.5 × 10–6
V
3.50 × 10–6
ADC Input Full Scale (Diff V p-p) with Margin
9.97 × 100
Input bias current drift (A/C)
2 × 10–13
A
2 × 10–13
1 × 100
Input bias current
1.5 × 10–7
A
2.44 × 10–3
Long-term drift (V) (5000 hrs)
3.75 × 10–3
V
1 × 10
Input offset current (A)
1 × 10–8
A
ADC Input Full Scale (Diff V p-p)
ADC LSB Size (V p-p)
Temperature Range (–50°C to +80°C)
1 = 26°C
0
Kelvin (K)
2.9915 × 102
PSRR (dB)
–1.2 × 102
V
Boltzmann’s Constant (W-s/K)
1.38 × 10–23
Input offset voltage (V)
2 × 10–4
V
LDO Reg Line Regulation (%/V)
5 × 10–2
1st stage CMRR (dB)
–8 × 101
V
1st Stage Amplifier CMR (V)
5 × 100
ADC buffer CMRR (dB)
–8 × 101
V
5 × 10–4
Amplifier Buffer CMR (V)
5 × 100
En_op (V/√Hz)
6 × 10–9
V
3.36 × 10–6
Supply Voltage
7 × 100
In_op (nA/√Hz)
8 × 10–13
A
4.4829 × 10–10
BW (Hz)
2 × 105
Noise voltage (V p-p)
1.5 × 10–7
V
5.303 × 10–8
Nosie BW (Hz)—1st-Order System
3.14 × 105
Nosie BW (Hz)—2nd-Order System
2.444 × 105
Inputs
1st Stage Amplifier Circuit—Difference Amplifier
Amplifier Gain (Av)
3.50 × 10–9
5 × 10–4
Minimum
Unit
Maximum
Total tolerance (RF1 + Rtol + RCOEFF + RLIFE)
2.48122 × 104
Ω
2.49878 × 104
2.49878 × 104
1 × 100
Total tolerance (RF1 + Rtol + Rcoeff + Rlife)
2.48745 × 104
Ω
RI1 (Ω)
2.49 × 104
Total tolerance (Rp1 + Rtol + Rcoeff + Rlife)
1.24217 × 104
Ω
1.24939 × 104
RF1 (Ω)
2.49 × 104
Total tolerance (Ro1 + Rtol + Rcoeff + Rlife)
9.96475 × 101
Ω
1.003525 × 102
RP1 (Ω) = Ri1 || Rf1
1.245 × 104
Total tolerance (Gain = Rf1/Ri1)
9.954660 × 10–1
Gain
1.0071 × 100
9.9547 × 100
V
1.00707 × 101
RO1 (Ω)
1 × 102
Signal level
Resistor Coefficient (ppm/°C)
2.5 × 101
Input current offset × RP1—RTO
8.748575 × 10–7
V
8.839525 × 10–7
Resistor Tolerance (%)
1 × 10–1
Input offset voltage—RTO
4.060773 × 10–4
V
4.084398 × 10–4
2.5 × 10
Input bias error—RTO
–2.16197 × 10
V
2.17455 × 10–5
1 stage total accuracy error (sum)
–3
1.3831 × 10
V
1.4346 × 10–3
1st stage total accuracy error (RSS)
1.0774 × 10–3
V
1.0837 × 10–3
Signal level (sum)
9.9560 × 10–0
V
1.00722 × 101
Resistor Life Tolerance (%), 5000 hrs
–1
–5
st
Signal level (RSS)
Signal Mux
RON (Ω)
4 × 102
Total tolerance (Ron + RTOL + Rcoeff)
Resistor Coefficient (ppm/C)
2 × 10
Channel-to-channel isolation error
Resistor Tolerance (%)
2 × 10
Channel Isolation (dB)
–7 × 101
2
9.9557 × 100
V
1.00718 × 101
3.199200 × 102
Ω
4.8008 × 102
–3
1.5811 × 10
V
1.5811 × 10–3
5.60574 × 104
1
Amplifier Buffer Circuit
Resistor Coefficient (ppm/C)
2.5 × 101
Total tolerance (Ri2 + Rtol + Rcoeff + Rlife)
55.9426 × 104
Ω
Resistor Tolerance (%)
1 × 10–1
Total tolerance (Rf2 + Rtol + Rcoeff + Rlife)
5.61424 × 103
Ω
5.62576 × 104
Total tolerance (Gain = Rf2/Ri2)
1.0015 × 100
Gain
1.0056 + × 100
V
1.01305 × 101
V
1.01301 × 101
2.805049 × 10
V
2.805039 × 10–4
Resistor Life Tolerance (%), 5000 hrs
Unity-Gain Buffer (Av)
2.5 × 10–1
Signal level (sum)
9.9727 × 100
Ri2 (Ω)
4
5.6 × 10
Signal level (RSS)
9.9724 × 10
Rf2 (Ω)
5.62 × 10
Input current offset × Ri2—RTO
Radc (Ω)
1 × 100
4
0
–4
3.32 × 10
Input offset voltage—RTO
3.9595 × 10
V
3.9758 × 10–3
RE1 (Ω), (Diode Resistance)
1 × 10–1
Input bias error—RTO
1.56844 × 10–5
V
7.43156 × 10–5
RE2 (Ω), (Diode Resistance)
1 × 10–1
ADC buffer total accuracy error (sum)
4.7564 × 10–3
V
4.8334 × 10–3
ADC buffer total accuracy error (RSS)
4.0009 × 10–3
V
4.0179 × 10–3
Signal level (sum)
9.9775 × 100
V
1.01353 × 101
Signal level (RSS)
9.9764 × 100
V
1.01342 × 101
1
–3
ADC Circuit
Linearity, INL (LSB) – 1.5 = DS
1.5 × 100
V
3.6621 × 10–3
Offset Error (LSB) – 10 = DS
1 × 101
V
2.44141 × 10–2
Gain Error (%FSR) – 0.1 = DS
1 × 10–1
V
1 × 10–2
Offset Drift (ppm/C) – 30 = DSFT
3 × 101
V
3 × 10–4
Gain Drift (ppm/C) – 40 = DSFT
4 × 101
V
4 × 10–4
PSRR (dB) – 5 LSB = DSFT
–6 × 101
V
3.5 × 10–6
Clock Rate, Fs (Hz)
4 × 105
V
2.66403 × 10–2
ADC total accuracy error
Ideal 12-bit SNR (dB)
1
7.4 × 10
Total accuracy error (summed)
3.43610 × 10
V
3.44895 × 10–2
Data Sheet Min SINAD FS (dB)
6.5 × 101
Total accuracy error (RSS)
2.7007 × 10–2
V
2.70097 × 10–2
Data Sheet ENOB (bits)
1.05 × 101
Signal level (summed)
1.00041 × 101
V
1.01620 × 101
Signal level (RSS)
1.00031 × 101
V
1.01608 × 101
DC accuracy (± – %)
1.5774 × 100
%
Input Variables
Signal Accumulation
–2
Error Accumulation
Output Results
5
References
1
Cletus J. Kaiser. The Resistor Handbook. 2nd Edition, 1-11.
2
MIL-PRF-55342H.
3
Walt Kester. The Data Conversation Handbook. Analog Devices Inc.
4
Walter G. Jung. IC Op Amp Cookbook. 3rd Edition.
AN102: “Errors, What Are They and How Bad Can They Be?”
Dataforth Corp.
5
6
AN504: “SCM5B, Interpreting Drift Specifications.” Dataforth Corp.
Eamon Nash. Errors and Error Budget Analysis in Instrumentation
Amplifier Applications. Analog Devices, Inc.
Online Support Community
Engage with the Analog Devices technology experts in our online
support community. Ask your tough design questions, browse FAQs,
or join a conversation.
ez.analog.com
7
Eamon Nash. A Practical Review of Common Mode and Instrumentation
Amplifiers. Analog Devices, Inc.
8
Robert G. Irvine. “Operational Amplifier Characteristics and
Applications.” 3rd Edition.
9
MT-230, Noise Considerations in High Speed Converter Signal Chains.
Analog Devices, Inc.
10
“Noise Considerations in High Speed Converter Signal Chains.” DSP—
FPGA, August 2013.
11
Rob Reeder. “An Inside Look at High Speed ADC Accuracy,” Electronic
Design, June, 2015.
12
Rob Reeder. “An Inside Look at High Speed ADC Accuracy, Part 2.”
Electronic Design, November 2015.
13
CN-0350: “12-Bit, 1 MSPS, Single-Supply, Two-Chip Data Acquisition
System for Piezoelectric Sensors.” Analog Devices, Inc.
14
About the Author
Rob Reeder is a system applications engineer at Analog Devices
in the Aerospace and Defense Group in Greensboro, NC, focusing
on military and aerospace applications. He has published numerous papers on converter interfaces, converter testing, and analog
signal chain design for a variety of applications. Formerly, Rob was
an applications engineer for the high speed converter product line
for eight years. His prior experience also includes test development
and analog design engineering for the Multichip Products Group at
ADI, designing analog signal chain modules for space, military, and
high reliability applications for five years. Rob received his MSEE
and BSEE from Northern Illinois University in DeKalb, III, in 1998 and
1996, respectively. When Rob isn’t writing papers late at night or in
the lab hacking up circuits, he enjoys hanging around at the gym,
mixing techno music, building furniture out of old pallets, and most
importantly, chilling out with his two boys.
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