MCP19114/5 MCP19114/5 Flash Memory Programming Specification 1.1 This document includes the programming specifications for the following devices: This family of devices requires one power supply for VIN, see Table 6-1. The VDD that is used to bias all internal circuitry is internally generated and regulated to 5V. Analog circuitry is powered from internally generated AVDD and is regulated to 4V. • MCP19114 • MCP19115 1.0 PROGRAMMING THE MCP19114 AND MCP19115 DEVICES 1.2 Program/Verify Mode The Program/Verify mode for this family of devices allows programming the user program memory, the user ID locations, the Calibration Word and the Configuration Word. The MCP19114/5 devices are programmed using a serial method. The Serial mode will allow these devices to be programmed while in the user’s system. These programming specifications apply to all of the above devices in all packages. GPB1/AN4/VREF2 ICOMP IFB VS VIN VDD 23 22 21 20 19 PIN DIAGRAM – 24-PIN QFN (MCP19114) 24 FIGURE 1-1: Hardware Requirements GPA0/AN0/TEST_OUT 1 18 VDR GPA1/AN1/CLKPIN 2 17 PDRV GPA2/AN2/T0CKI/INT 3 16 SDRV MCP19114 GPA3/AN3 4 15 PGND GPA7/SCL/ICSPCLK 5 14 AGND GPA6/CCD/ICSPDAT 6 13 IP 2014 Microchip Technology Inc. 11 12 ISN 9 DESATN ISP 8 GPB0/SDA DESATP/ISOUT 10 7 GPA5/MCLR/TEST_EN EXP-25 DS20005270A-page 1 MCP19114/5 TABLE 1-1: PIN DESCRIPTIONS IN PROGRAM/VERIFY MODE: MCP19114 During Programming Pin Name Function Pin Type GPA7 ICSPCLK I GPA6 ICSPDAT I/O MCLR Program/Verify mode Pin Description Clock Input – Schmitt Trigger Input Data Input/Output – Schmitt Trigger Input (1) Program Mode Select P VIN VIN P Device Power Supply Input VDD VDD P Power Supply Output GND VSS P Ground Legend: I = Input, O = Output, P = Power Note 1: In the MCP19114, the programming high voltage is internally generated. To activate the Program/Verify mode, voltage of VIHH and a current of IIHH (see Table 6-1) need to be applied to the MCLR input. GPB6/AN7 GPB5/AN6/ICSPCLK GPB1/AN4/VREF2 ICOMP IFB VS VIN 27 26 25 24 23 22 PIN DIAGRAM – 28-PIN QFN (MCP19115) 28 FIGURE 1-2: GPA0/AN0/TEST_OUT 1 21 VDD GPA1/AN1/CLKPIN 2 20 VDR GPA2/AN2/T0CKI/INT 3 19 PDRV GPB4/AN5/ICSPDAT 4 18 SDRV GPA3/AN3 5 17 PGND GPA7/SCL 6 16 AGND GPA6/CCD 7 15 IP MCP19115 DS20005270A-page 2 8 9 10 11 12 13 14 GPA5/MCLR/TEST_EN GPB7_CCD GPB0/SDA DESATN DESATP/ISOUT ISP ISN EXP-29 2014 Microchip Technology Inc. MCP19114/5 TABLE 1-2: PIN DESCRIPTIONS IN PROGRAM/VERIFY MODE: MCP19115 During Programming Pin Name Function Pin Type GPB5 ICSPCLK I GPB4 ICSPDAT I/O MCLR Program/Verify mode Pin Description Clock Input – Schmitt Trigger Input Data Input/Output – Schmitt Trigger Input (1) Program Mode Select P VIN VIN P Device Power Supply Input VDD VDD P Power Supply Output GND VSS P Ground Legend: I = Input, O = Output, P = Power Note 1: In the MCP19115, the programming high voltage is internally generated. To activate the Program/Verify mode, voltage of VIHH and a current of IIHH (see Table 6-1) need to be applied to the MCLR input. 2014 Microchip Technology Inc. DS20005270A-page 3 MCP19114/5 NOTES: DS20005270A-page 4 2014 Microchip Technology Inc. MCP19114/5 2.0 MEMORY DESCRIPTION 2.1 Program Memory Map The user memory space extends from 0x0000 to 0x1FFF. In Program/Verify mode, the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The Program Counter (PC) will increment from 0x0000 to 0x1FFF and wrap to 0x0000. If the PC is between 0x2000 and 0x3FFF, it will wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a ‘1’, thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter Program/Verify mode as described in Section 3.0 “Program/Verify Mode”. For all of the devices covered in this document, the configuration memory space, 0x2000 to 0x208F, is physically implemented. However, only locations 0x2000 to 0x2003, 0x2007 and 0x2080 to 0x2089 are available. Other locations are reserved. 2.2 User ID Locations A user may store identification information (user ID) in four designated locations. The user ID locations are mapped in 0x2000 to 0x2003. It is recommended that the user uses only the seven Least Significant bits (LSbs) of each user ID location. The user ID locations read out normally, even after code protection is enabled. It is recommended that ID locations are written as ‘xx xxxx xbbb bbbb’, where ‘bbb bbbb’ is the user ID information. The 14 bits may be programmed, but only the seven LSbs are read and displayed by the MPLAB® Integrated Development Environment (IDE). 2.3 Calibration Word For all of the devices covered in this document, Calibration Words are included to allow storing the trim values for various analog peripherals (i.e., INTOSC module) at final test. These values are stored in Calibration Words 0x2080, 0x2081, 0x2082, 0x2083,0x2084, 0x2085, 0x2086, 0x2087, 0x2088, 0x2089 and 0x208A. See the applicable device data sheet for more information. The Calibration Words do not necessarily participate in the erase operation, unless a specific procedure is executed. Therefore, the device can be erased without affecting the Calibration Words. This simplifies the erase procedure, since these values do not need to be read and restored after the device is erased. 2014 Microchip Technology Inc. DS20005270A-page 5 MCP19114/5 FIGURE 2-1: MCP19114 AND MCP19115 PROGRAM MEMORY MAPPING 4 kW Implemented 0FFF 2000 User ID Location 2001 User ID Location 2002 User ID Location 2003 User ID Location 2004 ICD Instruction 2005 Manufacturing Codes 2006 Device ID 2007 Configuration Word 2008-207F Reserved 2080-208F Calibration Words DS20005270A-page 6 Program Memory Maps to 0-FFF 1FFF 2000 Implemented 208F 2090 Unimplemented 2100 Maps to 2000-20FF Configuration Memory 3FFF 2014 Microchip Technology Inc. MCP19114/5 3.0 PROGRAM/VERIFY MODE Two methods are available to enter the Program/Verify mode. “TEST_EN-first” is entered by holding ICSPDAT and ICSPCLK low while raising the MCLR pin from VIL to VIHH (high voltage), then applying VDD and data. This method can be used for any Configuration Word selection and must be used if the internal MCLR option is selected (MCLRE = 0). The TEST_EN-first entry prevents the device from executing code prior to entering Program/Verify mode. See the timing diagram in Figure 3-1. The second entry method, “VDD-first”, is entered by applying VDD, holding ICSPDAT and ICSPCLK low, then raising MCLR pin from VIL to VIHH (high voltage), followed by data. This method can be used for any Configuration Word selection, except when the internal MCLR option is selected (MCLRE = 0). This technique is useful when programming the device with VDD already applied, for it is not necessary to disconnect the VDD to enter the Program/Verify mode. See the timing diagram in Figure 3-2. Once in Program/Verify mode, the program memory and configuration memory can be accessed and programmed in serial fashion. ICSPDAT and ICSPCLK are Schmitt Trigger inputs in this mode. The sequence that enters the device into the Program/Verify mode places all other logic into the Reset state (the MCLR pin was initially at VIL). Therefore, all I/Os are in the Reset state (high-impedance inputs) and the PC is cleared. To prevent a device configured with internal MCLR from executing after exiting Program/Verify mode, VDD needs to power down before TEST_EN. See Figure 3-3 for the timing. The MCP19114/5’s VDD is internally generated by applying voltage to the VIN pin. See Table 6-1 for the appropriate range for VIN. To remove VDD, VIN must be removed. FIGURE 3-1: TEST_EN-FIRST PROGRAM/VERIFY MODE ENTRY TPPDP THLD0 TEST_EN FIGURE 3-2: VDD-FIRST PROGRAM/VERIFY MODE ENTRY THLD0 TPPDP TEST_EN VDD ICSPDAT ICSPCLK Note: FIGURE 3-3: This method of entry is valid if the internal MCLR is not selected. PROGRAM/VERIFY MODE EXIT THLD0 TEST_EN VDD ICSPDAT ICSPCLK 3.1 Program/Erase Algorithms The MCP19114/5 program memory may be written in two ways. The fastest method writes four words at a time. However, one-word writes are also supported. The four-word algorithm is used to program the program memory only. The one-word algorithm can write any available memory location (i.e., program memory, configuration memory and calibration memory). After writing the array, the PC may be reset and read back to verify the write. It is not possible to verify immediately following the write because the PC can only increment, not decrement. A device Reset will clear the PC and set the address to ‘0’. The Increment Address command will increment the PC. The Load Configuration command will set the PC to 0x2000. The available commands are shown in Table 3-1. VDD ICSPDAT ICSPCLK Note: This method of entry is valid, regardless of the Configuration Word selected. 2014 Microchip Technology Inc. DS20005270A-page 7 MCP19114/5 3.1.1 FOUR-WORD PROGRAMMING The MCP19114/5 program memory can be written four words at a time using the four-word algorithm. Configuration memory (addresses >0x2000) and non-aligned (addresses modulo 4 not equal to zero) starting addresses must use the one-word programming algorithm. This algorithm writes four sequential addresses in program memory. The four addresses must point to a four-word block with address modulo 4 of 0, 1, 2 and 3. For example, programming address 4 through 7 can be programmed together. Programming addresses 2 through 5 will create an unexpected result. 3.1.2 ERASE ALGORITHMS The MCP19114/5 devices will erase different memory locations depending on the PC and CP. The following sequences can be used to erase noted memory locations. To erase the program memory and Configuration Word (0x2007), the following sequence must be performed. Note the Calibration Words (0x2080 to 0x208F) and User ID (0x2000-0x2003) will not be erased. 1. 2. Do a Bulk Erase Program Memory command. Wait TERA to complete erase. The sequence for programming four words of program memory at a time is: To erase the user ID (0x2000-0x2003), Configuration Word (0x2007) and program memory, use the following sequence. Note that the Calibration Words (0x2080 to 0x208F) will not be erased. 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Load a word at the current program memory address using the Load Data For Program Memory command. This location must be address modulo 4 equal to 0. Issue an Increment Address command to point to the next address in the block. Load a word at the current program memory address using the Load Data For Program Memory command. Issue an Increment Address command to point to the next address in the block. Load a word at the current program memory address using the Load Data For Program Memory command. Issue an Increment Address command to point to the next address in the book. Load a word at the current program memory address using the Load Data For Program Memory command. Issue a Begin Programming command externally timed. Wait TPROG1. Issue End Programming. Wait TDIS. Issue an Increment Address command to point to the start of the next block of addresses. Repeat steps 1 through 12 as required to write the desired range of program memory. See Figure 3-12 for more information. 2. 3. Perform Load Configuration with dummy data to point the PC to 0x2000. Perform a Bulk Erase Program Memory command. Wait TERA to complete erase. 3.1.3 SERIAL PROGRAM/VERIFY OPERATION The ICSPCLK pin is used as a clock input and the ICSPDAT pin is used for entering command bits and for data input/output during serial operation. To input a command, ICSPCLK is cycled six times. Each command bit is latched on the falling edge of the clock with the LSb of the command being input first. The data input onto the ICSPDAT pin is required to have a minimum setup and hold time (see Table 6-1), with respect to the falling edge of the clock. Commands that have data associated with them (Read and Load) are specified to have a minimum delay of 1 µs between the command and the data. After this delay, the clock pin is cycled 16 times with the first cycle being a Start bit and the last cycle being a Stop bit. During a read operation, the LSb will be transmitted onto the ICSPDAT pin on the rising edge of the second cycle. For a load operation, the LSb will be latched on the falling edge of the second cycle. A minimum 1 µs delay is also specified between consecutive commands, except for the End Programming command, which requires a 100 µs (TDIS). All commands and data words are transmitted LSb first. Data is transmitted on the rising edge and latched on the falling edge of the ICSPCLK. To allow decoding of commands and reversal of data pin configuration, a time separation of at least 1 µs (TDLY1) is required between a command and a data word. The commands that are available are described in Table 3-1. DS20005270A-page 8 2014 Microchip Technology Inc. MCP19114/5 TABLE 3-1: COMMAND MAPPING FOR MCP19114/5 Command Mapping (MSb … LSb) Load Configuration x x 0 0 Data 0 0, data (14), 0 0 Load Data for Program Memory x x 0 0 1 0 0, data (14), 0 Read Data from Program Memory x x 0 1 0 0 0, data (14), 0 Increment Address x x 0 1 1 0 Begin Programming x 1 1 0 0 0 End Programming x 0 1 0 1 0 Bulk Erase Program Memory x x 1 0 0 1 Internally Timed Row Erase Program Memory x 1 0 0 0 1 Internally Timed 3.1.3.1 Externally Timed Load Configuration The Load Configuration command is used to access the Configuration Word (0x2007), User ID (0x2000-0x2003) and Calibration Words (0x2080 to 0x208F). This command sets the PC to address 0x2000 and loads the data latches with one word of data. To access the configuration memory, send the Load Configuration command. Individual words within the configuration memory can be accessed by sending Increment Address commands and using load or read data for program memory. After the 6-bit command is input, the ICSPCLK pin is cycled an additional 16 times for the Start bit, 14 bits of data and the Stop bit (see Figure 3-4). After the configuration memory is entered, the only way to get back to the program memory is to exit the Program/Verify mode by taking MCLR low (VIL). FIGURE 3-4: LOAD CONFIGURATION COMMAND TDLY3 1 2 3 4 5 0 0 X 6 1 2 3 4 5 15 16 ICSPCLK ICSPDAT 0 00 X TDLY1 strt_bit LSb MSb stp_bit TSET1 THLD1 2014 Microchip Technology Inc. DS20005270A-page 9 MCP19114/5 3.1.3.2 Load Data For Program Memory After receiving this command, the chip will load in a 14-bit “data word” when 16 cycles are applied, as described in Section 3.1.3.1 “Load Configuration”. A timing diagram of this command is shown in Figure 3-5. FIGURE 3-5: LOAD DATA FOR PROGRAM MEMORY COMMAND 1 2 3 4 5 0 0 X 6 TDLY2 1 2 3 4 5 15 16 ICSPCLK 1 0 ICSPDAT TSET1 strt_bit X LSb MSb TDLY1 THLD1 3.1.3.3 stp_bit TSET1 THLD1 Read Data From Program Memory After receiving this command, the chip will transmit data bits out of the program memory (user or configuration) currently accessed, starting with the second rising edge of the clock input. The data pin will go into Output mode on the second rising clock edge and it will revert to Input mode (high-impedance) after the 16th rising edge. If the program memory is code-protected (CP = 0), the data is read as zeros. A timing diagram of this command is shown in Figure 3-6. FIGURE 3-6: READ DATA FROM PROGRAM MEMORY COMMAND TDLY3 1 2 3 4 1 0 5 1 6 2 3 ICSPCLK ICSPDAT 5 15 16 TDLY3 1 0 0 X X MSb strt_bit stp_bit LSb TSET1 THLD1 input DS20005270A-page 10 4 TDLY1 output input 2014 Microchip Technology Inc. MCP19114/5 3.1.3.4 Increment Address The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 3-7. Incrementing past 0x07FF in program memory rolls the program counter to ‘0’. Incrementing past 203Fh in test memory returns the program counter to 2000h. It is not possible to decrement the address counter. To reset this counter, the user should exit and reenter Program/Verify mode. FIGURE 3-7: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) TDLY2 1 2 3 4 5 Next Command 1 6 2 ICSPCLK 0 ICSPDAT 1 0 1 X X X 0 TSET1 THLD1 3.1.3.5 TDLY1 Begin Programming (Externally Timed) A Load command must be given before every Begin Programming command. Programming of the appropriate memory (program memory, configuration or calibration memory) will begin after this command is received and decoded. Programming requires (TPROG) time and is terminated using an End Programming command. A timing diagram for this command is shown in Figure 3-8. The addressed locations are not erased before programming. FIGURE 3-8: BEGIN PROGRAMMING (EXTERNALLY TIMED) VIHH TPROG MCLR End Programming Command 1 2 3 0 0 0 4 5 6 1 2 ICSPCLK ICSPDAT 1 1 X X 0 TSET1 THLD1 2014 Microchip Technology Inc. DS20005270A-page 11 MCP19114/5 3.1.3.6 End Programming After this command is performed, the write procedure will stop. A timing diagram of this command is shown in Figure 3-9. FIGURE 3-9: END PROGRAMMING (SERIAL PROGRAM/VERIFY) VIHH MCLR Next Command 1 2 3 0 1 0 4 5 1 6 2 ICSPCLK ICSPDAT 1 0 X X TDIS 0 TSET1 THLD1 3.1.3.7 Bulk Erase Program Memory After this command is performed, the entire program memory and Configuration Word (0x2007) are erased. The user ID and calibration memory may also be erased, depending on the value of the PC. See Section 3.1.2 “Erase Algorithms” for erase sequences. A timing diagram for this command is shown in Figure 3-10. FIGURE 3-10: BULK ERASE PROGRAM MEMORY COMMAND TERA 1 2 3 0 0 4 5 6 Next Command 1 2 ICSPCLK 1 ICSPDAT X X X 0 TSET1 TSET1 THLD1 DS20005270A-page 12 1 THLD1 2014 Microchip Technology Inc. MCP19114/5 3.1.3.8 Row Erase Program Memory This command erases the 16-word row of program memory pointed to by PC<11:4>. If the program memory array is protected (CP = 0) or the PC points to the configuration memory (>0x2000), the command is ignored. To perform a Row Erase Program Memory command, the following sequence must be performed. 1. 2. Execute a Row Erase Program Memory command. Wait TERA to complete a row erase. FIGURE 3-11: ROW ERASE PROGRAM MEMORY COMMAND TERA 1 2 3 4 5 0 0 0 1 Next Command 1 6 2 ICSPCLK 1 ICSPDAT FIGURE 3-12: x x 0 ONE-WORD PROGRAMMING FLOWCHART Start Bulk Erase Program Memory (1,2) Program Cycle Load Data for Program Memory One-word Program Cycle Begin Programming Command (Externally timed) Read Data from Program Memory Data Correct? No Report Programming Failure Wait TPROG Yes Increment Address Command No All Locations Done? End Programming Yes Program User ID/Config. bits Wait TDIS Done Note 1: 2: This step is optional if the device has already been erased or has not been previously programmed. If the device is code-protected or must be completely erased, then bulk erase the device per Figure 3-15. 2014 Microchip Technology Inc. DS20005270A-page 13 MCP19114/5 FIGURE 3-13: FOUR-WORD PROGRAMMING FLOWCHART Program Cycle Load Data for Program Memory Increment Address Command Start Bulk Erase Program Memory (1,2) Load Data for Program Memory Increment Address Command Four-word Program Cycle Increment Address Command No All Locations Done? Load Data for Program Memory Yes Increment Address Command Program User ID/Config. bits Done Load Data for Program Memory Begin Programming Command (Externally timed) Wait TPROG End Programming Wait TDIS Note 1: 2: This step is optional if the device is erased or not previously programmed. If the device is code-protected or must be completely erased, then bulk erase the device per Figure 3-15. DS20005270A-page 14 2014 Microchip Technology Inc. MCP19114/5 FIGURE 3-14: PROGRAM FLOWCHART – CONFIGURATION MEMORY Start Program Cycle Load Configuration Load Data for Program Memory One-word Program Cycle (User ID) Begin Programming Command (Externally timed) Read Data from Program Memory Command Wait TPROG Data Correct? No Report Programming Failure End Programming Yes Increment Address Command Wait TDIS No Address = 0x2004? Yes Increment Address Command Increment Address Command Increment Address Command One-word Program Cycle (Config. bits) Read Data from Program Memory Command Data Correct? No Report Programming Failure Yes Done 2014 Microchip Technology Inc. DS20005270A-page 15 MCP19114/5 FIGURE 3-15: PROGRAM FLOWCHART – ERASE FLASH DEVICES Start Load Configuration Bulk Erase(1) Program Memory Done Note 1: See Section 3.1.3.7 “Bulk Erase Program Memory” for more information on the bulk erase procedure. DS20005270A-page 16 2014 Microchip Technology Inc. MCP19114/5 4.0 CONFIGURATION WORD The MCP19114/5 devices have several Configuration bits. These bits can be programmed (reads ‘0’) or left unchanged (reads ‘1’), to select various device configurations. REGISTER 4-1: CONFIG: CONFIGURATION WORD (ADDRESS: 2007h) R/P-1 U-1 R/P-1 R/P-1 U-1 R/P-1 U-1 DBGEN — WRT1 WRT0 — BOREN — bit 13 R/P-1 R/P-1 R/P-1 R/P-1 U-1 U-1 U-1 CP MCLRE PWRTE WDTE — — — bit 6 Legend: x = Bit is unknown P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13 DBGEN: ICD Debug bit 1 = ICD Debug mode disabled 0 = ICD Debug mode enabled bit 12 Unimplemented: Read as ‘1’ bit 11-10 WRT<1:0>: Flash Program Memory Self-Write Enable bit 11 = Write protection off 10 = 000h to 3FFh write-protected, 400h to FFFh may be modified by PMCON1 control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON1 control 01 = 000h to FFFh write-protected, entire program memory is write-protected bit 9 Unimplemented: Read as ‘1’ bit 8 BOREN: Brown-out Reset Enable bits 1 = BOR disabled during Sleep and enabled during operation 0 = BOR disabled bit 7 Unimplemented: Read as ‘1’ bit 6 CP: Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is external read and write-protected bit 5 MCLRE: MCLR Pin Function Select bit 1 = MCLR pin is MCLR function and weak internal pull-up is enabled 0 = MCLR pin is alternate function, MCLR function is internally disabled bit 4 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 Unimplemented: Read as ‘1’ Note 1: Bit is reserved and not controlled by user. 2014 Microchip Technology Inc. DS20005270A-page 17 MCP19114/5 4.1 Device ID Word The device ID word for the MCP19114/5 is loaded at 2006h. This location cannot be erased. TABLE 4-2: DEVICE ID VALUES Device ID Values Device Dev Rev MCP19114 10 1110 010 0 0011 MCP19115 10 1110 010 0 0011 DS20005270A-page 18 2014 Microchip Technology Inc. MCP19114/5 5.0 CODE PROTECTION 5.3 Checksum Computation For MCP19114/5, once the CP bit is programmed to ‘0’, all program memory locations read all ‘0’s. The user ID locations and the Configuration Word read out in an unprotected fashion. Further programming is disabled for the entire program memory. The checksum is calculated by two different methods dependent on the setting of the CP Configuration bit. The user ID locations and the Configuration Word can be programmed regardless of the state of the CP bit. With the program code protection disabled, the checksum is computed by reading the contents of the program memory locations and adding up the program memory data starting at address 0x0000h, up to the maximum user addressable location. Any Carry bit exceeding 16 bits is ignored. Additionally, the relevant bits of the Configuration Words are added to the checksum. All unimplemented Configuration bits are masked to ‘0’. 5.1 Disabling Code Protection It is recommended to use the procedure in Figure 3-15 to disable code protection of the device. This sequence will erase the program memory, Configuration Word (0x2007) and user ID locations (0x2000-0x2003). The Calibration Words (0x2080 to 0x2083) will not be erased. 5.2 5.3.1 PROGRAM CODE PROTECTION DISABLED Embedding Configuration Word and User ID Information in the Hex File To allow portability of code, the programmer is required to read the Configuration Word and user ID locations from the hex file when loading it. If Configuration Word information was not present in the hex file, a simple warning message may be issued. Similarly, while saving a hex file, Configuration Word and user ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. EXAMPLE 5-1: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED (CP = 1), MCP19114 AND MCP19115 BLANK DEVICES Sum of Memory addresses 000h-0FFFh F000h1 Configuration Word 3FFFh2 2D78h3 Configuration Word mask Checksum = F000h + (3FFFh and 2D78h)4 = F000h + 2D78h = 1D78h Note 1: This value is obtained by taking the total number of program memory locations (0x000h to 0x0FFFh, which is 0x1000h) and multiplying it by the blank memory value of 0x3FFF to get the sum of 3FF F000h. Then truncate to 16 bits, thus having a final value of F000h. 2: This value is obtained by making all bits of the Configuration Word a ‘1’, then converting it to hex, thus having a value of 3FFFh. 3: This value is obtained by making all used bits of the Configuration Word a ‘1’, then converting it to hex, thus having a value of 2D78h. 4: This value is obtained by ANDing the Configuration Word value with the Configuration Word Mask value and adding it to the sum of memory addresses (3FFFh and 2D78) + F000h = 11C78h. Then truncate to 16 bits, thus having a final value of 1D78h. 2014 Microchip Technology Inc. DS20005270A-page 19 MCP19114/5 5.3.2 PROGRAM CODE PROTECTION ENABLED With the program code protection enabled, the checksum is computed in the following manner. The Least Significant nibble of each user ID is used to create a 16-bit value. The masked value of user ID location 2000h is the Most Significant nibble. This sum of user IDs is summed with the Configuration Word (all unimplemented Configuration bits are masked to ‘0’). EXAMPLE 5-2: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED (CP = 0), MCP19114 AND MCP19115 BLANK DEVICES Configuration Word 3FBFh(1) Configuration Word mask 2D38h(2) User ID (2000h) 0006h(3) User ID (2001h) 0007h(3) User ID (2002h) 0001h(3) User ID (2003h) 0002h(3) Sum of User IDs = (0006h and 000Fh) << 12 + (0007h and 000Fh) << 8 + (0001h and 000Fh) << 4 + (0002h and 000Fh)(4) = 6000h + 0700h + 0010h + 0002h = 6712h Checksum = (3FBFh and 2D38h) + Sum of User IDs(5) = 2D38h + 6712h = 944Ah Note 1: This value is obtained by making all bits of the Configuration Word a ‘1’, but the code protection bit is ‘0’ (thus, enabled), then converting it to a hex, thus having a value of 3FBFh. 2: This value is obtained by making all used bits of the Configuration Word a ‘1’, but the code protection bit is ‘0’ (thus, enabled), then converting to hex, thus having a value of 2D38h. 3: These values are picked at random for this example; they could be any 16-bit value. 4: In order to calculate the sum of user IDs, take the 16-bit value of the first user ID location (0006h), AND the address to (000Fh), thus masking the MSB. This gives you the value 0006h, then shift left 12 bits, giving you 6000h. Do the same procedure for the 16-bit value of the second user ID location (0007h), except shift left eight bits. Also do the same for the third user ID location (0001h), except shift left four bits. For the fourth user ID location, do not shift. Finally, add up all four user ID values to get the final sum of user IDs of 6712h. 5: This value is obtained by ANDing the Configuration Word value with the Configuration Mask value and adding it to the sum of user IDs: (3FBFh and 2D38h) + (6712h) = 944Ah. DS20005270A-page 20 2014 Microchip Technology Inc. MCP19114/5 6.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS TABLE 6-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE AC/DC CHARACTERISTICS Sym. Characteristics Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +85°C Operating Voltage 4.5V VDD 5.5V Min. Typ. Max. Units VIN level for read/write operations, program and data memory 4.5 — 42 V VIN level for bulk erase operations, program and data memory 4.5 — 42 V VDD + 3.5 — 13 V Conditions/Comments General VIN VIHH High voltage on MCLR for Program/Verify mode entry IIHH MCLR current during programming — 300 1000 µA TVHHR MCLR rise time (VSS to VHH) for Program/Verify mode entry — — 1.0 µs VDD regulated internally to 5V TPPDP Hold time after TEST_ENchanges 5 — — µs VIH1 (ICSPCLK, ICSPDAT) input high level 0.8 VDD — — V Schmitt Trigger input VIL1 (ICSPCLK, ICSPDAT) input low level 0.2 VDD — — V Schmitt Trigger input TSET0 ICSPCLK, ICSPDAT setup time before MCLR (Program/Verify mode selection pattern setup time) 100 — — ns THLD0 Hold time after VDD changes 5 — — µs Data in setup time before clock 100 — — ns THLD1 Data in hold time after clock 100 — — ns TDLY1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 — — µs TDLY2 Delay between clockto clockof next command or data 1.0 — — µs TDLY3 Clock to data out valid (during a Read Data command) — — 80 ns Serial Program/Verify TSET1 TERA Erase cycle time — 5 6 ms TPROG Programming cycle time 3 — — ms TDIS Time delay from program to compare (HV discharge time) 100 — — µs 2014 Microchip Technology Inc. +10°C TA +40°C DS20005270A-page 21 MCP19114/5 APPENDIX A: REVISION HISTORY Revision A (March 2014) • Original Release of this Document. DS20005270A-page 22 2014 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-63276-033-3 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2014 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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