Si91841/3 Vishay Siliconix 150-mA Ultra Low-Noise LDO Regulator With Discharge Option FEATURES D Si91841: Output, Auto-Discharge In Shutdown Mode D Si91843: Output, No-Discharge In Shutdown Mode D Fixed 1.8, 2.0, 2.2, 2.5, 2.6, 2.7, 2.8, 2.85, 2.9, 3.0, 3.3, 3.5, 3.6, 5.0-V Output Voltage Options D Thin SOT23-5 Package D Ultra Low Dropout—130 mV at 150-mA Load D Ultra Low Noise—30 mV(rms) (10-Hz to 100-kHz Bandwidth) D Shutdown Control D 110-mA Ground Current at 150-mA Load D 1.5% Guaranteed Output Voltage Accuracy D 300-mA Peak Output Current Capability D Uses Low ESR Ceramic Capacitors D Fast Start-Up (50 ms) D Fast Line and Load Transient Response (v 30 ms) D 1-mA Maximum Shutdown Current D Output Current Limit D Reverse Battery Protection D Built-in Short Circuit and Thermal Protection APPLICATIONS D Cellular Phones, Wireless Handsets D Noise-Sensitive Electronic Systems, Laptop and Palmtop Computers D PDAs D Pagers D Digital Cameras D MP3 Player D Wireless Modem DESCRIPTION The Si91841/3 is a 150-mA CMOS LDO (low dropout) voltage regulator. It is the perfect choice for low voltage, low power applications. An ultra low ground current makes this part attractive for battery operated power systems. The Si91841/3 also offers ultra low dropout voltage to prolong battery life in portable electronics. Systems requiring a quiet voltage source, such as RF applications, will benefit from the Si91841/3’s ultra low output noise. An external noise bypass capacitor connected to the device’s BP pin can further reduce the noise level. The Si91841/3 is designed to maintain regulation while delivering 300-mA peak current, making it ideal for systems that have a high surge current upon turn-on. pull-down circuit is built into the Si91841/3 to clamp the output voltage when it rises beyond normal regulation. The Si91841 automatically discharges the output voltage by connecting the output to ground through a 100-W n-channel MOSFET when the device is put in shutdown mode. The Si91841/3 features reverse battery protection to limit reverse current flow to approximately 1-mA in the event reversed battery is applied at the input, thus preventing damage to the IC. The Si91841/3 is available in both standard and lead (Pb)-free packages. For better transient response and regulation, an active TYPICAL APPLICATION CIRCUIT Si91841/3 VIN 1 VIN 2 GND 3 SD VOUT 5 VOUT 1 mF SD 1 mF BP 4 10 nF Thin SOT-23, 5-Lead Document Number: 71447 S-40592—Rev. C, 29-Mar-04 www.vishay.com 1 Si91841/3 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings Package Thermal Resistance, (qJA)a . . . . . . . . . . . . . . . . . . . . . . . . . 180_C/W Input Voltage, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −6.0 to 6.5 V Maximum Junction Temperature, TJ(max) . . . . . . . . . . . . . . . . . . . . . . . 150_C VSD (See Detailed Description) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VIN Output Current, IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected Output Voltage, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VIN + 0.3 V Package Power Dissipation, (Pd)b . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 mW Storage Temperature, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 5.5 mW/_C above TA = 70_C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V to 6 V Input Voltage, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VIN Operating Ambient Temperature, TA . . . . . . . . . . . . . . . . . . . . −40_C to 85_C CIN = COUT = 1 mF (ceramic), CBP = 0.01 mF (ceramic) Maximum ESR of COUT: 0.4 W SPECIFICATIONS Test Conditions Unless Specified Limits −40 to 85_C Symbol TA = 25_C, VIN = VOUT(nom) ( )+1V IOUT = 1 mA, CIN = 1 mF, COUT = 1.0 mF VSD = 1.5 V Tempa Start-Up BP Current IOUT ON/OFF = High Room Input Voltage Range VIN Parameter Output Voltage Accuracy VOUT Line Regulation (3.0 V < VOUT v3.6 V) DVIN 1 1.5 Full −2.5 1 2.5 Full −0.06 0.18 Full 0 0.3 From VIN = 5.5 V to 6 V Full 0 0.4 IOUT = 1 mA Room 1 Room 45 Full 50 90 Room 130 180 From VIN = VOUT(nom) + 1 V to VOUT(nom) + 2 V VIN − VOUT IOUT = 150 mA IOUT = 50 mA Dropout Voltaged, g (VOUT(nom) 2 6 V, V VIN w OUT( ) t 2.6 2 V) IOUT = 150 mA IOUT = 0 mA Currente, g Ground Pin (VOUT(nom) v 3 V) IOUT = 150 mA IGND IOUT = 0 mA Ground Pin Currente (VOUT(nom) u 3 V) Peak Output current www.vishay.com 2 IOUT = 150 mA IO(peak) VOUT w 0.95 x VOUT(nom). tPW = 2 ms 6 Full 65 Full % %/V mV 100 120 Room 190 Full 250 300 Room 100 Full 150 180 Room 110 Full 200 230 Room 110 Full 170 mA 200 Room 120 Full Full V 80 220 Room Unit mA −1.5 IOUT = 50 mA d g d, Dropoutt V D Voltage lt (VOUT(nom) w 2.6 V) 1 Room VOUT(nom) Line Regulation (5-V Version) Maxb 2 1 mA v IOUT v 150 mA 100 Typc Full Line Regulation (VOUT v 3 V) DVOUT Minb 200 230 300 mA Document Number: 71447 S-40592—Rev. C, 29-Mar-04 Si91841/3 Vishay Siliconix SPECIFICATIONS Parameter Limits TA = 25_C, VIN = VOUT(nom) + 1 V IOUT = 1 mA, CIN = 1 mF, COUT = 1.0 mF VSD = 1.5 V −40 to 85_C Symbol Output Noise Voltage Ripple pp Rejection j Test Conditions Unless Specified VNOM = 2.6 V, BW = 10 Hz to 100 kHz, 0 mA t IOUT t 150 mA, CNOISE = 0.01 mF eN DVOUT/DVIN IOUT = 150 mA Tempa Minb Typc Room 30 f = 1 kHz Room 60 f = 10 kHz Room 40 f = 100 kHz Room 30 Dynamic Line Regulation DVO(line) VIN : VOUT(nom) + 1 V to VOUT(nom) + 2 V tr/tf = 2 ms, IOUT = 150 mA Room 20 Dynamic Load Regulation DVO(load) IOUT : 1 mA to 150 mA, tr/tf = 2 ms Room 20 Thermal Shutdown Junction Temperature TJ(S/D) Room 150 Thermal Hysteresis THYST Room 20 Maxb Unit mV(rms) dB mV _C C Reverse current IR VIN = −6.0 V Room 1 mA Short Circuit Current ISC VOUT = 0 V Room 700 mA Shutdown Shutdown Supply Current ICC(off) SD Pin Input Voltage VSD VSD = 0 V Room High = Regulator ON (Rising) Full Low = Regulator OFF (Falling) Full 0.1 1.5 1 VIN 0.4 mA V Auto Discharge Resistance R_DIS Si91841 Only Room 100 W SD Pin Input Currentf IIN(SD) VSD = 1.5 V, VIN = 6 V Room 0.7 mA Full 150 mV 50 mS SD Hysteresis VHYST(SD) VOUT Turn-On Time tON VSD (See Figure 1), ILOAD = 100 nA Notes a. Room = 25_C, Full = −40 to 85_C. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typical values for dropout voltage at VOUT w 2 V are measured at VOUT = 3.3 V, while typical values for dropout voltage at VOUT < 2 V are measured at VOUT = 1.8 V. d. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-V differential, provided that VIN does not not drop below 2.0 V. e. Ground current is specified for normal operation as well as “drop-out” operation. f. The device’s shutdown pin includes a typical 2-MW internal pull-down resistor connected to ground. g. VOUT(nom) is VOUT when measured with a 1-V differential to VIN. TIMING WAVEFORMS VIN VSD tr v 1 ms 0V tON VNOM 0.95 VNOM VOUT FIGURE 1. Timing Diagram for Power-Up Document Number: 71447 S-40592—Rev. C, 29-Mar-04 www.vishay.com 3 Si91841/3 Vishay Siliconix PIN CONFIGURATION PIN DESCRIPTION Thin SOT-23, 5-Lead VIN 1 GND 2 SD 3 5 4 VOUT BP Pin No. Name Function 1 VIN 2 GND Input supply pin. Bypass this pin with a 1-mF ceramic or tantalum capacitor to ground 3 SD By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to VIN if unused 4 BP Noise bypass pin. For low noise applications, a 0.01 mF ceramic capacitor should be connected from this pin to ground. 5 VOUT Ground pin. For better thermal capability, directly connected to large ground plane Output voltage. Connect COUT between this pin and ground. ORDERING INFORMATIONSi91841 Part Number Lead (Pb)-Free Part Number Marking Voltage Si91841DT-18-T1 Si91841DT-18-T1—E3 B4LL 1.8 Si91841DT-20-T1 Si91841DT-20-T1—E3 B5LL 2.0 Si91841DT-22-T1 Si91841DT-22-T1—E3 B6LL 2.2 Si91841DT-25-T1 Si91841DT-25-T1—E3 B7LL 2.5 Si91841DT-26-T1 Si91841DT-26-T1—E3 B8LL 2.6 Si91841DT-27-T1 Si91841DT-27-T1—E3 B9LL 2.7 Si91841DT-28-T1 Si91841DT-28-T1—E3 B0LL 2.8 Si91841DT-285-T1 Si91841DT-285—E3 C1LL 2.85 Si91841DT-29-T1 Si91841DT-29-T1—E3 C2LL 2.9 Si91841DT-30-T1 Si91841DT-30-T1—E3 C3LL 3.0 Si91841DT-33-T1 Si91841DT-33-T1—E3 C4LL 3.3 Si91841DT-35-T1 Si91841DT-35-T1—E3 C5LL 3.5 Si91841DT-36-T1 Si91841DT-36-T1—E3 C6LL 3.6 Si91841DT-50-T1 Si91841DT-50-T1—E3 C7LL 5.0 Temperature Range Package −40 to 85_C Thin SOT23-5 Note: LL = Lot Code ORDERING INFORMATIONSi91843 Part Number Lead (Pb)-Free Part Number Marking Voltage Si91843DT-18-T1 Si91843DT-18-T1—E3 E2LL 1.8 Si91843DT-20-T1 Si91843DT-20-T1—E3 E3LL 2.0 Si91843DT-22-T1 Si91843DT-22-T1—E3 E4LL 2.2 Si91843DT-25-T1 Si91843DT-25-T1—E3 E5LL 2.5 Si91843DT-26-T1 Si91843DT-26-T1—E3 E6LL 2.6 Si91843DT-27-T1 Si91843DT-27-T1—E3 E7LL 2.7 Si91843DT-28-T1 Si91843DT-28-T1—E3 E8LL 2.8 Si91843DT-285-T1 Si91843DT-285—E3 E9LL 2.85 Si91843DT-29-T1 Si91843DT-29-T1—E3 E0LL 2.9 Si91843DT-30-T1 Si91843DT-30-T1—E3 F1LL 3.0 Si91843DT-33-T1 Si91843DT-33-T1—E3 F2LL 3.3 Si91843DT-35-T1 Si91843DT-35-T1—E3 F3LL 3.5 Si91843DT-36-T1 Si91843DT-36-T1—E3 F4LL 3.6 Si91843DT-50-T1 Si91843DT-50-T1—E3 F5LL 5.0 Temperature Range Package −40 to 85_C Thin SOT23-5 Note: LL = Lot Code www.vishay.com 4 Document Number: 71447 S-40592—Rev. C, 29-Mar-04 Si91841/3 Vishay Siliconix TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED) Normalized Output Voltage vs. Load Current 0.30 VIN = VOUT(nom) + 1 V VIN = VOUT(nom) + 1 V 0.15 Normalized VOUT vs. Temperature 0.4 0.2 −0.0 V OUT (%) Output Voltage (%) IOUT = 0 mA 0.00 −0.15 −0.30 −0.2 −0.6 −0.60 −0.8 0 25 50 75 100 125 IOUT = 150 mA −0.4 −0.45 −0.75 IOUT = 75 mA −1.0 −40 150 −15 Load Current (mA) GND Current vs. Load Current 150 VOUT = 3.0 V VIN = 4.0 V 10 35 60 85 Ambient Temperature (_C) No Load GND Pin Current vs. Input Voltage 300 85_C 250 125 200 I GND ( mA) I GND ( mA) 25_C 100 −40_C 150 85_C 25_C 100 −40_C 75 50 50 0 0 25 50 75 100 125 150 2 3 Load Current (mA) Power Supply Rejection 0 −20 4 5 6 7 Input Voltage (V) 750 Output Short Circuit Current vs. Temperature VOUT = 2.6 V CIN = 1 mF COUT = 1 mF ILOAD = 150 mA VOUT = 3.0 V 725 I SC (mA) Gain (dB) 700 −40 675 650 −60 625 −80 10 100 1000 10000 Frequency (Hz) Document Number: 71447 S-40592—Rev. C, 29-Mar-04 100000 1000000 600 −40 −15 10 35 60 85 AmbientTemperature (_C) www.vishay.com 5 Si91841/3 Vishay Siliconix TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED) Dropout Voltage vs. Load Current 350 VOUT = 3.0 V 300 VOUT = 3.0 V 2.5 250 2.0 V OUT (V) V DROP (mV) VIN − VOUT Transfer Characteristic 3.0 200 150 1.5 1.0 100 0.5 50 0 0.0 0 60 120 180 240 0 300 1 2 3 ILOAD (mA) 350 Dropout Voltage vs. Temperature Dropout Voltage (mV) V DROP (mV) 250 200 IOUT = 150 mA 100 6 250 200 150 IOUT = 150 mA IOUT = 75 mA 50 IOUT = 10 mA IOUT = 0 mA −25 0 25 50 75 100 Junction Temperature (_C) www.vishay.com IOUT = 300 mA 300 100 IOUT = 75 mA 50 0 −50 6 350 IOUT = 300 mA 150 5 Dropout Voltage vs. VOUT 400 VOUT = 3.0 V 300 4 VIN (V) 125 150 0 1.0 IOUT = 10 mA 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOUT Document Number: 71447 S-40592—Rev. C, 29-Mar-04 Si91841/3 Vishay Siliconix TYPICAL WAVEFORMS Load Transient Response-1 Load Transient Response-2 VOUT 10 mV/div VOUT 10 mV/div ILOAD 100 mA/div ILOAD 100 mA/div 20 ms/div 20 ms/div VOUT = 3.0 V COUT = 1 mF ILOAD = 1 to 150 mA trise = 2 msec VOUT = 3.0 V COUT = 1 mF ILOAD = 150 to 1 mA tfall = 2 msec LineTransient Response-1 LineTransient Respons-2 VOUT 10 mV/div VOUT 10 mV/div VIN 2 V/div VIN 2 V/div 20 ms/div 20 ms/div VINSTEP = 4 to 5 V VOUT = 3 V COUT = 1 mF CIN = 1 mF ILOAD = 150 mA trise = 5 msec Document Number: 71447 S-40592—Rev. C, 29-Mar-04 VINSTEP = 5 to 4 V VOUT = 3 V COUT = 1 mF CIN = 1 mF ILOAD = 150 mA tfall = 5 msec www.vishay.com 7 Si91841/3 Vishay Siliconix TYPICAL WAVEFORMS Output Noise Noise Spectrum Output Spectral Noise Density 10 VOUT 200 mV/div mVń ǸHz 0.01 4 ms/div 10 Hz VIN = 4 V VOUT = 3 V IOUT = 150 mA CNOISE = 0.01 mF BW = 10 Hz to 100 kHz www.vishay.com 8 1 MHz VIN = 4 V VOUT = 3 V ILOAD = 150 mA CNOISE = 0.01 mF Document Number: 71447 S-40592—Rev. C, 29-Mar-04 Si91841/3 Vishay Siliconix BLOCK DIAGRAM Si91841/3 VIN Reverse Polarity Protection BP Reference − + VOUT Thermal Sensor Si91841 Only Current Limit SD Shutdown Control GND DETAILED DESCRIPTION The Si91841/3 is a low-noise, low drop-out and low quiescent current linear voltage regulator, packaged in a small footprint Thin SOT23-5 package. The Si91841/3 can supply loads up to 300 mA. As shown in the block diagram, the circuit consists of a bandgap reference error, amplifier, p-channel pass transistor and feedback resistor string. An external bypass capacitor connected to the BP pin reduces noise at the output. Additional blocks, not shown in the block diagram, include a precise current limiter, reverse battery and current protection and thermal sensor. Thermal Overload Protection The thermal overload protection limits the total power dissipation and protects the device from being damaged. When the junction temperature exceeds 150_, the device turns the p-channel pass transistor off. Reverse Battery Protection The Si91841/3 has a battery reverse protection circuitry that disconnects the internal circuitry when VIN drops below the GND voltage. There is no current drawn in such an event. When the SD pin is hardwired to VIN, the user must connect the SD pin to VIN via a 100-kW resistor if reverse battery Document Number: 71447 S-40592—Rev. C, 29-Mar-04 protection is desired. Hardwiring the SD pin directly to the VIN pin is allowed when reverse battery protection is not desired. Noise Reduction An external 10-nF bypass capacitor at BP is used to create a low pass filter for noise reduction. The start-up time is fast, since a power-on circuit pre-charges the bypass capacitor. After the power-up sequence the pre-charge circuit is switched to standby mode in order to save current. It is therefore not recommended to use larger bypass capacitor values than 50 nF. When the circuit is used without a capacitor, stable operation is guaranteed. Auto-Discharge/No-Discharge For Si91841 only, VOUT has an internal 100-W (typ.) discharge path to ground when the SD pin is low. The Si91843 does not have a discharge path when the SD pin is low. Stability The circuit is stable with only a small output capacitor equal to 6 nF/mA (= 1 mF @ 150 mA). Since the bandwidth of the error amplifier is around 1−3 MHz and the dominant pole is at the output node, the capacitor should be capacitive in this range, i.e., for 150-mA load current, an ESR <0.4 W is necessary. Parasitic inductance of about 10 nH can be tolerated. www.vishay.com 9