Data Sheet

Freescale Semiconductor
Addendum
Document Number: QFN_Addendum
Rev. 0, 07/2014
Addendum for New QFN
Package Migration
This addendum provides the changes to the 98A case outline numbers for products covered in this book.
Case outlines were changed because of the migration from gold wire to copper wire in some packages. See
the table below for the old (gold wire) package versus the new (copper wire) package.
To view the new drawing, go to Freescale.com and search on the new 98A package number for your
device.
For more information about QFN package use, see EB806: Electrical Connection Recommendations for
the Exposed Pad on QFN and DFN Packages.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
Part Number
MC68HC908JW32
Package Description
Original (gold wire)
Current (copper wire)
package document number package document number
48 QFN
98ARH99048A
98ASA00466D
MC9RS08LA8
48 QFN
98ARL10606D
98ASA00466D
MC9S08GT16A
32 QFN
98ARH99035A
98ASA00473D
MC9S908QE32
32 QFN
98ARE10566D
98ASA00473D
MC9S908QE8
32 QFN
98ASA00071D
98ASA00736D
MC9S08JS16
24 QFN
98ARL10608D
98ASA00734D
MC9S08QG8
24 QFN
98ARL10605D
98ASA00474D
MC9S08SH8
24 QFN
98ARE10714D
98ASA00474D
MC9RS08KB12
24 QFN
98ASA00087D
98ASA00602D
MC9S08QG8
16 QFN
98ARE10614D
98ASA00671D
MC9RS08KB12
8 DFN
98ARL10557D
98ASA00672D
6 DFN
98ARL10602D
98ASA00735D
MC9S08AC16
MC9S908AC60
MC9S08AC128
MC9S08AW60
MC9S08GB60A
MC9S08GT16A
MC9S08JM16
MC9S08JM60
MC9S08LL16
MC9S08QE128
MC9S08QE32
MC9S08RG60
MCF51CN128
MC9S08QB8
MC9S08QG8
MC9RS08KA2
Addendum for New QFN Package Migration, Rev. 0
2
Freescale Semiconductor
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9RS08LA8
Rev. 2, 1/2012
MC9RS08LA8
48 QFN
Case 1975
7 mm2
TBD
48 LQFP
Case 932
7 mm2
MC9RS08LA8
Features:
• 8-Bit RS08 Central Processor Unit (CPU)
– Up to 20 MHz CPU at 2.7 V to 5.5 V across temperature
range of –40°C to 85°C
– Subset of HC08 instruction set with added BGND
instruction
• On-Chip Memory
– 8 KB flash read/program/erase over full operating
voltage and temperature
– 256-byte random-access memory (RAM)
– Security circuitry to prevent unauthorized access to flash
contents
• Power-Saving Modes
– Wait and stop
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
39.0625 kHz or 1 MHz to 16 MHz
– Internal clock source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal or external reference; supports bus
frequencies up to 10 MHz
• System Protection
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1 kHz internal clock
source or bus clock
– Low-voltage detection with reset or interrupt; selectable
trip points
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
• Peripherals
– LCD — Up to 8 × 21 or 4 × 25 segments; compatible
with 5 V or 3 V LCD glass displays using on-chip charge
pump; functional in wait, stop modes for very low power
LCD operation; frontplane and backplane pins
multiplexed with GPIO functions; selectable frontplane
and backplane configurations
– ADC — 6-channel, 10-bit resolution; 2.5 μs conversion
time; automatic compare function; 1.7 mV/°C
temperature sensor; internal bandgap reference channel;
operation in stop; fully functional from 2.7 V to 5.5 V.
– TPM — One 2-channel 16-bit timer/pulse-width
modulator (TPM) module
– SCI — One 2-channel serial communications interface
module with optional 13-bit break; LIN extensions
– SPI — One serial peripheral interface module in 8-bit
data length mode with a receive data buffer hardware
match function
– ACMP — Analog comparator with option to compare to
internal reference
– MTIM — One 8-bit modulo timer
– KBI — 8-pin keyboard interrupt module
– RTI — One real-time interrupt module with optional
reference clock.
• Input/Output
– 33 GPIOs including 1 output only pin and 1 input only
pin.
– Hysteresis and configurable pullup device on all input
pins; configurable slew rate and drive strength on all
output pins.
• Package Options
– 48-pin QFN
– 48-pin LQFP
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008-2012. All rights reserved.
Table of Contents
1
2
3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .7
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .8
3.4 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .9
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .14
3.7 External (XOSC) and Internal (ICS) Oscillator
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4
5
3.8.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 TPM/MTIM Module Timing . . . . . . . . . . . . . . . .
3.9 Analog Comparator (ACMP) Electrical . . . . . . . . . . . .
3.10 Internal Clock Source Characteristics . . . . . . . . . . . . .
3.11 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information and Mechanical Drawings . . . . . . . . . .
17
18
19
19
20
22
22
23
25
26
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Date
Description of Changes
1
10/9/2008
Initial public released.
2
1/30/2012
Updated the case number of 48-pin QFN to 1975; updated 48-pin QFN case outline drawing.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9RS08LA8RM)
Contains extensive product information including modes of operation, memory, resets and
interrupts, register definition, port pins, CPU, and all module information.
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
2
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of the MC9RS08LA8 MCU.
6-CH 10-BIT
ANALOG-TO-DIGITAL
CONVERTER(ADC)
4-BIT KEYBORAD
INTERRUPT(KBI)
RS08 CORE
BDC
ANALOG COMPARATOR
(ACMP)
COP
XTAL
EXTAL
RTI
VPP
LVD
SS
SPSCK
MISO
MOSI
ACMP+
ACMP–
ACMPO
RESET
2-CH TIMER/PWM
WAKEUP
KBIP[0:7]
MODULE (TPM)
USER RAM
256 BYTES
SERIAL COMMUNICATION
INTERFACE (SCI)
PTB1/XTAL
PTB2/RESET/VPP
PTC1/TxD
PTC2/TPMCH0
PTC3/TPMCH1
PTC6/ACMPO/BKGD/MS
TxD
RxD
PTC7/TCLK/LCD28
PTD0/LCD0
PTD1/LCD1
8-bit Modulo Timer
(MTIM)
TCLK
1 MHz to 16 MHz
(XOSC)
PTD2/LCD2
PTD3/LCD3
PTD4/LCD4
PTD5/LCD5
VDD
VSS
PTB0/EXTAL
PTC0/RxD
PORT D
31.25 kHz to 38.4 kHz
PTA4/KBIP4/ADP4/LCD23
PTA7/KBIP7/ACMP–
20 MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
PTA3/MOSI/KBIP3/ADP3/TxD/LCD24
PTA6/KBIP6/ACMP+
TPMCH0
TPMCH1
TCLK
USER FLASH
8192 BYTES
PTA2/MISO/KBIP2/ADP2/RxD/LCD25
PTA5/KBIP5/ADP5/LCD22
PORT B
RS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PTA1/SPSCK/KBIP1/ADP1/LCD26
PORT C
CPU
SERIAL PERIPHERAL
INTERFACE (SPI)
PTA0/SS/KBIP0/ADP0/LCD27
ADP[5:0]
PORT A
VREFH
VREFL
VDDAD
VSSAD
PTD6/LCD6
VOLTAGE REGULATOR
PTD7/LCD7
PTE0/LCD8
LCD[0:7]
VLL2
VLL3
LIQUID CRYSTAL DISPLAY
DRIVER (LCD)
VCAP1
LCD[16:21]
PORT E
LCD[8:15]
VLL1
PTE1/LCD9
PTE2/LCD10
PTE3/LCD11
PTE4/LCD12
PTE5/LCD13
LCD[22:27]
VCAP2
PTE6/LCD14
PTE7/LCD15
LCD28
LCD[16:21]
NOTES:
1. PTB2/RESET/VPP is an input only pin when used as port pin
2. PTC6/ACMPO/BKGD/MS is an output only pin
Figure 1. MC9RS08LA8 Series Block Diagram
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
3
Pin Assignments
2
Pin Assignments
This section shows the pin assignments in the packages available for the MC9RS08LA8 series.
Table 1. Pin Availability by Package Pin-Count
Pin Number
48
<-- Lowest Priority
Port Pin
Alt 1
Alt 2
--> Highest
Alt 3
Alt 4
Alt 5
1
PTD7
LCD7
2
PTD6
LCD6
3
PTD5
LCD5
4
PTD4
LCD4
5
PTD3
LCD3
6
PTD2
LCD2
7
PTD1
LCD1
8
PTD0
LCD0
9
VCAP1
10
VCAP2
11
VLL1
12
VLL2
13
VLL3
14
PTA6
KBIP6
ACMP+
15
PTA7
KBIP7
ACMP–
16
VSSAD/VREFL
17
VDDAD/VREFH
18
PTB0
EXTAL
19
PTB1
XTAL
20
VDD
21
VSS
22
PTB2
RESET
23
PTC0
RxD
24
PTC1
TxD
25
PTC2
TPMCH0
26
PTC3
TPMCH1
27
PTC6
28
PTC7
29
PTA0
SS
KBIP0
ADP0
LCD27
30
PTA1
SPSCK
KBIP1
ADP1
LCD26
31
PTA2
MISO
KBIP2
RxD
ACMPO
BKGD
VPP
MS
TCLK
LCD28
ADP2
LCD25
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
4
Freescale Semiconductor
Pin Assignments
Table 1. Pin Availability by Package Pin-Count (continued)
Pin Number
48
<-- Lowest Priority
Port Pin
32
PTA3
33
34
Alt 1
MOSI
Alt 2
--> Highest
Alt 3
Alt 4
ADP3
Alt 5
KBIP3
TxD
LCD24
PTA4
KBIP4
ADP4
LCD23
PTA5
KBIP5
ADP5
LCD22
35
LCD21
36
LCD20
37
LCD19
38
LCD18
39
LCD17
40
LCD16
41
PTE7
LCD15
42
PTE6
LCD14
43
PTE5
LCD13
44
PTE4
LCD12
45
PTE3
LCD11
46
PTE2
LCD10
47
PTE1
LCD9
48
PTE0
LCD8
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
5
LCD19
LCD18
LCD17
LCD16
PTE7/LCD15
PTE6/LCD14
PTE5/LCD13
PTE4/LCD12
PTE3/LCD11
PTE2/LCD10
PTE1/LCD9
PTE0/LCD8
Pin Assignments
48 47 46 45 44 43 42 41 40 39 38 37
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTD1/LCD1
PTD0/LCD0
VCAP1
VCAP2
VLL1
VLL2
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
LCD20
LCD21
PTA5/KBIP5/ADP5/LCD22
PTA4/KBIP4/ADP4/LCD23
PTA3/MOSI/KBIP3/ADP3/TxD/LCD24
PTA2/MISO/KBIP2/ADP2/RxD/LCD25
PTA1/SPSCK/KBIP1/ADP1/LCD26
PTA0/SS/KBIP0/ADP0/LCD27
PTC7/TCLK/LCD28
PTC6/ACMPO/BKGD/MS
PTC3/TPMCH1
PTC2/TPMCH0
PTC1/TxD
PTC0/RxD
VSS
PTB2/RESET/VPP
VDD
PTB1/XTAL
PTB0/EXTAL
VSSAD/VREFL
VDDAD/VREFH
PTA7/KBIP7/ACMP–
PTA6/KBIP6/ACMP+
VLL3
13 14 15 16 17 18 19 20 21 22 23 24
Figure 2. MC9RS08LA8 Series in 48-Pin QFN/LQFP Package
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
6
Freescale Semiconductor
Electrical Characteristics
3
Electrical Characteristics
This chapter contains electrical and timing specifications.
3.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
3.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this chapter.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pull-up resistor associated with the pin is enabled.
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
2.7 to 5.5
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
±25
mA
Tstg
–55 to 150
°C
Storage temperature range
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
7
Electrical Characteristics
1
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two
resistance values.
2
All functional non-supply pins are internally clamped to VSS and VDD except the RESET/VPP pin which is internally
clamped to VSS only.
3
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD
and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater
than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are:
if no system clock is present, or if the clock rate is very low which would reduce overall power consumption.
3.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the
MCU design. In order to take PI/O into account in power calculations, determine the difference between
actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
Table 4. Thermal Characteristics
Rating
Symbol
Value
Unit
Operating temperature range (packaged)
TA
TL to TH
–40 to 85
°C
Maximum junction temperature
TJMAX
105
°C
48-pin LQFP
48-pin QFN θJA
71
84
°C/W
48-pin LQFP
48-pin QFN
49
28
Thermal resistance
Single layer board
Four layer board
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C /W
PD = Pint + PI/O
Pint = IDD × VDD, Watts chip internal power
PI/O = Power dissipation on input and output pins user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
8
Freescale Semiconductor
Electrical Characteristics
(if PI/O is neglected) is:
PD = K ÷ (TJ + 273°C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA× (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation A-3 by
measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be
obtained by solving equations 1 and 2 iteratively for any value of TA.
3.4
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table 5. ESD and Latch-up Test Conditions
Model
Human
Body
Machine
Latch-up
Description
Symbol
Value
Unit
Series resistance
R1
1500
Ω
Storage capacitance
C
100
pF
Number of pulses per pin
—
3
—
Series resistance
R1
0
Ω
Storage capacitance
C
200
pF
Number of pulses per pin
—
3
—
Minimum input voltage limit
—
–2.5
V
Maximum input voltage limit
—
7.5
V
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
9
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics
Rating1
No.
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
±2000
—
V
2
Machine model (MM)
VMM
±200
—
V
3
Charge device model (CDM)
VCDM
±500
—
V
Latch-up current at TA = 85°C
ILAT
±1002
—
mA
Latch-up current at TA = 85°C
ILAT
±753
—
mA
4
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
2
These pins meet JESD78A Class II (section 1.2) Level A (section 1.3) requirement of ±100 mA.
3
This pin meets JESD78A Class II (section 1.2) Level B (section 1.3) characterization to ±75 mA.
3.5
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power
supply current in various operating modes.
Table 7. DC Characteristics (Temperature Range = –40 to 85°C Ambient)
Num
C
Parameter
1
P
Supply voltage (run, wait and stop modes)
0 < fBus <10 MHz
2
D
Minimum RAM retention supply voltage applied to
VDD
3
P
Low-voltage Detection threshold
(VDD falling)
Symbol
Min
Typical
Max
Unit
VDD
2.7
—
5.5
V
VRAM
0.81
—
—
V
VLVD
—
1.8
—
V
4
C
Power on RESET (POR) voltage
VPOR
0.9
1.4
1.7
V
5
P
Input high voltage (VDD > 5V) (all digital inputs)
VIH
0.70 × VDD
—
—
V
6
P
Input high voltage (2.7 V ≤ VDD ≤ 5 V) (all digital
inputs)
VIH
0.85 × VDD
—
—
V
7
P
Input low voltage (VDD > 5 V) (all digital inputs)
VIL
—
—
0.30 × VDD
V
8
P
Input low voltage (2.7 V ≤ VDD ≤ 5 V)
VIL
—
—
0.30 × VDD
V
9
C
Input hysteresis (all digital inputs)
Vhys
0.06 × VDD
—
—
V
10
P
Input leakage current (per pin)
VIn = VDD or VSS, all input only pins
|IIn|
—
0.025
1.0
μA
11
P
High impedance (off-state) leakage current (per pin)
VIn = VDD or VSS, all input/output
|IOZ|
—
0.025
1.0
μA
12
C
Internal pullup/pulldown resistors2(all port pins)
RPU
20
45
65
kΩ
VOH
VDD – 0.8
—
—
V
|IOHT|
—
—
100
mA
(all digital inputs)
3,4
13
P
Output high voltage (all ports)
IOH = –5 mA (VDD ≥ 4.5 V)
IOH = –3 mA (VDD ≥ 3 V)
14
C
Maximum total IOH for all port pins
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
10
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (Temperature Range = –40 to 85°C Ambient) (continued)
Num
15
C
P
Parameter
Output low voltage (port A)4
IOL = 5 mA (VDD ≥ 4.5 V)
Symbol
Min
Typical
VOL
—
—
IOLT
—
—
100
mA
—
—
—
—
0.2
0.8
mA
mA
—
—
7
pF
IOL = 3 mA (VDD ≥ 3 V)
16
C
Maximum total IOL for all port pins
Max
0.8
0.8
Unit
V
current5,6,7
1
2
3
4
5
6
7
17
C
dc injection
VIn < VSS, VIn > VDD
Single pin limit
Total MCU limit, includes sum of all stressed pins
18
C
Input capacitance (all non-supply pins)
CIn
This parameter is characterized and not tested on each device.
Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown.
The IOH is for high output drive strength.
It is tested under high output drive strength only.
All functional non-supply pins are internally clamped to VSS and VDD except the RESET/VPP which is internally clamped to
VSS only
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
This parameter is characterized and not tested on each device.
Typical IOH vs. VDD-VOH VDD = 5.5 V
800
700
600
mV
500
-40C
25C
85C
400
300
200
100
0
3mA
6mA
9mA
12mA
15mA
Figure 3. Typical IOH vs. VDD-VOH (VDD = 5.5 V)
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
11
Electrical Characteristics
Typical IOH vs. V DD-V OH V DD = 3.3 V
1800
1600
1400
mV
1200
-40C
1000
25C
800
85C
600
400
200
0
3mA
6mA
9mA
12mA
15mA
Figure 4. Typical IOH vs. VDD-VOH (VDD = 3.3 V)
Typical IOL vs. V OL V DD = 5.5 V
0.8
0.7
0.6
V
0.5
-40C
25C
0.4
85C
0.3
0.2
0.1
0
3mA
6mA
9mA
12mA
15mA
Figure 5. Typical IOL vs. VOL (VDD = 5.5 V)
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
12
Freescale Semiconductor
Electrical Characteristics
Typical IOL vs. VOL VDD = 3.3 V
1.4
1.2
1
0.8
V
-40C
25C
85C
0.6
0.4
0.2
0
3mA
6mA
9mA
12mA
15mA
Figure 6. Typical IOL vs. VOL (VDD = 3.3 V)
VIH vs VDD
3.5
3
2.5
2
V
-40C
25C
85C
1.5
1
0.5
0
2.8V
3.0V
3.3V
4.5V
5.0V
5.5V
Figure 7. Typical VDD vs. VIH
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
13
Electrical Characteristics
VIL vs VDD
2.5
2
1.5
V
-40C
25C
85C
1
0.5
0
2.8V
3.0V
3.3V
4.5V
5.0V
5.5V
Figure 8. Typical VDD vs. VIL
3.6
Supply Current Characteristics
Table 8. Supply Current Characteristics
Num
1
2
3
4
5
C
P
P
P
C
C
Parameter
Run supply current
(fBus = 10 MHz)
2 measured
Wait mode supply current
Stop mode supply current
ADC adder from stop3
ACMP adder from stop
(ACME = 1)
Symbol
at
RIDD10
WIDD1
SIDD
—
VDD (V)
Typical1
Unit
5
3.71
mA
3.3
3.68
mA
3
3.67
mA
2.7
3.66
mA
5
1.37
mA
3.3
1.37
mA
3
1.37
mA
2.7
1.36
mA
5
1.40
μA
3.3
1.35
μA
3
1.31
μA
2.7
1.25
μA
5
125.45
μA
3.3
122.04
μA
3
121.59
μA
2.7
121.22
μA
5
21
μA
3
18.5
μA
—
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
14
Freescale Semiconductor
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Num
C
Parameter
Symbol
6
C
RTI adder from stop
with 1 kHz clock source enabled4
—
8
C
LVI adder from stop
(LVDE = 1 and LVDSE = 1)
—
VDD (V)
Typical1
Unit
5
2.4
μA
3
1.9
μA
5
70
μA
3
65
μA
1
Typicals are measured at 25 °C.
Does not include any dc loads on port pins
3
Required asynchronous ADC clock and LVD to be enabled.
4
Most customers are expected to find that auto-wakeup from stop can be used instead of the higher current wait mode.
Wait mode typical is 1.37 mA at 5 V and 3 V with fBus = 10 MHz.
2
3.7
External (XOSC) and Internal (ICS) Oscillator Characteristics
Reference Figure 9 for crystal or resonator circuit.
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
15
Electrical Characteristics
Table 9. External Oscillator Specifications (Temperature Range = –40 to 85°C Ambient)
Characteristic
Symbol
Min
Typical1
Max
Unit
Oscillator crystal or resonator (EREFS = 1)
Low range, (IREFS = x)
High range, FLL bypassed external (CLKS = 10, IREFS = x)
High range, FLL engaged external (CLKS = 00, IREFS = 0)
flo
fhi_byp
fhi_eng
32
1
1
—
—
—
38.4
10
10
kHz
MHz
MHz
Load capacitors
C1
C2
See Note 2
Feedback resistor
Low range (32 kHz to 100 kHz)
High range (1 MHz to 16 MHz)
RF
10
1
Series resistor
Low range
Low Gain (HGO = 0)
High Gain (HGO = 1)
High range
Low Gain (HGO = 0)
High Gain (HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
MΩ
MΩ
—
—
0
100
—
—
—
0
—
—
—
—
0
10
20
—
—
—
t
CSTL
t
CSTH
—
—
500
4
—
—
Square wave input clock frequency (EREFS = 0)
FLL bypass external (CLKS = 10)
FLL engaged external (CLKS = 00)
fextal
0
0.03125
—
—
20
5
MHz
Average internal reference frequency - untrimmed
fint_ut
25
31.25
41.66
kHz
Average internal reference frequency - trimmed
fint_t
31.25
31.25
39.0625
kHz
DCO output frequency range - untrimmed
fdco_ut
12.8
16
21.33
MHz
DCO output frequency range - trimmed
fdco_t
16
16
20
MHz
Δfdco_res_t
—
—
±0.2
%fdco
Total deviation of trimmed DCO output frequency
over voltage and temperature
Δfdco_t
—
—
±2
%fdco
FLL acquisition time 3,5
tacquire
—
—
1
ms
Long term Jitter 6 of DCO output clock
(averaged over 2ms interval)
CJitter
—
—
0.6
%fdco
RS
Crystal start-up time 3, 4
Low range
High range
Resolution of trimmed DCO output frequency
at fixed voltage and temperature
kΩ
ms
1
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
See crystal or resonator manufacturer’s recommendation.
3
This parameter is characterized and not tested on each device.
4 Proper PC board layout procedures must be followed to achieve specifications.
5 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used
as the reference, this specification assumes it is already running.
2
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
16
Freescale Semiconductor
Electrical Characteristics
6
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter
percentage for a given interval.
XOSC
EXTAL
XTAL
RS
RF
C1
Crystal or Resonator
C2
Figure 9. Typical Crystal or Resonator Circuit
3.8
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.8.1
Control Timing
Table 10. Control Timing
Parameter
Symbol
Min
Typical
Max
Unit
Bus frequency (tcyc = 1/fBus)
fBus
0
—
10
MHz
Real time interrupt internal oscillator period
tRTI
700
1000
1300
μs
textrst
150
—
—
ns
KBI pulse width2
tKBIPW
1.5 tcyc
—
—
ns
KBI pulse width in stop1
tKBIPWS
100
—
—
ns
tRise, tFall
—
—
11
35
—
—
ns
External RESET pulse width1
Port rise and fall time (load = 50 pF)3
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
1
This is the shortest pulse that is guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be
recognized.
2 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
3 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 85°C.
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
17
Electrical Characteristics
textrst
RESET
Figure 10. Reset Timing
tKBIPWS
tKBIPW
KBI Pin
(rising or high level)
KBI Pin
(falling or low level)
tKBIPW
tKBIPWS
Figure 11. KBI Pulse Width
3.8.2
TPM/MTIM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 11. TPM/MTIM Input Timing
Function
Symbol
Min
Max
Unit
External clock frequency
fTCLK
0
fBus1/4
MHz
External clock period
tTCLK
4
—
tCYC
External clock high time
tclkh
1.5
—
tCYC
External clock low time
tclkl
1.5
—
tCYC
fICPW
1.5
—
tCYC
Input capture pulse width
tTCLK
tclkh
TCLK
tclkl
Figure 12. Timer External Clock
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
18
Freescale Semiconductor
Electrical Characteristics
tICPW
TPMCHn
TPMCHn
tICPW
Figure 13. Timer Input Capture Pulse
3.9
Analog Comparator (ACMP) Electrical
Table 12. Analog Comparator Electrical Specifications
Characteristic
Supply voltage
Symbol
Min
Typical
Max
Unit
VDD
2.7
—
5.5
V
IDDAC
—
20
35
μA
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
Analog input offset voltage1
VAIO
—
20
40
mV
Analog Comparator hysteresis1
VH
3.0
9.0
15.0
mV
Analog source impedance
RAS
—
—
10
kΩ
Supply current (active)
Analog input leakage current
IALKG
—
—
1.0
μA
Analog Comparator initialization delay
tAINIT
—
—
1.0
μs
Analog Comparator bandgap reference voltage
VBG
1.208
1.208
1.208
V
1
These data are characterized but not production tested. Measurements are made with the device entered STOP mode.
3.10
Internal Clock Source Characteristics
Table 13. Internal Clock Source Specifications
Characteristic
Symbol
Min
Typical1
Max
Unit
Average internal reference frequency — untrimmed
fint_ut
25
31.25
41.66
kHz
Average internal reference frequency — trimmed
fint_t
31.25
39.06252
39.0625
kHz
DCO output frequency range — untrimmed
fdco_ut
12.8
16
21.33
MHz
DCO output frequency range — trimmed
fdco_t
16
203
20
MHz
Δfdco_res_t
—
—
0.2
%fdco
Total deviation of trimmed DCO output frequency
over voltage and temperature
Δfdco_t
—
—
2
%fdco
FLL acquisition time4,5
tacquire
—
—
1
ms
Stop recovery time (FLL wakeup to previous acquired
frequency)
IREFSTEN = 0
IREFSTEN = 1
twakeup
—
—
μs
Resolution of trimmed DCO output frequency
at fixed voltage and temperature
100
86
1
Data in typical column was characterized at 3.0 V and 5.0 V, 25 °C or is typical recommended value.
This value has been trimmed to 39.0625 kHz when out of factory
3 This value has been trimmed to 20 MHz when out of factory
2
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
19
Electrical Characteristics
4
5
This parameter is characterized and not tested on each device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBILP) to FLL enabled (FEI, FBI).
3.11
ADC Characteristics
Table 14. 5 Volt 10-bit ADC Operating Conditions
Symbol
Min
Typical1
Max
Unit
VDDAD
2.7
—
5.5
V
Delta to VDD (VDD – VDDAD)2
ΔVDDAD
–100
0
100
mV
Ground voltage
Delta to VSS (VSS – VSSAD)2
ΔVSSAD
–100
0
100
mV
Ref voltage high
—
VREFH
2.7
VDDAD
VDDAD
V
Ref voltage low
—
VREFL
VSSAD
VSSAD
VSSAD
V
Input voltage
—
VADIN
VREFL
—
VREFH
V
Input capacitance
—
CADIN
—
4.5
5.5
pF
Input resistance
—
RADIN
—
3
5
kΩ
Analog source resistance
external to MCU
10-bit mode
fADCK > 4MHz
fADCK < 4MHz
RAS
—
—
—
—
5
10
kΩ
—
—
10
0.4
—
8.0
0.4
—
4.0
Characteristic
Supply voltage
Conditions
Absolute
8-bit mode (all valid fADCK)
ADC conversion clock
frequency
High speed (ADLPC = 0)
Low power (ADLPC = 1)
fADCK
MHz
1
Typical values assume VDDAD = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2
DC potential difference.
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
20
Freescale Semiconductor
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
RADIN
ADC SA
ENGINE
+
VADIN
VAS
–
CAS
+
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 14. ADC Input Impedance Equivalency Diagram
Table 15. 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
C
Symbol
Min
Typical1
Max
Unit
Supply current
ADLPC=1
ADLSMP=1
ADCO=1
T
IDDAD
—
133
—
μA
Supply current
ADLPC=1
ADLSMP=0
ADCO=1
T
IDDAD
—
218
—
μA
Supply current
ADLPC=0
ADLSMP=1
ADCO=1
T
IDDAD
—
327
—
μA
P
IDDAD
—
0.582
1
mA
IDDAD
—
0.011
1
μA
2
3.3
5
1.25
2
3.3
Characteristic
Conditions
Supply current
ADLPC=0
ADLSMP=0
ADCO=1
VDDAD ≤ 5.5 V
Supply current
Stop, Reset, Module Off
ADC asynchronous clock
source
High Speed (ADLPC = 0)
Low Power (ADLPC = 1)
P
fADACK
MHz
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
21
Electrical Characteristics
Table 15. 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic
Conversion time (Including
sample time)
Conditions
Short Sample (ADLSMP = 0)
Long Sample (ADLSMP = 1)
Short Sample (ADLSMP = 0)
Sample time
Long Sample (ADLSMP = 1)
Total unadjusted error
10-bit mode
8-bit mode
10-bit mode
Differential non-linearity
8-bit mode
C
Symbol
P
tADC
P
tADS
P
ETUE
P
DNL
Min
Typical1
Max
Unit
—
20
—
—
40
—
ADCK
cycles
—
3.5
—
—
23.5
—
—
±1
±2.5
—
±0.5
±1.0
—
±0.5
±1.0
—
±0.3
±0.5
ADCK
cycles
LSB2
LSB2
Monotonicity and no-missing-code guaranteed
10-bit mode
Integral non-linearity
8-bit mode
10-bit mode
Zero-scale error
8-bit mode
10-bit mode
Full-scale error
VADIN = VDDA
8-bit mode
10-bit mode
Quantization error
8-bit mode
10-bit mode
Input leakage error
pad leakage3 * RAS
8-bit mode
C
INL
P
EZS
P
EFS
D
EQ
D
EIL
—
±0.5
±1.0
—
±0.3
±0.5
—
±0.5
±1.5
—
±0.5
±0.5
—
±0.5
±1.5
—
±0.5
±0.5
—
—
±0.5
—
—
±0.5
—
±0.2
±2.5
—
±0.1
±1
LSB2
LSB2
LSB2
LSB2
LSB2
1
Typical values assume VDDAD = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2 1 LSB = (V
N
REFH – VREFL)/2
3 Based on input pad leakage current. Refer to pad electrical.
3.12
AC Characteristics
This section describes AC timing characteristics for each peripheral system.
3.12.1
Control Timing
Table 16. Control Timing
Characteristic
Symbol
Min
Typical
Max
Unit
Bus frequency (tcyc = 1/fBus)
fBus
DC
—
10
MHz
Real time interrupt internal oscillator period
tRTI
700
1000
1300
μs
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
22
Freescale Semiconductor
Electrical Characteristics
Table 16. Control Timing (continued)
Characteristic
External RESET pulse width1
KBI pulse width2
KBI pulse width in
stop1
Port rise and fall time (load = 50 pF)3
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
Symbol
Min
textrst
Typical
Max
Unit
150
—
ns
tKBIPW
1.5 tcyc
—
ns
tKBIPWS
100
—
ns
tRise, tFall
—
—
—
—
ns
11
35
1
This is the shortest pulse that is guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be
recognized.
2
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
3
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 85 °C.
textrst
RESET
Figure 15. Reset Timing
tKBIPWS
tKBIPW
KBI Pin
(rising or high level)
KBI Pin
(falling or low level)
tKBIPW
tKBIPWS
Figure 16. KBI Pulse Width
3.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash
memory. For detailed information about program/erase operations, see the reference manual.
Table 17. Flash Characteristics
Symbol
Min
Typical1
Max
Unit
Supply voltage for program/erase
VDD
2.7
—
5.5
V
Program/Erase voltage
VPP
11.8
12
12.2
V
IVPP_prog
IVPP_erase
—
—
—
—
200
100
μA
μA
VRead
2.7
—
5.5
V
Characteristic
VPP current
Program
Mass erase
Supply voltage for read operation 0 < fBus < 10 MHz
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
23
Electrical Characteristics
Table 17. Flash Characteristics (continued)
Characteristic
Symbol
Min
Typical1
Max
Unit
Byte program time
tprog
20
—
40
μs
Mass erase time
tme
500
—
—
ms
Cumulative program HV time2
thv
—
—
8
ms
thv_total
—
—
2
hours
HVEN to program setup time
tpgs
10
—
—
μs
PGM/MASS to HVEN setup time
tnvs
5
—
—
μs
Total cumulative HV time
(total of tme & thv applied to device)
HVEN hold time for PGM
tnvh
5
—
—
μs
HVEN hold time for MASS
tnvh1
100
—
—
μs
VPP to PGM/MASS setup time
tvps
20
—
—
ns
HVEN to VPP hold time
tvph
20
—
—
ns
time3
tvrs
200
—
—
ns
Recovery time
trcv
1
—
—
μs
Program/erase endurance
TL to TH = –40 °C to 85 °C
—
1000
—
—
cycles
tD_ret
15
—
—
years
VPP rise
Data retention
1
Typicals are measured at 25 °C.
thv is the cumulative high voltage programming time to the same row before next erase. Same address can not be
programmed more than twice before next erase.
3 Fast V
PP rise time may potentially trigger the ESD protection structure, which may result in over current flowing into the pad
and cause permanent damage to the pad. External filtering for the VPP power source is recommended. An example VPP
filter is shown in Figure 17.
2
100 Ω
VPP
12 V
1 nF
Figure 17. Example VPP Filtering
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
24
Freescale Semiconductor
Ordering Information
tprog
WRITE DATA1
Next
Data
Data
tpgs
PGM
tnvs
tnvh
trcv
HVEN
trs
VPP2
tvps
tvph
thv
1
Next Data applies if programming multiple bytes in a single row, refer to MC9RS08LA8 Series Reference
Manual.
2 V
DD must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
Figure 18. Flash Program Timing
tme
trcv
MASS
tnvs
tnvh1
HVEN
trs
VPP1
1
tvps
tvph
VDD must be at a valid operating voltage before voltage is applied or removed from
the VPP pin.
Figure 19. Flash Mass Erase Timing
4
Ordering Information
This section contains ordering information for MC9RS08LA8 devices. See below for an example of the
device numbering system.
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
25
Package Information and Mechanical Drawings
MC 9 RS08 LA 8 C XX
Status
(MC = Fully Qualified)
Memory
(9 = Flash-based)
Core
Package designator (See Table 18)
Temperature range
(C = –40°C to 85° C)
Approximate memory size (in KB)
Family
5
Package Information and Mechanical Drawings
Table 18 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MC9RS08LA8 Series Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
• Click on the appropriate link in Table 18, or
• Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate
document number (from Table 18) in the “Enter Keyword” search box at the top of the page.
Table 18. Device Numbering System
Device Number
MC9RS08LA8
Memory
Package
FLASH
RAM
8 KB
256 bytes
Type
Designator
Document No.
48-Pin QFN
FT
98ARL10606D
48-Pin LQFP
LF
98ASH00962A
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
26
Freescale Semiconductor
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
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Document Number: MC9RS08LA8
Rev. 2
1/2012
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